Merge patch series "can: esd: add support for esd GmbH PCIe/402 CAN interface"

+7

MAINTAINERS

··· 7887 7887 F: include/linux/errseq.h 7888 7888 F: lib/errseq.c 7889 7889 7890 + ESD CAN NETWORK DRIVERS 7891 + M: Stefan Mätje <stefan.maetje@esd.eu> 7892 + R: socketcan@esd.eu 7893 + L: linux-can@vger.kernel.org 7894 + S: Maintained 7895 + F: drivers/net/can/esd/ 7896 + 7890 7897 ESD CAN/USB DRIVERS 7891 7898 M: Frank Jungclaus <frank.jungclaus@esd.eu> 7892 7899 R: socketcan@esd.eu

+1

drivers/net/can/Kconfig

··· 218 218 source "drivers/net/can/c_can/Kconfig" 219 219 source "drivers/net/can/cc770/Kconfig" 220 220 source "drivers/net/can/ctucanfd/Kconfig" 221 + source "drivers/net/can/esd/Kconfig" 221 222 source "drivers/net/can/ifi_canfd/Kconfig" 222 223 source "drivers/net/can/m_can/Kconfig" 223 224 source "drivers/net/can/mscan/Kconfig"

+1

drivers/net/can/Makefile

··· 8 8 obj-$(CONFIG_CAN_SLCAN) += slcan/ 9 9 10 10 obj-y += dev/ 11 + obj-y += esd/ 11 12 obj-y += rcar/ 12 13 obj-y += spi/ 13 14 obj-y += usb/

+12

drivers/net/can/esd/Kconfig

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + config CAN_ESD_402_PCI 3 + tristate "esd electronics gmbh CAN-PCI(e)/402 family" 4 + depends on PCI && HAS_DMA 5 + help 6 + Support for C402 card family from esd electronics gmbh. 7 + This card family is based on the ESDACC CAN controller and 8 + available in several form factors: PCI, PCIe, PCIe Mini, 9 + M.2 PCIe, CPCIserial, PMC, XMC (see https://esd.eu/en) 10 + 11 + This driver can also be built as a module. In this case the 12 + module will be called esd_402_pci.

+7

drivers/net/can/esd/Makefile

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + # 3 + # Makefile for esd gmbh ESDACC controller driver 4 + # 5 + esd_402_pci-objs := esdacc.o esd_402_pci-core.o 6 + 7 + obj-$(CONFIG_CAN_ESD_402_PCI) += esd_402_pci.o

+514

drivers/net/can/esd/esd_402_pci-core.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh 3 + * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh 4 + */ 5 + 6 + #include <linux/can/dev.h> 7 + #include <linux/can.h> 8 + #include <linux/can/netlink.h> 9 + #include <linux/delay.h> 10 + #include <linux/dma-mapping.h> 11 + #include <linux/ethtool.h> 12 + #include <linux/interrupt.h> 13 + #include <linux/io.h> 14 + #include <linux/kernel.h> 15 + #include <linux/module.h> 16 + #include <linux/netdevice.h> 17 + #include <linux/pci.h> 18 + 19 + #include "esdacc.h" 20 + 21 + #define ESD_PCI_DEVICE_ID_PCIE402 0x0402 22 + 23 + #define PCI402_FPGA_VER_MIN 0x003d 24 + #define PCI402_MAX_CORES 6 25 + #define PCI402_BAR 0 26 + #define PCI402_IO_OV_OFFS 0 27 + #define PCI402_IO_PCIEP_OFFS 0x10000 28 + #define PCI402_IO_LEN_TOTAL 0x20000 29 + #define PCI402_IO_LEN_CORE 0x2000 30 + #define PCI402_PCICFG_MSICAP 0x50 31 + 32 + #define PCI402_DMA_MASK DMA_BIT_MASK(32) 33 + #define PCI402_DMA_SIZE ALIGN(0x10000, PAGE_SIZE) 34 + 35 + #define PCI402_PCIEP_OF_INT_ENABLE 0x0050 36 + #define PCI402_PCIEP_OF_BM_ADDR_LO 0x1000 37 + #define PCI402_PCIEP_OF_BM_ADDR_HI 0x1004 38 + #define PCI402_PCIEP_OF_MSI_ADDR_LO 0x1008 39 + #define PCI402_PCIEP_OF_MSI_ADDR_HI 0x100c 40 + 41 + struct pci402_card { 42 + /* Actually mapped io space, all other iomem derived from this */ 43 + void __iomem *addr; 44 + void __iomem *addr_pciep; 45 + 46 + void *dma_buf; 47 + dma_addr_t dma_hnd; 48 + 49 + struct acc_ov ov; 50 + struct acc_core *cores; 51 + 52 + bool msi_enabled; 53 + }; 54 + 55 + /* The BTR register capabilities described by the can_bittiming_const structures 56 + * below are valid since esdACC version 0x0032. 57 + */ 58 + 59 + /* Used if the esdACC FPGA is built as CAN-Classic version. */ 60 + static const struct can_bittiming_const pci402_bittiming_const = { 61 + .name = "esd_402", 62 + .tseg1_min = 1, 63 + .tseg1_max = 16, 64 + .tseg2_min = 1, 65 + .tseg2_max = 8, 66 + .sjw_max = 4, 67 + .brp_min = 1, 68 + .brp_max = 512, 69 + .brp_inc = 1, 70 + }; 71 + 72 + /* Used if the esdACC FPGA is built as CAN-FD version. */ 73 + static const struct can_bittiming_const pci402_bittiming_const_canfd = { 74 + .name = "esd_402fd", 75 + .tseg1_min = 1, 76 + .tseg1_max = 256, 77 + .tseg2_min = 1, 78 + .tseg2_max = 128, 79 + .sjw_max = 128, 80 + .brp_min = 1, 81 + .brp_max = 256, 82 + .brp_inc = 1, 83 + }; 84 + 85 + static const struct net_device_ops pci402_acc_netdev_ops = { 86 + .ndo_open = acc_open, 87 + .ndo_stop = acc_close, 88 + .ndo_start_xmit = acc_start_xmit, 89 + .ndo_change_mtu = can_change_mtu, 90 + .ndo_eth_ioctl = can_eth_ioctl_hwts, 91 + }; 92 + 93 + static const struct ethtool_ops pci402_acc_ethtool_ops = { 94 + .get_ts_info = can_ethtool_op_get_ts_info_hwts, 95 + }; 96 + 97 + static irqreturn_t pci402_interrupt(int irq, void *dev_id) 98 + { 99 + struct pci_dev *pdev = dev_id; 100 + struct pci402_card *card = pci_get_drvdata(pdev); 101 + irqreturn_t irq_status; 102 + 103 + irq_status = acc_card_interrupt(&card->ov, card->cores); 104 + 105 + return irq_status; 106 + } 107 + 108 + static int pci402_set_msiconfig(struct pci_dev *pdev) 109 + { 110 + struct pci402_card *card = pci_get_drvdata(pdev); 111 + u32 addr_lo_offs = 0; 112 + u32 addr_lo = 0; 113 + u32 addr_hi = 0; 114 + u32 data = 0; 115 + u16 csr = 0; 116 + int err; 117 + 118 + /* The FPGA hard IP PCIe core implements a 64-bit MSI Capability 119 + * Register Format 120 + */ 121 + err = pci_read_config_word(pdev, PCI402_PCICFG_MSICAP + PCI_MSI_FLAGS, &csr); 122 + if (err) 123 + goto failed; 124 + 125 + err = pci_read_config_dword(pdev, PCI402_PCICFG_MSICAP + PCI_MSI_ADDRESS_LO, 126 + &addr_lo); 127 + if (err) 128 + goto failed; 129 + err = pci_read_config_dword(pdev, PCI402_PCICFG_MSICAP + PCI_MSI_ADDRESS_HI, 130 + &addr_hi); 131 + if (err) 132 + goto failed; 133 + 134 + err = pci_read_config_dword(pdev, PCI402_PCICFG_MSICAP + PCI_MSI_DATA_64, 135 + &data); 136 + if (err) 137 + goto failed; 138 + 139 + addr_lo_offs = addr_lo & 0x0000ffff; 140 + addr_lo &= 0xffff0000; 141 + 142 + if (addr_hi) 143 + addr_lo |= 1; /* To enable 64-Bit addressing in PCIe endpoint */ 144 + 145 + if (!(csr & PCI_MSI_FLAGS_ENABLE)) { 146 + err = -EINVAL; 147 + goto failed; 148 + } 149 + 150 + iowrite32(addr_lo, card->addr_pciep + PCI402_PCIEP_OF_MSI_ADDR_LO); 151 + iowrite32(addr_hi, card->addr_pciep + PCI402_PCIEP_OF_MSI_ADDR_HI); 152 + acc_ov_write32(&card->ov, ACC_OV_OF_MSI_ADDRESSOFFSET, addr_lo_offs); 153 + acc_ov_write32(&card->ov, ACC_OV_OF_MSI_DATA, data); 154 + 155 + return 0; 156 + 157 + failed: 158 + pci_warn(pdev, "Error while setting MSI configuration:\n" 159 + "CSR: 0x%.4x, addr: 0x%.8x%.8x, offs: 0x%.4x, data: 0x%.8x\n", 160 + csr, addr_hi, addr_lo, addr_lo_offs, data); 161 + 162 + return err; 163 + } 164 + 165 + static int pci402_init_card(struct pci_dev *pdev) 166 + { 167 + struct pci402_card *card = pci_get_drvdata(pdev); 168 + 169 + card->ov.addr = card->addr + PCI402_IO_OV_OFFS; 170 + card->addr_pciep = card->addr + PCI402_IO_PCIEP_OFFS; 171 + 172 + acc_reset_fpga(&card->ov); 173 + acc_init_ov(&card->ov, &pdev->dev); 174 + 175 + if (card->ov.version < PCI402_FPGA_VER_MIN) { 176 + pci_err(pdev, 177 + "esdACC version (0x%.4x) outdated, please update\n", 178 + card->ov.version); 179 + return -EINVAL; 180 + } 181 + 182 + if (card->ov.timestamp_frequency != ACC_TS_FREQ_80MHZ) { 183 + pci_err(pdev, 184 + "esdACC timestamp frequency of %uHz not supported by driver. Aborted.\n", 185 + card->ov.timestamp_frequency); 186 + return -EINVAL; 187 + } 188 + 189 + if (card->ov.active_cores > PCI402_MAX_CORES) { 190 + pci_err(pdev, 191 + "Card with %u active cores not supported by driver. Aborted.\n", 192 + card->ov.active_cores); 193 + return -EINVAL; 194 + } 195 + card->cores = devm_kcalloc(&pdev->dev, card->ov.active_cores, 196 + sizeof(struct acc_core), GFP_KERNEL); 197 + if (!card->cores) 198 + return -ENOMEM; 199 + 200 + if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD) { 201 + pci_warn(pdev, 202 + "esdACC with CAN-FD feature detected. This driver doesn't support CAN-FD yet.\n"); 203 + } 204 + 205 + #ifdef __LITTLE_ENDIAN 206 + /* So card converts all busmastered data to LE for us: */ 207 + acc_ov_set_bits(&card->ov, ACC_OV_OF_MODE, 208 + ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE); 209 + #endif 210 + 211 + return 0; 212 + } 213 + 214 + static int pci402_init_interrupt(struct pci_dev *pdev) 215 + { 216 + struct pci402_card *card = pci_get_drvdata(pdev); 217 + int err; 218 + 219 + err = pci_enable_msi(pdev); 220 + if (!err) { 221 + err = pci402_set_msiconfig(pdev); 222 + if (!err) { 223 + card->msi_enabled = true; 224 + acc_ov_set_bits(&card->ov, ACC_OV_OF_MODE, 225 + ACC_OV_REG_MODE_MASK_MSI_ENABLE); 226 + pci_dbg(pdev, "MSI preparation done\n"); 227 + } 228 + } 229 + 230 + err = devm_request_irq(&pdev->dev, pdev->irq, pci402_interrupt, 231 + IRQF_SHARED, dev_name(&pdev->dev), pdev); 232 + if (err) 233 + goto failure_msidis; 234 + 235 + iowrite32(1, card->addr_pciep + PCI402_PCIEP_OF_INT_ENABLE); 236 + 237 + return 0; 238 + 239 + failure_msidis: 240 + if (card->msi_enabled) { 241 + acc_ov_clear_bits(&card->ov, ACC_OV_OF_MODE, 242 + ACC_OV_REG_MODE_MASK_MSI_ENABLE); 243 + pci_disable_msi(pdev); 244 + card->msi_enabled = false; 245 + } 246 + 247 + return err; 248 + } 249 + 250 + static void pci402_finish_interrupt(struct pci_dev *pdev) 251 + { 252 + struct pci402_card *card = pci_get_drvdata(pdev); 253 + 254 + iowrite32(0, card->addr_pciep + PCI402_PCIEP_OF_INT_ENABLE); 255 + devm_free_irq(&pdev->dev, pdev->irq, pdev); 256 + 257 + if (card->msi_enabled) { 258 + acc_ov_clear_bits(&card->ov, ACC_OV_OF_MODE, 259 + ACC_OV_REG_MODE_MASK_MSI_ENABLE); 260 + pci_disable_msi(pdev); 261 + card->msi_enabled = false; 262 + } 263 + } 264 + 265 + static int pci402_init_dma(struct pci_dev *pdev) 266 + { 267 + struct pci402_card *card = pci_get_drvdata(pdev); 268 + int err; 269 + 270 + err = dma_set_coherent_mask(&pdev->dev, PCI402_DMA_MASK); 271 + if (err) { 272 + pci_err(pdev, "DMA set mask failed!\n"); 273 + return err; 274 + } 275 + 276 + /* The esdACC DMA engine needs the DMA buffer aligned to a 64k 277 + * boundary. The DMA API guarantees to align the returned buffer to the 278 + * smallest PAGE_SIZE order which is greater than or equal to the 279 + * requested size. With PCI402_DMA_SIZE == 64kB this suffices here. 280 + */ 281 + card->dma_buf = dma_alloc_coherent(&pdev->dev, PCI402_DMA_SIZE, 282 + &card->dma_hnd, GFP_KERNEL); 283 + if (!card->dma_buf) 284 + return -ENOMEM; 285 + 286 + acc_init_bm_ptr(&card->ov, card->cores, card->dma_buf); 287 + 288 + iowrite32(card->dma_hnd, 289 + card->addr_pciep + PCI402_PCIEP_OF_BM_ADDR_LO); 290 + iowrite32(0, card->addr_pciep + PCI402_PCIEP_OF_BM_ADDR_HI); 291 + 292 + pci_set_master(pdev); 293 + 294 + acc_ov_set_bits(&card->ov, ACC_OV_OF_MODE, 295 + ACC_OV_REG_MODE_MASK_BM_ENABLE); 296 + 297 + return 0; 298 + } 299 + 300 + static void pci402_finish_dma(struct pci_dev *pdev) 301 + { 302 + struct pci402_card *card = pci_get_drvdata(pdev); 303 + int i; 304 + 305 + acc_ov_clear_bits(&card->ov, ACC_OV_OF_MODE, 306 + ACC_OV_REG_MODE_MASK_BM_ENABLE); 307 + 308 + pci_clear_master(pdev); 309 + 310 + iowrite32(0, card->addr_pciep + PCI402_PCIEP_OF_BM_ADDR_LO); 311 + iowrite32(0, card->addr_pciep + PCI402_PCIEP_OF_BM_ADDR_HI); 312 + 313 + card->ov.bmfifo.messages = NULL; 314 + card->ov.bmfifo.irq_cnt = NULL; 315 + for (i = 0; i < card->ov.active_cores; i++) { 316 + struct acc_core *core = &card->cores[i]; 317 + 318 + core->bmfifo.messages = NULL; 319 + core->bmfifo.irq_cnt = NULL; 320 + } 321 + 322 + dma_free_coherent(&pdev->dev, PCI402_DMA_SIZE, card->dma_buf, 323 + card->dma_hnd); 324 + card->dma_buf = NULL; 325 + } 326 + 327 + static void pci402_unregister_core(struct acc_core *core) 328 + { 329 + netdev_info(core->netdev, "unregister\n"); 330 + unregister_candev(core->netdev); 331 + 332 + free_candev(core->netdev); 333 + core->netdev = NULL; 334 + } 335 + 336 + static int pci402_init_cores(struct pci_dev *pdev) 337 + { 338 + struct pci402_card *card = pci_get_drvdata(pdev); 339 + int err; 340 + int i; 341 + 342 + for (i = 0; i < card->ov.active_cores; i++) { 343 + struct acc_core *core = &card->cores[i]; 344 + struct acc_net_priv *priv; 345 + struct net_device *netdev; 346 + u32 fifo_config; 347 + 348 + core->addr = card->ov.addr + (i + 1) * PCI402_IO_LEN_CORE; 349 + 350 + fifo_config = acc_read32(core, ACC_CORE_OF_TXFIFO_CONFIG); 351 + core->tx_fifo_size = (fifo_config >> 24); 352 + if (core->tx_fifo_size <= 1) { 353 + pci_err(pdev, "Invalid tx_fifo_size!\n"); 354 + err = -EINVAL; 355 + goto failure; 356 + } 357 + 358 + netdev = alloc_candev(sizeof(*priv), core->tx_fifo_size); 359 + if (!netdev) { 360 + err = -ENOMEM; 361 + goto failure; 362 + } 363 + core->netdev = netdev; 364 + 365 + netdev->flags |= IFF_ECHO; 366 + netdev->dev_port = i; 367 + netdev->netdev_ops = &pci402_acc_netdev_ops; 368 + netdev->ethtool_ops = &pci402_acc_ethtool_ops; 369 + SET_NETDEV_DEV(netdev, &pdev->dev); 370 + 371 + priv = netdev_priv(netdev); 372 + priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 373 + CAN_CTRLMODE_LISTENONLY | 374 + CAN_CTRLMODE_BERR_REPORTING | 375 + CAN_CTRLMODE_CC_LEN8_DLC; 376 + 377 + priv->can.clock.freq = card->ov.core_frequency; 378 + if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD) 379 + priv->can.bittiming_const = &pci402_bittiming_const_canfd; 380 + else 381 + priv->can.bittiming_const = &pci402_bittiming_const; 382 + priv->can.do_set_bittiming = acc_set_bittiming; 383 + priv->can.do_set_mode = acc_set_mode; 384 + priv->can.do_get_berr_counter = acc_get_berr_counter; 385 + 386 + priv->core = core; 387 + priv->ov = &card->ov; 388 + 389 + err = register_candev(netdev); 390 + if (err) { 391 + free_candev(core->netdev); 392 + core->netdev = NULL; 393 + goto failure; 394 + } 395 + 396 + netdev_info(netdev, "registered\n"); 397 + } 398 + 399 + return 0; 400 + 401 + failure: 402 + for (i--; i >= 0; i--) 403 + pci402_unregister_core(&card->cores[i]); 404 + 405 + return err; 406 + } 407 + 408 + static void pci402_finish_cores(struct pci_dev *pdev) 409 + { 410 + struct pci402_card *card = pci_get_drvdata(pdev); 411 + int i; 412 + 413 + for (i = 0; i < card->ov.active_cores; i++) 414 + pci402_unregister_core(&card->cores[i]); 415 + } 416 + 417 + static int pci402_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 418 + { 419 + struct pci402_card *card = NULL; 420 + int err; 421 + 422 + err = pci_enable_device(pdev); 423 + if (err) 424 + return err; 425 + 426 + card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 427 + if (!card) { 428 + err = -ENOMEM; 429 + goto failure_disable_pci; 430 + } 431 + 432 + pci_set_drvdata(pdev, card); 433 + 434 + err = pci_request_regions(pdev, pci_name(pdev)); 435 + if (err) 436 + goto failure_disable_pci; 437 + 438 + card->addr = pci_iomap(pdev, PCI402_BAR, PCI402_IO_LEN_TOTAL); 439 + if (!card->addr) { 440 + err = -ENOMEM; 441 + goto failure_release_regions; 442 + } 443 + 444 + err = pci402_init_card(pdev); 445 + if (err) 446 + goto failure_unmap; 447 + 448 + err = pci402_init_dma(pdev); 449 + if (err) 450 + goto failure_unmap; 451 + 452 + err = pci402_init_interrupt(pdev); 453 + if (err) 454 + goto failure_finish_dma; 455 + 456 + err = pci402_init_cores(pdev); 457 + if (err) 458 + goto failure_finish_interrupt; 459 + 460 + return 0; 461 + 462 + failure_finish_interrupt: 463 + pci402_finish_interrupt(pdev); 464 + 465 + failure_finish_dma: 466 + pci402_finish_dma(pdev); 467 + 468 + failure_unmap: 469 + pci_iounmap(pdev, card->addr); 470 + 471 + failure_release_regions: 472 + pci_release_regions(pdev); 473 + 474 + failure_disable_pci: 475 + pci_disable_device(pdev); 476 + 477 + return err; 478 + } 479 + 480 + static void pci402_remove(struct pci_dev *pdev) 481 + { 482 + struct pci402_card *card = pci_get_drvdata(pdev); 483 + 484 + pci402_finish_interrupt(pdev); 485 + pci402_finish_cores(pdev); 486 + pci402_finish_dma(pdev); 487 + pci_iounmap(pdev, card->addr); 488 + pci_release_regions(pdev); 489 + pci_disable_device(pdev); 490 + } 491 + 492 + static const struct pci_device_id pci402_tbl[] = { 493 + { 494 + .vendor = PCI_VENDOR_ID_ESDGMBH, 495 + .device = ESD_PCI_DEVICE_ID_PCIE402, 496 + .subvendor = PCI_VENDOR_ID_ESDGMBH, 497 + .subdevice = PCI_ANY_ID, 498 + }, 499 + { 0, } 500 + }; 501 + MODULE_DEVICE_TABLE(pci, pci402_tbl); 502 + 503 + static struct pci_driver pci402_driver = { 504 + .name = KBUILD_MODNAME, 505 + .id_table = pci402_tbl, 506 + .probe = pci402_probe, 507 + .remove = pci402_remove, 508 + }; 509 + module_pci_driver(pci402_driver); 510 + 511 + MODULE_DESCRIPTION("Socket-CAN driver for esd CAN 402 card family with esdACC core on PCIe"); 512 + MODULE_AUTHOR("Thomas Körper <socketcan@esd.eu>"); 513 + MODULE_AUTHOR("Stefan Mätje <stefan.maetje@esd.eu>"); 514 + MODULE_LICENSE("GPL");

+764

drivers/net/can/esd/esdacc.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh 3 + * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh 4 + */ 5 + 6 + #include "esdacc.h" 7 + 8 + #include <linux/bitfield.h> 9 + #include <linux/delay.h> 10 + #include <linux/io.h> 11 + #include <linux/ktime.h> 12 + 13 + /* esdACC ID register layout */ 14 + #define ACC_ID_ID_MASK GENMASK(28, 0) 15 + #define ACC_ID_EFF_FLAG BIT(29) 16 + 17 + /* esdACC DLC register layout */ 18 + #define ACC_DLC_DLC_MASK GENMASK(3, 0) 19 + #define ACC_DLC_RTR_FLAG BIT(4) 20 + #define ACC_DLC_TXD_FLAG BIT(5) 21 + 22 + /* ecc value of esdACC equals SJA1000's ECC register */ 23 + #define ACC_ECC_SEG 0x1f 24 + #define ACC_ECC_DIR 0x20 25 + #define ACC_ECC_BIT 0x00 26 + #define ACC_ECC_FORM 0x40 27 + #define ACC_ECC_STUFF 0x80 28 + #define ACC_ECC_MASK 0xc0 29 + 30 + /* esdACC Status Register bits. Unused bits not documented. */ 31 + #define ACC_REG_STATUS_MASK_STATUS_ES BIT(17) 32 + #define ACC_REG_STATUS_MASK_STATUS_EP BIT(18) 33 + #define ACC_REG_STATUS_MASK_STATUS_BS BIT(19) 34 + 35 + /* esdACC Overview Module BM_IRQ_Mask register related defines */ 36 + /* Two bit wide command masks to mask or unmask a single core IRQ */ 37 + #define ACC_BM_IRQ_UNMASK BIT(0) 38 + #define ACC_BM_IRQ_MASK (ACC_BM_IRQ_UNMASK << 1) 39 + /* Command to unmask all IRQ sources. Created by shifting 40 + * and oring the two bit wide ACC_BM_IRQ_UNMASK 16 times. 41 + */ 42 + #define ACC_BM_IRQ_UNMASK_ALL 0x55555555U 43 + 44 + static void acc_resetmode_enter(struct acc_core *core) 45 + { 46 + acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, 47 + ACC_REG_CONTROL_MASK_MODE_RESETMODE); 48 + 49 + /* Read back reset mode bit to flush PCI write posting */ 50 + acc_resetmode_entered(core); 51 + } 52 + 53 + static void acc_resetmode_leave(struct acc_core *core) 54 + { 55 + acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE, 56 + ACC_REG_CONTROL_MASK_MODE_RESETMODE); 57 + 58 + /* Read back reset mode bit to flush PCI write posting */ 59 + acc_resetmode_entered(core); 60 + } 61 + 62 + static void acc_txq_put(struct acc_core *core, u32 acc_id, u8 acc_dlc, 63 + const void *data) 64 + { 65 + acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1, 66 + *((const u32 *)(data + 4))); 67 + acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_0, 68 + *((const u32 *)data)); 69 + acc_write32(core, ACC_CORE_OF_TXFIFO_DLC, acc_dlc); 70 + /* CAN id must be written at last. This write starts TX. */ 71 + acc_write32(core, ACC_CORE_OF_TXFIFO_ID, acc_id); 72 + } 73 + 74 + static u8 acc_tx_fifo_next(struct acc_core *core, u8 tx_fifo_idx) 75 + { 76 + ++tx_fifo_idx; 77 + if (tx_fifo_idx >= core->tx_fifo_size) 78 + tx_fifo_idx = 0U; 79 + return tx_fifo_idx; 80 + } 81 + 82 + /* Convert timestamp from esdACC time stamp ticks to ns 83 + * 84 + * The conversion factor ts2ns from time stamp counts to ns is basically 85 + * ts2ns = NSEC_PER_SEC / timestamp_frequency 86 + * 87 + * We handle here only a fixed timestamp frequency of 80MHz. The 88 + * resulting ts2ns factor would be 12.5. 89 + * 90 + * At the end we multiply by 12 and add the half of the HW timestamp 91 + * to get a multiplication by 12.5. This way any overflow is 92 + * avoided until ktime_t itself overflows. 93 + */ 94 + #define ACC_TS_FACTOR (NSEC_PER_SEC / ACC_TS_FREQ_80MHZ) 95 + #define ACC_TS_80MHZ_SHIFT 1 96 + 97 + static ktime_t acc_ts2ktime(struct acc_ov *ov, u64 ts) 98 + { 99 + u64 ns; 100 + 101 + ns = (ts * ACC_TS_FACTOR) + (ts >> ACC_TS_80MHZ_SHIFT); 102 + 103 + return ns_to_ktime(ns); 104 + } 105 + 106 + #undef ACC_TS_FACTOR 107 + #undef ACC_TS_80MHZ_SHIFT 108 + 109 + void acc_init_ov(struct acc_ov *ov, struct device *dev) 110 + { 111 + u32 temp; 112 + 113 + temp = acc_ov_read32(ov, ACC_OV_OF_VERSION); 114 + ov->version = temp; 115 + ov->features = (temp >> 16); 116 + 117 + temp = acc_ov_read32(ov, ACC_OV_OF_INFO); 118 + ov->total_cores = temp; 119 + ov->active_cores = (temp >> 8); 120 + 121 + ov->core_frequency = acc_ov_read32(ov, ACC_OV_OF_CANCORE_FREQ); 122 + ov->timestamp_frequency = acc_ov_read32(ov, ACC_OV_OF_TS_FREQ_LO); 123 + 124 + /* Depending on esdACC feature NEW_PSC enable the new prescaler 125 + * or adjust core_frequency according to the implicit division by 2. 126 + */ 127 + if (ov->features & ACC_OV_REG_FEAT_MASK_NEW_PSC) { 128 + acc_ov_set_bits(ov, ACC_OV_OF_MODE, 129 + ACC_OV_REG_MODE_MASK_NEW_PSC_ENABLE); 130 + } else { 131 + ov->core_frequency /= 2; 132 + } 133 + 134 + dev_dbg(dev, 135 + "esdACC v%u, freq: %u/%u, feat/strap: 0x%x/0x%x, cores: %u/%u\n", 136 + ov->version, ov->core_frequency, ov->timestamp_frequency, 137 + ov->features, acc_ov_read32(ov, ACC_OV_OF_INFO) >> 16, 138 + ov->active_cores, ov->total_cores); 139 + } 140 + 141 + void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores, const void *mem) 142 + { 143 + unsigned int u; 144 + 145 + /* DMA buffer layout as follows where N is the number of CAN cores 146 + * implemented in the FPGA, i.e. N = ov->total_cores 147 + * 148 + * Section Layout Section size 149 + * ---------------------------------------------- 150 + * FIFO Card/Overview ACC_CORE_DMABUF_SIZE 151 + * FIFO Core0 ACC_CORE_DMABUF_SIZE 152 + * ... ... 153 + * FIFO CoreN ACC_CORE_DMABUF_SIZE 154 + * irq_cnt Card/Overview sizeof(u32) 155 + * irq_cnt Core0 sizeof(u32) 156 + * ... ... 157 + * irq_cnt CoreN sizeof(u32) 158 + */ 159 + ov->bmfifo.messages = mem; 160 + ov->bmfifo.irq_cnt = mem + (ov->total_cores + 1U) * ACC_CORE_DMABUF_SIZE; 161 + 162 + for (u = 0U; u < ov->active_cores; u++) { 163 + struct acc_core *core = &cores[u]; 164 + 165 + core->bmfifo.messages = mem + (u + 1U) * ACC_CORE_DMABUF_SIZE; 166 + core->bmfifo.irq_cnt = ov->bmfifo.irq_cnt + (u + 1U); 167 + } 168 + } 169 + 170 + int acc_open(struct net_device *netdev) 171 + { 172 + struct acc_net_priv *priv = netdev_priv(netdev); 173 + struct acc_core *core = priv->core; 174 + u32 tx_fifo_status; 175 + u32 ctrl_mode; 176 + int err; 177 + 178 + /* Retry to enter RESET mode if out of sync. */ 179 + if (priv->can.state != CAN_STATE_STOPPED) { 180 + netdev_warn(netdev, "Entered %s() with bad can.state: %s\n", 181 + __func__, can_get_state_str(priv->can.state)); 182 + acc_resetmode_enter(core); 183 + priv->can.state = CAN_STATE_STOPPED; 184 + } 185 + 186 + err = open_candev(netdev); 187 + if (err) 188 + return err; 189 + 190 + ctrl_mode = ACC_REG_CONTROL_MASK_IE_RXTX | 191 + ACC_REG_CONTROL_MASK_IE_TXERROR | 192 + ACC_REG_CONTROL_MASK_IE_ERRWARN | 193 + ACC_REG_CONTROL_MASK_IE_OVERRUN | 194 + ACC_REG_CONTROL_MASK_IE_ERRPASS; 195 + 196 + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 197 + ctrl_mode |= ACC_REG_CONTROL_MASK_IE_BUSERR; 198 + 199 + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 200 + ctrl_mode |= ACC_REG_CONTROL_MASK_MODE_LOM; 201 + 202 + acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, ctrl_mode); 203 + 204 + acc_resetmode_leave(core); 205 + priv->can.state = CAN_STATE_ERROR_ACTIVE; 206 + 207 + /* Resync TX FIFO indices to HW state after (re-)start. */ 208 + tx_fifo_status = acc_read32(core, ACC_CORE_OF_TXFIFO_STATUS); 209 + core->tx_fifo_head = tx_fifo_status & 0xff; 210 + core->tx_fifo_tail = (tx_fifo_status >> 8) & 0xff; 211 + 212 + netif_start_queue(netdev); 213 + return 0; 214 + } 215 + 216 + int acc_close(struct net_device *netdev) 217 + { 218 + struct acc_net_priv *priv = netdev_priv(netdev); 219 + struct acc_core *core = priv->core; 220 + 221 + acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE, 222 + ACC_REG_CONTROL_MASK_IE_RXTX | 223 + ACC_REG_CONTROL_MASK_IE_TXERROR | 224 + ACC_REG_CONTROL_MASK_IE_ERRWARN | 225 + ACC_REG_CONTROL_MASK_IE_OVERRUN | 226 + ACC_REG_CONTROL_MASK_IE_ERRPASS | 227 + ACC_REG_CONTROL_MASK_IE_BUSERR); 228 + 229 + netif_stop_queue(netdev); 230 + acc_resetmode_enter(core); 231 + priv->can.state = CAN_STATE_STOPPED; 232 + 233 + /* Mark pending TX requests to be aborted after controller restart. */ 234 + acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff); 235 + 236 + /* ACC_REG_CONTROL_MASK_MODE_LOM is only accessible in RESET mode */ 237 + acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE, 238 + ACC_REG_CONTROL_MASK_MODE_LOM); 239 + 240 + close_candev(netdev); 241 + return 0; 242 + } 243 + 244 + netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) 245 + { 246 + struct acc_net_priv *priv = netdev_priv(netdev); 247 + struct acc_core *core = priv->core; 248 + struct can_frame *cf = (struct can_frame *)skb->data; 249 + u8 tx_fifo_head = core->tx_fifo_head; 250 + int fifo_usage; 251 + u32 acc_id; 252 + u8 acc_dlc; 253 + 254 + if (can_dropped_invalid_skb(netdev, skb)) 255 + return NETDEV_TX_OK; 256 + 257 + /* Access core->tx_fifo_tail only once because it may be changed 258 + * from the interrupt level. 259 + */ 260 + fifo_usage = tx_fifo_head - core->tx_fifo_tail; 261 + if (fifo_usage < 0) 262 + fifo_usage += core->tx_fifo_size; 263 + 264 + if (fifo_usage >= core->tx_fifo_size - 1) { 265 + netdev_err(core->netdev, 266 + "BUG: TX ring full when queue awake!\n"); 267 + netif_stop_queue(netdev); 268 + return NETDEV_TX_BUSY; 269 + } 270 + 271 + if (fifo_usage == core->tx_fifo_size - 2) 272 + netif_stop_queue(netdev); 273 + 274 + acc_dlc = can_get_cc_dlc(cf, priv->can.ctrlmode); 275 + if (cf->can_id & CAN_RTR_FLAG) 276 + acc_dlc |= ACC_DLC_RTR_FLAG; 277 + 278 + if (cf->can_id & CAN_EFF_FLAG) { 279 + acc_id = cf->can_id & CAN_EFF_MASK; 280 + acc_id |= ACC_ID_EFF_FLAG; 281 + } else { 282 + acc_id = cf->can_id & CAN_SFF_MASK; 283 + } 284 + 285 + can_put_echo_skb(skb, netdev, core->tx_fifo_head, 0); 286 + 287 + core->tx_fifo_head = acc_tx_fifo_next(core, tx_fifo_head); 288 + 289 + acc_txq_put(core, acc_id, acc_dlc, cf->data); 290 + 291 + return NETDEV_TX_OK; 292 + } 293 + 294 + int acc_get_berr_counter(const struct net_device *netdev, 295 + struct can_berr_counter *bec) 296 + { 297 + struct acc_net_priv *priv = netdev_priv(netdev); 298 + u32 core_status = acc_read32(priv->core, ACC_CORE_OF_STATUS); 299 + 300 + bec->txerr = (core_status >> 8) & 0xff; 301 + bec->rxerr = core_status & 0xff; 302 + 303 + return 0; 304 + } 305 + 306 + int acc_set_mode(struct net_device *netdev, enum can_mode mode) 307 + { 308 + struct acc_net_priv *priv = netdev_priv(netdev); 309 + 310 + switch (mode) { 311 + case CAN_MODE_START: 312 + /* Paranoid FIFO index check. */ 313 + { 314 + const u32 tx_fifo_status = 315 + acc_read32(priv->core, ACC_CORE_OF_TXFIFO_STATUS); 316 + const u8 hw_fifo_head = tx_fifo_status; 317 + 318 + if (hw_fifo_head != priv->core->tx_fifo_head || 319 + hw_fifo_head != priv->core->tx_fifo_tail) { 320 + netdev_warn(netdev, 321 + "TX FIFO mismatch: T %2u H %2u; TFHW %#08x\n", 322 + priv->core->tx_fifo_tail, 323 + priv->core->tx_fifo_head, 324 + tx_fifo_status); 325 + } 326 + } 327 + acc_resetmode_leave(priv->core); 328 + /* To leave the bus-off state the esdACC controller begins 329 + * here a grace period where it counts 128 "idle conditions" (each 330 + * of 11 consecutive recessive bits) on the bus as required 331 + * by the CAN spec. 332 + * 333 + * During this time the TX FIFO may still contain already 334 + * aborted "zombie" frames that are only drained from the FIFO 335 + * at the end of the grace period. 336 + * 337 + * To not to interfere with this drain process we don't 338 + * call netif_wake_queue() here. When the controller reaches 339 + * the error-active state again, it informs us about that 340 + * with an acc_bmmsg_errstatechange message. Then 341 + * netif_wake_queue() is called from 342 + * handle_core_msg_errstatechange() instead. 343 + */ 344 + break; 345 + 346 + default: 347 + return -EOPNOTSUPP; 348 + } 349 + 350 + return 0; 351 + } 352 + 353 + int acc_set_bittiming(struct net_device *netdev) 354 + { 355 + struct acc_net_priv *priv = netdev_priv(netdev); 356 + const struct can_bittiming *bt = &priv->can.bittiming; 357 + u32 brp; 358 + u32 btr; 359 + 360 + if (priv->ov->features & ACC_OV_REG_FEAT_MASK_CANFD) { 361 + u32 fbtr = 0; 362 + 363 + netdev_dbg(netdev, "bit timing: brp %u, prop %u, ph1 %u ph2 %u, sjw %u\n", 364 + bt->brp, bt->prop_seg, 365 + bt->phase_seg1, bt->phase_seg2, bt->sjw); 366 + 367 + brp = FIELD_PREP(ACC_REG_BRP_FD_MASK_BRP, bt->brp - 1); 368 + 369 + btr = FIELD_PREP(ACC_REG_BTR_FD_MASK_TSEG1, bt->phase_seg1 + bt->prop_seg - 1); 370 + btr |= FIELD_PREP(ACC_REG_BTR_FD_MASK_TSEG2, bt->phase_seg2 - 1); 371 + btr |= FIELD_PREP(ACC_REG_BTR_FD_MASK_SJW, bt->sjw - 1); 372 + 373 + /* Keep order of accesses to ACC_CORE_OF_BRP and ACC_CORE_OF_BTR. */ 374 + acc_write32(priv->core, ACC_CORE_OF_BRP, brp); 375 + acc_write32(priv->core, ACC_CORE_OF_BTR, btr); 376 + 377 + netdev_dbg(netdev, "esdACC: BRP %u, NBTR 0x%08x, DBTR 0x%08x", 378 + brp, btr, fbtr); 379 + } else { 380 + netdev_dbg(netdev, "bit timing: brp %u, prop %u, ph1 %u ph2 %u, sjw %u\n", 381 + bt->brp, bt->prop_seg, 382 + bt->phase_seg1, bt->phase_seg2, bt->sjw); 383 + 384 + brp = FIELD_PREP(ACC_REG_BRP_CL_MASK_BRP, bt->brp - 1); 385 + 386 + btr = FIELD_PREP(ACC_REG_BTR_CL_MASK_TSEG1, bt->phase_seg1 + bt->prop_seg - 1); 387 + btr |= FIELD_PREP(ACC_REG_BTR_CL_MASK_TSEG2, bt->phase_seg2 - 1); 388 + btr |= FIELD_PREP(ACC_REG_BTR_CL_MASK_SJW, bt->sjw - 1); 389 + 390 + /* Keep order of accesses to ACC_CORE_OF_BRP and ACC_CORE_OF_BTR. */ 391 + acc_write32(priv->core, ACC_CORE_OF_BRP, brp); 392 + acc_write32(priv->core, ACC_CORE_OF_BTR, btr); 393 + 394 + netdev_dbg(netdev, "esdACC: BRP %u, BTR 0x%08x", brp, btr); 395 + } 396 + 397 + return 0; 398 + } 399 + 400 + static void handle_core_msg_rxtxdone(struct acc_core *core, 401 + const struct acc_bmmsg_rxtxdone *msg) 402 + { 403 + struct acc_net_priv *priv = netdev_priv(core->netdev); 404 + struct net_device_stats *stats = &core->netdev->stats; 405 + struct sk_buff *skb; 406 + 407 + if (msg->acc_dlc.len & ACC_DLC_TXD_FLAG) { 408 + u8 tx_fifo_tail = core->tx_fifo_tail; 409 + 410 + if (core->tx_fifo_head == tx_fifo_tail) { 411 + netdev_warn(core->netdev, 412 + "TX interrupt, but queue is empty!?\n"); 413 + return; 414 + } 415 + 416 + /* Direct access echo skb to attach HW time stamp. */ 417 + skb = priv->can.echo_skb[tx_fifo_tail]; 418 + if (skb) { 419 + skb_hwtstamps(skb)->hwtstamp = 420 + acc_ts2ktime(priv->ov, msg->ts); 421 + } 422 + 423 + stats->tx_packets++; 424 + stats->tx_bytes += can_get_echo_skb(core->netdev, tx_fifo_tail, 425 + NULL); 426 + 427 + core->tx_fifo_tail = acc_tx_fifo_next(core, tx_fifo_tail); 428 + 429 + netif_wake_queue(core->netdev); 430 + 431 + } else { 432 + struct can_frame *cf; 433 + 434 + skb = alloc_can_skb(core->netdev, &cf); 435 + if (!skb) { 436 + stats->rx_dropped++; 437 + return; 438 + } 439 + 440 + cf->can_id = msg->id & ACC_ID_ID_MASK; 441 + if (msg->id & ACC_ID_EFF_FLAG) 442 + cf->can_id |= CAN_EFF_FLAG; 443 + 444 + can_frame_set_cc_len(cf, msg->acc_dlc.len & ACC_DLC_DLC_MASK, 445 + priv->can.ctrlmode); 446 + 447 + if (msg->acc_dlc.len & ACC_DLC_RTR_FLAG) { 448 + cf->can_id |= CAN_RTR_FLAG; 449 + } else { 450 + memcpy(cf->data, msg->data, cf->len); 451 + stats->rx_bytes += cf->len; 452 + } 453 + stats->rx_packets++; 454 + 455 + skb_hwtstamps(skb)->hwtstamp = acc_ts2ktime(priv->ov, msg->ts); 456 + 457 + netif_rx(skb); 458 + } 459 + } 460 + 461 + static void handle_core_msg_txabort(struct acc_core *core, 462 + const struct acc_bmmsg_txabort *msg) 463 + { 464 + struct net_device_stats *stats = &core->netdev->stats; 465 + u8 tx_fifo_tail = core->tx_fifo_tail; 466 + u32 abort_mask = msg->abort_mask; /* u32 extend to avoid warnings later */ 467 + 468 + /* The abort_mask shows which frames were aborted in esdACC's FIFO. */ 469 + while (tx_fifo_tail != core->tx_fifo_head && (abort_mask)) { 470 + const u32 tail_mask = (1U << tx_fifo_tail); 471 + 472 + if (!(abort_mask & tail_mask)) 473 + break; 474 + abort_mask &= ~tail_mask; 475 + 476 + can_free_echo_skb(core->netdev, tx_fifo_tail, NULL); 477 + stats->tx_dropped++; 478 + stats->tx_aborted_errors++; 479 + 480 + tx_fifo_tail = acc_tx_fifo_next(core, tx_fifo_tail); 481 + } 482 + core->tx_fifo_tail = tx_fifo_tail; 483 + if (abort_mask) 484 + netdev_warn(core->netdev, "Unhandled aborted messages\n"); 485 + 486 + if (!acc_resetmode_entered(core)) 487 + netif_wake_queue(core->netdev); 488 + } 489 + 490 + static void handle_core_msg_overrun(struct acc_core *core, 491 + const struct acc_bmmsg_overrun *msg) 492 + { 493 + struct acc_net_priv *priv = netdev_priv(core->netdev); 494 + struct net_device_stats *stats = &core->netdev->stats; 495 + struct can_frame *cf; 496 + struct sk_buff *skb; 497 + 498 + /* lost_cnt may be 0 if not supported by esdACC version */ 499 + if (msg->lost_cnt) { 500 + stats->rx_errors += msg->lost_cnt; 501 + stats->rx_over_errors += msg->lost_cnt; 502 + } else { 503 + stats->rx_errors++; 504 + stats->rx_over_errors++; 505 + } 506 + 507 + skb = alloc_can_err_skb(core->netdev, &cf); 508 + if (!skb) 509 + return; 510 + 511 + cf->can_id |= CAN_ERR_CRTL; 512 + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 513 + 514 + skb_hwtstamps(skb)->hwtstamp = acc_ts2ktime(priv->ov, msg->ts); 515 + 516 + netif_rx(skb); 517 + } 518 + 519 + static void handle_core_msg_buserr(struct acc_core *core, 520 + const struct acc_bmmsg_buserr *msg) 521 + { 522 + struct acc_net_priv *priv = netdev_priv(core->netdev); 523 + struct net_device_stats *stats = &core->netdev->stats; 524 + struct can_frame *cf; 525 + struct sk_buff *skb; 526 + const u32 reg_status = msg->reg_status; 527 + const u8 rxerr = reg_status; 528 + const u8 txerr = (reg_status >> 8); 529 + u8 can_err_prot_type = 0U; 530 + 531 + priv->can.can_stats.bus_error++; 532 + 533 + /* Error occurred during transmission? */ 534 + if (msg->ecc & ACC_ECC_DIR) { 535 + stats->rx_errors++; 536 + } else { 537 + can_err_prot_type |= CAN_ERR_PROT_TX; 538 + stats->tx_errors++; 539 + } 540 + /* Determine error type */ 541 + switch (msg->ecc & ACC_ECC_MASK) { 542 + case ACC_ECC_BIT: 543 + can_err_prot_type |= CAN_ERR_PROT_BIT; 544 + break; 545 + case ACC_ECC_FORM: 546 + can_err_prot_type |= CAN_ERR_PROT_FORM; 547 + break; 548 + case ACC_ECC_STUFF: 549 + can_err_prot_type |= CAN_ERR_PROT_STUFF; 550 + break; 551 + default: 552 + can_err_prot_type |= CAN_ERR_PROT_UNSPEC; 553 + break; 554 + } 555 + 556 + skb = alloc_can_err_skb(core->netdev, &cf); 557 + if (!skb) 558 + return; 559 + 560 + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR | CAN_ERR_CNT; 561 + 562 + /* Set protocol error type */ 563 + cf->data[2] = can_err_prot_type; 564 + /* Set error location */ 565 + cf->data[3] = msg->ecc & ACC_ECC_SEG; 566 + 567 + /* Insert CAN TX and RX error counters. */ 568 + cf->data[6] = txerr; 569 + cf->data[7] = rxerr; 570 + 571 + skb_hwtstamps(skb)->hwtstamp = acc_ts2ktime(priv->ov, msg->ts); 572 + 573 + netif_rx(skb); 574 + } 575 + 576 + static void 577 + handle_core_msg_errstatechange(struct acc_core *core, 578 + const struct acc_bmmsg_errstatechange *msg) 579 + { 580 + struct acc_net_priv *priv = netdev_priv(core->netdev); 581 + struct can_frame *cf = NULL; 582 + struct sk_buff *skb; 583 + const u32 reg_status = msg->reg_status; 584 + const u8 rxerr = reg_status; 585 + const u8 txerr = (reg_status >> 8); 586 + enum can_state new_state; 587 + 588 + if (reg_status & ACC_REG_STATUS_MASK_STATUS_BS) { 589 + new_state = CAN_STATE_BUS_OFF; 590 + } else if (reg_status & ACC_REG_STATUS_MASK_STATUS_EP) { 591 + new_state = CAN_STATE_ERROR_PASSIVE; 592 + } else if (reg_status & ACC_REG_STATUS_MASK_STATUS_ES) { 593 + new_state = CAN_STATE_ERROR_WARNING; 594 + } else { 595 + new_state = CAN_STATE_ERROR_ACTIVE; 596 + if (priv->can.state == CAN_STATE_BUS_OFF) { 597 + /* See comment in acc_set_mode() for CAN_MODE_START */ 598 + netif_wake_queue(core->netdev); 599 + } 600 + } 601 + 602 + skb = alloc_can_err_skb(core->netdev, &cf); 603 + 604 + if (new_state != priv->can.state) { 605 + enum can_state tx_state, rx_state; 606 + 607 + tx_state = (txerr >= rxerr) ? 608 + new_state : CAN_STATE_ERROR_ACTIVE; 609 + rx_state = (rxerr >= txerr) ? 610 + new_state : CAN_STATE_ERROR_ACTIVE; 611 + 612 + /* Always call can_change_state() to update the state 613 + * even if alloc_can_err_skb() may have failed. 614 + * can_change_state() can cope with a NULL cf pointer. 615 + */ 616 + can_change_state(core->netdev, cf, tx_state, rx_state); 617 + } 618 + 619 + if (skb) { 620 + cf->can_id |= CAN_ERR_CNT; 621 + cf->data[6] = txerr; 622 + cf->data[7] = rxerr; 623 + 624 + skb_hwtstamps(skb)->hwtstamp = acc_ts2ktime(priv->ov, msg->ts); 625 + 626 + netif_rx(skb); 627 + } 628 + 629 + if (new_state == CAN_STATE_BUS_OFF) { 630 + acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff); 631 + can_bus_off(core->netdev); 632 + } 633 + } 634 + 635 + static void handle_core_interrupt(struct acc_core *core) 636 + { 637 + u32 msg_fifo_head = core->bmfifo.local_irq_cnt & 0xff; 638 + 639 + while (core->bmfifo.msg_fifo_tail != msg_fifo_head) { 640 + const union acc_bmmsg *msg = 641 + &core->bmfifo.messages[core->bmfifo.msg_fifo_tail]; 642 + 643 + switch (msg->msg_id) { 644 + case BM_MSG_ID_RXTXDONE: 645 + handle_core_msg_rxtxdone(core, &msg->rxtxdone); 646 + break; 647 + 648 + case BM_MSG_ID_TXABORT: 649 + handle_core_msg_txabort(core, &msg->txabort); 650 + break; 651 + 652 + case BM_MSG_ID_OVERRUN: 653 + handle_core_msg_overrun(core, &msg->overrun); 654 + break; 655 + 656 + case BM_MSG_ID_BUSERR: 657 + handle_core_msg_buserr(core, &msg->buserr); 658 + break; 659 + 660 + case BM_MSG_ID_ERRPASSIVE: 661 + case BM_MSG_ID_ERRWARN: 662 + handle_core_msg_errstatechange(core, 663 + &msg->errstatechange); 664 + break; 665 + 666 + default: 667 + /* Ignore all other BM messages (like the CAN-FD messages) */ 668 + break; 669 + } 670 + 671 + core->bmfifo.msg_fifo_tail = 672 + (core->bmfifo.msg_fifo_tail + 1) & 0xff; 673 + } 674 + } 675 + 676 + /** 677 + * acc_card_interrupt() - handle the interrupts of an esdACC FPGA 678 + * 679 + * @ov: overview module structure 680 + * @cores: array of core structures 681 + * 682 + * This function handles all interrupts pending for the overview module and the 683 + * CAN cores of the esdACC FPGA. 684 + * 685 + * It examines for all cores (the overview module core and the CAN cores) 686 + * the bmfifo.irq_cnt and compares it with the previously saved 687 + * bmfifo.local_irq_cnt. An IRQ is pending if they differ. The esdACC FPGA 688 + * updates the bmfifo.irq_cnt values by DMA. 689 + * 690 + * The pending interrupts are masked by writing to the IRQ mask register at 691 + * ACC_OV_OF_BM_IRQ_MASK. This register has for each core a two bit command 692 + * field evaluated as follows: 693 + * 694 + * Define, bit pattern: meaning 695 + * 00: no action 696 + * ACC_BM_IRQ_UNMASK, 01: unmask interrupt 697 + * ACC_BM_IRQ_MASK, 10: mask interrupt 698 + * 11: no action 699 + * 700 + * For each CAN core with a pending IRQ handle_core_interrupt() handles all 701 + * busmaster messages from the message FIFO. The last handled message (FIFO 702 + * index) is written to the CAN core to acknowledge its handling. 703 + * 704 + * Last step is to unmask all interrupts in the FPGA using 705 + * ACC_BM_IRQ_UNMASK_ALL. 706 + * 707 + * Return: 708 + * IRQ_HANDLED, if card generated an interrupt that was handled 709 + * IRQ_NONE, if the interrupt is not ours 710 + */ 711 + irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores) 712 + { 713 + u32 irqmask; 714 + int i; 715 + 716 + /* First we look for whom interrupts are pending, card/overview 717 + * or any of the cores. Two bits in irqmask are used for each; 718 + * Each two bit field is set to ACC_BM_IRQ_MASK if an IRQ is 719 + * pending. 720 + */ 721 + irqmask = 0U; 722 + if (READ_ONCE(*ov->bmfifo.irq_cnt) != ov->bmfifo.local_irq_cnt) { 723 + irqmask |= ACC_BM_IRQ_MASK; 724 + ov->bmfifo.local_irq_cnt = READ_ONCE(*ov->bmfifo.irq_cnt); 725 + } 726 + 727 + for (i = 0; i < ov->active_cores; i++) { 728 + struct acc_core *core = &cores[i]; 729 + 730 + if (READ_ONCE(*core->bmfifo.irq_cnt) != core->bmfifo.local_irq_cnt) { 731 + irqmask |= (ACC_BM_IRQ_MASK << (2 * (i + 1))); 732 + core->bmfifo.local_irq_cnt = READ_ONCE(*core->bmfifo.irq_cnt); 733 + } 734 + } 735 + 736 + if (!irqmask) 737 + return IRQ_NONE; 738 + 739 + /* At second we tell the card we're working on them by writing irqmask, 740 + * call handle_{ov|core}_interrupt and then acknowledge the 741 + * interrupts by writing irq_cnt: 742 + */ 743 + acc_ov_write32(ov, ACC_OV_OF_BM_IRQ_MASK, irqmask); 744 + 745 + if (irqmask & ACC_BM_IRQ_MASK) { 746 + /* handle_ov_interrupt(); - no use yet. */ 747 + acc_ov_write32(ov, ACC_OV_OF_BM_IRQ_COUNTER, 748 + ov->bmfifo.local_irq_cnt); 749 + } 750 + 751 + for (i = 0; i < ov->active_cores; i++) { 752 + struct acc_core *core = &cores[i]; 753 + 754 + if (irqmask & (ACC_BM_IRQ_MASK << (2 * (i + 1)))) { 755 + handle_core_interrupt(core); 756 + acc_write32(core, ACC_OV_OF_BM_IRQ_COUNTER, 757 + core->bmfifo.local_irq_cnt); 758 + } 759 + } 760 + 761 + acc_ov_write32(ov, ACC_OV_OF_BM_IRQ_MASK, ACC_BM_IRQ_UNMASK_ALL); 762 + 763 + return IRQ_HANDLED; 764 + }

+356

drivers/net/can/esd/esdacc.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh 3 + * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh 4 + */ 5 + 6 + #include <linux/bits.h> 7 + #include <linux/can/dev.h> 8 + #include <linux/kernel.h> 9 + #include <linux/netdevice.h> 10 + #include <linux/units.h> 11 + 12 + #define ACC_TS_FREQ_80MHZ (80 * HZ_PER_MHZ) 13 + #define ACC_I2C_ADDON_DETECT_DELAY_MS 10 14 + 15 + /* esdACC Overview Module */ 16 + #define ACC_OV_OF_PROBE 0x0000 17 + #define ACC_OV_OF_VERSION 0x0004 18 + #define ACC_OV_OF_INFO 0x0008 19 + #define ACC_OV_OF_CANCORE_FREQ 0x000c 20 + #define ACC_OV_OF_TS_FREQ_LO 0x0010 21 + #define ACC_OV_OF_TS_FREQ_HI 0x0014 22 + #define ACC_OV_OF_IRQ_STATUS_CORES 0x0018 23 + #define ACC_OV_OF_TS_CURR_LO 0x001c 24 + #define ACC_OV_OF_TS_CURR_HI 0x0020 25 + #define ACC_OV_OF_IRQ_STATUS 0x0028 26 + #define ACC_OV_OF_MODE 0x002c 27 + #define ACC_OV_OF_BM_IRQ_COUNTER 0x0070 28 + #define ACC_OV_OF_BM_IRQ_MASK 0x0074 29 + #define ACC_OV_OF_MSI_DATA 0x0080 30 + #define ACC_OV_OF_MSI_ADDRESSOFFSET 0x0084 31 + 32 + /* Feature flags are contained in the upper 16 bit of the version 33 + * register at ACC_OV_OF_VERSION but only used with these masks after 34 + * extraction into an extra variable => (xx - 16). 35 + */ 36 + #define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16) 37 + #define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16) 38 + 39 + #define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0) 40 + #define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1) 41 + #define ACC_OV_REG_MODE_MASK_MODE_LED BIT(2) 42 + #define ACC_OV_REG_MODE_MASK_TIMER_ENABLE BIT(4) 43 + #define ACC_OV_REG_MODE_MASK_TIMER_ONE_SHOT BIT(5) 44 + #define ACC_OV_REG_MODE_MASK_TIMER_ABSOLUTE BIT(6) 45 + #define ACC_OV_REG_MODE_MASK_TIMER GENMASK(6, 4) 46 + #define ACC_OV_REG_MODE_MASK_TS_SRC GENMASK(8, 7) 47 + #define ACC_OV_REG_MODE_MASK_I2C_ENABLE BIT(11) 48 + #define ACC_OV_REG_MODE_MASK_MSI_ENABLE BIT(14) 49 + #define ACC_OV_REG_MODE_MASK_NEW_PSC_ENABLE BIT(15) 50 + #define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31) 51 + 52 + /* esdACC CAN Core Module */ 53 + #define ACC_CORE_OF_CTRL_MODE 0x0000 54 + #define ACC_CORE_OF_STATUS_IRQ 0x0008 55 + #define ACC_CORE_OF_BRP 0x000c 56 + #define ACC_CORE_OF_BTR 0x0010 57 + #define ACC_CORE_OF_FBTR 0x0014 58 + #define ACC_CORE_OF_STATUS 0x0030 59 + #define ACC_CORE_OF_TXFIFO_CONFIG 0x0048 60 + #define ACC_CORE_OF_TXFIFO_STATUS 0x004c 61 + #define ACC_CORE_OF_TX_STATUS_IRQ 0x0050 62 + #define ACC_CORE_OF_TX_ABORT_MASK 0x0054 63 + #define ACC_CORE_OF_BM_IRQ_COUNTER 0x0070 64 + #define ACC_CORE_OF_TXFIFO_ID 0x00c0 65 + #define ACC_CORE_OF_TXFIFO_DLC 0x00c4 66 + #define ACC_CORE_OF_TXFIFO_DATA_0 0x00c8 67 + #define ACC_CORE_OF_TXFIFO_DATA_1 0x00cc 68 + 69 + #define ACC_REG_CONTROL_MASK_MODE_RESETMODE BIT(0) 70 + #define ACC_REG_CONTROL_MASK_MODE_LOM BIT(1) 71 + #define ACC_REG_CONTROL_MASK_MODE_STM BIT(2) 72 + #define ACC_REG_CONTROL_MASK_MODE_TRANSEN BIT(5) 73 + #define ACC_REG_CONTROL_MASK_MODE_TS BIT(6) 74 + #define ACC_REG_CONTROL_MASK_MODE_SCHEDULE BIT(7) 75 + 76 + #define ACC_REG_CONTROL_MASK_IE_RXTX BIT(8) 77 + #define ACC_REG_CONTROL_MASK_IE_TXERROR BIT(9) 78 + #define ACC_REG_CONTROL_MASK_IE_ERRWARN BIT(10) 79 + #define ACC_REG_CONTROL_MASK_IE_OVERRUN BIT(11) 80 + #define ACC_REG_CONTROL_MASK_IE_TSI BIT(12) 81 + #define ACC_REG_CONTROL_MASK_IE_ERRPASS BIT(13) 82 + #define ACC_REG_CONTROL_MASK_IE_ALI BIT(14) 83 + #define ACC_REG_CONTROL_MASK_IE_BUSERR BIT(15) 84 + 85 + /* BRP and BTR register layout for CAN-Classic version */ 86 + #define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0) 87 + #define ACC_REG_BTR_CL_MASK_TSEG1 GENMASK(3, 0) 88 + #define ACC_REG_BTR_CL_MASK_TSEG2 GENMASK(18, 16) 89 + #define ACC_REG_BTR_CL_MASK_SJW GENMASK(25, 24) 90 + 91 + /* BRP and BTR register layout for CAN-FD version */ 92 + #define ACC_REG_BRP_FD_MASK_BRP GENMASK(7, 0) 93 + #define ACC_REG_BTR_FD_MASK_TSEG1 GENMASK(7, 0) 94 + #define ACC_REG_BTR_FD_MASK_TSEG2 GENMASK(22, 16) 95 + #define ACC_REG_BTR_FD_MASK_SJW GENMASK(30, 24) 96 + 97 + /* 256 BM_MSGs of 32 byte size */ 98 + #define ACC_CORE_DMAMSG_SIZE 32U 99 + #define ACC_CORE_DMABUF_SIZE (256U * ACC_CORE_DMAMSG_SIZE) 100 + 101 + enum acc_bmmsg_id { 102 + BM_MSG_ID_RXTXDONE = 0x01, 103 + BM_MSG_ID_TXABORT = 0x02, 104 + BM_MSG_ID_OVERRUN = 0x03, 105 + BM_MSG_ID_BUSERR = 0x04, 106 + BM_MSG_ID_ERRPASSIVE = 0x05, 107 + BM_MSG_ID_ERRWARN = 0x06, 108 + BM_MSG_ID_TIMESLICE = 0x07, 109 + BM_MSG_ID_HWTIMER = 0x08, 110 + BM_MSG_ID_HOTPLUG = 0x09, 111 + }; 112 + 113 + /* The struct acc_bmmsg_* structure declarations that follow here provide 114 + * access to the ring buffer of bus master messages maintained by the FPGA 115 + * bus master engine. All bus master messages have the same size of 116 + * ACC_CORE_DMAMSG_SIZE and a minimum alignment of ACC_CORE_DMAMSG_SIZE in 117 + * memory. 118 + * 119 + * All structure members are natural aligned. Therefore we should not need 120 + * a __packed attribute. All struct acc_bmmsg_* declarations have at least 121 + * reserved* members to fill the structure to the full ACC_CORE_DMAMSG_SIZE. 122 + * 123 + * A failure of this property due padding will be detected at compile time 124 + * by static_assert(sizeof(union acc_bmmsg) == ACC_CORE_DMAMSG_SIZE). 125 + */ 126 + 127 + struct acc_bmmsg_rxtxdone { 128 + u8 msg_id; 129 + u8 txfifo_level; 130 + u8 reserved1[2]; 131 + u8 txtsfifo_level; 132 + u8 reserved2[3]; 133 + u32 id; 134 + struct { 135 + u8 len; 136 + u8 txdfifo_idx; 137 + u8 zeroes8; 138 + u8 reserved; 139 + } acc_dlc; 140 + u8 data[CAN_MAX_DLEN]; 141 + /* Time stamps in struct acc_ov::timestamp_frequency ticks. */ 142 + u64 ts; 143 + }; 144 + 145 + struct acc_bmmsg_txabort { 146 + u8 msg_id; 147 + u8 txfifo_level; 148 + u16 abort_mask; 149 + u8 txtsfifo_level; 150 + u8 reserved2[1]; 151 + u16 abort_mask_txts; 152 + u64 ts; 153 + u32 reserved3[4]; 154 + }; 155 + 156 + struct acc_bmmsg_overrun { 157 + u8 msg_id; 158 + u8 txfifo_level; 159 + u8 lost_cnt; 160 + u8 reserved1; 161 + u8 txtsfifo_level; 162 + u8 reserved2[3]; 163 + u64 ts; 164 + u32 reserved3[4]; 165 + }; 166 + 167 + struct acc_bmmsg_buserr { 168 + u8 msg_id; 169 + u8 txfifo_level; 170 + u8 ecc; 171 + u8 reserved1; 172 + u8 txtsfifo_level; 173 + u8 reserved2[3]; 174 + u64 ts; 175 + u32 reg_status; 176 + u32 reg_btr; 177 + u32 reserved3[2]; 178 + }; 179 + 180 + struct acc_bmmsg_errstatechange { 181 + u8 msg_id; 182 + u8 txfifo_level; 183 + u8 reserved1[2]; 184 + u8 txtsfifo_level; 185 + u8 reserved2[3]; 186 + u64 ts; 187 + u32 reg_status; 188 + u32 reserved3[3]; 189 + }; 190 + 191 + struct acc_bmmsg_timeslice { 192 + u8 msg_id; 193 + u8 txfifo_level; 194 + u8 reserved1[2]; 195 + u8 txtsfifo_level; 196 + u8 reserved2[3]; 197 + u64 ts; 198 + u32 reserved3[4]; 199 + }; 200 + 201 + struct acc_bmmsg_hwtimer { 202 + u8 msg_id; 203 + u8 reserved1[3]; 204 + u32 reserved2[1]; 205 + u64 timer; 206 + u32 reserved3[4]; 207 + }; 208 + 209 + struct acc_bmmsg_hotplug { 210 + u8 msg_id; 211 + u8 reserved1[3]; 212 + u32 reserved2[7]; 213 + }; 214 + 215 + union acc_bmmsg { 216 + u8 msg_id; 217 + struct acc_bmmsg_rxtxdone rxtxdone; 218 + struct acc_bmmsg_txabort txabort; 219 + struct acc_bmmsg_overrun overrun; 220 + struct acc_bmmsg_buserr buserr; 221 + struct acc_bmmsg_errstatechange errstatechange; 222 + struct acc_bmmsg_timeslice timeslice; 223 + struct acc_bmmsg_hwtimer hwtimer; 224 + }; 225 + 226 + /* Check size of union acc_bmmsg to be of expected size. */ 227 + static_assert(sizeof(union acc_bmmsg) == ACC_CORE_DMAMSG_SIZE); 228 + 229 + struct acc_bmfifo { 230 + const union acc_bmmsg *messages; 231 + /* irq_cnt points to an u32 value where the esdACC FPGA deposits 232 + * the bm_fifo head index in coherent DMA memory. Only bits 7..0 233 + * are valid. Use READ_ONCE() to access this memory location. 234 + */ 235 + const u32 *irq_cnt; 236 + u32 local_irq_cnt; 237 + u32 msg_fifo_tail; 238 + }; 239 + 240 + struct acc_core { 241 + void __iomem *addr; 242 + struct net_device *netdev; 243 + struct acc_bmfifo bmfifo; 244 + u8 tx_fifo_size; 245 + u8 tx_fifo_head; 246 + u8 tx_fifo_tail; 247 + }; 248 + 249 + struct acc_ov { 250 + void __iomem *addr; 251 + struct acc_bmfifo bmfifo; 252 + u32 timestamp_frequency; 253 + u32 core_frequency; 254 + u16 version; 255 + u16 features; 256 + u8 total_cores; 257 + u8 active_cores; 258 + }; 259 + 260 + struct acc_net_priv { 261 + struct can_priv can; /* must be the first member! */ 262 + struct acc_core *core; 263 + struct acc_ov *ov; 264 + }; 265 + 266 + static inline u32 acc_read32(struct acc_core *core, unsigned short offs) 267 + { 268 + return ioread32be(core->addr + offs); 269 + } 270 + 271 + static inline void acc_write32(struct acc_core *core, 272 + unsigned short offs, u32 v) 273 + { 274 + iowrite32be(v, core->addr + offs); 275 + } 276 + 277 + static inline void acc_write32_noswap(struct acc_core *core, 278 + unsigned short offs, u32 v) 279 + { 280 + iowrite32(v, core->addr + offs); 281 + } 282 + 283 + static inline void acc_set_bits(struct acc_core *core, 284 + unsigned short offs, u32 mask) 285 + { 286 + u32 v = acc_read32(core, offs); 287 + 288 + v |= mask; 289 + acc_write32(core, offs, v); 290 + } 291 + 292 + static inline void acc_clear_bits(struct acc_core *core, 293 + unsigned short offs, u32 mask) 294 + { 295 + u32 v = acc_read32(core, offs); 296 + 297 + v &= ~mask; 298 + acc_write32(core, offs, v); 299 + } 300 + 301 + static inline int acc_resetmode_entered(struct acc_core *core) 302 + { 303 + u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL_MODE); 304 + 305 + return (ctrl & ACC_REG_CONTROL_MASK_MODE_RESETMODE) != 0; 306 + } 307 + 308 + static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs) 309 + { 310 + return ioread32be(ov->addr + offs); 311 + } 312 + 313 + static inline void acc_ov_write32(struct acc_ov *ov, 314 + unsigned short offs, u32 v) 315 + { 316 + iowrite32be(v, ov->addr + offs); 317 + } 318 + 319 + static inline void acc_ov_set_bits(struct acc_ov *ov, 320 + unsigned short offs, u32 b) 321 + { 322 + u32 v = acc_ov_read32(ov, offs); 323 + 324 + v |= b; 325 + acc_ov_write32(ov, offs, v); 326 + } 327 + 328 + static inline void acc_ov_clear_bits(struct acc_ov *ov, 329 + unsigned short offs, u32 b) 330 + { 331 + u32 v = acc_ov_read32(ov, offs); 332 + 333 + v &= ~b; 334 + acc_ov_write32(ov, offs, v); 335 + } 336 + 337 + static inline void acc_reset_fpga(struct acc_ov *ov) 338 + { 339 + acc_ov_write32(ov, ACC_OV_OF_MODE, ACC_OV_REG_MODE_MASK_FPGA_RESET); 340 + 341 + /* (Re-)start and wait for completion of addon detection on the I^2C bus */ 342 + acc_ov_set_bits(ov, ACC_OV_OF_MODE, ACC_OV_REG_MODE_MASK_I2C_ENABLE); 343 + mdelay(ACC_I2C_ADDON_DETECT_DELAY_MS); 344 + } 345 + 346 + void acc_init_ov(struct acc_ov *ov, struct device *dev); 347 + void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores, 348 + const void *mem); 349 + int acc_open(struct net_device *netdev); 350 + int acc_close(struct net_device *netdev); 351 + netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev); 352 + int acc_get_berr_counter(const struct net_device *netdev, 353 + struct can_berr_counter *bec); 354 + int acc_set_mode(struct net_device *netdev, enum can_mode mode); 355 + int acc_set_bittiming(struct net_device *netdev); 356 + irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores);

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