Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"The pending MIPS fixes for 3.19. All across the field and nothing
particularly severe or dramatic"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (23 commits)
IRQCHIP: mips-gic: Avoid rerouting timer IRQs for smp-cmp
MIPS: Fix syscall_get_nr for the syscall exit tracing.
MIPS: elf2ecoff: Ignore PT_MIPS_ABIFLAGS program headers.
MIPS: elf2ecoff: Rewrite main processing loop to switch.
MIPS: fork: Fix MSA/FPU/DSP context duplication race
MIPS: Fix C0_Pagegrain[IEC] support.
MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
MIPS: mipsregs.h: Add write_32bit_cp1_register()
MIPS: Fix kernel lockup or crash after CPU offline/online
MIPS: OCTEON: fix kernel crash when offlining a CPU
MIPS: ARC: Fix build error.
MIPS: IRQ: Fix disable_irq on CPU IRQs
MIPS: smp-mt,smp-cmp: Enable all HW IRQs on secondary CPUs
MIPS: Fix restart of indirect syscalls
MIPS: ELF: fix loading o32 binaries on 64-bit kernels
MIPS: mips-cm: Fix sparse warnings
MIPS: Kconfig: Fix recursive dependency.
MIPS: Compat: Fix build error if CONFIG_MIPS32_COMPAT but no compat ABI.
MIPS: JZ4740: Fixup #include's (sparse)
MIPS: Wire up execveat(2).
...
+186
-111
+10
-13
arch/mips/Kconfig
+10
-13
arch/mips/Kconfig
···
2656
2656
bool
2657
2657
2658
2658
config MIPS32_COMPAT
2659
-
bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
2660
-
depends on 64BIT
2661
-
help
2662
-
Select this option if you want Linux/MIPS 32-bit binary
2663
-
compatibility. Since all software available for Linux/MIPS is
2664
-
currently 32-bit you should say Y here.
2659
+
bool
2665
2660
2666
2661
config COMPAT
2667
2662
bool
2668
-
depends on MIPS32_COMPAT
2669
-
select ARCH_WANT_OLD_COMPAT_IPC
2670
-
default y
2671
2663
2672
2664
config SYSVIPC_COMPAT
2673
2665
bool
2674
-
depends on COMPAT && SYSVIPC
2675
-
default y
2676
2666
2677
2667
config MIPS32_O32
2678
2668
bool "Kernel support for o32 binaries"
2679
-
depends on MIPS32_COMPAT
2669
+
depends on 64BIT
2670
+
select ARCH_WANT_OLD_COMPAT_IPC
2671
+
select COMPAT
2672
+
select MIPS32_COMPAT
2673
+
select SYSVIPC_COMPAT if SYSVIPC
2680
2674
help
2681
2675
Select this option if you want to run o32 binaries. These are pure
2682
2676
32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
···
2680
2686
2681
2687
config MIPS32_N32
2682
2688
bool "Kernel support for n32 binaries"
2683
-
depends on MIPS32_COMPAT
2689
+
depends on 64BIT
2690
+
select COMPAT
2691
+
select MIPS32_COMPAT
2692
+
select SYSVIPC_COMPAT if SYSVIPC
2684
2693
help
2685
2694
Select this option if you want to run n32 binaries. These are
2686
2695
64-bit binaries using 32-bit quantities for addressing and certain
+36
-28
arch/mips/boot/elf2ecoff.c
+36
-28
arch/mips/boot/elf2ecoff.c
···
49
49
/*
50
50
* Some extra ELF definitions
51
51
*/
52
-
#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
52
+
#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
53
+
#define PT_MIPS_ABIFLAGS 0x70000003 /* Records ABI related flags */
53
54
54
55
/* -------------------------------------------------------------------- */
55
56
···
350
349
351
350
for (i = 0; i < ex.e_phnum; i++) {
352
351
/* Section types we can ignore... */
353
-
if (ph[i].p_type == PT_NULL || ph[i].p_type == PT_NOTE ||
354
-
ph[i].p_type == PT_PHDR
355
-
|| ph[i].p_type == PT_MIPS_REGINFO)
352
+
switch (ph[i].p_type) {
353
+
case PT_NULL:
354
+
case PT_NOTE:
355
+
case PT_PHDR:
356
+
case PT_MIPS_REGINFO:
357
+
case PT_MIPS_ABIFLAGS:
356
358
continue;
357
-
/* Section types we can't handle... */
358
-
else if (ph[i].p_type != PT_LOAD) {
359
+
360
+
case PT_LOAD:
361
+
/* Writable (data) segment? */
362
+
if (ph[i].p_flags & PF_W) {
363
+
struct sect ndata, nbss;
364
+
365
+
ndata.vaddr = ph[i].p_vaddr;
366
+
ndata.len = ph[i].p_filesz;
367
+
nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
368
+
nbss.len = ph[i].p_memsz - ph[i].p_filesz;
369
+
370
+
combine(&data, &ndata, 0);
371
+
combine(&bss, &nbss, 1);
372
+
} else {
373
+
struct sect ntxt;
374
+
375
+
ntxt.vaddr = ph[i].p_vaddr;
376
+
ntxt.len = ph[i].p_filesz;
377
+
378
+
combine(&text, &ntxt, 0);
379
+
}
380
+
/* Remember the lowest segment start address. */
381
+
if (ph[i].p_vaddr < cur_vma)
382
+
cur_vma = ph[i].p_vaddr;
383
+
break;
384
+
385
+
default:
386
+
/* Section types we can't handle... */
359
387
fprintf(stderr,
360
388
"Program header %d type %d can't be converted.\n",
361
389
ex.e_phnum, ph[i].p_type);
362
390
exit(1);
363
391
}
364
-
/* Writable (data) segment? */
365
-
if (ph[i].p_flags & PF_W) {
366
-
struct sect ndata, nbss;
367
-
368
-
ndata.vaddr = ph[i].p_vaddr;
369
-
ndata.len = ph[i].p_filesz;
370
-
nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
371
-
nbss.len = ph[i].p_memsz - ph[i].p_filesz;
372
-
373
-
combine(&data, &ndata, 0);
374
-
combine(&bss, &nbss, 1);
375
-
} else {
376
-
struct sect ntxt;
377
-
378
-
ntxt.vaddr = ph[i].p_vaddr;
379
-
ntxt.len = ph[i].p_filesz;
380
-
381
-
combine(&text, &ntxt, 0);
382
-
}
383
-
/* Remember the lowest segment start address. */
384
-
if (ph[i].p_vaddr < cur_vma)
385
-
cur_vma = ph[i].p_vaddr;
386
392
}
387
393
388
394
/* Sections must be in order to be converted... */
-2
arch/mips/cavium-octeon/smp.c
-2
arch/mips/cavium-octeon/smp.c
+4
-12
arch/mips/configs/malta_defconfig
+4
-12
arch/mips/configs/malta_defconfig
···
132
132
CONFIG_IP_NF_MATCH_TTL=m
133
133
CONFIG_IP_NF_FILTER=m
134
134
CONFIG_IP_NF_TARGET_REJECT=m
135
-
CONFIG_IP_NF_TARGET_ULOG=m
136
135
CONFIG_IP_NF_MANGLE=m
137
136
CONFIG_IP_NF_TARGET_CLUSTERIP=m
138
137
CONFIG_IP_NF_TARGET_ECN=m
···
174
175
CONFIG_BRIDGE_EBT_REDIRECT=m
175
176
CONFIG_BRIDGE_EBT_SNAT=m
176
177
CONFIG_BRIDGE_EBT_LOG=m
177
-
CONFIG_BRIDGE_EBT_ULOG=m
178
178
CONFIG_BRIDGE_EBT_NFLOG=m
179
179
CONFIG_IP_SCTP=m
180
180
CONFIG_BRIDGE=m
···
218
220
CONFIG_NET_CLS_IND=y
219
221
CONFIG_CFG80211=m
220
222
CONFIG_MAC80211=m
221
-
CONFIG_MAC80211_RC_PID=y
222
-
CONFIG_MAC80211_RC_DEFAULT_PID=y
223
223
CONFIG_MAC80211_MESH=y
224
224
CONFIG_RFKILL=m
225
225
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
···
244
248
CONFIG_IDE=y
245
249
CONFIG_BLK_DEV_IDECD=y
246
250
CONFIG_IDE_GENERIC=y
247
-
CONFIG_BLK_DEV_GENERIC=y
248
-
CONFIG_BLK_DEV_PIIX=y
249
-
CONFIG_BLK_DEV_IT8213=m
250
-
CONFIG_BLK_DEV_TC86C001=m
251
251
CONFIG_RAID_ATTRS=m
252
-
CONFIG_SCSI=m
253
-
CONFIG_BLK_DEV_SD=m
252
+
CONFIG_BLK_DEV_SD=y
254
253
CONFIG_CHR_DEV_ST=m
255
254
CONFIG_CHR_DEV_OSST=m
256
255
CONFIG_BLK_DEV_SR=m
257
256
CONFIG_BLK_DEV_SR_VENDOR=y
258
257
CONFIG_CHR_DEV_SG=m
259
-
CONFIG_SCSI_MULTI_LUN=y
260
258
CONFIG_SCSI_CONSTANTS=y
261
259
CONFIG_SCSI_LOGGING=y
262
260
CONFIG_SCSI_SCAN_ASYNC=y
···
263
273
CONFIG_SCSI_AIC7XXX=m
264
274
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
265
275
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
276
+
CONFIG_ATA=y
277
+
CONFIG_ATA_PIIX=y
266
278
CONFIG_MD=y
267
279
CONFIG_BLK_DEV_MD=m
268
280
CONFIG_MD_LINEAR=m
···
332
340
CONFIG_UIO_CIF=m
333
341
CONFIG_EXT2_FS=y
334
342
CONFIG_EXT3_FS=y
343
+
CONFIG_EXT4_FS=y
335
344
CONFIG_REISERFS_FS=m
336
345
CONFIG_REISERFS_PROC_INFO=y
337
346
CONFIG_REISERFS_FS_XATTR=y
···
434
441
CONFIG_CRYPTO_TEA=m
435
442
CONFIG_CRYPTO_TWOFISH=m
436
443
# CONFIG_CRYPTO_ANSI_CPRNG is not set
437
-
CONFIG_CRC16=m
+26
-17
arch/mips/include/asm/fpu.h
+26
-17
arch/mips/include/asm/fpu.h
···
64
64
return SIGFPE;
65
65
66
66
/* set FRE */
67
-
write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
67
+
set_c0_config5(MIPS_CONF5_FRE);
68
68
goto fr_common;
69
69
70
70
case FPU_64BIT:
···
74
74
#endif
75
75
/* fall through */
76
76
case FPU_32BIT:
77
-
/* clear FRE */
78
-
write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
77
+
if (cpu_has_fre) {
78
+
/* clear FRE */
79
+
clear_c0_config5(MIPS_CONF5_FRE);
80
+
}
79
81
fr_common:
80
82
/* set CU1 & change FR appropriately */
81
83
fr = (int)mode & FPU_FR_MASK;
···
184
182
int ret = 0;
185
183
186
184
if (cpu_has_fpu) {
185
+
unsigned int config5;
186
+
187
187
ret = __own_fpu();
188
-
if (!ret) {
189
-
unsigned int config5 = read_c0_config5();
188
+
if (ret)
189
+
return ret;
190
190
191
-
/*
192
-
* Ensure FRE is clear whilst running _init_fpu, since
193
-
* single precision FP instructions are used. If FRE
194
-
* was set then we'll just end up initialising all 32
195
-
* 64b registers.
196
-
*/
197
-
write_c0_config5(config5 & ~MIPS_CONF5_FRE);
198
-
enable_fpu_hazard();
199
-
191
+
if (!cpu_has_fre) {
200
192
_init_fpu();
201
193
202
-
/* Restore FRE */
203
-
write_c0_config5(config5);
204
-
enable_fpu_hazard();
194
+
return 0;
205
195
}
196
+
197
+
/*
198
+
* Ensure FRE is clear whilst running _init_fpu, since
199
+
* single precision FP instructions are used. If FRE
200
+
* was set then we'll just end up initialising all 32
201
+
* 64b registers.
202
+
*/
203
+
config5 = clear_c0_config5(MIPS_CONF5_FRE);
204
+
enable_fpu_hazard();
205
+
206
+
_init_fpu();
207
+
208
+
/* Restore FRE */
209
+
write_c0_config5(config5);
210
+
enable_fpu_hazard();
206
211
} else
207
212
fpu_emulator_init_fpu();
208
213
+3
-3
arch/mips/include/asm/fw/arc/hinv.h
+3
-3
arch/mips/include/asm/fw/arc/hinv.h
···
119
119
#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */
120
120
#endif
121
121
122
-
typedef struct component {
122
+
typedef struct {
123
123
CONFIGCLASS Class;
124
124
CONFIGTYPE Type;
125
125
IDENTIFIERFLAG Flags;
···
140
140
};
141
141
142
142
/* System ID */
143
-
typedef struct systemid {
143
+
typedef struct {
144
144
CHAR VendorId[8];
145
145
CHAR ProductId[8];
146
146
} SYSTEMID;
···
166
166
#endif /* _NT_PROM */
167
167
} MEMORYTYPE;
168
168
169
-
typedef struct memorydescriptor {
169
+
typedef struct {
170
170
MEMORYTYPE Type;
171
171
LONG BasePage;
172
172
LONG PageCount;
+2
-2
arch/mips/include/asm/mips-cm.h
+2
-2
arch/mips/include/asm/mips-cm.h
···
89
89
90
90
/* Macros to ease the creation of register access functions */
91
91
#define BUILD_CM_R_(name, off) \
92
-
static inline u32 *addr_gcr_##name(void) \
92
+
static inline u32 __iomem *addr_gcr_##name(void) \
93
93
{ \
94
-
return (u32 *)(mips_cm_base + (off)); \
94
+
return (u32 __iomem *)(mips_cm_base + (off)); \
95
95
} \
96
96
\
97
97
static inline u32 read_gcr_##name(void) \
+15
arch/mips/include/asm/mipsregs.h
+15
arch/mips/include/asm/mipsregs.h
···
1386
1386
__res; \
1387
1387
})
1388
1388
1389
+
#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1390
+
do { \
1391
+
__asm__ __volatile__( \
1392
+
" .set push \n" \
1393
+
" .set reorder \n" \
1394
+
" "STR(gas_hardfloat)" \n" \
1395
+
" ctc1 %0,"STR(dest)" \n" \
1396
+
" .set pop \n" \
1397
+
: : "r" (val)); \
1398
+
} while (0)
1399
+
1389
1400
#ifdef GAS_HAS_SET_HARDFLOAT
1390
1401
#define read_32bit_cp1_register(source) \
1391
1402
_read_32bit_cp1_register(source, .set hardfloat)
1403
+
#define write_32bit_cp1_register(dest, val) \
1404
+
_write_32bit_cp1_register(dest, val, .set hardfloat)
1392
1405
#else
1393
1406
#define read_32bit_cp1_register(source) \
1394
1407
_read_32bit_cp1_register(source, )
1408
+
#define write_32bit_cp1_register(dest, val) \
1409
+
_write_32bit_cp1_register(dest, val, )
1395
1410
#endif
1396
1411
1397
1412
#ifdef HAVE_AS_DSP
+1
-7
arch/mips/include/asm/syscall.h
+1
-7
arch/mips/include/asm/syscall.h
···
29
29
static inline long syscall_get_nr(struct task_struct *task,
30
30
struct pt_regs *regs)
31
31
{
32
-
/* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
33
-
if ((config_enabled(CONFIG_32BIT) ||
34
-
test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
35
-
(regs->regs[2] == __NR_syscall))
36
-
return regs->regs[4];
37
-
else
38
-
return regs->regs[2];
32
+
return current_thread_info()->syscall;
39
33
}
40
34
41
35
static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
+1
arch/mips/include/asm/thread_info.h
+1
arch/mips/include/asm/thread_info.h
+9
-6
arch/mips/include/uapi/asm/unistd.h
+9
-6
arch/mips/include/uapi/asm/unistd.h
···
376
376
#define __NR_getrandom (__NR_Linux + 353)
377
377
#define __NR_memfd_create (__NR_Linux + 354)
378
378
#define __NR_bpf (__NR_Linux + 355)
379
+
#define __NR_execveat (__NR_Linux + 356)
379
380
380
381
/*
381
382
* Offset of the last Linux o32 flavoured syscall
382
383
*/
383
-
#define __NR_Linux_syscalls 355
384
+
#define __NR_Linux_syscalls 356
384
385
385
386
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
386
387
387
388
#define __NR_O32_Linux 4000
388
-
#define __NR_O32_Linux_syscalls 355
389
+
#define __NR_O32_Linux_syscalls 356
389
390
390
391
#if _MIPS_SIM == _MIPS_SIM_ABI64
391
392
···
710
709
#define __NR_getrandom (__NR_Linux + 313)
711
710
#define __NR_memfd_create (__NR_Linux + 314)
712
711
#define __NR_bpf (__NR_Linux + 315)
712
+
#define __NR_execveat (__NR_Linux + 316)
713
713
714
714
/*
715
715
* Offset of the last Linux 64-bit flavoured syscall
716
716
*/
717
-
#define __NR_Linux_syscalls 315
717
+
#define __NR_Linux_syscalls 316
718
718
719
719
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
720
720
721
721
#define __NR_64_Linux 5000
722
-
#define __NR_64_Linux_syscalls 315
722
+
#define __NR_64_Linux_syscalls 316
723
723
724
724
#if _MIPS_SIM == _MIPS_SIM_NABI32
725
725
···
1048
1046
#define __NR_getrandom (__NR_Linux + 317)
1049
1047
#define __NR_memfd_create (__NR_Linux + 318)
1050
1048
#define __NR_bpf (__NR_Linux + 319)
1049
+
#define __NR_execveat (__NR_Linux + 320)
1051
1050
1052
1051
/*
1053
1052
* Offset of the last N32 flavoured syscall
1054
1053
*/
1055
-
#define __NR_Linux_syscalls 319
1054
+
#define __NR_Linux_syscalls 320
1056
1055
1057
1056
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1058
1057
1059
1058
#define __NR_N32_Linux 6000
1060
-
#define __NR_N32_Linux_syscalls 319
1059
+
#define __NR_N32_Linux_syscalls 320
1061
1060
1062
1061
#endif /* _UAPI_ASM_UNISTD_H */
+3
arch/mips/jz4740/irq.c
+3
arch/mips/jz4740/irq.c
+4
-4
arch/mips/kernel/elf.c
+4
-4
arch/mips/kernel/elf.c
···
19
19
int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
20
20
bool is_interp, struct arch_elf_state *state)
21
21
{
22
-
struct elfhdr *ehdr = _ehdr;
23
-
struct elf_phdr *phdr = _phdr;
22
+
struct elf32_hdr *ehdr = _ehdr;
23
+
struct elf32_phdr *phdr = _phdr;
24
24
struct mips_elf_abiflags_v0 abiflags;
25
25
int ret;
26
26
···
48
48
return 0;
49
49
}
50
50
51
-
static inline unsigned get_fp_abi(struct elfhdr *ehdr, int in_abi)
51
+
static inline unsigned get_fp_abi(struct elf32_hdr *ehdr, int in_abi)
52
52
{
53
53
/* If the ABI requirement is provided, simply return that */
54
54
if (in_abi != -1)
···
65
65
int arch_check_elf(void *_ehdr, bool has_interpreter,
66
66
struct arch_elf_state *state)
67
67
{
68
-
struct elfhdr *ehdr = _ehdr;
68
+
struct elf32_hdr *ehdr = _ehdr;
69
69
unsigned fp_abi, interp_fp_abi, abi0, abi1;
70
70
71
71
/* Ignore non-O32 binaries */
+4
arch/mips/kernel/irq_cpu.c
+4
arch/mips/kernel/irq_cpu.c
···
57
57
.irq_mask_ack = mask_mips_irq,
58
58
.irq_unmask = unmask_mips_irq,
59
59
.irq_eoi = unmask_mips_irq,
60
+
.irq_disable = mask_mips_irq,
61
+
.irq_enable = unmask_mips_irq,
60
62
};
61
63
62
64
/*
···
95
93
.irq_mask_ack = mips_mt_cpu_irq_ack,
96
94
.irq_unmask = unmask_mips_irq,
97
95
.irq_eoi = unmask_mips_irq,
96
+
.irq_disable = mask_mips_irq,
97
+
.irq_enable = unmask_mips_irq,
98
98
};
99
99
100
100
asmlinkage void __weak plat_irq_dispatch(void)
+24
-12
arch/mips/kernel/process.c
+24
-12
arch/mips/kernel/process.c
···
82
82
{
83
83
}
84
84
85
+
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
86
+
{
87
+
/*
88
+
* Save any process state which is live in hardware registers to the
89
+
* parent context prior to duplication. This prevents the new child
90
+
* state becoming stale if the parent is preempted before copy_thread()
91
+
* gets a chance to save the parent's live hardware registers to the
92
+
* child context.
93
+
*/
94
+
preempt_disable();
95
+
96
+
if (is_msa_enabled())
97
+
save_msa(current);
98
+
else if (is_fpu_owner())
99
+
_save_fp(current);
100
+
101
+
save_dsp(current);
102
+
103
+
preempt_enable();
104
+
105
+
*dst = *src;
106
+
return 0;
107
+
}
108
+
85
109
int copy_thread(unsigned long clone_flags, unsigned long usp,
86
110
unsigned long arg, struct task_struct *p)
87
111
{
···
115
91
p->set_child_tid = p->clear_child_tid = NULL;
116
92
117
93
childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
118
-
119
-
preempt_disable();
120
-
121
-
if (is_msa_enabled())
122
-
save_msa(p);
123
-
else if (is_fpu_owner())
124
-
save_fp(p);
125
-
126
-
if (cpu_has_dsp)
127
-
save_dsp(p);
128
-
129
-
preempt_enable();
130
94
131
95
/* set up new TSS. */
132
96
childregs = (struct pt_regs *) childksp - 1;
+2
arch/mips/kernel/ptrace.c
+2
arch/mips/kernel/ptrace.c
+2
arch/mips/kernel/scall32-o32.S
+2
arch/mips/kernel/scall32-o32.S
···
181
181
sll t1, t0, 2
182
182
beqz v0, einval
183
183
lw t2, sys_call_table(t1) # syscall routine
184
+
sw a0, PT_R2(sp) # call routine directly on restart
184
185
185
186
/* Some syscalls like execve get their arguments from struct pt_regs
186
187
and claim zero arguments in the syscall table. Thus we have to
···
581
580
PTR sys_getrandom
582
581
PTR sys_memfd_create
583
582
PTR sys_bpf /* 4355 */
583
+
PTR sys_execveat
+1
arch/mips/kernel/scall64-64.S
+1
arch/mips/kernel/scall64-64.S
+1
arch/mips/kernel/scall64-n32.S
+1
arch/mips/kernel/scall64-n32.S
+2
arch/mips/kernel/scall64-o32.S
+2
arch/mips/kernel/scall64-o32.S
···
186
186
dsll t1, t0, 3
187
187
beqz v0, einval
188
188
ld t2, sys32_call_table(t1) # syscall routine
189
+
sd a0, PT_R2(sp) # call routine directly on restart
189
190
190
191
move a0, a1 # shift argument registers
191
192
move a1, a2
···
566
565
PTR sys_getrandom
567
566
PTR sys_memfd_create
568
567
PTR sys_bpf /* 4355 */
568
+
PTR compat_sys_execveat
569
569
.size sys32_call_table,.-sys32_call_table
+2
-2
arch/mips/kernel/smp-cmp.c
+2
-2
arch/mips/kernel/smp-cmp.c
···
44
44
struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
45
45
46
46
/* Assume GIC is present */
47
-
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
48
-
STATUSF_IP7);
47
+
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
48
+
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
49
49
50
50
/* Enable per-cpu interrupts: platform specific */
51
51
+2
-1
arch/mips/kernel/smp-mt.c
+2
-1
arch/mips/kernel/smp-mt.c
···
161
161
#ifdef CONFIG_MIPS_GIC
162
162
/* This is Malta specific: IPI,performance and timer interrupts */
163
163
if (gic_present)
164
-
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
164
+
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
165
+
STATUSF_IP4 | STATUSF_IP5 |
165
166
STATUSF_IP6 | STATUSF_IP7);
166
167
else
167
168
#endif
+1
-1
arch/mips/kernel/smp.c
+1
-1
arch/mips/kernel/smp.c
+2
-1
arch/mips/kernel/traps.c
+2
-1
arch/mips/kernel/traps.c
+2
arch/mips/mm/tlb-r4k.c
+2
arch/mips/mm/tlb-r4k.c
+27
drivers/irqchip/irq-mips-gic.c
+27
drivers/irqchip/irq-mips-gic.c
···
37
37
static int gic_shared_intrs;
38
38
static int gic_vpes;
39
39
static unsigned int gic_cpu_pin;
40
+
static unsigned int timer_cpu_pin;
40
41
static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
41
42
42
43
static void __gic_irq_dispatch(void);
···
617
616
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
618
617
break;
619
618
case GIC_LOCAL_INT_TIMER:
619
+
/* CONFIG_MIPS_CMP workaround (see __gic_init) */
620
+
val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
620
621
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
621
622
break;
622
623
case GIC_LOCAL_INT_PERFCTR:
···
716
713
if (cpu_has_veic) {
717
714
/* Always use vector 1 in EIC mode */
718
715
gic_cpu_pin = 0;
716
+
timer_cpu_pin = gic_cpu_pin;
719
717
set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
720
718
__gic_irq_dispatch);
721
719
} else {
722
720
gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
723
721
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
724
722
gic_irq_dispatch);
723
+
/*
724
+
* With the CMP implementation of SMP (deprecated), other CPUs
725
+
* are started by the bootloader and put into a timer based
726
+
* waiting poll loop. We must not re-route those CPU's local
727
+
* timer interrupts as the wait instruction will never finish,
728
+
* so just handle whatever CPU interrupt it is routed to by
729
+
* default.
730
+
*
731
+
* This workaround should be removed when CMP support is
732
+
* dropped.
733
+
*/
734
+
if (IS_ENABLED(CONFIG_MIPS_CMP) &&
735
+
gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
736
+
timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL,
737
+
GIC_VPE_TIMER_MAP)) &
738
+
GIC_MAP_MSK;
739
+
irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
740
+
GIC_CPU_PIN_OFFSET +
741
+
timer_cpu_pin,
742
+
gic_irq_dispatch);
743
+
} else {
744
+
timer_cpu_pin = gic_cpu_pin;
745
+
}
725
746
}
726
747
727
748
gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +