Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'irq-urgent-2021-09-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"A set of fixes for interrupt chip drivers:
- Work around a bad GIC integration on a Renesas platform which can't
handle byte-sized MMIO access
- Plug a potential memory leak in the GICv4 driver
- Fix a regression in the Armada 370-XP IPI code which was caused by
issuing EOI instack of ACK.
- A couple of small fixes here and there"
* tag 'irq-urgent-2021-09-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic: Work around broken Renesas integration
irqchip/renesas-rza1: Use semicolons instead of commas
irqchip/gic-v3-its: Fix potential VPE leak on error
irqchip/goldfish-pic: Select GENERIC_IRQ_CHIP to fix build
irqchip/mbigen: Repair non-kernel-doc notation
irqdomain: Change the type of 'size' in __irq_domain_add() to be consistent
irqchip/armada-370-xp: Fix ack/eoi breakage
Documentation: Fix irq-domain.rst build warning
+69
-17
+3
-2
Documentation/core-api/irq/irq-domain.rst
+3
-2
Documentation/core-api/irq/irq-domain.rst
···
175
175
case the Linux IRQ numbers cannot be dynamically assigned and the legacy
176
176
mapping should be used.
177
177
178
-
As the name implies, the *_legacy() functions are deprecated and only
178
+
As the name implies, the \*_legacy() functions are deprecated and only
179
179
exist to ease the support of ancient platforms. No new users should be
180
-
added.
180
+
added. Same goes for the \*_simple() functions when their use results
181
+
in the legacy behaviour.
181
182
182
183
The legacy map assumes a contiguous range of IRQ numbers has already
183
184
been allocated for the controller and that the IRQ number can be
+1
drivers/irqchip/Kconfig
+1
drivers/irqchip/Kconfig
+2
-2
drivers/irqchip/irq-armada-370-xp.c
+2
-2
drivers/irqchip/irq-armada-370-xp.c
···
359
359
ARMADA_370_XP_SW_TRIG_INT_OFFS);
360
360
}
361
361
362
-
static void armada_370_xp_ipi_eoi(struct irq_data *d)
362
+
static void armada_370_xp_ipi_ack(struct irq_data *d)
363
363
{
364
364
writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
365
365
}
366
366
367
367
static struct irq_chip ipi_irqchip = {
368
368
.name = "IPI",
369
+
.irq_ack = armada_370_xp_ipi_ack,
369
370
.irq_mask = armada_370_xp_ipi_mask,
370
371
.irq_unmask = armada_370_xp_ipi_unmask,
371
-
.irq_eoi = armada_370_xp_ipi_eoi,
372
372
.ipi_send_mask = armada_370_xp_ipi_send_mask,
373
373
};
374
374
+1
-1
drivers/irqchip/irq-gic-v3-its.c
+1
-1
drivers/irqchip/irq-gic-v3-its.c
+51
-1
drivers/irqchip/irq-gic.c
+51
-1
drivers/irqchip/irq-gic.c
···
107
107
108
108
#endif
109
109
110
+
static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
111
+
110
112
/*
111
113
* The GIC mapping of CPU interfaces does not necessarily match
112
114
* the logical CPU numbering. Let's use a mapping as returned
···
776
774
#endif
777
775
778
776
#ifdef CONFIG_SMP
777
+
static void rmw_writeb(u8 bval, void __iomem *addr)
778
+
{
779
+
static DEFINE_RAW_SPINLOCK(rmw_lock);
780
+
unsigned long offset = (unsigned long)addr & 3UL;
781
+
unsigned long shift = offset * 8;
782
+
unsigned long flags;
783
+
u32 val;
784
+
785
+
raw_spin_lock_irqsave(&rmw_lock, flags);
786
+
787
+
addr -= offset;
788
+
val = readl_relaxed(addr);
789
+
val &= ~GENMASK(shift + 7, shift);
790
+
val |= bval << shift;
791
+
writel_relaxed(val, addr);
792
+
793
+
raw_spin_unlock_irqrestore(&rmw_lock, flags);
794
+
}
795
+
779
796
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
780
797
bool force)
781
798
{
···
809
788
if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
810
789
return -EINVAL;
811
790
812
-
writeb_relaxed(gic_cpu_map[cpu], reg);
791
+
if (static_branch_unlikely(&needs_rmw_access))
792
+
rmw_writeb(gic_cpu_map[cpu], reg);
793
+
else
794
+
writeb_relaxed(gic_cpu_map[cpu], reg);
813
795
irq_data_update_effective_affinity(d, cpumask_of(cpu));
814
796
815
797
return IRQ_SET_MASK_OK_DONE;
···
1399
1375
return true;
1400
1376
}
1401
1377
1378
+
static bool gic_enable_rmw_access(void *data)
1379
+
{
1380
+
/*
1381
+
* The EMEV2 class of machines has a broken interconnect, and
1382
+
* locks up on accesses that are less than 32bit. So far, only
1383
+
* the affinity setting requires it.
1384
+
*/
1385
+
if (of_machine_is_compatible("renesas,emev2")) {
1386
+
static_branch_enable(&needs_rmw_access);
1387
+
return true;
1388
+
}
1389
+
1390
+
return false;
1391
+
}
1392
+
1393
+
static const struct gic_quirk gic_quirks[] = {
1394
+
{
1395
+
.desc = "broken byte access",
1396
+
.compatible = "arm,pl390",
1397
+
.init = gic_enable_rmw_access,
1398
+
},
1399
+
{ },
1400
+
};
1401
+
1402
1402
static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1403
1403
{
1404
1404
if (!gic || !node)
···
1438
1390
1439
1391
if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1440
1392
gic->percpu_offset = 0;
1393
+
1394
+
gic_enable_of_quirks(node, gic_quirks, gic);
1441
1395
1442
1396
return 0;
1443
1397
+3
-3
drivers/irqchip/irq-mbigen.c
+3
-3
drivers/irqchip/irq-mbigen.c
···
25
25
/* The maximum IRQ pin number of mbigen chip(start from 0) */
26
26
#define MAXIMUM_IRQ_PIN_NUM 1407
27
27
28
-
/**
28
+
/*
29
29
* In mbigen vector register
30
30
* bit[21:12]: event id value
31
31
* bit[11:0]: device id
···
39
39
/* offset of vector register in mbigen node */
40
40
#define REG_MBIGEN_VEC_OFFSET 0x200
41
41
42
-
/**
42
+
/*
43
43
* offset of clear register in mbigen node
44
44
* This register is used to clear the status
45
45
* of interrupt
46
46
*/
47
47
#define REG_MBIGEN_CLEAR_OFFSET 0xa000
48
48
49
-
/**
49
+
/*
50
50
* offset of interrupt type register
51
51
* This register is used to configure interrupt
52
52
* trigger type
+6
-6
drivers/irqchip/irq-renesas-rza1.c
+6
-6
drivers/irqchip/irq-renesas-rza1.c
···
223
223
goto out_put_node;
224
224
}
225
225
226
-
priv->chip.name = "rza1-irqc",
227
-
priv->chip.irq_mask = irq_chip_mask_parent,
228
-
priv->chip.irq_unmask = irq_chip_unmask_parent,
229
-
priv->chip.irq_eoi = rza1_irqc_eoi,
230
-
priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy,
231
-
priv->chip.irq_set_type = rza1_irqc_set_type,
226
+
priv->chip.name = "rza1-irqc";
227
+
priv->chip.irq_mask = irq_chip_mask_parent;
228
+
priv->chip.irq_unmask = irq_chip_unmask_parent;
229
+
priv->chip.irq_eoi = rza1_irqc_eoi;
230
+
priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy;
231
+
priv->chip.irq_set_type = rza1_irqc_set_type;
232
232
priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
233
233
234
234
priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
+1
-1
include/linux/irqdomain.h
+1
-1
include/linux/irqdomain.h
···
251
251
}
252
252
253
253
void irq_domain_free_fwnode(struct fwnode_handle *fwnode);
254
-
struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size,
254
+
struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size,
255
255
irq_hw_number_t hwirq_max, int direct_max,
256
256
const struct irq_domain_ops *ops,
257
257
void *host_data);
+1
-1
kernel/irq/irqdomain.c
+1
-1
kernel/irq/irqdomain.c
···
136
136
* Allocates and initializes an irq_domain structure.
137
137
* Returns pointer to IRQ domain, or NULL on failure.
138
138
*/
139
-
struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size,
139
+
struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size,
140
140
irq_hw_number_t hwirq_max, int direct_max,
141
141
const struct irq_domain_ops *ops,
142
142
void *host_data)