Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: set flip bits for RAS bad pages
Make the code more general, user doesn't need to pay attention to the
detail of flip bits setting.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Tao Zhou
and committed by
Alex Deucher
dc111f8f
7e340d3c
+7
-13
+7
-13
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+7
-13
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
···
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col_lower = (err_addr >> 1) & 0x3ULL;
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/* extra row bit will be handled later */
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row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL;
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+
row_lower &= ~BIT_ULL(adev->umc.flip_bits.flip_row_bit);
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if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 5, 0)) {
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-
row_high = (soc_pa >> UMC_V12_0_PA_R13_BIT) & 0x3ULL;
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+
row_high = (soc_pa >> adev->umc.flip_bits.r13_in_pa) & 0x3ULL;
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/* it's 2.25GB in each channel, from MCA address to PA
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* [R14 R13] is converted if the two bits value are 0x3,
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* get them from PA instead of MCA address.
···
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soc_pa |= (((column >> i) & 0x1ULL) << flip_bits[i]);
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col = ((column & 0x7) << 2) | col_lower;
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-
/* add row bit 13 */
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-
row = ((column >> 3) << 13) | row_lower;
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+
/* handle extra row bit */
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+
if (bit_num == RETIRE_FLIP_BITS_NUM)
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+
row = ((column >> 3) << adev->umc.flip_bits.flip_row_bit) |
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+
row_lower;
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if (dump_addr)
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dev_info(adev->dev,
···
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uint64_t err_addr, pa_addr = 0;
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struct ras_ecc_err *ecc_err;
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struct ta_ras_query_address_output addr_out;
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-
enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;
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-
uint32_t shift_bit = UMC_V12_0_PA_C4_BIT;
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+
uint32_t shift_bit = adev->umc.flip_bits.flip_bits_in_pa[2];
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int count, ret, i;
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hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
···
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ecc_err->addr = addr;
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ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT;
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ecc_err->channel_idx = addr_out.pa.channel_idx;
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-
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-
if (adev->gmc.gmc_funcs->query_mem_partition_mode)
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-
nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
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-
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-
if (nps == AMDGPU_NPS2_PARTITION_MODE)
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-
shift_bit = UMC_V12_0_PA_B1_BIT;
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-
if (nps == AMDGPU_NPS4_PARTITION_MODE)
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-
shift_bit = UMC_V12_0_PA_B0_BIT;
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/* If converted pa_pfn is 0, use pa C4 pfn. */
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if (!ecc_err->pa_pfn)