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arm_mpam: Add workaround for T241-MPAM-6

The registers MSMON_MBWU_L and MSMON_MBWU return the number of requests
rather than the number of bytes transferred.

Bandwidth resource monitoring is performed at the last level cache, where
each request arrive in 64Byte granularity. The current implementation
returns the number of transactions received at the last level cache but
does not provide the value in bytes. Scaling by 64 gives an accurate byte
count to match the MPAM specification for the MSMON_MBWU and MSMON_MBWU_L
registers. This patch fixes the issue by reporting the actual number of
bytes instead of the number of transactions from __ris_msmon_read().

Tested-by: Gavin Shan <gshan@redhat.com>
Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Tested-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com>
Tested-by: Peter Newman <peternewman@google.com>
Tested-by: Jesse Chick <jessechick@os.amperecomputing.com>
Reviewed-by: Zeng Heng <zengheng4@huawei.com>
Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>

authored by

Shanker Donthineni and committed by
James Morse dc48eb1f a7efe23e

+27 -2
+2
Documentation/arch/arm64/silicon-errata.rst
··· 251 251 +----------------+-----------------+-----------------+-----------------------------+ 252 252 | NVIDIA | T241 MPAM | T241-MPAM-4 | N/A | 253 253 +----------------+-----------------+-----------------+-----------------------------+ 254 + | NVIDIA | T241 MPAM | T241-MPAM-6 | N/A | 255 + +----------------+-----------------+-----------------+-----------------------------+ 254 256 +----------------+-----------------+-----------------+-----------------------------+ 255 257 | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | 256 258 +----------------+-----------------+-----------------+-----------------------------+
+24 -2
drivers/resctrl/mpam_devices.c
··· 685 685 .iidr_mask = MPAM_IIDR_MATCH_ONE, 686 686 .workaround = T241_FORCE_MBW_MIN_TO_ONE, 687 687 }, 688 + { 689 + /* NVIDIA t241 erratum T241-MPAM-6 */ 690 + .iidr = MPAM_IIDR_NVIDIA_T241, 691 + .iidr_mask = MPAM_IIDR_MATCH_ONE, 692 + .workaround = T241_MBW_COUNTER_SCALE_64, 693 + }, 688 694 { NULL } /* Sentinel */ 689 695 }; 690 696 ··· 1152 1146 } 1153 1147 } 1154 1148 1155 - static u64 mpam_msmon_overflow_val(enum mpam_device_features type) 1149 + static u64 __mpam_msmon_overflow_val(enum mpam_device_features type) 1156 1150 { 1157 1151 /* TODO: implement scaling counters */ 1158 1152 switch (type) { ··· 1165 1159 default: 1166 1160 return 0; 1167 1161 } 1162 + } 1163 + 1164 + static u64 mpam_msmon_overflow_val(enum mpam_device_features type, 1165 + struct mpam_msc *msc) 1166 + { 1167 + u64 overflow_val = __mpam_msmon_overflow_val(type); 1168 + 1169 + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc) && 1170 + type != mpam_feat_msmon_mbwu_63counter) 1171 + overflow_val *= 64; 1172 + 1173 + return overflow_val; 1168 1174 } 1169 1175 1170 1176 static void __ris_msmon_read(void *arg) ··· 1269 1251 now = FIELD_GET(MSMON___VALUE, now); 1270 1252 } 1271 1253 1254 + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc) && 1255 + m->type != mpam_feat_msmon_mbwu_63counter) 1256 + now *= 64; 1257 + 1272 1258 if (nrdy) 1273 1259 break; 1274 1260 1275 1261 mbwu_state = &ris->mbwu_state[ctx->mon]; 1276 1262 1277 1263 if (overflow) 1278 - mbwu_state->correction += mpam_msmon_overflow_val(m->type); 1264 + mbwu_state->correction += mpam_msmon_overflow_val(m->type, msc); 1279 1265 1280 1266 /* 1281 1267 * Include bandwidth consumed before the last hardware reset and
+1
drivers/resctrl/mpam_internal.h
··· 225 225 enum mpam_device_quirks { 226 226 T241_SCRUB_SHADOW_REGS, 227 227 T241_FORCE_MBW_MIN_TO_ONE, 228 + T241_MBW_COUNTER_SCALE_64, 228 229 MPAM_QUIRK_LAST 229 230 }; 230 231