clk: remove round_rate() clk ops · tjh.dev/kernel@dc652a3

+1 -8

Documentation/driver-api/clk.rst

··· 77 77 void (*disable_unused)(struct clk_hw *hw); 78 78 unsigned long (*recalc_rate)(struct clk_hw *hw, 79 79 unsigned long parent_rate); 80 - long (*round_rate)(struct clk_hw *hw, 81 - unsigned long rate, 82 - unsigned long *parent_rate); 83 80 int (*determine_rate)(struct clk_hw *hw, 84 81 struct clk_rate_request *req); 85 82 int (*set_parent)(struct clk_hw *hw, u8 index); ··· 217 220 +----------------+------+-------------+---------------+-------------+------+ 218 221 |.recalc_rate | | y | | | | 219 222 +----------------+------+-------------+---------------+-------------+------+ 220 - |.round_rate | | y [1]_ | | | | 221 - +----------------+------+-------------+---------------+-------------+------+ 222 - |.determine_rate | | y [1]_ | | | | 223 + |.determine_rate | | y | | | | 223 224 +----------------+------+-------------+---------------+-------------+------+ 224 225 |.set_rate | | y | | | | 225 226 +----------------+------+-------------+---------------+-------------+------+ ··· 232 237 +----------------+------+-------------+---------------+-------------+------+ 233 238 |.init | | | | | | 234 239 +----------------+------+-------------+---------------+-------------+------+ 235 - 236 - .. [1] either one of round_rate or determine_rate is required. 237 240 238 241 Finally, register your clock at run-time with a hardware-specific 239 242 registration function. This function simply populates struct clk_foo's

+14 -25

drivers/clk/clk.c

··· 1560 1560 static int clk_core_determine_round_nolock(struct clk_core *core, 1561 1561 struct clk_rate_request *req) 1562 1562 { 1563 - long rate; 1564 - 1565 1563 lockdep_assert_held(&prepare_lock); 1566 1564 1567 1565 if (!core) ··· 1589 1591 req->rate = core->rate; 1590 1592 } else if (core->ops->determine_rate) { 1591 1593 return core->ops->determine_rate(core->hw, req); 1592 - } else if (core->ops->round_rate) { 1593 - rate = core->ops->round_rate(core->hw, req->rate, 1594 - &req->best_parent_rate); 1595 - if (rate < 0) 1596 - return rate; 1597 - 1598 - req->rate = rate; 1599 1594 } else { 1600 1595 return -EINVAL; 1601 1596 } ··· 1673 1682 1674 1683 static bool clk_core_can_round(struct clk_core * const core) 1675 1684 { 1676 - return core->ops->determine_rate || core->ops->round_rate; 1685 + return core->ops->determine_rate; 1677 1686 } 1678 1687 1679 1688 static int clk_core_round_rate_nolock(struct clk_core *core, ··· 1741 1750 * use. 1742 1751 * 1743 1752 * Context: prepare_lock must be held. 1744 - * For clk providers to call from within clk_ops such as .round_rate, 1753 + * For clk providers to call from within clk_ops such as 1745 1754 * .determine_rate. 1746 1755 * 1747 - * Return: returns rounded rate of hw clk if clk supports round_rate operation 1748 - * else returns the parent rate. 1756 + * Return: returns rounded rate of hw clk if clk supports determine_rate 1757 + * operation; else returns the parent rate. 1749 1758 */ 1750 1759 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate) 1751 1760 { ··· 2560 2569 * 2561 2570 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to 2562 2571 * propagate up to clk's parent; whether or not this happens depends on the 2563 - * outcome of clk's .round_rate implementation. If *parent_rate is unchanged 2564 - * after calling .round_rate then upstream parent propagation is ignored. If 2565 - * *parent_rate comes back with a new rate for clk's parent then we propagate 2566 - * up to clk's parent and set its rate. Upward propagation will continue 2567 - * until either a clk does not support the CLK_SET_RATE_PARENT flag or 2568 - * .round_rate stops requesting changes to clk's parent_rate. 2572 + * outcome of clk's .determine_rate implementation. If req->best_parent_rate 2573 + * is unchanged after calling .determine_rate then upstream parent propagation 2574 + * is ignored. If req->best_parent_rate comes back with a new rate for clk's 2575 + * parent then we propagate up to clk's parent and set its rate. Upward 2576 + * propagation will continue until either a clk does not support the 2577 + * CLK_SET_RATE_PARENT flag or .determine_rate stops requesting changes to 2578 + * clk's parent_rate. 2569 2579 * 2570 2580 * Rate changes are accomplished via tree traversal that also recalculates the 2571 2581 * rates for the clocks and fires off POST_RATE_CHANGE notifiers. ··· 2695 2703 * FIXME: 2696 2704 * There is a catch. It may fail for the usual reason (clock 2697 2705 * broken, clock protected, etc) but also because: 2698 - * - round_rate() was not favorable and fell on the wrong 2699 - * side of the boundary 2700 2706 * - the determine_rate() callback does not really check for 2701 2707 * this corner case when determining the rate 2702 2708 */ ··· 3905 3915 } 3906 3916 3907 3917 /* check that clk_ops are sane. See Documentation/driver-api/clk.rst */ 3908 - if (core->ops->set_rate && 3909 - !((core->ops->round_rate || core->ops->determine_rate) && 3910 - core->ops->recalc_rate)) { 3911 - pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n", 3918 + if (core->ops->set_rate && !core->ops->determine_rate && 3919 + core->ops->recalc_rate) { 3920 + pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n", 3912 3921 __func__, core->name); 3913 3922 ret = -EINVAL; 3914 3923 goto out;

+6 -12

include/linux/clk-provider.h

··· 136 136 * 0. Returns the calculated rate. Optional, but recommended - if 137 137 * this op is not set then clock rate will be initialized to 0. 138 138 * 139 - * @round_rate: Given a target rate as input, returns the closest rate actually 140 - * supported by the clock. The parent rate is an input/output 141 - * parameter. 142 - * 143 139 * @determine_rate: Given a target rate as input, returns the closest rate 144 140 * actually supported by the clock, and optionally the parent clock 145 141 * that should be used to provide the clock rate. ··· 159 163 * 160 164 * @set_rate: Change the rate of this clock. The requested rate is specified 161 165 * by the second argument, which should typically be the return 162 - * of .round_rate call. The third argument gives the parent rate 163 - * which is likely helpful for most .set_rate implementation. 166 + * of .determine_rate call. The third argument gives the parent 167 + * rate which is likely helpful for most .set_rate implementation. 164 168 * Returns 0 on success, -EERROR otherwise. 165 169 * 166 170 * @set_rate_and_parent: Change the rate and the parent of this clock. The 167 171 * requested rate is specified by the second argument, which 168 - * should typically be the return of .round_rate call. The 172 + * should typically be the return of clk_round_rate() call. The 169 173 * third argument gives the parent rate which is likely helpful 170 174 * for most .set_rate_and_parent implementation. The fourth 171 175 * argument gives the parent index. This callback is optional (and ··· 240 244 void (*restore_context)(struct clk_hw *hw); 241 245 unsigned long (*recalc_rate)(struct clk_hw *hw, 242 246 unsigned long parent_rate); 243 - long (*round_rate)(struct clk_hw *hw, unsigned long rate, 244 - unsigned long *parent_rate); 245 247 int (*determine_rate)(struct clk_hw *hw, 246 248 struct clk_rate_request *req); 247 249 int (*set_parent)(struct clk_hw *hw, u8 index); ··· 673 679 * @lock: register lock 674 680 * 675 681 * Clock with an adjustable divider affecting its output frequency. Implements 676 - * .recalc_rate, .set_rate and .round_rate 682 + * .recalc_rate, .set_rate and .determine_rate 677 683 * 678 684 * @flags: 679 685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the ··· 1120 1126 * 1121 1127 * Clock with a fixed multiplier and divider. The output frequency is the 1122 1128 * parent clock rate divided by div and multiplied by mult. 1123 - * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy 1129 + * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy 1124 1130 * 1125 1131 * Flags: 1126 1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the ··· 1248 1254 * @lock: register lock 1249 1255 * 1250 1256 * Clock with an adjustable multiplier affecting its output frequency. 1251 - * Implements .recalc_rate, .set_rate and .round_rate 1257 + * Implements .recalc_rate, .set_rate and .determine_rate 1252 1258 * 1253 1259 * @flags: 1254 1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read

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