Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
media: rkvdec: Switch to using structs instead of writel
In an effort to merge the rkvdec2 driver [1] with this one, switch from
writel() calls to using structs to represent the register mappings.
This is done in order to have all supported decoders use the same format
in the future and ease reading of the code.
Using structs also improves stability as the hardware is tested and
validated downstream using a similar method.
It was noticed, on decoders, that:
- Some registers require to be writen in increasing order [2]
- Some registers, even if unrelated, need to be written to their reset
values (it was the case here for axi_ddr_[rw]data).
Using structs can also help improving performance later when, e.g.
multicore support is added on RK3588.
Performance seems to be slightly improved, but at least, not made worse.
Running fluster's JVT-AVC_V1 test suite with GStreamer on the Radxa ROCK
PI 4 SE gives the following times:
Before this patch:
- --jobs 1: Ran 129/135 tests successfully in 77.167 secs
- --jobs 6: Ran 129/135 tests successfully in 23.046 secs
With this patch:
- --jobs 1: Ran 129/135 tests successfully in 70.698 secs
- --jobs 6: Ran 129/135 tests successfully in 22.917 secs
This also shows that the fluster score hasn't changed.
[1]: https://lore.kernel.org/all/20250325213303.826925-1-detlev.casanova@collabora.com/
[2]: https://lore.kernel.org/all/20200127143009.15677-5-andrzej.p@collabora.com/
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock 5B
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
authored by
Detlev Casanova
and committed by
Hans Verkuil
dc689898
4cb9cd80
+562
-413
+71
-95
drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
+71
-95
drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
···
115
115
struct rkvdec_h264_ctx {
116
116
struct rkvdec_aux_buf priv_tbl;
117
117
struct rkvdec_h264_reflists reflists;
118
+
struct rkvdec_regs regs;
118
119
};
119
120
120
121
#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \
···
842
841
}
843
842
844
843
/*
845
-
* dpb poc related registers table
844
+
* Set the ref POC in the correct register.
845
+
*
846
+
* The 32 registers are spread across 3 regions, each alternating top and bottom ref POCs:
847
+
* - 1: ref 0 to 14 contain top 0 to 7 and bottoms 0 to 6
848
+
* - 2: ref 15 to 29 contain top 8 to 14 and bottoms 7 to 14
849
+
* - 3: ref 30 and 31 which correspond to top 15 and bottom 15 respectively.
846
850
*/
847
-
static const u32 poc_reg_tbl_top_field[16] = {
848
-
RKVDEC_REG_H264_POC_REFER0(0),
849
-
RKVDEC_REG_H264_POC_REFER0(2),
850
-
RKVDEC_REG_H264_POC_REFER0(4),
851
-
RKVDEC_REG_H264_POC_REFER0(6),
852
-
RKVDEC_REG_H264_POC_REFER0(8),
853
-
RKVDEC_REG_H264_POC_REFER0(10),
854
-
RKVDEC_REG_H264_POC_REFER0(12),
855
-
RKVDEC_REG_H264_POC_REFER0(14),
856
-
RKVDEC_REG_H264_POC_REFER1(1),
857
-
RKVDEC_REG_H264_POC_REFER1(3),
858
-
RKVDEC_REG_H264_POC_REFER1(5),
859
-
RKVDEC_REG_H264_POC_REFER1(7),
860
-
RKVDEC_REG_H264_POC_REFER1(9),
861
-
RKVDEC_REG_H264_POC_REFER1(11),
862
-
RKVDEC_REG_H264_POC_REFER1(13),
863
-
RKVDEC_REG_H264_POC_REFER2(0)
864
-
};
865
-
866
-
static const u32 poc_reg_tbl_bottom_field[16] = {
867
-
RKVDEC_REG_H264_POC_REFER0(1),
868
-
RKVDEC_REG_H264_POC_REFER0(3),
869
-
RKVDEC_REG_H264_POC_REFER0(5),
870
-
RKVDEC_REG_H264_POC_REFER0(7),
871
-
RKVDEC_REG_H264_POC_REFER0(9),
872
-
RKVDEC_REG_H264_POC_REFER0(11),
873
-
RKVDEC_REG_H264_POC_REFER0(13),
874
-
RKVDEC_REG_H264_POC_REFER1(0),
875
-
RKVDEC_REG_H264_POC_REFER1(2),
876
-
RKVDEC_REG_H264_POC_REFER1(4),
877
-
RKVDEC_REG_H264_POC_REFER1(6),
878
-
RKVDEC_REG_H264_POC_REFER1(8),
879
-
RKVDEC_REG_H264_POC_REFER1(10),
880
-
RKVDEC_REG_H264_POC_REFER1(12),
881
-
RKVDEC_REG_H264_POC_REFER1(14),
882
-
RKVDEC_REG_H264_POC_REFER2(1)
883
-
};
851
+
static void set_poc_reg(struct rkvdec_regs *regs, uint32_t poc, int id, bool bottom)
852
+
{
853
+
if (!bottom) {
854
+
switch (id) {
855
+
case 0 ... 7:
856
+
regs->h26x.ref0_14_poc[id * 2] = poc;
857
+
break;
858
+
case 8 ... 14:
859
+
regs->h26x.ref15_29_poc[(id - 8) * 2 + 1] = poc;
860
+
break;
861
+
case 15:
862
+
regs->h26x.ref30_poc = poc;
863
+
break;
864
+
}
865
+
} else {
866
+
switch (id) {
867
+
case 0 ... 6:
868
+
regs->h26x.ref0_14_poc[id * 2 + 1] = poc;
869
+
break;
870
+
case 7 ... 14:
871
+
regs->h26x.ref15_29_poc[(id - 7) * 2] = poc;
872
+
break;
873
+
case 15:
874
+
regs->h26x.ref31_poc = poc;
875
+
break;
876
+
}
877
+
}
878
+
}
884
879
885
880
static void config_registers(struct rkvdec_ctx *ctx,
886
881
struct rkvdec_h264_run *run)
···
891
894
struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
892
895
struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
893
896
const struct v4l2_format *f;
897
+
struct rkvdec_regs *regs = &h264_ctx->regs;
894
898
dma_addr_t rlc_addr;
895
899
dma_addr_t refer_addr;
896
900
u32 rlc_len;
···
901
903
u32 yuv_virstride = 0;
902
904
u32 offset;
903
905
dma_addr_t dst_addr;
904
-
u32 reg, i;
906
+
u32 i;
905
907
906
-
reg = RKVDEC_MODE(RKVDEC_MODE_H264);
907
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
908
+
memset(regs, 0, sizeof(*regs));
909
+
910
+
regs->common.reg02.dec_mode = RKVDEC_MODE_H264;
908
911
909
912
f = &ctx->decoded_fmt;
910
913
dst_fmt = &f->fmt.pix_mp;
···
920
921
else if (sps->chroma_format_idc == 2)
921
922
yuv_virstride = 2 * y_virstride;
922
923
923
-
reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
924
-
RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
925
-
RKVDEC_SLICE_NUM_HIGHBIT |
926
-
RKVDEC_SLICE_NUM_LOWBITS(0x7ff);
927
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
924
+
regs->common.reg03.uv_hor_virstride = hor_virstride / 16;
925
+
regs->common.reg03.y_hor_virstride = hor_virstride / 16;
926
+
regs->common.reg03.slice_num_highbit = 1;
927
+
regs->common.reg03.slice_num_lowbits = 0x7ff;
928
928
929
929
/* config rlc base address */
930
930
rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
931
-
writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
932
-
writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_RLCWRITE_BASE);
931
+
regs->common.strm_rlc_base = rlc_addr;
932
+
regs->h26x.rlcwrite_base = rlc_addr;
933
933
934
934
rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
935
-
reg = RKVDEC_STRM_LEN(rlc_len);
936
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
935
+
regs->common.stream_len = rlc_len;
937
936
938
937
/* config cabac table */
939
938
offset = offsetof(struct rkvdec_h264_priv_tbl, cabac_table);
940
-
writel_relaxed(priv_start_addr + offset,
941
-
rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
939
+
regs->common.cabactbl_base = priv_start_addr + offset;
942
940
943
941
/* config output base address */
944
942
dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
945
-
writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
943
+
regs->common.decout_base = dst_addr;
946
944
947
-
reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
948
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
945
+
regs->common.reg08.y_virstride = y_virstride / 16;
949
946
950
-
reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
951
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
947
+
regs->common.reg09.yuv_virstride = yuv_virstride / 16;
952
948
953
949
/* config ref pic address & poc */
954
950
for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
955
951
struct vb2_buffer *vb_buf = run->ref_buf[i];
952
+
struct ref_base *base;
956
953
957
954
/*
958
955
* If a DPB entry is unused or invalid, address of current destination
···
958
963
vb_buf = &dst_buf->vb2_buf;
959
964
refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
960
965
961
-
if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
962
-
refer_addr |= RKVDEC_COLMV_USED_FLAG_REF;
963
-
if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD)
964
-
refer_addr |= RKVDEC_FIELD_REF;
965
-
966
-
if (dpb[i].fields & V4L2_H264_TOP_FIELD_REF)
967
-
refer_addr |= RKVDEC_TOPFIELD_USED_REF;
968
-
if (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF)
969
-
refer_addr |= RKVDEC_BOTFIELD_USED_REF;
970
-
971
-
writel_relaxed(dpb[i].top_field_order_cnt,
972
-
rkvdec->regs + poc_reg_tbl_top_field[i]);
973
-
writel_relaxed(dpb[i].bottom_field_order_cnt,
974
-
rkvdec->regs + poc_reg_tbl_bottom_field[i]);
975
-
976
966
if (i < V4L2_H264_NUM_DPB_ENTRIES - 1)
977
-
writel_relaxed(refer_addr,
978
-
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
967
+
base = ®s->h26x.ref0_14_base[i];
979
968
else
980
-
writel_relaxed(refer_addr,
981
-
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15);
969
+
base = ®s->h26x.ref15_base;
970
+
971
+
base->base_addr = refer_addr >> 4;
972
+
base->field_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD);
973
+
base->colmv_use_flag_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
974
+
base->topfield_used_ref = !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF);
975
+
base->botfield_used_ref = !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF);
976
+
977
+
set_poc_reg(regs, dpb[i].top_field_order_cnt, i, false);
978
+
set_poc_reg(regs, dpb[i].bottom_field_order_cnt, i, true);
982
979
}
983
980
984
-
reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt);
985
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
986
-
987
-
reg = RKVDEC_CUR_POC(dec_params->bottom_field_order_cnt);
988
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC1);
981
+
regs->h26x.cur_poc = dec_params->top_field_order_cnt;
982
+
regs->h26x.cur_poc1 = dec_params->bottom_field_order_cnt;
989
983
990
984
/* config hw pps address */
991
985
offset = offsetof(struct rkvdec_h264_priv_tbl, param_set);
992
-
writel_relaxed(priv_start_addr + offset,
993
-
rkvdec->regs + RKVDEC_REG_PPS_BASE);
986
+
regs->h26x.pps_base = priv_start_addr + offset;
994
987
995
988
/* config hw rps address */
996
989
offset = offsetof(struct rkvdec_h264_priv_tbl, rps);
997
-
writel_relaxed(priv_start_addr + offset,
998
-
rkvdec->regs + RKVDEC_REG_RPS_BASE);
999
-
1000
-
reg = RKVDEC_AXI_DDR_RDATA(0);
1001
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
1002
-
1003
-
reg = RKVDEC_AXI_DDR_WDATA(0);
1004
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
990
+
regs->h26x.rps_base = priv_start_addr + offset;
1005
991
1006
992
offset = offsetof(struct rkvdec_h264_priv_tbl, err_info);
1007
-
writel_relaxed(priv_start_addr + offset,
1008
-
rkvdec->regs + RKVDEC_REG_H264_ERRINFO_BASE);
993
+
regs->h26x.errorinfo_base = priv_start_addr + offset;
994
+
995
+
rkvdec_memcpy_toio(rkvdec->regs, regs,
996
+
MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs));
1009
997
}
1010
998
1011
999
#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2
···
1159
1181
1160
1182
schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
1161
1183
1162
-
writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
1163
-
writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
1164
1184
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
1165
1185
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
1166
1186
+28
-36
drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
+28
-36
drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
···
129
129
struct rkvdec_hevc_ctx {
130
130
struct rkvdec_aux_buf priv_tbl;
131
131
struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
132
+
struct rkvdec_regs regs;
132
133
};
133
134
134
135
struct scaling_factor {
···
549
548
const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
550
549
const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
551
550
struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
551
+
struct rkvdec_regs *regs = &hevc_ctx->regs;
552
552
dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
553
553
const struct v4l2_pix_format_mplane *dst_fmt;
554
554
struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
···
566
564
dma_addr_t dst_addr;
567
565
u32 reg, i;
568
566
569
-
reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
570
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
567
+
memset(regs, 0, sizeof(*regs));
568
+
569
+
regs->common.reg02.dec_mode = RKVDEC_MODE_HEVC;
571
570
572
571
f = &ctx->decoded_fmt;
573
572
dst_fmt = &f->fmt.pix_mp;
···
583
580
else if (sps->chroma_format_idc == 2)
584
581
yuv_virstride = 2 * y_virstride;
585
582
586
-
reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
587
-
RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
588
-
RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
589
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
583
+
regs->common.reg03.slice_num_lowbits = run->num_slices;
584
+
regs->common.reg03.uv_hor_virstride = hor_virstride / 16;
585
+
regs->common.reg03.y_hor_virstride = hor_virstride / 16;
590
586
591
587
/* config rlc base address */
592
588
rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
593
-
writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
589
+
regs->common.strm_rlc_base = rlc_addr;
594
590
595
591
rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
596
-
reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
597
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
592
+
regs->common.stream_len = round_up(rlc_len, 16) + 64;
598
593
599
594
/* config cabac table */
600
595
offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
601
-
writel_relaxed(priv_start_addr + offset,
602
-
rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
596
+
regs->common.cabactbl_base = priv_start_addr + offset;
603
597
604
598
/* config output base address */
605
599
dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
606
-
writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
600
+
regs->common.decout_base = dst_addr;
607
601
608
-
reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
609
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
610
-
611
-
reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
612
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
602
+
regs->common.reg08.y_virstride = y_virstride / 16;
603
+
regs->common.reg09.yuv_virstride = yuv_virstride / 16;
613
604
614
605
/* config ref pic address */
615
606
for (i = 0; i < 15; i++) {
···
617
620
}
618
621
619
622
refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
620
-
writel_relaxed(refer_addr | reg,
621
-
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
622
623
623
-
reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
624
-
dpb[i].pic_order_cnt_val : 0);
625
-
writel_relaxed(reg,
626
-
rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
624
+
regs->h26x.ref0_14_base[i].base_addr = refer_addr >> 4;
625
+
regs->h26x.ref0_14_base[i].field_ref = !!(reg & 1);
626
+
regs->h26x.ref0_14_base[i].topfield_used_ref = !!(reg & 2);
627
+
regs->h26x.ref0_14_base[i].botfield_used_ref = !!(reg & 4);
628
+
regs->h26x.ref0_14_base[i].colmv_use_flag_ref = !!(reg & 8);
629
+
630
+
regs->h26x.ref0_14_poc[i] = i < decode_params->num_active_dpb_entries
631
+
? dpb[i].pic_order_cnt_val
632
+
: 0;
627
633
}
628
634
629
-
reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
630
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
635
+
regs->h26x.cur_poc = sl_params->slice_pic_order_cnt;
631
636
632
637
/* config hw pps address */
633
638
offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
634
-
writel_relaxed(priv_start_addr + offset,
635
-
rkvdec->regs + RKVDEC_REG_PPS_BASE);
639
+
regs->h26x.pps_base = priv_start_addr + offset;
636
640
637
641
/* config hw rps address */
638
642
offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
639
-
writel_relaxed(priv_start_addr + offset,
640
-
rkvdec->regs + RKVDEC_REG_RPS_BASE);
643
+
regs->h26x.rps_base = priv_start_addr + offset;
641
644
642
-
reg = RKVDEC_AXI_DDR_RDATA(0);
643
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
644
-
645
-
reg = RKVDEC_AXI_DDR_WDATA(0);
646
-
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
645
+
rkvdec_memcpy_toio(rkvdec->regs, regs,
646
+
MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs));
647
647
}
648
648
649
649
#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
···
778
784
779
785
schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
780
786
781
-
writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
782
-
writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
783
787
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
784
788
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
785
789
+355
-149
drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h
+355
-149
drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h
···
3
3
#ifndef RKVDEC_REGS_H_
4
4
#define RKVDEC_REGS_H_
5
5
6
-
/* rkvcodec registers */
6
+
#include <linux/types.h>
7
+
8
+
/*
9
+
* REG_INTERRUPT is accessed via writel to enable the decoder after
10
+
* configuring it and clear interrupt strmd_error_status
11
+
*/
7
12
#define RKVDEC_REG_INTERRUPT 0x004
8
13
#define RKVDEC_INTERRUPT_DEC_E BIT(0)
9
14
#define RKVDEC_CONFIG_DEC_CLK_GATE_E BIT(1)
···
35
30
#define RKVDEC_SOFTRESET_RDY BIT(22)
36
31
#define RKVDEC_WR_DDR_ALIGN_EN BIT(23)
37
32
38
-
#define RKVDEC_REG_SYSCTRL 0x008
39
-
#define RKVDEC_IN_ENDIAN BIT(0)
40
-
#define RKVDEC_IN_SWAP32_E BIT(1)
41
-
#define RKVDEC_IN_SWAP64_E BIT(2)
42
-
#define RKVDEC_STR_ENDIAN BIT(3)
43
-
#define RKVDEC_STR_SWAP32_E BIT(4)
44
-
#define RKVDEC_STR_SWAP64_E BIT(5)
45
-
#define RKVDEC_OUT_ENDIAN BIT(6)
46
-
#define RKVDEC_OUT_SWAP32_E BIT(7)
47
-
#define RKVDEC_OUT_CBCR_SWAP BIT(8)
48
-
#define RKVDEC_RLC_MODE_DIRECT_WRITE BIT(10)
49
-
#define RKVDEC_RLC_MODE BIT(11)
50
-
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
51
-
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
33
+
#define RKVDEC_REG_QOS_CTRL 0x18C
34
+
35
+
/*
36
+
* Cache configuration is not covered in the range of the register struct
37
+
*/
38
+
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
39
+
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
40
+
41
+
/*
42
+
* Define the mode values
43
+
*/
52
44
#define RKVDEC_MODE_HEVC 0
53
45
#define RKVDEC_MODE_H264 1
54
46
#define RKVDEC_MODE_VP9 2
55
-
#define RKVDEC_RPS_MODE BIT(24)
56
-
#define RKVDEC_STRM_MODE BIT(25)
57
-
#define RKVDEC_H264_STRM_LASTPKT BIT(26)
58
-
#define RKVDEC_H264_FIRSTSLICE_FLAG BIT(27)
59
-
#define RKVDEC_H264_FRAME_ORSLICE BIT(28)
60
-
#define RKVDEC_BUSPR_SLOT_DIS BIT(29)
61
47
62
-
#define RKVDEC_REG_PICPAR 0x00C
63
-
#define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
64
-
#define RKVDEC_SLICE_NUM_HIGHBIT BIT(11)
65
-
#define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
66
-
#define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
48
+
/* rkvcodec registers */
49
+
struct rkvdec_common_regs {
50
+
struct rkvdec_id {
51
+
u32 minor_ver : 8;
52
+
u32 level : 1;
53
+
u32 dec_support : 3;
54
+
u32 profile : 1;
55
+
u32 reserved0 : 1;
56
+
u32 codec_flag : 1;
57
+
u32 reserved1 : 1;
58
+
u32 prod_num : 16;
59
+
} reg00;
67
60
68
-
#define RKVDEC_REG_STRM_RLC_BASE 0x010
61
+
struct rkvdec_int {
62
+
u32 dec_e : 1;
63
+
u32 dec_clkgate_e : 1;
64
+
u32 dec_e_strmd_clkgate_dis : 1;
65
+
u32 timeout_mode : 1;
66
+
u32 dec_irq_dis : 1;
67
+
u32 dec_timeout_e : 1;
68
+
u32 buf_empty_en : 1;
69
+
u32 stmerror_waitdecfifo_empty : 1;
70
+
u32 dec_irq : 1;
71
+
u32 dec_irq_raw : 1;
72
+
u32 reserved2 : 2;
73
+
u32 dec_rdy_sta : 1;
74
+
u32 dec_bus_sta : 1;
75
+
u32 dec_error_sta : 1;
76
+
u32 dec_timeout_sta : 1;
77
+
u32 dec_empty_sta : 1;
78
+
u32 colmv_ref_error_sta : 1;
79
+
u32 cabu_end_sta : 1;
80
+
u32 h264orvp9_error_mode : 1;
81
+
u32 softrst_en_p : 1;
82
+
u32 force_softreset_valid : 1;
83
+
u32 softreset_rdy : 1;
84
+
u32 wr_ddr_align_en : 1;
85
+
u32 scl_down_en : 1;
86
+
u32 allow_not_wr_unref_bframe : 1;
87
+
u32 reserved1 : 6;
88
+
} reg01;
69
89
70
-
#define RKVDEC_REG_STRM_LEN 0x014
71
-
#define RKVDEC_STRM_LEN(x) ((x) & 0x7ffffff)
90
+
struct rkvdec_sysctrl {
91
+
u32 in_endian : 1;
92
+
u32 in_swap32_e : 1;
93
+
u32 in_swap64_e : 1;
94
+
u32 str_endian : 1;
95
+
u32 str_swap32_e : 1;
96
+
u32 str_swap64_e : 1;
97
+
u32 out_endian : 1;
98
+
u32 out_swap32_e : 1;
99
+
u32 out_cbcr_swap : 1;
100
+
u32 reserved0 : 1;
101
+
u32 rlc_mode_direct_write : 1;
102
+
u32 rlc_mode : 1;
103
+
u32 strm_start_bit : 7;
104
+
u32 reserved1 : 1;
105
+
u32 dec_mode : 2;
106
+
u32 reserved2 : 2;
107
+
u32 rps_mode : 1;
108
+
u32 stream_mode : 1;
109
+
u32 stream_lastpacket : 1;
110
+
u32 firstslice_flag : 1;
111
+
u32 frame_orslice : 1;
112
+
u32 buspr_slot_disable : 1;
113
+
u32 colmv_mode : 1;
114
+
u32 ycacherd_prior : 1;
115
+
} reg02;
72
116
73
-
#define RKVDEC_REG_CABACTBL_PROB_BASE 0x018
74
-
#define RKVDEC_REG_DECOUT_BASE 0x01C
117
+
struct rkvdec_picpar {
118
+
u32 y_hor_virstride : 9;
119
+
u32 reserved : 2;
120
+
u32 slice_num_highbit : 1;
121
+
u32 uv_hor_virstride : 9;
122
+
u32 slice_num_lowbits : 11;
123
+
} reg03;
75
124
76
-
#define RKVDEC_REG_Y_VIRSTRIDE 0x020
77
-
#define RKVDEC_Y_VIRSTRIDE(x) ((x) & 0xfffff)
125
+
u32 strm_rlc_base;
126
+
u32 stream_len;
127
+
u32 cabactbl_base;
128
+
u32 decout_base;
78
129
79
-
#define RKVDEC_REG_YUV_VIRSTRIDE 0x024
80
-
#define RKVDEC_YUV_VIRSTRIDE(x) ((x) & 0x1fffff)
81
-
#define RKVDEC_REG_H264_BASE_REFER(i) (((i) * 0x04) + 0x028)
130
+
struct rkvdec_y_virstride {
131
+
u32 y_virstride : 20;
132
+
u32 reserved0 : 12;
133
+
} reg08;
82
134
83
-
#define RKVDEC_REG_H264_BASE_REFER15 0x0C0
84
-
#define RKVDEC_FIELD_REF BIT(0)
85
-
#define RKVDEC_TOPFIELD_USED_REF BIT(1)
86
-
#define RKVDEC_BOTFIELD_USED_REF BIT(2)
87
-
#define RKVDEC_COLMV_USED_FLAG_REF BIT(3)
135
+
struct rkvdec_yuv_virstride {
136
+
u32 yuv_virstride : 21;
137
+
u32 reserved0 : 11;
138
+
} reg09;
139
+
} __packed;
88
140
89
-
#define RKVDEC_REG_VP9_LAST_FRAME_BASE 0x02c
90
-
#define RKVDEC_REG_VP9_GOLDEN_FRAME_BASE 0x030
91
-
#define RKVDEC_REG_VP9_ALTREF_FRAME_BASE 0x034
141
+
struct ref_base {
142
+
u32 field_ref : 1;
143
+
u32 topfield_used_ref : 1;
144
+
u32 botfield_used_ref : 1;
145
+
u32 colmv_use_flag_ref : 1;
146
+
u32 base_addr : 28;
147
+
};
92
148
93
-
#define RKVDEC_REG_VP9_CPRHEADER_OFFSET 0x028
94
-
#define RKVDEC_VP9_CPRHEADER_OFFSET(x) ((x) & 0xffff)
149
+
struct rkvdec_h26x_regs {
150
+
struct ref_base ref0_14_base[15];
151
+
u32 ref0_14_poc[15];
95
152
96
-
#define RKVDEC_REG_VP9_REFERLAST_BASE 0x02C
97
-
#define RKVDEC_REG_VP9_REFERGOLDEN_BASE 0x030
98
-
#define RKVDEC_REG_VP9_REFERALFTER_BASE 0x034
153
+
u32 cur_poc;
154
+
u32 rlcwrite_base;
155
+
u32 pps_base;
156
+
u32 rps_base;
99
157
100
-
#define RKVDEC_REG_VP9COUNT_BASE 0x038
101
-
#define RKVDEC_VP9COUNT_UPDATE_EN BIT(0)
158
+
u32 strmd_error_e;
102
159
103
-
#define RKVDEC_REG_VP9_SEGIDLAST_BASE 0x03C
104
-
#define RKVDEC_REG_VP9_SEGIDCUR_BASE 0x040
105
-
#define RKVDEC_REG_VP9_FRAME_SIZE(i) ((i) * 0x04 + 0x044)
106
-
#define RKVDEC_VP9_FRAMEWIDTH(x) (((x) & 0xffff) << 0)
107
-
#define RKVDEC_VP9_FRAMEHEIGHT(x) (((x) & 0xffff) << 16)
160
+
struct {
161
+
u32 strmd_error_status : 28;
162
+
u32 colmv_error_ref_picidx : 4;
163
+
} reg45;
108
164
109
-
#define RKVDEC_VP9_SEGID_GRP(i) ((i) * 0x04 + 0x050)
110
-
#define RKVDEC_SEGID_ABS_DELTA(x) ((x) & 0x1)
111
-
#define RKVDEC_SEGID_FRAME_QP_DELTA_EN(x) (((x) & 0x1) << 1)
112
-
#define RKVDEC_SEGID_FRAME_QP_DELTA(x) (((x) & 0x1ff) << 2)
113
-
#define RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(x) (((x) & 0x1) << 11)
114
-
#define RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(x) (((x) & 0x7f) << 12)
115
-
#define RKVDEC_SEGID_REFERINFO_EN(x) (((x) & 0x1) << 19)
116
-
#define RKVDEC_SEGID_REFERINFO(x) (((x) & 0x03) << 20)
117
-
#define RKVDEC_SEGID_FRAME_SKIP_EN(x) (((x) & 0x1) << 22)
165
+
struct {
166
+
u32 strmd_error_ctu_xoffset : 8;
167
+
u32 strmd_error_ctu_yoffset : 8;
168
+
u32 streamfifo_space2full : 7;
169
+
u32 reserved0 : 1;
170
+
u32 vp9_error_ctu0_en : 1;
171
+
u32 reserved1 : 7;
172
+
} reg46;
118
173
119
-
#define RKVDEC_VP9_CPRHEADER_CONFIG 0x070
120
-
#define RKVDEC_VP9_TX_MODE(x) ((x) & 0x07)
121
-
#define RKVDEC_VP9_FRAME_REF_MODE(x) (((x) & 0x03) << 3)
174
+
struct {
175
+
u32 saowr_xoffet : 9;
176
+
u32 reserved0 : 7;
177
+
u32 saowr_yoffset : 10;
178
+
u32 reserved1 : 6;
179
+
} reg47;
122
180
123
-
#define RKVDEC_VP9_REF_SCALE(i) ((i) * 0x04 + 0x074)
124
-
#define RKVDEC_VP9_REF_HOR_SCALE(x) ((x) & 0xffff)
125
-
#define RKVDEC_VP9_REF_VER_SCALE(x) (((x) & 0xffff) << 16)
181
+
struct ref_base ref15_base;
126
182
127
-
#define RKVDEC_VP9_REF_DELTAS_LASTFRAME 0x080
128
-
#define RKVDEC_REF_DELTAS_LASTFRAME(pos, val) (((val) & 0x7f) << ((pos) * 7))
183
+
u32 ref15_29_poc[15];
129
184
130
-
#define RKVDEC_VP9_INFO_LASTFRAME 0x084
131
-
#define RKVDEC_MODE_DELTAS_LASTFRAME(pos, val) (((val) & 0x7f) << ((pos) * 7))
132
-
#define RKVDEC_SEG_EN_LASTFRAME BIT(16)
133
-
#define RKVDEC_LAST_SHOW_FRAME BIT(17)
134
-
#define RKVDEC_LAST_INTRA_ONLY BIT(18)
135
-
#define RKVDEC_LAST_WIDHHEIGHT_EQCUR BIT(19)
136
-
#define RKVDEC_COLOR_SPACE_LASTKEYFRAME(x) (((x) & 0x07) << 20)
185
+
u32 performance_cycle;
186
+
u32 axi_ddr_rdata;
187
+
u32 axi_ddr_wdata;
137
188
138
-
#define RKVDEC_VP9_INTERCMD_BASE 0x088
189
+
struct {
190
+
u32 busifd_resetn : 1;
191
+
u32 cabac_resetn : 1;
192
+
u32 dec_ctrl_resetn : 1;
193
+
u32 transd_resetn : 1;
194
+
u32 intra_resetn : 1;
195
+
u32 inter_resetn : 1;
196
+
u32 recon_resetn : 1;
197
+
u32 filer_resetn : 1;
198
+
u32 reserved0 : 24;
199
+
} reg67;
139
200
140
-
#define RKVDEC_VP9_INTERCMD_NUM 0x08C
141
-
#define RKVDEC_INTERCMD_NUM(x) ((x) & 0xffffff)
201
+
struct {
202
+
u32 perf_cnt0_sel : 6;
203
+
u32 reserved0 : 2;
204
+
u32 perf_cnt1_sel : 6;
205
+
u32 reserved1 : 2;
206
+
u32 perf_cnt2_sel : 6;
207
+
u32 reserved2 : 10;
208
+
} reg68;
142
209
143
-
#define RKVDEC_VP9_LASTTILE_SIZE 0x090
144
-
#define RKVDEC_LASTTILE_SIZE(x) ((x) & 0xffffff)
210
+
u32 perf_cnt0;
211
+
u32 perf_cnt1;
212
+
u32 perf_cnt2;
213
+
u32 ref30_poc;
214
+
u32 ref31_poc;
215
+
u32 cur_poc1;
216
+
u32 errorinfo_base;
145
217
146
-
#define RKVDEC_VP9_HOR_VIRSTRIDE(i) ((i) * 0x04 + 0x094)
147
-
#define RKVDEC_HOR_Y_VIRSTRIDE(x) ((x) & 0x1ff)
148
-
#define RKVDEC_HOR_UV_VIRSTRIDE(x) (((x) & 0x1ff) << 16)
218
+
struct {
219
+
u32 slicedec_num : 14;
220
+
u32 reserved0 : 1;
221
+
u32 strmd_detect_error_flag : 1;
222
+
u32 error_packet_num : 14;
223
+
u32 reserved1 : 2;
224
+
} reg76;
149
225
150
-
#define RKVDEC_REG_H264_POC_REFER0(i) (((i) * 0x04) + 0x064)
151
-
#define RKVDEC_REG_H264_POC_REFER1(i) (((i) * 0x04) + 0x0C4)
152
-
#define RKVDEC_REG_H264_POC_REFER2(i) (((i) * 0x04) + 0x120)
153
-
#define RKVDEC_POC_REFER(x) ((x) & 0xffffffff)
226
+
struct {
227
+
u32 error_en_highbits : 30;
228
+
u32 strmd_error_slice_en : 1;
229
+
u32 strmd_error_frame_en : 1;
230
+
} reg77;
154
231
155
-
#define RKVDEC_REG_CUR_POC0 0x0A0
156
-
#define RKVDEC_REG_CUR_POC1 0x128
157
-
#define RKVDEC_CUR_POC(x) ((x) & 0xffffffff)
232
+
u32 colmv_cur_base;
233
+
u32 colmv_ref_base[16];
234
+
u32 scanlist_addr;
235
+
u32 reg96_sd_decout_base;
236
+
u32 sd_y_virstride;
237
+
u32 sd_hor_stride;
238
+
u32 qos_ctrl;
239
+
u32 perf[8];
240
+
u32 qos1;
241
+
} __packed;
158
242
159
-
#define RKVDEC_REG_RLCWRITE_BASE 0x0A4
160
-
#define RKVDEC_REG_PPS_BASE 0x0A8
161
-
#define RKVDEC_REG_RPS_BASE 0x0AC
243
+
struct rkvdec_vp9_regs {
244
+
struct cprheader_offset {
245
+
u32 cprheader_offset : 16;
246
+
u32 reserved : 16;
247
+
} reg10;
162
248
163
-
#define RKVDEC_REG_STRMD_ERR_EN 0x0B0
164
-
#define RKVDEC_STRMD_ERR_EN(x) ((x) & 0xffffffff)
249
+
u32 refer_bases[3];
250
+
u32 count_base;
251
+
u32 segidlast_base;
252
+
u32 segidcur_base;
165
253
166
-
#define RKVDEC_REG_STRMD_ERR_STA 0x0B4
167
-
#define RKVDEC_STRMD_ERR_STA(x) ((x) & 0xfffffff)
168
-
#define RKVDEC_COLMV_ERR_REF_PICIDX(x) (((x) & 0x0f) << 28)
254
+
struct frame_sizes {
255
+
u32 framewidth : 16;
256
+
u32 frameheight : 16;
257
+
} reg17_19[3];
169
258
170
-
#define RKVDEC_REG_STRMD_ERR_CTU 0x0B8
171
-
#define RKVDEC_STRMD_ERR_CTU(x) ((x) & 0xff)
172
-
#define RKVDEC_STRMD_ERR_CTU_YOFFSET(x) (((x) & 0xff) << 8)
173
-
#define RKVDEC_STRMFIFO_SPACE2FULL(x) (((x) & 0x7f) << 16)
174
-
#define RKVDEC_VP9_ERR_EN_CTU0 BIT(24)
259
+
struct segid_grp {
260
+
u32 segid_abs_delta : 1;
261
+
u32 segid_frame_qp_delta_en : 1;
262
+
u32 segid_frame_qp_delta : 9;
263
+
u32 segid_frame_loopfilter_value_en : 1;
264
+
u32 segid_frame_loopfilter_value : 7;
265
+
u32 segid_referinfo_en : 1;
266
+
u32 segid_referinfo : 2;
267
+
u32 segid_frame_skip_en : 1;
268
+
u32 reserved : 9;
269
+
} reg20_27[8];
175
270
176
-
#define RKVDEC_REG_SAO_CTU_POS 0x0BC
177
-
#define RKVDEC_SAOWR_XOFFSET(x) ((x) & 0x1ff)
178
-
#define RKVDEC_SAOWR_YOFFSET(x) (((x) & 0x3ff) << 16)
271
+
struct cprheader_config {
272
+
u32 tx_mode : 3;
273
+
u32 frame_reference_mode : 2;
274
+
u32 reserved : 27;
275
+
} reg28;
179
276
180
-
#define RKVDEC_VP9_LAST_FRAME_YSTRIDE 0x0C0
181
-
#define RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE 0x0C4
182
-
#define RKVDEC_VP9_ALTREF_FRAME_YSTRIDE 0x0C8
183
-
#define RKVDEC_VP9_REF_YSTRIDE(x) (((x) & 0xfffff) << 0)
277
+
struct ref_scale {
278
+
u32 ref_hor_scale : 16;
279
+
u32 ref_ver_scale : 16;
280
+
} reg29_31[3];
184
281
185
-
#define RKVDEC_VP9_LAST_FRAME_YUVSTRIDE 0x0CC
186
-
#define RKVDEC_VP9_REF_YUVSTRIDE(x) (((x) & 0x1fffff) << 0)
282
+
struct ref_deltas_lastframe {
283
+
u32 ref_deltas_lastframe0 : 7;
284
+
u32 ref_deltas_lastframe1 : 7;
285
+
u32 ref_deltas_lastframe2 : 7;
286
+
u32 ref_deltas_lastframe3 : 7;
287
+
u32 reserved : 4;
288
+
} reg32;
187
289
188
-
#define RKVDEC_VP9_REF_COLMV_BASE 0x0D0
290
+
struct info_lastframe {
291
+
u32 mode_deltas_lastframe0 : 7;
292
+
u32 mode_deltas_lastframe1 : 7;
293
+
u32 reserved0 : 2;
294
+
u32 segmentation_enable_lstframe : 1;
295
+
u32 last_show_frame : 1;
296
+
u32 last_intra_only : 1;
297
+
u32 last_widthheight_eqcur : 1;
298
+
u32 color_space_lastkeyframe : 3;
299
+
u32 reserved1 : 9;
300
+
} reg33;
189
301
190
-
#define RKVDEC_REG_PERFORMANCE_CYCLE 0x100
191
-
#define RKVDEC_PERFORMANCE_CYCLE(x) ((x) & 0xffffffff)
302
+
u32 intercmd_base;
192
303
193
-
#define RKVDEC_REG_AXI_DDR_RDATA 0x104
194
-
#define RKVDEC_AXI_DDR_RDATA(x) ((x) & 0xffffffff)
304
+
struct intercmd_num {
305
+
u32 intercmd_num : 24;
306
+
u32 reserved : 8;
307
+
} reg35;
195
308
196
-
#define RKVDEC_REG_AXI_DDR_WDATA 0x108
197
-
#define RKVDEC_AXI_DDR_WDATA(x) ((x) & 0xffffffff)
309
+
struct lasttile_size {
310
+
u32 lasttile_size : 24;
311
+
u32 reserved : 8;
312
+
} reg36;
198
313
199
-
#define RKVDEC_REG_FPGADEBUG_RESET 0x10C
200
-
#define RKVDEC_BUSIFD_RESETN BIT(0)
201
-
#define RKVDEC_CABAC_RESETN BIT(1)
202
-
#define RKVDEC_DEC_CTRL_RESETN BIT(2)
203
-
#define RKVDEC_TRANSD_RESETN BIT(3)
204
-
#define RKVDEC_INTRA_RESETN BIT(4)
205
-
#define RKVDEC_INTER_RESETN BIT(5)
206
-
#define RKVDEC_RECON_RESETN BIT(6)
207
-
#define RKVDEC_FILER_RESETN BIT(7)
314
+
struct hor_virstride {
315
+
u32 y_hor_virstride : 9;
316
+
u32 reserved0 : 7;
317
+
u32 uv_hor_virstride : 9;
318
+
u32 reserved1 : 7;
319
+
} reg37_39[3];
208
320
209
-
#define RKVDEC_REG_PERFORMANCE_SEL 0x110
210
-
#define RKVDEC_PERF_SEL_CNT0(x) ((x) & 0x3f)
211
-
#define RKVDEC_PERF_SEL_CNT1(x) (((x) & 0x3f) << 8)
212
-
#define RKVDEC_PERF_SEL_CNT2(x) (((x) & 0x3f) << 16)
321
+
u32 cur_poc;
213
322
214
-
#define RKVDEC_REG_PERFORMANCE_CNT(i) ((i) * 0x04 + 0x114)
215
-
#define RKVDEC_PERF_CNT(x) ((x) & 0xffffffff)
323
+
struct rlcwrite_base {
324
+
u32 reserved : 3;
325
+
u32 rlcwrite_base : 29;
326
+
} reg41;
216
327
217
-
#define RKVDEC_REG_H264_ERRINFO_BASE 0x12C
328
+
struct pps_base {
329
+
u32 reserved : 4;
330
+
u32 pps_base : 28;
331
+
} reg42;
218
332
219
-
#define RKVDEC_REG_H264_ERRINFO_NUM 0x130
220
-
#define RKVDEC_SLICEDEC_NUM(x) ((x) & 0x3fff)
221
-
#define RKVDEC_STRMD_DECT_ERR_FLAG BIT(15)
222
-
#define RKVDEC_ERR_PKT_NUM(x) (((x) & 0x3fff) << 16)
333
+
struct rps_base {
334
+
u32 reserved : 4;
335
+
u32 rps_base : 28;
336
+
} reg43;
223
337
224
-
#define RKVDEC_REG_H264_ERR_E 0x134
225
-
#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff)
338
+
struct strmd_error_en {
339
+
u32 strmd_error_e : 28;
340
+
u32 reserved : 4;
341
+
} reg44;
226
342
227
-
#define RKVDEC_REG_QOS_CTRL 0x18C
343
+
u32 vp9_error_info0;
228
344
229
-
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
230
-
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
345
+
struct strmd_error_ctu {
346
+
u32 strmd_error_ctu_xoffset : 8;
347
+
u32 strmd_error_ctu_yoffset : 8;
348
+
u32 streamfifo_space2full : 7;
349
+
u32 reserved0 : 1;
350
+
u32 error_ctu0_en : 1;
351
+
u32 reserved1 : 7;
352
+
} reg46;
353
+
354
+
struct sao_ctu_position {
355
+
u32 saowr_xoffet : 9;
356
+
u32 reserved0 : 7;
357
+
u32 saowr_yoffset : 10;
358
+
u32 reserved1 : 6;
359
+
} reg47;
360
+
361
+
struct ystride {
362
+
u32 virstride : 20;
363
+
u32 reserved : 12;
364
+
} reg48_50[3];
365
+
366
+
struct lastref_yuvstride {
367
+
u32 lastref_yuv_virstride : 21;
368
+
u32 reserved : 11;
369
+
} reg51;
370
+
371
+
u32 refcolmv_base;
372
+
373
+
u32 reserved0[11];
374
+
375
+
u32 performance_cycle;
376
+
u32 axi_ddr_rdata;
377
+
u32 axi_ddr_wdata;
378
+
379
+
struct fpgadebug_reset {
380
+
u32 busifd_resetn : 1;
381
+
u32 cabac_resetn : 1;
382
+
u32 dec_ctrl_resetn : 1;
383
+
u32 transd_resetn : 1;
384
+
u32 intra_resetn : 1;
385
+
u32 inter_resetn : 1;
386
+
u32 recon_resetn : 1;
387
+
u32 filer_resetn : 1;
388
+
u32 reserved : 24;
389
+
} reg67;
390
+
391
+
struct performance_sel {
392
+
u32 perf_cnt0_sel : 6;
393
+
u32 reserved0 : 2;
394
+
u32 perf_cnt1_sel : 6;
395
+
u32 reserved1 : 2;
396
+
u32 perf_cnt2_sel : 6;
397
+
u32 reserved : 10;
398
+
} reg68;
399
+
400
+
u32 perf_cnt0;
401
+
u32 perf_cnt1;
402
+
u32 perf_cnt2;
403
+
404
+
u32 reserved1[3];
405
+
406
+
u32 vp9_error_info1;
407
+
408
+
struct error_ctu1 {
409
+
u32 vp9_error_ctu1_x : 6;
410
+
u32 reserved0 : 2;
411
+
u32 vp9_error_ctu1_y : 6;
412
+
u32 reserved1 : 1;
413
+
u32 vp9_error_ctu1_en : 1;
414
+
u32 reserved2 : 16;
415
+
} reg76;
416
+
417
+
u32 reserved2;
418
+
} __packed;
419
+
420
+
struct rkvdec_regs {
421
+
struct rkvdec_common_regs common;
422
+
union {
423
+
struct rkvdec_h26x_regs h26x;
424
+
struct rkvdec_vp9_regs vp9;
425
+
};
426
+
} __packed;
231
427
232
428
#endif /* RKVDEC_REGS_H_ */
+98
-132
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
+98
-132
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
···
163
163
struct v4l2_vp9_frame_context frame_context[4];
164
164
struct rkvdec_vp9_frame_info cur;
165
165
struct rkvdec_vp9_frame_info last;
166
+
struct rkvdec_regs regs;
166
167
};
167
168
168
169
static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane)
···
348
347
init_inter_probs(ctx, run);
349
348
}
350
349
351
-
struct rkvdec_vp9_ref_reg {
352
-
u32 reg_frm_size;
353
-
u32 reg_hor_stride;
354
-
u32 reg_y_stride;
355
-
u32 reg_yuv_stride;
356
-
u32 reg_ref_base;
357
-
};
358
-
359
-
static struct rkvdec_vp9_ref_reg ref_regs[] = {
360
-
{
361
-
.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(0),
362
-
.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(0),
363
-
.reg_y_stride = RKVDEC_VP9_LAST_FRAME_YSTRIDE,
364
-
.reg_yuv_stride = RKVDEC_VP9_LAST_FRAME_YUVSTRIDE,
365
-
.reg_ref_base = RKVDEC_REG_VP9_LAST_FRAME_BASE,
366
-
},
367
-
{
368
-
.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(1),
369
-
.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(1),
370
-
.reg_y_stride = RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE,
371
-
.reg_yuv_stride = 0,
372
-
.reg_ref_base = RKVDEC_REG_VP9_GOLDEN_FRAME_BASE,
373
-
},
374
-
{
375
-
.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(2),
376
-
.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(2),
377
-
.reg_y_stride = RKVDEC_VP9_ALTREF_FRAME_YSTRIDE,
378
-
.reg_yuv_stride = 0,
379
-
.reg_ref_base = RKVDEC_REG_VP9_ALTREF_FRAME_BASE,
380
-
}
381
-
};
382
-
383
350
static struct rkvdec_decoded_buffer *
384
351
get_ref_buf(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp)
385
352
{
···
381
412
static void config_ref_registers(struct rkvdec_ctx *ctx,
382
413
const struct rkvdec_vp9_run *run,
383
414
struct rkvdec_decoded_buffer *ref_buf,
384
-
struct rkvdec_vp9_ref_reg *ref_reg)
415
+
int i)
385
416
{
386
417
unsigned int aligned_pitch, aligned_height, y_len, yuv_len;
387
-
struct rkvdec_dev *rkvdec = ctx->dev;
418
+
struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
419
+
struct rkvdec_regs *regs = &vp9_ctx->regs;
388
420
389
421
aligned_height = round_up(ref_buf->vp9.height, 64);
390
-
writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(ref_buf->vp9.width) |
391
-
RKVDEC_VP9_FRAMEHEIGHT(ref_buf->vp9.height),
392
-
rkvdec->regs + ref_reg->reg_frm_size);
422
+
regs->vp9.reg17_19[i].frameheight = ref_buf->vp9.height;
423
+
regs->vp9.reg17_19[i].framewidth = ref_buf->vp9.width;
393
424
394
-
writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0),
395
-
rkvdec->regs + ref_reg->reg_ref_base);
425
+
regs->vp9.refer_bases[i] = vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0);
396
426
397
427
if (&ref_buf->base.vb == run->base.bufs.dst)
398
428
return;
···
400
432
y_len = aligned_height * aligned_pitch;
401
433
yuv_len = (y_len * 3) / 2;
402
434
403
-
writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) |
404
-
RKVDEC_HOR_UV_VIRSTRIDE(aligned_pitch / 16),
405
-
rkvdec->regs + ref_reg->reg_hor_stride);
406
-
writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16),
407
-
rkvdec->regs + ref_reg->reg_y_stride);
435
+
regs->vp9.reg37_39[i].y_hor_virstride = aligned_pitch / 16;
436
+
regs->vp9.reg37_39[i].uv_hor_virstride = aligned_pitch / 16;
437
+
regs->vp9.reg48_50[i].virstride = y_len / 16;
408
438
409
-
if (!ref_reg->reg_yuv_stride)
410
-
return;
411
-
412
-
writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16),
413
-
rkvdec->regs + ref_reg->reg_yuv_stride);
439
+
if (!i)
440
+
regs->vp9.reg51.lastref_yuv_virstride = yuv_len / 16;
414
441
}
415
442
416
443
static void config_seg_registers(struct rkvdec_ctx *ctx, unsigned int segid)
417
444
{
418
445
struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
446
+
struct rkvdec_regs *regs = &vp9_ctx->regs;
419
447
const struct v4l2_vp9_segmentation *seg;
420
-
struct rkvdec_dev *rkvdec = ctx->dev;
421
448
s16 feature_val;
422
449
int feature_id;
423
-
u32 val = 0;
424
450
425
451
seg = vp9_ctx->last.valid ? &vp9_ctx->last.seg : &vp9_ctx->cur.seg;
426
452
feature_id = V4L2_VP9_SEG_LVL_ALT_Q;
427
453
if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) {
428
454
feature_val = seg->feature_data[segid][feature_id];
429
-
val |= RKVDEC_SEGID_FRAME_QP_DELTA_EN(1) |
430
-
RKVDEC_SEGID_FRAME_QP_DELTA(feature_val);
455
+
regs->vp9.reg20_27[segid].segid_frame_qp_delta_en = 1;
456
+
regs->vp9.reg20_27[segid].segid_frame_qp_delta = feature_val;
431
457
}
432
458
433
459
feature_id = V4L2_VP9_SEG_LVL_ALT_L;
434
460
if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) {
435
461
feature_val = seg->feature_data[segid][feature_id];
436
-
val |= RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(1) |
437
-
RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(feature_val);
462
+
regs->vp9.reg20_27[segid].segid_frame_loopfilter_value_en = 1;
463
+
regs->vp9.reg20_27[segid].segid_frame_loopfilter_value = feature_val;
438
464
}
439
465
440
466
feature_id = V4L2_VP9_SEG_LVL_REF_FRAME;
441
467
if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) {
442
468
feature_val = seg->feature_data[segid][feature_id];
443
-
val |= RKVDEC_SEGID_REFERINFO_EN(1) |
444
-
RKVDEC_SEGID_REFERINFO(feature_val);
469
+
regs->vp9.reg20_27[segid].segid_referinfo_en = 1;
470
+
regs->vp9.reg20_27[segid].segid_referinfo = feature_val;
445
471
}
446
472
447
473
feature_id = V4L2_VP9_SEG_LVL_SKIP;
448
-
if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid))
449
-
val |= RKVDEC_SEGID_FRAME_SKIP_EN(1);
474
+
regs->vp9.reg20_27[segid].segid_frame_skip_en =
475
+
v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid);
450
476
451
-
if (!segid &&
452
-
(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE))
453
-
val |= RKVDEC_SEGID_ABS_DELTA(1);
454
-
455
-
writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid));
477
+
regs->vp9.reg20_27[segid].segid_abs_delta = !segid &&
478
+
(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE);
456
479
}
457
480
458
481
static void update_dec_buf_info(struct rkvdec_decoded_buffer *buf,
···
480
521
struct rkvdec_decoded_buffer *ref_bufs[3];
481
522
struct rkvdec_decoded_buffer *dst, *last, *mv_ref;
482
523
struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
483
-
u32 val, last_frame_info = 0;
524
+
struct rkvdec_regs *regs = &vp9_ctx->regs;
484
525
const struct v4l2_vp9_segmentation *seg;
485
526
struct rkvdec_dev *rkvdec = ctx->dev;
486
527
dma_addr_t addr;
···
506
547
(V4L2_VP9_FRAME_FLAG_KEY_FRAME |
507
548
V4L2_VP9_FRAME_FLAG_INTRA_ONLY));
508
549
509
-
writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9),
510
-
rkvdec->regs + RKVDEC_REG_SYSCTRL);
550
+
regs->common.reg02.dec_mode = RKVDEC_MODE_VP9;
511
551
512
552
bit_depth = dec_params->bit_depth;
513
553
aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64);
···
518
560
uv_len = y_len / 2;
519
561
yuv_len = y_len + uv_len;
520
562
521
-
writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) |
522
-
RKVDEC_UV_HOR_VIRSTRIDE(aligned_pitch / 16),
523
-
rkvdec->regs + RKVDEC_REG_PICPAR);
524
-
writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16),
525
-
rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
526
-
writel_relaxed(RKVDEC_YUV_VIRSTRIDE(yuv_len / 16),
527
-
rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
563
+
regs->common.reg03.y_hor_virstride = aligned_pitch / 16;
564
+
regs->common.reg03.uv_hor_virstride = aligned_pitch / 16;
565
+
regs->common.reg08.y_virstride = y_len / 16;
566
+
regs->common.reg09.yuv_virstride = yuv_len / 16;
528
567
529
568
stream_len = vb2_get_plane_payload(&run->base.bufs.src->vb2_buf, 0);
530
-
writel_relaxed(RKVDEC_STRM_LEN(stream_len),
531
-
rkvdec->regs + RKVDEC_REG_STRM_LEN);
569
+
570
+
regs->common.stream_len = stream_len;
532
571
533
572
/*
534
573
* Reset count buffer, because decoder only output intra related syntax
···
543
588
vp9_ctx->cur.segmapid++;
544
589
545
590
for (i = 0; i < ARRAY_SIZE(ref_bufs); i++)
546
-
config_ref_registers(ctx, run, ref_bufs[i], &ref_regs[i]);
591
+
config_ref_registers(ctx, run, ref_bufs[i], i);
547
592
548
593
for (i = 0; i < 8; i++)
549
594
config_seg_registers(ctx, i);
550
595
551
-
writel_relaxed(RKVDEC_VP9_TX_MODE(vp9_ctx->cur.tx_mode) |
552
-
RKVDEC_VP9_FRAME_REF_MODE(dec_params->reference_mode),
553
-
rkvdec->regs + RKVDEC_VP9_CPRHEADER_CONFIG);
596
+
regs->vp9.reg28.tx_mode = vp9_ctx->cur.tx_mode;
597
+
regs->vp9.reg28.frame_reference_mode = dec_params->reference_mode;
554
598
555
599
if (!intra_only) {
556
600
const struct v4l2_vp9_loop_filter *lf;
···
560
606
else
561
607
lf = &vp9_ctx->cur.lf;
562
608
563
-
val = 0;
564
609
for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) {
565
610
delta = lf->ref_deltas[i];
566
-
val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta);
611
+
switch (i) {
612
+
case 0:
613
+
regs->vp9.reg32.ref_deltas_lastframe0 = delta;
614
+
break;
615
+
case 1:
616
+
regs->vp9.reg32.ref_deltas_lastframe1 = delta;
617
+
break;
618
+
case 2:
619
+
regs->vp9.reg32.ref_deltas_lastframe2 = delta;
620
+
break;
621
+
case 3:
622
+
regs->vp9.reg32.ref_deltas_lastframe3 = delta;
623
+
break;
624
+
}
567
625
}
568
-
569
-
writel_relaxed(val,
570
-
rkvdec->regs + RKVDEC_VP9_REF_DELTAS_LASTFRAME);
571
626
572
627
for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) {
573
628
delta = lf->mode_deltas[i];
574
-
last_frame_info |= RKVDEC_MODE_DELTAS_LASTFRAME(i,
575
-
delta);
629
+
switch (i) {
630
+
case 0:
631
+
regs->vp9.reg33.mode_deltas_lastframe0 = delta;
632
+
break;
633
+
case 1:
634
+
regs->vp9.reg33.mode_deltas_lastframe1 = delta;
635
+
break;
636
+
}
576
637
}
577
638
}
578
639
579
-
if (vp9_ctx->last.valid && !intra_only &&
580
-
vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED)
581
-
last_frame_info |= RKVDEC_SEG_EN_LASTFRAME;
640
+
regs->vp9.reg33.segmentation_enable_lstframe =
641
+
vp9_ctx->last.valid && !intra_only &&
642
+
vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED;
582
643
583
-
if (vp9_ctx->last.valid &&
584
-
vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME)
585
-
last_frame_info |= RKVDEC_LAST_SHOW_FRAME;
644
+
regs->vp9.reg33.last_show_frame =
645
+
vp9_ctx->last.valid &&
646
+
vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME;
586
647
587
-
if (vp9_ctx->last.valid &&
588
-
vp9_ctx->last.flags &
589
-
(V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY))
590
-
last_frame_info |= RKVDEC_LAST_INTRA_ONLY;
648
+
regs->vp9.reg33.last_intra_only =
649
+
vp9_ctx->last.valid &&
650
+
vp9_ctx->last.flags &
651
+
(V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY);
591
652
592
-
if (vp9_ctx->last.valid &&
593
-
last->vp9.width == dst->vp9.width &&
594
-
last->vp9.height == dst->vp9.height)
595
-
last_frame_info |= RKVDEC_LAST_WIDHHEIGHT_EQCUR;
653
+
regs->vp9.reg33.last_widthheight_eqcur =
654
+
vp9_ctx->last.valid &&
655
+
last->vp9.width == dst->vp9.width &&
656
+
last->vp9.height == dst->vp9.height;
596
657
597
-
writel_relaxed(last_frame_info,
598
-
rkvdec->regs + RKVDEC_VP9_INFO_LASTFRAME);
599
-
600
-
writel_relaxed(stream_len - dec_params->compressed_header_size -
601
-
dec_params->uncompressed_header_size,
602
-
rkvdec->regs + RKVDEC_VP9_LASTTILE_SIZE);
658
+
regs->vp9.reg36.lasttile_size =
659
+
stream_len - dec_params->compressed_header_size -
660
+
dec_params->uncompressed_header_size;
603
661
604
662
for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) {
605
663
unsigned int refw = ref_bufs[i]->vp9.width;
···
620
654
621
655
hscale = (refw << 14) / dst->vp9.width;
622
656
vscale = (refh << 14) / dst->vp9.height;
623
-
writel_relaxed(RKVDEC_VP9_REF_HOR_SCALE(hscale) |
624
-
RKVDEC_VP9_REF_VER_SCALE(vscale),
625
-
rkvdec->regs + RKVDEC_VP9_REF_SCALE(i));
657
+
658
+
regs->vp9.reg29_31[i].ref_hor_scale = hscale;
659
+
regs->vp9.reg29_31[i].ref_ver_scale = vscale;
626
660
}
627
661
628
662
addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0);
629
-
writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
663
+
regs->common.decout_base = addr;
630
664
addr = vb2_dma_contig_plane_dma_addr(&run->base.bufs.src->vb2_buf, 0);
631
-
writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
632
-
writel_relaxed(vp9_ctx->priv_tbl.dma +
633
-
offsetof(struct rkvdec_vp9_priv_tbl, probs),
634
-
rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
635
-
writel_relaxed(vp9_ctx->count_tbl.dma,
636
-
rkvdec->regs + RKVDEC_REG_VP9COUNT_BASE);
665
+
regs->common.strm_rlc_base = addr;
637
666
638
-
writel_relaxed(vp9_ctx->priv_tbl.dma +
639
-
offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
640
-
(RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid),
641
-
rkvdec->regs + RKVDEC_REG_VP9_SEGIDCUR_BASE);
642
-
writel_relaxed(vp9_ctx->priv_tbl.dma +
643
-
offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
644
-
(RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)),
645
-
rkvdec->regs + RKVDEC_REG_VP9_SEGIDLAST_BASE);
667
+
regs->common.cabactbl_base = vp9_ctx->priv_tbl.dma +
668
+
offsetof(struct rkvdec_vp9_priv_tbl, probs);
669
+
670
+
regs->vp9.count_base = vp9_ctx->count_tbl.dma;
671
+
672
+
regs->vp9.segidlast_base = vp9_ctx->priv_tbl.dma +
673
+
offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
674
+
(RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid));
675
+
676
+
regs->vp9.segidcur_base = vp9_ctx->priv_tbl.dma +
677
+
offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
678
+
(RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid);
646
679
647
680
if (!intra_only &&
648
681
!(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) &&
···
650
685
else
651
686
mv_ref = dst;
652
687
653
-
writel_relaxed(get_mv_base_addr(mv_ref),
654
-
rkvdec->regs + RKVDEC_VP9_REF_COLMV_BASE);
688
+
regs->vp9.refcolmv_base = get_mv_base_addr(mv_ref);
655
689
656
-
writel_relaxed(ctx->decoded_fmt.fmt.pix_mp.width |
657
-
(ctx->decoded_fmt.fmt.pix_mp.height << 16),
658
-
rkvdec->regs + RKVDEC_REG_PERFORMANCE_CYCLE);
690
+
regs->vp9.performance_cycle = ctx->decoded_fmt.fmt.pix_mp.width |
691
+
(ctx->decoded_fmt.fmt.pix_mp.height << 16);
692
+
693
+
regs->vp9.reg44.strmd_error_e = 0xe;
694
+
695
+
rkvdec_memcpy_toio(rkvdec->regs, regs,
696
+
MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs));
659
697
}
660
698
661
699
static int validate_dec_params(struct rkvdec_ctx *ctx,
···
790
822
791
823
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
792
824
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
793
-
794
-
writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
795
825
796
826
if (rkvdec->variant->quirks & RKVDEC_QUIRK_DISABLE_QOS)
797
827
rkvdec_quirks_disable_qos(ctx);
+9
-1
drivers/media/platform/rockchip/rkvdec/rkvdec.c
+9
-1
drivers/media/platform/rockchip/rkvdec/rkvdec.c
···
914
914
writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
915
915
}
916
916
917
+
void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len)
918
+
{
919
+
#ifdef CONFIG_ARM64
920
+
__iowrite32_copy(dst, src, len / 4);
921
+
#else
922
+
memcpy_toio(dst, src, len);
923
+
#endif
924
+
}
925
+
917
926
static void rkvdec_device_run(void *priv)
918
927
{
919
928
struct rkvdec_ctx *ctx = priv;
···
1236
1227
if (ctx) {
1237
1228
dev_err(rkvdec->dev, "Frame processing timed out!\n");
1238
1229
writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
1239
-
writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
1240
1230
rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
1241
1231
}
1242
1232
}
+1
drivers/media/platform/rockchip/rkvdec/rkvdec.h
+1
drivers/media/platform/rockchip/rkvdec/rkvdec.h
···
151
151
152
152
void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
153
153
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
154
+
void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len);
154
155
155
156
void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx);
156
157