tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

perf c2c: Update documentation for adding memory event table

Users may occasionally need to see which options are applied to memory
events.

This helps to understand the behavior of "perf c2c" and "perf mem", and
provides guidance for configuring memory event options directly.

Add a table to track memory events and their corresponding options, and
include the Arm SPE events in it.

Suggested-by: Al Grant <al.grant@arm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

authored by

Leo Yan and committed by
Arnaldo Carvalho de Melo dc7fb075 e524dda4

+36 -13
+36 -13
tools/perf/Documentation/perf-c2c.txt
··· 160 160 161 161 -W,-d,--phys-data,--sample-cpu 162 162 163 - Unless specified otherwise with '-e' option, following events are monitored by 164 - default on Intel: 163 + The following table lists the events monitored on different architectures. 164 + Unless specified otherwise with the -e option, the tool will select the 165 + default events. 165 166 166 - cpu/mem-loads,ldlat=30/P 167 - cpu/mem-stores/P 168 - 169 - following on AMD: 170 - 171 - ibs_op// 172 - 173 - and following on PowerPC: 174 - 175 - cpu/mem-loads/ 176 - cpu/mem-stores/ 167 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 168 + | Arch | Configuration | Options | Events | 169 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 170 + | Intel | Default | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | 171 + | | | -e ldlat-stores | cpu/mem-stores/P | 172 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 173 + | | Load only | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | 174 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 175 + | | Store only | -e ldlat-stores | cpu/mem-stores/P | 176 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 177 + | Intel | Default | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | 178 + | with | | -e ldlat-stores | cpu/mem-stores/P | 179 + | AUX |--------------+------------------+--------------------------------------------------------------------------------+ 180 + | | Load only | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | 181 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 182 + | | Store only | -e ldlat-stores | cpu/mem-stores/P | 183 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 184 + | AMD | Default | -e mem-ldst | ibs_op// (without latency support) | 185 + | | | | ibs_op/ldlat=30/ (with latency support) | 186 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 187 + | PowerPC| Default | -e ldlat-loads | cpu/mem-loads/ | 188 + | | | -e ldlat-stores | cpu/mem-stores/ | 189 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 190 + | | Load only | -e ldlat-loads | cpu/mem-loads/ | 191 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 192 + | | Store only | -e ldlat-stores | cpu/mem-stores/ | 193 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 194 + | Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=30/ | 195 + | SPE |---------------+-----------------+--------------------------------------------------------------------------------+ 196 + | | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/ | 197 + | |---------------+-----------------+--------------------------------------------------------------------------------+ 198 + | | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ | 199 + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 177 200 178 201 User can pass any 'perf record' option behind '--' mark, like (to enable 179 202 callchains and system wide monitoring):