Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/vcn: custom video info caps for sriov
for sriov, we added a new flag to indicate av1 support,
this will override the original caps info.
Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Jane Jian
and committed by
Alex Deucher
dcaf5000
0fb44d54
+99
-11
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
···
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AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
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/* Indirect Reg Access enabled */
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AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
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/* AV1 Support MODE*/
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AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
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};
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enum AMDGIM_REG_ACCESS_FLAG {
···
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((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
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#define amdgpu_sriov_is_normal(adev) \
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((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
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#define amdgpu_sriov_is_av1_support(adev) \
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((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+93
-10
drivers/gpu/drm/amd/amdgpu/soc21.c
+93
-10
drivers/gpu/drm/amd/amdgpu/soc21.c
···
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.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
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};
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/* SRIOV SOC21, not const since data is controlled by host */
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static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
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};
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static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
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};
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+
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static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
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.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
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.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
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};
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static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
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.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
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.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
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};
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static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
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};
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+
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static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
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};
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static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
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.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
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.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
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};
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static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
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.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
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.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
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};
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static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
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const struct amdgpu_video_codecs **codecs)
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{
···
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case IP_VERSION(4, 0, 0):
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case IP_VERSION(4, 0, 2):
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case IP_VERSION(4, 0, 4):
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if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
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if (encode)
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*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
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else
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*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
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if (amdgpu_sriov_vf(adev)) {
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if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
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!amdgpu_sriov_is_av1_support(adev)) {
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if (encode)
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*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
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else
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*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
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} else {
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if (encode)
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*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
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else
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*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
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}
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} else {
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if (encode)
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*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
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else
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*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
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if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
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if (encode)
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*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
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else
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*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
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} else {
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if (encode)
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*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
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else
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*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
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}
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}
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return 0;
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default:
···
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (amdgpu_sriov_vf(adev))
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if (amdgpu_sriov_vf(adev)) {
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xgpu_nv_mailbox_get_irq(adev);
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if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
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!amdgpu_sriov_is_av1_support(adev)) {
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amdgpu_virt_update_sriov_video_codec(adev,
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sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
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ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
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sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
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ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
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} else {
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amdgpu_virt_update_sriov_video_codec(adev,
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sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
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ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
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sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
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ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
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}
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}
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return 0;
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}