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coresight-etm4x: Conditionally access register TRCEXTINSELR

The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
To avoid invalid accesses, introduce a check on numextinsel
(derived from TRCIDR5[11:9]) before reading or writing to this register.

Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses")
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250812-trcextinselr_issue-v2-1-e6eb121dfcf4@oss.qualcomm.com

authored by

Yuanfang Zhang and committed by
Suzuki K Poulose dcdc42f5 21dd3f8b

+10 -3
+8 -3
drivers/hwtracing/coresight/coresight-etm4x-core.c
··· 529 529 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); 530 530 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); 531 531 } 532 - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 532 + if (drvdata->numextinsel) 533 + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 533 534 for (i = 0; i < drvdata->nr_cntr; i++) { 534 535 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); 535 536 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); ··· 1425 1424 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); 1426 1425 /* NUMEXTIN, bits[8:0] number of external inputs implemented */ 1427 1426 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); 1427 + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); 1428 1428 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ 1429 1429 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); 1430 1430 /* ATBTRIG, bit[22] implementation can support ATB triggers? */ ··· 1855 1853 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); 1856 1854 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); 1857 1855 } 1858 - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1856 + 1857 + if (drvdata->numextinsel) 1858 + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1859 1859 1860 1860 for (i = 0; i < drvdata->nr_cntr; i++) { 1861 1861 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); ··· 1989 1985 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); 1990 1986 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); 1991 1987 } 1992 - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 1988 + if (drvdata->numextinsel) 1989 + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 1993 1990 1994 1991 for (i = 0; i < drvdata->nr_cntr; i++) { 1995 1992 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
+2
drivers/hwtracing/coresight/coresight-etm4x.h
··· 162 162 #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) 163 163 164 164 #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) 165 + #define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) 165 166 #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) 166 167 #define TRCIDR5_ATBTRIG BIT(22) 167 168 #define TRCIDR5_LPOVERRIDE BIT(23) ··· 1000 999 u8 nr_cntr; 1001 1000 u8 nr_ext_inp; 1002 1001 u8 numcidc; 1002 + u8 numextinsel; 1003 1003 u8 numvmidc; 1004 1004 u8 nrseqstate; 1005 1005 u8 nr_event;