+13 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 2690 2690 break; 2691 2691 default: 2692 2692 r = amdgpu_discovery_set_ip_blocks(adev); 2693 2693 - if (r) 2693 2693 + if (r) { 2694 2694 + adev->num_ip_blocks = 0; 2694 2695 return r; 2696 2696 + } 2695 2697 break; 2696 2698 } 2697 2699 ··· 3249 3247 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; 3250 3248 if (!adev->ip_blocks[i].status.late_initialized) 3251 3249 continue; 3250 3250 + if (!adev->ip_blocks[i].version) 3251 3251 + continue; 3252 3252 /* skip CG for GFX, SDMA on S0ix */ 3253 3253 if (adev->in_s0ix && 3254 3254 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || ··· 3289 3285 for (j = 0; j < adev->num_ip_blocks; j++) { 3290 3286 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; 3291 3287 if (!adev->ip_blocks[i].status.late_initialized) 3288 3288 + continue; 3289 3289 + if (!adev->ip_blocks[i].version) 3292 3290 continue; 3293 3291 /* skip PG for GFX, SDMA on S0ix */ 3294 3292 if (adev->in_s0ix && ··· 3499 3493 int i, r; 3500 3494 3501 3495 for (i = 0; i < adev->num_ip_blocks; i++) { 3496 3496 + if (!adev->ip_blocks[i].version) 3497 3497 + continue; 3502 3498 if (!adev->ip_blocks[i].version->funcs->early_fini) 3503 3499 continue; 3504 3500 ··· 3578 3570 if (!adev->ip_blocks[i].status.sw) 3579 3571 continue; 3580 3572 3573 3573 + if (!adev->ip_blocks[i].version) 3574 3574 + continue; 3581 3575 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { 3582 3576 amdgpu_ucode_free_bo(adev); 3583 3577 amdgpu_free_static_csa(&adev->virt.csa_obj); ··· 3605 3595 3606 3596 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 3607 3597 if (!adev->ip_blocks[i].status.late_initialized) 3598 3598 + continue; 3599 3599 + if (!adev->ip_blocks[i].version) 3608 3600 continue; 3609 3601 if (adev->ip_blocks[i].version->funcs->late_fini) 3610 3602 adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

reviewed

··· 83 83 { 84 84 struct amdgpu_device *adev = drm_to_adev(dev); 85 85 86 86 - if (adev == NULL) 86 86 + if (adev == NULL || !adev->num_ip_blocks) 87 87 return; 88 88 89 89 amdgpu_unregister_gpu_instance(adev);

+8 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

reviewed

··· 368 368 369 369 struct drm_property *plane_ctm_property; 370 370 /** 371 371 - * @shaper_lut_property: Plane property to set pre-blending shaper LUT 372 372 - * that converts color content before 3D LUT. If 373 373 - * plane_shaper_tf_property != Identity TF, AMD color module will 371 371 + * @plane_shaper_lut_property: Plane property to set pre-blending 372 372 + * shaper LUT that converts color content before 3D LUT. 373 373 + * If plane_shaper_tf_property != Identity TF, AMD color module will 374 374 * combine the user LUT values with pre-defined TF into the LUT 375 375 * parameters to be programmed. 376 376 */ 377 377 struct drm_property *plane_shaper_lut_property; 378 378 /** 379 379 - * @shaper_lut_size_property: Plane property for the size of 379 379 + * @plane_shaper_lut_size_property: Plane property for the size of 380 380 * pre-blending shaper LUT as supported by the driver (read-only). 381 381 */ 382 382 struct drm_property *plane_shaper_lut_size_property; ··· 400 400 */ 401 401 struct drm_property *plane_lut3d_property; 402 402 /** 403 403 - * @plane_degamma_lut_size_property: Plane property to define the max 404 404 - * size of 3D LUT as supported by the driver (read-only). The max size 405 405 - * is the max size of one dimension and, therefore, the max number of 406 406 - * entries for 3D LUT array is the 3D LUT size cubed; 403 403 + * @plane_lut3d_size_property: Plane property to define the max size 404 404 + * of 3D LUT as supported by the driver (read-only). The max size is 405 405 + * the max size of one dimension and, therefore, the max number of 406 406 + * entries for 3D LUT array is the 3D LUT size cubed. 407 407 */ 408 408 struct drm_property *plane_lut3d_size_property; 409 409 /**

+4 -1

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

reviewed

··· 731 731 int i; 732 732 struct amdgpu_device *adev = mes->adev; 733 733 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 734 734 + uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ? 735 735 + (mes->sched_version & AMDGPU_MES_VERSION_MASK) : 736 736 + (mes->kiq_version & AMDGPU_MES_VERSION_MASK); 734 737 735 738 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 736 739 ··· 788 785 * handling support, other queue will not use the oversubscribe timer. 789 786 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 790 787 */ 791 791 - mes_set_hw_res_pkt.oversubscription_timer = 50; 788 788 + mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50; 792 789 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 793 790 794 791 if (amdgpu_mes_log_enable) {

+1

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

reviewed

··· 593 593 p->queue_size)) { 594 594 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 595 595 p->queue_address, p->queue_size); 596 596 + amdgpu_bo_unreserve(vm->root.bo); 596 597 return -EFAULT; 597 598 } 598 599

+5 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

reviewed

··· 38 38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ 39 39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ 40 40 SR(DISPCLK_FREQ_CHANGE_CNTL),\ 41 41 - SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 41 41 + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 42 42 + SR(MICROSECOND_TIME_BASE_DIV),\ 43 43 + SR(MILLISECOND_TIME_BASE_DIV),\ 44 44 + SR(DCCG_GATE_DISABLE_CNTL),\ 45 45 + SR(DCCG_GATE_DISABLE_CNTL2) 42 46 43 47 #define DCCG_REG_LIST_DCN2() \ 44 48 DCCG_COMMON_REG_LIST_DCN_BASE(),\

+20 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

reviewed

··· 96 96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; 97 97 } 98 98 99 99 + /* 100 100 + * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to 101 101 + * 0x00120464 as a marker that golden init has already been done. 102 102 + * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init() 103 103 + * to decide whether to skip golden init. 104 104 + * 105 105 + * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to 106 106 + * 0x00120264, destroying the marker before it can be read. 107 107 + * 108 108 + * Guard the call: if the S0i3 marker is present, skip dccg2_init() so the 109 109 + * WA can function correctly. bios_golden_init() will handle init in that case. 110 110 + */ 111 111 + static void dccg21_init(struct dccg *dccg) 112 112 + { 113 113 + if (dccg2_is_s0i3_golden_init_wa_done(dccg)) 114 114 + return; 115 115 + 116 116 + dccg2_init(dccg); 117 117 + } 99 118 100 119 static const struct dccg_funcs dccg21_funcs = { 101 120 .update_dpp_dto = dccg21_update_dpp_dto, ··· 122 103 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 123 104 .otg_add_pixel = dccg2_otg_add_pixel, 124 105 .otg_drop_pixel = dccg2_otg_drop_pixel, 125 125 - .dccg_init = dccg2_init, 106 106 + .dccg_init = dccg21_init, 126 107 .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ 127 108 .allow_clock_gating = dccg2_allow_clock_gating, 128 109 .enable_memory_low_power = dccg2_enable_memory_low_power,

+7 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h

reviewed

··· 34 34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 35 35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ 36 36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ 37 37 - SR(REFCLK_CNTL) 37 37 + SR(REFCLK_CNTL),\ 38 38 + SR(DISPCLK_FREQ_CHANGE_CNTL),\ 39 39 + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 40 40 + SR(MICROSECOND_TIME_BASE_DIV),\ 41 41 + SR(MILLISECOND_TIME_BASE_DIV),\ 42 42 + SR(DCCG_GATE_DISABLE_CNTL),\ 43 43 + SR(DCCG_GATE_DISABLE_CNTL2) 38 44 39 45 #define DCCG_MASK_SH_LIST_DCN301(mask_sh) \ 40 46 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\

+4 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

reviewed

··· 64 64 SR(DSCCLK1_DTO_PARAM),\ 65 65 SR(DSCCLK2_DTO_PARAM),\ 66 66 SR(DSCCLK_DTO_CTRL),\ 67 67 + SR(DCCG_GATE_DISABLE_CNTL),\ 67 68 SR(DCCG_GATE_DISABLE_CNTL2),\ 68 69 SR(DCCG_GATE_DISABLE_CNTL3),\ 69 69 - SR(HDMISTREAMCLK0_DTO_PARAM) 70 70 + SR(HDMISTREAMCLK0_DTO_PARAM),\ 71 71 + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 72 72 + SR(MICROSECOND_TIME_BASE_DIV) 70 73 71 74 72 75 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \

+4 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

reviewed

··· 70 70 SR(DSCCLK2_DTO_PARAM),\ 71 71 SR(DSCCLK3_DTO_PARAM),\ 72 72 SR(DSCCLK_DTO_CTRL),\ 73 73 + SR(DCCG_GATE_DISABLE_CNTL),\ 73 74 SR(DCCG_GATE_DISABLE_CNTL2),\ 74 75 SR(DCCG_GATE_DISABLE_CNTL3),\ 75 76 SR(HDMISTREAMCLK0_DTO_PARAM),\ 76 77 SR(OTG_PIXEL_RATE_DIV),\ 77 77 - SR(DTBCLK_P_CNTL) 78 78 + SR(DTBCLK_P_CNTL),\ 79 79 + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 80 80 + SR(MICROSECOND_TIME_BASE_DIV) 78 81 79 82 #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ 80 83 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

reviewed

··· 2222 2222 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | 2223 2223 BIT(PP_OD_FEATURE_UCLK_BIT) | 2224 2224 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | 2225 2225 - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 2225 2225 + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | 2226 2226 + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 2226 2227 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table); 2227 2228 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 2228 2229 if (res == 0)

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

reviewed

··· 2224 2224 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | 2225 2225 BIT(PP_OD_FEATURE_UCLK_BIT) | 2226 2226 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | 2227 2227 - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 2227 2227 + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | 2228 2228 + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 2228 2229 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table); 2229 2230 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 2230 2231 if (res == 0)

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

reviewed

··· 2311 2311 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | 2312 2312 BIT(PP_OD_FEATURE_UCLK_BIT) | 2313 2313 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | 2314 2314 - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 2314 2314 + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | 2315 2315 + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 2315 2316 res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table); 2316 2317 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 2317 2318 if (res == 0)