Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*()
The underscore prefixed masked field helper names aren't great. Rename
them REG_MASKED_FIELD(), REG_MASKED_FIELD_ENABLE(), and
REG_MASKED_FIELD_DISABLE(). This is more in line with the existing
REG_FIELD_PREP() etc. helpers, and using "field" instead of "bit" is
more accurate for the functionality.
This is done with:
sed -i 's/_MASKED_FIELD/REG_MASKED_FIELD/g' $(git grep -wl _MASKED_FIELD)
sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE)
sed -i 's/_MASKED_BIT_DISABLE/REG_MASKED_FIELD_DISABLE/g' $(git grep -wl _MASKED_BIT_DISABLE)
with some manual indentation fixes on top.
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/49dc20448a12f3e03f5f8347540d167a281b8987.1772042022.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+164
-167
+4
-4
drivers/gpu/drm/i915/display/i9xx_wm.c
+4
-4
drivers/gpu/drm/i915/display/i9xx_wm.c
···
182
182
intel_de_posting_read(display, DSPFW3(display));
183
183
} else if (display->platform.i945g || display->platform.i945gm) {
184
184
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
185
-
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
186
-
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
185
+
val = enable ? REG_MASKED_FIELD_ENABLE(FW_BLC_SELF_EN) :
186
+
REG_MASKED_FIELD_DISABLE(FW_BLC_SELF_EN);
187
187
intel_de_write(display, FW_BLC_SELF, val);
188
188
intel_de_posting_read(display, FW_BLC_SELF);
189
189
} else if (display->platform.i915gm) {
···
193
193
* FW_BLC_SELF. What's going on?
194
194
*/
195
195
was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
196
-
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
197
-
_MASKED_BIT_DISABLE(INSTPM_SELF_EN);
196
+
val = enable ? REG_MASKED_FIELD_ENABLE(INSTPM_SELF_EN) :
197
+
REG_MASKED_FIELD_DISABLE(INSTPM_SELF_EN);
198
198
intel_de_write(display, INSTPM, val);
199
199
intel_de_posting_read(display, INSTPM);
200
200
} else {
+2
-2
drivers/gpu/drm/i915/display/intel_display_irq.c
+2
-2
drivers/gpu/drm/i915/display/intel_display_irq.c
···
1619
1619
*/
1620
1620
if (display->irq.vblank_enabled++ == 0)
1621
1621
intel_de_write(display, SCPD0,
1622
-
_MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1622
+
REG_MASKED_FIELD_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1623
1623
}
1624
1624
1625
1625
static void i915gm_irq_cstate_wa_disable(struct intel_display *display)
···
1628
1628
1629
1629
if (--display->irq.vblank_enabled == 0)
1630
1630
intel_de_write(display, SCPD0,
1631
-
_MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1631
+
REG_MASKED_FIELD_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1632
1632
}
1633
1633
1634
1634
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
+1
-1
drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+1
-1
drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+5
-5
drivers/gpu/drm/i915/gt/intel_engine_cs.c
+5
-5
drivers/gpu/drm/i915/gt/intel_engine_cs.c
···
1233
1233
engine->class == VIDEO_ENHANCEMENT_CLASS ||
1234
1234
engine->class == COMPUTE_CLASS ||
1235
1235
engine->class == OTHER_CLASS))
1236
-
engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
1236
+
engine->tlb_inv.request = REG_MASKED_FIELD_ENABLE(val);
1237
1237
else
1238
1238
engine->tlb_inv.request = val;
1239
1239
···
1628
1628
const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1629
1629
int err;
1630
1630
1631
-
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1631
+
intel_uncore_write_fw(uncore, mode, REG_MASKED_FIELD_ENABLE(STOP_RING));
1632
1632
1633
1633
/*
1634
1634
* Wa_22011802037: Prior to doing a reset, ensure CS is
···
1636
1636
*/
1637
1637
if (intel_engine_reset_needs_wa_22011802037(engine->gt))
1638
1638
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1639
-
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1639
+
REG_MASKED_FIELD_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1640
1640
1641
1641
err = __intel_wait_for_register_fw(engine->uncore, mode,
1642
1642
MODE_IDLE, MODE_IDLE,
···
1692
1692
{
1693
1693
ENGINE_TRACE(engine, "\n");
1694
1694
1695
-
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1695
+
ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING));
1696
1696
}
1697
1697
1698
1698
static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
···
2552
2552
return;
2553
2553
2554
2554
intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2555
-
_MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2555
+
REG_MASKED_FIELD_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2556
2556
}
2557
2557
2558
2558
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+1
-1
drivers/gpu/drm/i915/gt/intel_engine_pm.c
+1
-1
drivers/gpu/drm/i915/gt/intel_engine_pm.c
···
24
24
if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
25
25
intel_uncore_write(engine->gt->uncore,
26
26
RC_PSMI_CTRL_GSCCS,
27
-
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
27
+
REG_MASKED_FIELD_DISABLE(IDLE_MSG_DISABLE));
28
28
/* hysteresis 0xA=5us as recommended in spec*/
29
29
intel_uncore_write(engine->gt->uncore,
30
30
PWRCTX_MAXCNT_GSCCS,
+3
-3
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+3
-3
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
···
2934
2934
intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
2935
2935
2936
2936
if (GRAPHICS_VER(engine->i915) >= 11)
2937
-
mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
2937
+
mode = REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
2938
2938
else
2939
-
mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
2939
+
mode = REG_MASKED_FIELD_ENABLE(GFX_RUN_LIST_ENABLE);
2940
2940
ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
2941
2941
2942
-
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
2942
+
ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING));
2943
2943
2944
2944
ENGINE_WRITE_FW(engine,
2945
2945
RING_HWS_PGA,
+3
-3
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+3
-3
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
···
916
916
if (GRAPHICS_VER(i915) == 6)
917
917
intel_uncore_write(uncore,
918
918
ARB_MODE,
919
-
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
919
+
REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_SNB));
920
920
else if (GRAPHICS_VER(i915) == 7)
921
921
intel_uncore_write(uncore,
922
922
ARB_MODE,
923
-
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
923
+
REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_IVB));
924
924
else if (GRAPHICS_VER(i915) == 8)
925
925
intel_uncore_write(uncore,
926
926
GAMTARBMODE,
927
-
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
927
+
REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_BDW));
928
928
else
929
929
MISSING_CASE(GRAPHICS_VER(i915));
930
930
}
+9
-9
drivers/gpu/drm/i915/gt/intel_lrc.c
+9
-9
drivers/gpu/drm/i915/gt/intel_lrc.c
···
846
846
u32 ctl;
847
847
int loc;
848
848
849
-
ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
850
-
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
849
+
ctl = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
850
+
ctl |= REG_MASKED_FIELD_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
851
851
if (inhibit)
852
852
ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
853
853
if (GRAPHICS_VER(engine->i915) < 11)
854
-
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
855
-
CTX_CTRL_RS_CTX_ENABLE);
854
+
ctl |= REG_MASKED_FIELD_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
855
+
CTX_CTRL_RS_CTX_ENABLE);
856
856
/* Wa_14019159160 - Case 2.*/
857
857
if (ctx_needs_runalone(ce))
858
-
ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);
858
+
ctl |= REG_MASKED_FIELD_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);
859
859
regs[CTX_CONTEXT_CONTROL] = ctl;
860
860
861
861
regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
···
1344
1344
{
1345
1345
*cs++ = MI_LOAD_REGISTER_IMM(1);
1346
1346
*cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
1347
-
*cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
1347
+
*cs++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
1348
1348
return cs;
1349
1349
}
1350
1350
···
1736
1736
/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1737
1737
{
1738
1738
COMMON_SLICE_CHICKEN2,
1739
-
_MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE),
1739
+
REG_MASKED_FIELD_DISABLE(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE),
1740
1740
},
1741
1741
1742
1742
/* BSpec: 11391 */
1743
1743
{
1744
1744
FF_SLICE_CHICKEN,
1745
-
_MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1745
+
REG_MASKED_FIELD_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1746
1746
},
1747
1747
1748
1748
/* BSpec: 11299 */
1749
1749
{
1750
1750
_3D_CHICKEN3,
1751
-
_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1751
+
REG_MASKED_FIELD_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1752
1752
}
1753
1753
};
1754
1754
+11
-11
drivers/gpu/drm/i915/gt/intel_rc6.c
+11
-11
drivers/gpu/drm/i915/gt/intel_rc6.c
···
378
378
379
379
/* Allows RC6 residency counter to work */
380
380
intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
381
-
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
382
-
VLV_MEDIA_RC6_COUNT_EN |
383
-
VLV_RENDER_RC6_COUNT_EN));
381
+
REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH |
382
+
VLV_MEDIA_RC6_COUNT_EN |
383
+
VLV_RENDER_RC6_COUNT_EN));
384
384
385
385
/* 3: Enable RC6 */
386
386
rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
···
403
403
404
404
/* Allows RC6 residency counter to work */
405
405
intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
406
-
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
407
-
VLV_MEDIA_RC0_COUNT_EN |
408
-
VLV_RENDER_RC0_COUNT_EN |
409
-
VLV_MEDIA_RC6_COUNT_EN |
410
-
VLV_RENDER_RC6_COUNT_EN));
406
+
REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH |
407
+
VLV_MEDIA_RC0_COUNT_EN |
408
+
VLV_RENDER_RC0_COUNT_EN |
409
+
VLV_MEDIA_RC6_COUNT_EN |
410
+
VLV_RENDER_RC6_COUNT_EN));
411
411
412
412
rc6->ctl_enable =
413
413
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
···
763
763
* set the high bit to be safe.
764
764
*/
765
765
intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
766
-
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
766
+
REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH));
767
767
upper = intel_uncore_read_fw(uncore, reg);
768
768
do {
769
769
tmp = upper;
770
770
771
771
intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
772
-
_MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
772
+
REG_MASKED_FIELD_DISABLE(VLV_COUNT_RANGE_HIGH));
773
773
lower = intel_uncore_read_fw(uncore, reg);
774
774
775
775
intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
776
-
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
776
+
REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH));
777
777
upper = intel_uncore_read_fw(uncore, reg);
778
778
} while (upper != tmp && --loop);
779
779
+2
-2
drivers/gpu/drm/i915/gt/intel_reset.c
+2
-2
drivers/gpu/drm/i915/gt/intel_reset.c
···
586
586
return 0;
587
587
}
588
588
589
-
intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
589
+
intel_uncore_write_fw(uncore, reg, REG_MASKED_FIELD_ENABLE(request));
590
590
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
591
591
700, 0, NULL);
592
592
if (ret)
···
602
602
{
603
603
intel_uncore_write_fw(engine->uncore,
604
604
RING_RESET_CTL(engine->mmio_base),
605
-
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
605
+
REG_MASKED_FIELD_DISABLE(RESET_CTL_REQUEST_RESET));
606
606
}
607
607
608
608
static int gen8_reset_engines(struct intel_gt *gt,
+8
-11
drivers/gpu/drm/i915/gt/intel_ring_submission.c
+8
-11
drivers/gpu/drm/i915/gt/intel_ring_submission.c
···
128
128
engine->name);
129
129
130
130
ENGINE_WRITE_FW(engine, RING_INSTPM,
131
-
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
132
-
INSTPM_SYNC_FLUSH));
131
+
REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE | INSTPM_SYNC_FLUSH));
133
132
if (__intel_wait_for_register_fw(engine->uncore,
134
133
RING_INSTPM(engine->mmio_base),
135
134
INSTPM_SYNC_FLUSH, 0,
···
171
172
if (GRAPHICS_VER(engine->i915) >= 7) {
172
173
ENGINE_WRITE_FW(engine,
173
174
RING_MODE_GEN7,
174
-
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
175
+
REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE));
175
176
}
176
177
}
177
178
···
275
276
276
277
if (GRAPHICS_VER(engine->i915) > 2) {
277
278
ENGINE_WRITE_FW(engine,
278
-
RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
279
+
RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING));
279
280
ENGINE_POSTING_READ(engine, RING_MI_MODE);
280
281
}
281
282
···
718
719
719
720
*cs++ = MI_LOAD_REGISTER_IMM(1);
720
721
*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
721
-
*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
722
+
*cs++ = REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE);
722
723
723
724
intel_ring_advance(rq, cs);
724
725
···
767
768
768
769
*cs++ = i915_mmio_reg_offset(
769
770
RING_PSMI_CTL(signaller->mmio_base));
770
-
*cs++ = _MASKED_BIT_ENABLE(
771
-
GEN6_PSMI_SLEEP_MSG_DISABLE);
771
+
*cs++ = REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
772
772
}
773
773
}
774
774
} else if (GRAPHICS_VER(i915) == 5) {
···
820
822
821
823
last_reg = RING_PSMI_CTL(signaller->mmio_base);
822
824
*cs++ = i915_mmio_reg_offset(last_reg);
823
-
*cs++ = _MASKED_BIT_DISABLE(
824
-
GEN6_PSMI_SLEEP_MSG_DISABLE);
825
+
*cs++ = REG_MASKED_FIELD_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
825
826
}
826
827
827
828
/* Insert a delay before the next switch! */
···
1052
1055
* will then assume that it is busy and bring it out of rc6.
1053
1056
*/
1054
1057
intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1055
-
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1058
+
REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1056
1059
1057
1060
/* Clear the context id. Here be magic! */
1058
1061
intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
···
1073
1076
* and so let it sleep to conserve power when idle.
1074
1077
*/
1075
1078
intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1076
-
_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1079
+
REG_MASKED_FIELD_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
1077
1080
1078
1081
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1079
1082
}
+12
-12
drivers/gpu/drm/i915/gt/intel_workarounds.c
+12
-12
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
300
300
static void
301
301
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
302
302
{
303
-
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
303
+
wa_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true);
304
304
}
305
305
306
306
static void
307
307
wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
308
308
{
309
-
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
309
+
wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true);
310
310
}
311
311
312
312
static void
313
313
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
314
314
{
315
-
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
315
+
wa_add(wal, reg, 0, REG_MASKED_FIELD_DISABLE(val), val, true);
316
316
}
317
317
318
318
static void
319
319
wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
320
320
{
321
-
wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
321
+
wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD_DISABLE(val), val, true);
322
322
}
323
323
324
324
static void
325
325
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
326
326
u32 mask, u32 val)
327
327
{
328
-
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
328
+
wa_add(wal, reg, 0, REG_MASKED_FIELD(mask, val), mask, true);
329
329
}
330
330
331
331
static void
332
332
wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
333
333
u32 mask, u32 val)
334
334
{
335
-
wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
335
+
wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD(mask, val), mask, true);
336
336
}
337
337
338
338
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
···
666
666
667
667
/* WaEnableFloatBlendOptimization:icl */
668
668
wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
669
-
_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
669
+
REG_MASKED_FIELD_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
670
670
0 /* write-only, so skip validation */,
671
671
true);
672
672
···
1131
1131
1132
1132
wa_add(wal,
1133
1133
HSW_ROW_CHICKEN3, 0,
1134
-
_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
1134
+
REG_MASKED_FIELD_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
1135
1135
0 /* XXX does this reg exist? */, true);
1136
1136
1137
1137
/* WaVSRefCountFullforceMissDisable:hsw */
···
2272
2272
IS_DG2(i915)) {
2273
2273
/* Wa_14015150844 */
2274
2274
wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
2275
-
_MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
2275
+
REG_MASKED_FIELD_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
2276
2276
0, true);
2277
2277
}
2278
2278
···
2663
2663
if (IS_GRAPHICS_VER(i915, 4, 6))
2664
2664
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
2665
2665
wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
2666
-
0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
2666
+
0, REG_MASKED_FIELD_ENABLE(VS_TIMER_DISPATCH),
2667
2667
/* XXX bit doesn't stick on Broadwater */
2668
2668
IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
2669
2669
···
2679
2679
* enabled.
2680
2680
*/
2681
2681
wa_add(wal, ECOSKPD(RENDER_RING_BASE),
2682
-
0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
2682
+
0, REG_MASKED_FIELD_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
2683
2683
0 /* XXX bit doesn't stick on Broadwater */,
2684
2684
true);
2685
2685
}
···
2879
2879
* we need to explicitly skip the readback.
2880
2880
*/
2881
2881
wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2882
-
_MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
2882
+
REG_MASKED_FIELD_ENABLE(ENABLE_PREFETCH_INTO_IC),
2883
2883
0 /* write-only, so skip validation */,
2884
2884
true);
2885
2885
}
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
···
4414
4414
{
4415
4415
ENGINE_WRITE_FW(engine,
4416
4416
RING_MODE_GEN7,
4417
-
_MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
4417
+
REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
4418
4418
4419
-
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
4419
+
ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING));
4420
4420
ENGINE_POSTING_READ(engine, RING_MI_MODE);
4421
4421
}
4422
4422
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
···
1065
1065
1066
1066
/* Start the DMA */
1067
1067
intel_uncore_write_fw(uncore, DMA_CTRL,
1068
-
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
1068
+
REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA));
1069
1069
1070
1070
/* Wait for DMA to finish */
1071
1071
ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100, NULL);
···
1075
1075
intel_uncore_read_fw(uncore, DMA_CTRL));
1076
1076
1077
1077
/* Disable the bits once DMA is over */
1078
-
intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
1078
+
intel_uncore_write_fw(uncore, DMA_CTRL, REG_MASKED_FIELD_DISABLE(dma_flags));
1079
1079
1080
1080
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1081
1081
+5
-5
drivers/gpu/drm/i915/gvt/handlers.c
+5
-5
drivers/gpu/drm/i915/gvt/handlers.c
···
2047
2047
bool enable_execlist;
2048
2048
int ret;
2049
2049
2050
-
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2050
+
(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(1);
2051
2051
if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2052
2052
IS_COMETLAKE(vgpu->gvt->gt->i915))
2053
-
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2053
+
(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(2);
2054
2054
write_vreg(vgpu, offset, p_data, bytes);
2055
2055
2056
2056
if (IS_MASKED_BITS_ENABLED(data, 1)) {
···
2139
2139
2140
2140
if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
2141
2141
data |= RESET_CTL_READY_TO_RESET;
2142
-
else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
2142
+
else if (data & REG_MASKED_FIELD_DISABLE(RESET_CTL_REQUEST_RESET))
2143
2143
data &= ~RESET_CTL_READY_TO_RESET;
2144
2144
2145
2145
vgpu_vreg(vgpu, offset) = data;
···
2152
2152
{
2153
2153
u32 data = *(u32 *)p_data;
2154
2154
2155
-
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2155
+
(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(0x18);
2156
2156
write_vreg(vgpu, offset, p_data, bytes);
2157
2157
2158
2158
if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
···
2534
2534
2535
2535
#define RING_REG(base) _MMIO((base) + 0xd0)
2536
2536
MMIO_RING_F(RING_REG, 4, F_RO, 0,
2537
-
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2537
+
~REG_MASKED_FIELD_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2538
2538
ring_reset_ctl_write);
2539
2539
#undef RING_REG
2540
2540
+1
-1
drivers/gpu/drm/i915/gvt/mmio_context.c
+1
-1
drivers/gpu/drm/i915/gvt/mmio_context.c
···
476
476
{
477
477
const u32 *reg_state = ce->lrc_reg_state;
478
478
u32 inhibit_mask =
479
-
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
479
+
REG_MASKED_FIELD_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
480
480
481
481
return inhibit_mask ==
482
482
(reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
+2
-2
drivers/gpu/drm/i915/gvt/reg.h
+2
-2
drivers/gpu/drm/i915/gvt/reg.h
···
91
91
((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
92
92
93
93
#define IS_MASKED_BITS_ENABLED(_val, _b) \
94
-
(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
94
+
(((_val) & REG_MASKED_FIELD_ENABLE(_b)) == REG_MASKED_FIELD_ENABLE(_b))
95
95
#define IS_MASKED_BITS_DISABLED(_val, _b) \
96
-
((_val) & _MASKED_BIT_DISABLE(_b))
96
+
((_val) & REG_MASKED_FIELD_DISABLE(_b))
97
97
98
98
#define FORCEWAKE_RENDER_GEN9_REG 0xa278
99
99
#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
+17
-17
drivers/gpu/drm/i915/i915_perf.c
+17
-17
drivers/gpu/drm/i915/i915_perf.c
···
2635
2635
{
2636
2636
RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2637
2637
CTX_CONTEXT_CONTROL,
2638
-
_MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2639
-
active ?
2640
-
GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2641
-
0)
2638
+
REG_MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2639
+
active ?
2640
+
GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2641
+
0)
2642
2642
},
2643
2643
};
2644
2644
···
2827
2827
*/
2828
2828
if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2829
2829
intel_uncore_write(uncore, GEN8_OA_DEBUG,
2830
-
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2831
-
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2830
+
REG_MASKED_FIELD_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2831
+
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2832
2832
}
2833
2833
2834
2834
/*
···
2847
2847
2848
2848
static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2849
2849
{
2850
-
return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2851
-
(stream->sample_flags & SAMPLE_OA_REPORT) ?
2852
-
0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2850
+
return REG_MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2851
+
(stream->sample_flags & SAMPLE_OA_REPORT) ?
2852
+
0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2853
2853
}
2854
2854
2855
2855
static int
···
2870
2870
*/
2871
2871
if (IS_DG2(i915)) {
2872
2872
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2873
-
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
2873
+
REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE));
2874
2874
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2875
-
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
2875
+
REG_MASKED_FIELD_ENABLE(GEN12_DISABLE_DOP_GATING));
2876
2876
}
2877
2877
2878
2878
intel_uncore_write(uncore, __oa_regs(stream)->oa_debug,
2879
2879
/* Disable clk ratio reports, like previous Gens. */
2880
-
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2881
-
GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2880
+
REG_MASKED_FIELD_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2881
+
GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2882
2882
/*
2883
2883
* If the user didn't require OA reports, instruct
2884
2884
* the hardware not to emit ctx switch reports.
···
2949
2949
*/
2950
2950
if (IS_DG2(i915)) {
2951
2951
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2952
-
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
2952
+
REG_MASKED_FIELD_DISABLE(STALL_DOP_GATING_DISABLE));
2953
2953
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2954
-
_MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
2954
+
REG_MASKED_FIELD_DISABLE(GEN12_DISABLE_DOP_GATING));
2955
2955
}
2956
2956
2957
2957
/* disable the context save/restore or OAR counters */
···
4475
4475
* programmed by userspace doesn't change this.
4476
4476
*/
4477
4477
if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4478
-
val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4478
+
val = val & ~REG_MASKED_FIELD_ENABLE(GEN8_ST_PO_DISABLE);
4479
4479
4480
4480
/*
4481
4481
* WAIT_FOR_RC6_EXIT has only one bit fulfilling the function
···
4483
4483
* configs.
4484
4484
*/
4485
4485
if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4486
-
val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4486
+
val = val & ~REG_MASKED_FIELD_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4487
4487
4488
4488
return val;
4489
4489
}
+5
-5
drivers/gpu/drm/i915/i915_reg_defs.h
+5
-5
drivers/gpu/drm/i915/i915_reg_defs.h
···
105
105
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
106
106
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
107
107
108
-
#define _MASKED_FIELD(mask, value) \
108
+
#define REG_MASKED_FIELD(mask, value) \
109
109
(BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \
110
110
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \
111
111
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \
112
112
((mask) << 16 | (value)))
113
113
114
-
#define _MASKED_BIT_ENABLE(a) \
115
-
(__builtin_choose_expr(__builtin_constant_p(a), _MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })))
114
+
#define REG_MASKED_FIELD_ENABLE(a) \
115
+
(__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); })))
116
116
117
-
#define _MASKED_BIT_DISABLE(a) \
118
-
(_MASKED_FIELD((a), 0))
117
+
#define REG_MASKED_FIELD_DISABLE(a) \
118
+
(REG_MASKED_FIELD((a), 0))
119
119
120
120
/*
121
121
* Given the first two numbers __a and __b of arbitrarily many evenly spaced
+19
-19
drivers/gpu/drm/i915/intel_clock_gating.c
+19
-19
drivers/gpu/drm/i915/intel_clock_gating.c
···
454
454
GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
455
455
456
456
intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
457
-
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
457
+
REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
458
458
459
459
/* WaDisableSDEUnitClockGating:bdw */
460
460
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
···
519
519
520
520
if (INTEL_INFO(i915)->gt == 1)
521
521
intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
522
-
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
522
+
REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));
523
523
else {
524
524
/* must write both registers */
525
525
intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
526
-
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
526
+
REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));
527
527
intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2,
528
-
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
528
+
REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));
529
529
}
530
530
531
531
/*
···
559
559
560
560
/* WaDisableDopClockGating:vlv */
561
561
intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
562
-
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
562
+
REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));
563
563
564
564
/* This is required by WaCatErrorRejectionIssue:vlv */
565
565
intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
···
594
594
595
595
/* WaDisableSemaphoreAndSyncFlipWait:chv */
596
596
intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
597
-
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
597
+
REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
598
598
599
599
/* WaDisableCSUnitClockGating:chv */
600
600
intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
···
640
640
intel_uncore_write16(uncore, DEUC, 0);
641
641
intel_uncore_write(uncore,
642
642
MI_ARB_STATE,
643
-
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
643
+
REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
644
644
}
645
645
646
646
static void i965g_init_clock_gating(struct drm_i915_private *i915)
···
652
652
I965_FBC_CLOCK_GATE_DISABLE);
653
653
intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0);
654
654
intel_uncore_write(&i915->uncore, MI_ARB_STATE,
655
-
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
655
+
REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
656
656
}
657
657
658
658
static void gen3_init_clock_gating(struct drm_i915_private *i915)
···
665
665
666
666
if (IS_PINEVIEW(i915))
667
667
intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
668
-
_MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
668
+
REG_MASKED_FIELD_ENABLE(ECO_GATING_CX_ONLY));
669
669
670
670
/* IIR "flip pending" means done if this bit is set */
671
671
intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
672
-
_MASKED_BIT_DISABLE(ECO_FLIP_DONE));
672
+
REG_MASKED_FIELD_DISABLE(ECO_FLIP_DONE));
673
673
674
674
/* interrupts should cause a wake up from C3 */
675
-
intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
675
+
intel_uncore_write(&i915->uncore, INSTPM, REG_MASKED_FIELD_ENABLE(INSTPM_AGPBUSY_INT_EN));
676
676
677
677
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
678
678
intel_uncore_write(&i915->uncore, MI_ARB_STATE,
679
-
_MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
679
+
REG_MASKED_FIELD_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
680
680
681
681
intel_uncore_write(&i915->uncore, MI_ARB_STATE,
682
-
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
682
+
REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
683
683
}
684
684
685
685
static void i85x_init_clock_gating(struct drm_i915_private *i915)
···
687
687
intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
688
688
689
689
/* interrupts should cause a wake up from C3 */
690
-
intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
691
-
_MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
690
+
intel_uncore_write(&i915->uncore, MI_STATE, REG_MASKED_FIELD_ENABLE(MI_AGPBUSY_INT_EN) |
691
+
REG_MASKED_FIELD_DISABLE(MI_AGPBUSY_830_MODE));
692
692
693
693
intel_uncore_write(&i915->uncore, MEM_MODE,
694
-
_MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
694
+
REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
695
695
696
696
/*
697
697
* Have FBC ignore 3D activity since we use software
···
701
701
* until a 2D blit occurs.
702
702
*/
703
703
intel_uncore_write(&i915->uncore, SCPD0,
704
-
_MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
704
+
REG_MASKED_FIELD_ENABLE(SCPD_FBC_IGNORE_3D));
705
705
}
706
706
707
707
static void i830_init_clock_gating(struct drm_i915_private *i915)
708
708
{
709
709
intel_uncore_write(&i915->uncore, MEM_MODE,
710
-
_MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
711
-
_MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
710
+
REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
711
+
REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
712
712
}
713
713
714
714
void intel_clock_gating_init(struct drm_device *drm)
+2
-2
drivers/gpu/drm/i915/intel_uncore.c
+2
-2
drivers/gpu/drm/i915/intel_uncore.c
···
132
132
}
133
133
134
134
#define fw_ack(d) readl((d)->reg_ack)
135
-
#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
136
-
#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
135
+
#define fw_set(d, val) writel(REG_MASKED_FIELD_ENABLE((val)), (d)->reg_set)
136
+
#define fw_clear(d, val) writel(REG_MASKED_FIELD_DISABLE((val)), (d)->reg_set)
137
137
138
138
static inline void
139
139
fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
+2
-2
drivers/gpu/drm/i915/pxp/intel_pxp.c
+2
-2
drivers/gpu/drm/i915/pxp/intel_pxp.c
···
66
66
67
67
static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
68
68
{
69
-
u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
70
-
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
69
+
u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
70
+
REG_MASKED_FIELD_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
71
71
72
72
intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
73
73
}
+10
-10
drivers/gpu/drm/xe/xe_eu_stall.c
+10
-10
drivers/gpu/drm/xe/xe_eu_stall.c
···
442
442
* On Xe2 and later GPUs, the bit has to be cleared by writing 0 to it.
443
443
*/
444
444
if (GRAPHICS_VER(xe) >= 20)
445
-
write_ptr_reg = _MASKED_BIT_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
445
+
write_ptr_reg = REG_MASKED_FIELD_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
446
446
else
447
-
write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
447
+
write_ptr_reg = REG_MASKED_FIELD_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
448
448
449
449
xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance);
450
450
}
···
504
504
/* Read pointer can overflow into one additional bit */
505
505
read_ptr &= (buf_size << 1) - 1;
506
506
read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, (read_ptr >> 6));
507
-
read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
507
+
read_ptr_reg = REG_MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
508
508
xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance);
509
509
xecore_buf->read = read_ptr;
510
510
trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
···
674
674
675
675
if (XE_GT_WA(gt, 22016596838))
676
676
xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2,
677
-
_MASKED_BIT_ENABLE(DISABLE_DOP_GATING));
677
+
REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING));
678
678
679
679
for_each_dss_steering(xecore, gt, group, instance) {
680
680
write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT, group, instance);
···
683
683
clear_dropped_eviction_line_bit(gt, group, instance);
684
684
write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
685
685
read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, write_ptr);
686
-
read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
686
+
read_ptr_reg = REG_MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
687
687
/* Initialize the read pointer to the write pointer */
688
688
xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance);
689
689
write_ptr <<= 6;
···
695
695
stream->data_drop.reported_to_user = false;
696
696
bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
697
697
698
-
reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,
699
-
REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) |
700
-
REG_FIELD_PREP(EUSTALL_SAMPLE_RATE,
701
-
stream->sampling_rate_mult));
698
+
reg_value = REG_MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,
699
+
REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) |
700
+
REG_FIELD_PREP(EUSTALL_SAMPLE_RATE,
701
+
stream->sampling_rate_mult));
702
702
xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, reg_value);
703
703
/* GGTT addresses can never be > 32 bits */
704
704
xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE_UPPER, 0);
···
830
830
831
831
if (XE_GT_WA(gt, 22016596838))
832
832
xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2,
833
-
_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
833
+
REG_MASKED_FIELD_DISABLE(DISABLE_DOP_GATING));
834
834
835
835
xe_force_wake_put(gt_to_fw(gt), stream->fw_ref);
836
836
xe_pm_runtime_put(gt_to_xe(gt));
+3
-3
drivers/gpu/drm/xe/xe_execlist.c
+3
-3
drivers/gpu/drm/xe/xe_execlist.c
···
47
47
struct xe_mmio *mmio = >->mmio;
48
48
struct xe_device *xe = gt_to_xe(gt);
49
49
u64 lrc_desc;
50
-
u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE);
50
+
u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE);
51
51
52
52
lrc_desc = xe_lrc_descriptor(lrc);
53
53
···
61
61
62
62
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
63
63
xe_mmio_write32(mmio, RCU_MODE,
64
-
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
64
+
REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE));
65
65
66
66
xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
67
67
lrc->ring.old_tail = lrc->ring.tail;
···
83
83
xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));
84
84
85
85
if (xe_device_has_msix(gt_to_xe(hwe->gt)))
86
-
ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
86
+
ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
87
87
xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode);
88
88
89
89
xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
+4
-4
drivers/gpu/drm/xe/xe_hw_engine.c
+4
-4
drivers/gpu/drm/xe/xe_hw_engine.c
···
327
327
{
328
328
u32 ccs_mask =
329
329
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
330
-
u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE);
330
+
u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE);
331
331
332
332
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
333
333
xe_mmio_write32(&hwe->gt->mmio, RCU_MODE,
334
-
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
334
+
REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE));
335
335
336
336
xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
337
337
xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
338
338
xe_bo_ggtt_addr(hwe->hwsp));
339
339
340
340
if (xe_device_has_msix(gt_to_xe(hwe->gt)))
341
-
ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
341
+
ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
342
342
xe_hw_engine_mmio_write32(hwe, RING_MODE(0), ring_mode);
343
343
xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
344
-
_MASKED_BIT_DISABLE(STOP_RING));
344
+
REG_MASKED_FIELD_DISABLE(STOP_RING));
345
345
xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
346
346
}
347
347
+6
-6
drivers/gpu/drm/xe/xe_lrc.c
+6
-6
drivers/gpu/drm/xe/xe_lrc.c
···
637
637
638
638
static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)
639
639
{
640
-
regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
641
-
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
640
+
regs[CTX_CONTEXT_CONTROL] = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
641
+
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
642
642
643
643
if (xe_gt_has_indirect_ring_state(hwe->gt))
644
644
regs[CTX_CONTEXT_CONTROL] |=
645
-
_MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);
645
+
REG_MASKED_FIELD_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);
646
646
}
647
647
648
648
static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
···
1204
1204
1205
1205
*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);
1206
1206
*cmd++ = CS_DEBUG_MODE2(0).addr;
1207
-
*cmd++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
1207
+
*cmd++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
1208
1208
1209
1209
return cmd - batch;
1210
1210
}
···
1542
1542
if (init_flags & XE_LRC_CREATE_RUNALONE)
1543
1543
xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL,
1544
1544
xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) |
1545
-
_MASKED_BIT_ENABLE(CTX_CTRL_RUN_ALONE));
1545
+
REG_MASKED_FIELD_ENABLE(CTX_CTRL_RUN_ALONE));
1546
1546
1547
1547
if (init_flags & XE_LRC_CREATE_PXP)
1548
1548
xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL,
1549
1549
xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) |
1550
-
_MASKED_BIT_ENABLE(CTX_CTRL_PXP_ENABLE));
1550
+
REG_MASKED_FIELD_ENABLE(CTX_CTRL_PXP_ENABLE));
1551
1551
1552
1552
lrc->ctx_timestamp = 0;
1553
1553
xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0);
+19
-19
drivers/gpu/drm/xe/xe_oa.c
+19
-19
drivers/gpu/drm/xe/xe_oa.c
···
758
758
},
759
759
{
760
760
RING_CONTEXT_CONTROL(stream->hwe->mmio_base),
761
-
_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,
762
-
enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0)
761
+
REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,
762
+
enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0)
763
763
},
764
764
};
765
765
···
782
782
},
783
783
{
784
784
RING_CONTEXT_CONTROL(stream->hwe->mmio_base),
785
-
_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,
786
-
enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) |
787
-
_MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0),
785
+
REG_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,
786
+
enable ? CTX_CTRL_OAC_CONTEXT_ENABLE : 0) |
787
+
REG_MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0),
788
788
},
789
789
};
790
790
···
812
812
813
813
static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool enable)
814
814
{
815
-
return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG,
816
-
enable && stream && stream->sample ?
817
-
0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG);
815
+
return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG,
816
+
enable && stream && stream->sample ?
817
+
0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG);
818
818
}
819
819
820
820
static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
···
825
825
/* Enable thread stall DOP gating and EU DOP gating. */
826
826
if (XE_GT_WA(stream->gt, 1508761755)) {
827
827
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
828
-
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
828
+
REG_MASKED_FIELD_DISABLE(STALL_DOP_GATING_DISABLE));
829
829
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
830
-
_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
830
+
REG_MASKED_FIELD_DISABLE(DISABLE_DOP_GATING));
831
831
}
832
832
833
833
xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
···
1059
1059
static u32 oag_report_ctx_switches(const struct xe_oa_stream *stream)
1060
1060
{
1061
1061
/* If user didn't require OA reports, ask HW not to emit ctx switch reports */
1062
-
return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
1063
-
stream->sample ?
1064
-
0 : OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
1062
+
return REG_MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
1063
+
stream->sample ?
1064
+
0 : OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
1065
1065
}
1066
1066
1067
1067
static u32 oag_buf_size_select(const struct xe_oa_stream *stream)
1068
1068
{
1069
-
return _MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT,
1070
-
xe_bo_size(stream->oa_buffer.bo) > SZ_16M ?
1071
-
OAG_OA_DEBUG_BUF_SIZE_SELECT : 0);
1069
+
return REG_MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT,
1070
+
xe_bo_size(stream->oa_buffer.bo) > SZ_16M ?
1071
+
OAG_OA_DEBUG_BUF_SIZE_SELECT : 0);
1072
1072
}
1073
1073
1074
1074
static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
···
1083
1083
*/
1084
1084
if (XE_GT_WA(stream->gt, 1508761755)) {
1085
1085
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
1086
-
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
1086
+
REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE));
1087
1087
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
1088
-
_MASKED_BIT_ENABLE(DISABLE_DOP_GATING));
1088
+
REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING));
1089
1089
}
1090
1090
1091
1091
/* Disable clk ratio reports */
···
1100
1100
OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL;
1101
1101
1102
1102
xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
1103
-
_MASKED_BIT_ENABLE(oa_debug) |
1103
+
REG_MASKED_FIELD_ENABLE(oa_debug) |
1104
1104
oag_report_ctx_switches(stream) |
1105
1105
oag_buf_size_select(stream) |
1106
1106
oag_configure_mmio_trigger(stream, true));
+2
-2
drivers/gpu/drm/xe/xe_pxp.c
+2
-2
drivers/gpu/drm/xe/xe_pxp.c
···
312
312
313
313
static int kcr_pxp_set_status(const struct xe_pxp *pxp, bool enable)
314
314
{
315
-
u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
316
-
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
315
+
u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
316
+
REG_MASKED_FIELD_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
317
317
318
318
CLASS(xe_force_wake, fw_ref)(gt_to_fw(pxp->gt), XE_FW_GT);
319
319
if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
+2
-2
drivers/gpu/drm/xe/xe_uc_fw.c
+2
-2
drivers/gpu/drm/xe/xe_uc_fw.c
···
881
881
882
882
/* Start the DMA */
883
883
xe_mmio_write32(mmio, DMA_CTRL,
884
-
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
884
+
REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA));
885
885
886
886
/* Wait for DMA to finish */
887
887
ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
···
891
891
xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
892
892
893
893
/* Disable the bits once DMA is over */
894
-
xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
894
+
xe_mmio_write32(mmio, DMA_CTRL, REG_MASKED_FIELD_DISABLE(dma_flags));
895
895
896
896
return ret;
897
897
}