phy: qcom: qmp-combo: introduce QMPPHY_MODE

Introduce an enum for the QMP Combo PHY modes, use it in the
QMP commmon phy init function and default to COMBO mode.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[konrad: some renaming and rewording]
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on Lenovo Thinkpad T14S
Link: https://lore.kernel.org/r/20250807-topic-4ln_dp_respin-v4-4-43272d6eca92@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Neil Armstrong and committed by

Vinod Koul 10 months ago dd331112 86390472

+39 -5

1 changed file

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drivers

phy

qualcomm

phy-qcom-qmp-combo.c

+39 -5

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

··· 62 62 63 63 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 64 65 + enum qmpphy_mode { 66 + QMPPHY_MODE_USB3DP = 0, 67 + QMPPHY_MODE_DP_ONLY, 68 + QMPPHY_MODE_USB3_ONLY, 69 + }; 70 + 65 71 /* set of registers with offsets different per-PHY */ 66 72 enum qphy_reg_layout { 67 73 /* PCS registers */ ··· 1850 1844 1851 1845 struct mutex phy_mutex; 1852 1846 int init_count; 1847 + enum qmpphy_mode qmpphy_mode; 1853 1848 1854 1849 struct phy *usb_phy; 1855 1850 enum phy_mode phy_mode; ··· 3044 3037 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 3045 3038 val |= SW_PORTSELECT_VAL; 3046 3039 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 3047 - writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3048 3040 3049 - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 3050 - qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3051 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3052 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3041 + switch (qmp->qmpphy_mode) { 3042 + case QMPPHY_MODE_USB3DP: 3043 + writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3044 + 3045 + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 3046 + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3047 + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3048 + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3049 + break; 3050 + 3051 + case QMPPHY_MODE_DP_ONLY: 3052 + writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3053 + 3054 + /* bring QMP DP PHY PCS block out of reset */ 3055 + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3056 + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET); 3057 + break; 3058 + 3059 + case QMPPHY_MODE_USB3_ONLY: 3060 + writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3061 + 3062 + /* bring QMP USB PHY PCS block out of reset */ 3063 + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3064 + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3065 + break; 3066 + } 3053 3067 3054 3068 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 3055 3069 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ··· 4080 4052 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 4081 4053 if (ret) 4082 4054 goto err_node_put; 4055 + 4056 + /* 4057 + * The hw default is USB3_ONLY, but USB3+DP mode lets us more easily 4058 + * check both sub-blocks' init tables for blunders at probe time. 4059 + */ 4060 + qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 4083 4061 4084 4062 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 4085 4063 if (IS_ERR(qmp->usb_phy)) {

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