tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"I realise this a bit bigger than I would want at this point.

Exynos is a large chunk, I got them to half what they wanted already,
and hey its ARM based, so not going to hurt many people.

Radeon has only two fixes, but the PLL fixes were a bit bigger, but
required for a lot of scenarios, the fence fix is really urgent.

vmwgfx: I've pulled in a dumb ioctl support patch that I was going to
shove in later and cc stable, but we need it asap, its mainly to stop
mesa growing a really ugly dependency in userspace to run stuff on
vmware, and if I don't stick it in the kernel now, everyone will have
to ship ugly userspace libs to workaround it.

nouveau: single urgent fix found in F18 testing, causes X to not start
properly when f18 plymouth is used

i915: smattering of fixes and debug quieting

gma500: single regression fix

So as I said a bit large, but its fairly well scattered and its all
stuff I'll be shipping in F18's 3.6 kernel."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (26 commits)
drm/nouveau: fix booting with plymouth + dumb support
drm/radeon: make 64bit fences more robust v3
drm/radeon: rework pll selection (v3)
drm: Drop the NV12M and YUV420M formats
drm/exynos: remove DRM_FORMAT_NV12M from plane module
drm/exynos: fix double call of drm_prime_(init/destroy)_file_private
drm/exynos: add dummy support for dmabuf-mmap
drm/exynos: Add missing braces around sizeof in exynos_mixer.c
drm/exynos: Add missing braces around sizeof in exynos_hdmi.c
drm/exynos: Make g2d_pm_ops static
drm/exynos: Add dependency for G2D in Kconfig
drm/exynos: fixed page align bug.
drm/exynos: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(.. [1]
drm/exynos: Use devm_* functions in exynos_drm_g2d.c file
drm/exynos: Use devm_kzalloc in exynos_drm_hdmi.c file
drm/exynos: Use devm_kzalloc in exynos_drm_vidi.c file
drm/exynos: Remove redundant check in exynos_drm_fimd.c file
drm/exynos: Remove redundant check in exynos_hdmi.c file
vmwgfx: add dumb ioctl support
gma500: Fix regression on Oaktrail devices
...

Linus Torvalds dd383af6 889cb3b9

+298 -138
+1 -1
drivers/gpu/drm/exynos/Kconfig
··· 36 36 37 37 config DRM_EXYNOS_G2D 38 38 bool "Exynos DRM G2D" 39 - depends on DRM_EXYNOS 39 + depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_G2D 40 40 help 41 41 Choose this option if you want to use Exynos G2D for DRM.
+7
drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
··· 163 163 /* TODO */ 164 164 } 165 165 166 + static int exynos_gem_dmabuf_mmap(struct dma_buf *dma_buf, 167 + struct vm_area_struct *vma) 168 + { 169 + return -ENOTTY; 170 + } 171 + 166 172 static struct dma_buf_ops exynos_dmabuf_ops = { 167 173 .map_dma_buf = exynos_gem_map_dma_buf, 168 174 .unmap_dma_buf = exynos_gem_unmap_dma_buf, ··· 176 170 .kmap_atomic = exynos_gem_dmabuf_kmap_atomic, 177 171 .kunmap = exynos_gem_dmabuf_kunmap, 178 172 .kunmap_atomic = exynos_gem_dmabuf_kunmap_atomic, 173 + .mmap = exynos_gem_dmabuf_mmap, 179 174 .release = exynos_dmabuf_release, 180 175 }; 181 176
-2
drivers/gpu/drm/exynos/exynos_drm_drv.c
··· 160 160 if (!file_priv) 161 161 return -ENOMEM; 162 162 163 - drm_prime_init_file_private(&file->prime); 164 163 file->driver_priv = file_priv; 165 164 166 165 return exynos_drm_subdrv_open(dev, file); ··· 183 184 e->base.destroy(&e->base); 184 185 } 185 186 } 186 - drm_prime_destroy_file_private(&file->prime); 187 187 spin_unlock_irqrestore(&dev->event_lock, flags); 188 188 189 189 exynos_drm_subdrv_close(dev, file);
-5
drivers/gpu/drm/exynos/exynos_drm_fimd.c
··· 831 831 } 832 832 833 833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 834 - if (!res) { 835 - dev_err(dev, "failed to find registers\n"); 836 - ret = -ENOENT; 837 - goto err_clk; 838 - } 839 834 840 835 ctx->regs = devm_request_and_ioremap(&pdev->dev, res); 841 836 if (!ctx->regs) {
+11 -41
drivers/gpu/drm/exynos/exynos_drm_g2d.c
··· 129 129 struct g2d_data { 130 130 struct device *dev; 131 131 struct clk *gate_clk; 132 - struct resource *regs_res; 133 132 void __iomem *regs; 134 133 int irq; 135 134 struct workqueue_struct *g2d_workq; ··· 750 751 struct exynos_drm_subdrv *subdrv; 751 752 int ret; 752 753 753 - g2d = kzalloc(sizeof(*g2d), GFP_KERNEL); 754 + g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL); 754 755 if (!g2d) { 755 756 dev_err(dev, "failed to allocate driver data\n"); 756 757 return -ENOMEM; ··· 758 759 759 760 g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab", 760 761 sizeof(struct g2d_runqueue_node), 0, 0, NULL); 761 - if (!g2d->runqueue_slab) { 762 - ret = -ENOMEM; 763 - goto err_free_mem; 764 - } 762 + if (!g2d->runqueue_slab) 763 + return -ENOMEM; 765 764 766 765 g2d->dev = dev; 767 766 ··· 791 794 pm_runtime_enable(dev); 792 795 793 796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 - if (!res) { 795 - dev_err(dev, "failed to get I/O memory\n"); 796 - ret = -ENOENT; 797 - goto err_put_clk; 798 - } 799 797 800 - g2d->regs_res = request_mem_region(res->start, resource_size(res), 801 - dev_name(dev)); 802 - if (!g2d->regs_res) { 803 - dev_err(dev, "failed to request I/O memory\n"); 804 - ret = -ENOENT; 805 - goto err_put_clk; 806 - } 807 - 808 - g2d->regs = ioremap(res->start, resource_size(res)); 798 + g2d->regs = devm_request_and_ioremap(&pdev->dev, res); 809 799 if (!g2d->regs) { 810 800 dev_err(dev, "failed to remap I/O memory\n"); 811 801 ret = -ENXIO; 812 - goto err_release_res; 802 + goto err_put_clk; 813 803 } 814 804 815 805 g2d->irq = platform_get_irq(pdev, 0); 816 806 if (g2d->irq < 0) { 817 807 dev_err(dev, "failed to get irq\n"); 818 808 ret = g2d->irq; 819 - goto err_unmap_base; 809 + goto err_put_clk; 820 810 } 821 811 822 - ret = request_irq(g2d->irq, g2d_irq_handler, 0, "drm_g2d", g2d); 812 + ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0, 813 + "drm_g2d", g2d); 823 814 if (ret < 0) { 824 815 dev_err(dev, "irq request failed\n"); 825 - goto err_unmap_base; 816 + goto err_put_clk; 826 817 } 827 818 828 819 platform_set_drvdata(pdev, g2d); ··· 823 838 ret = exynos_drm_subdrv_register(subdrv); 824 839 if (ret < 0) { 825 840 dev_err(dev, "failed to register drm g2d device\n"); 826 - goto err_free_irq; 841 + goto err_put_clk; 827 842 } 828 843 829 844 dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n", ··· 831 846 832 847 return 0; 833 848 834 - err_free_irq: 835 - free_irq(g2d->irq, g2d); 836 - err_unmap_base: 837 - iounmap(g2d->regs); 838 - err_release_res: 839 - release_resource(g2d->regs_res); 840 - kfree(g2d->regs_res); 841 849 err_put_clk: 842 850 pm_runtime_disable(dev); 843 851 clk_put(g2d->gate_clk); ··· 840 862 destroy_workqueue(g2d->g2d_workq); 841 863 err_destroy_slab: 842 864 kmem_cache_destroy(g2d->runqueue_slab); 843 - err_free_mem: 844 - kfree(g2d); 845 865 return ret; 846 866 } 847 867 ··· 849 873 850 874 cancel_work_sync(&g2d->runqueue_work); 851 875 exynos_drm_subdrv_unregister(&g2d->subdrv); 852 - free_irq(g2d->irq, g2d); 853 876 854 877 while (g2d->runqueue_node) { 855 878 g2d_free_runqueue_node(g2d, g2d->runqueue_node); 856 879 g2d->runqueue_node = g2d_get_runqueue_node(g2d); 857 880 } 858 - 859 - iounmap(g2d->regs); 860 - release_resource(g2d->regs_res); 861 - kfree(g2d->regs_res); 862 881 863 882 pm_runtime_disable(&pdev->dev); 864 883 clk_put(g2d->gate_clk); ··· 861 890 g2d_fini_cmdlist(g2d); 862 891 destroy_workqueue(g2d->g2d_workq); 863 892 kmem_cache_destroy(g2d->runqueue_slab); 864 - kfree(g2d); 865 893 866 894 return 0; 867 895 } ··· 894 924 } 895 925 #endif 896 926 897 - SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume); 927 + static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume); 898 928 899 929 struct platform_driver g2d_driver = { 900 930 .probe = g2d_probe,
+2 -2
drivers/gpu/drm/exynos/exynos_drm_gem.c
··· 122 122 __free_page(pages[i]); 123 123 124 124 drm_free_large(pages); 125 - return ERR_PTR(PTR_ERR(p)); 125 + return ERR_CAST(p); 126 126 } 127 127 128 128 static void exynos_gem_put_pages(struct drm_gem_object *obj, ··· 662 662 */ 663 663 664 664 args->pitch = args->width * ((args->bpp + 7) / 8); 665 - args->size = PAGE_ALIGN(args->pitch * args->height); 665 + args->size = args->pitch * args->height; 666 666 667 667 exynos_gem_obj = exynos_drm_gem_create(dev, args->flags, args->size); 668 668 if (IS_ERR(exynos_gem_obj))
+1 -2
drivers/gpu/drm/exynos/exynos_drm_hdmi.c
··· 345 345 346 346 DRM_DEBUG_KMS("%s\n", __FILE__); 347 347 348 - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 348 + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 349 349 if (!ctx) { 350 350 DRM_LOG_KMS("failed to alloc common hdmi context.\n"); 351 351 return -ENOMEM; ··· 371 371 DRM_DEBUG_KMS("%s\n", __FILE__); 372 372 373 373 exynos_drm_subdrv_unregister(&ctx->subdrv); 374 - kfree(ctx); 375 374 376 375 return 0; 377 376 }
-1
drivers/gpu/drm/exynos/exynos_drm_plane.c
··· 29 29 DRM_FORMAT_XRGB8888, 30 30 DRM_FORMAT_ARGB8888, 31 31 DRM_FORMAT_NV12, 32 - DRM_FORMAT_NV12M, 33 32 DRM_FORMAT_NV12MT, 34 33 }; 35 34
+1 -3
drivers/gpu/drm/exynos/exynos_drm_vidi.c
··· 633 633 634 634 DRM_DEBUG_KMS("%s\n", __FILE__); 635 635 636 - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 636 + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 637 637 if (!ctx) 638 638 return -ENOMEM; 639 639 ··· 672 672 kfree(ctx->raw_edid); 673 673 ctx->raw_edid = NULL; 674 674 } 675 - 676 - kfree(ctx); 677 675 678 676 return 0; 679 677 }
+3 -8
drivers/gpu/drm/exynos/exynos_hdmi.c
··· 2172 2172 2173 2173 DRM_DEBUG_KMS("HDMI resource init\n"); 2174 2174 2175 - memset(res, 0, sizeof *res); 2175 + memset(res, 0, sizeof(*res)); 2176 2176 2177 2177 /* get clocks, power */ 2178 2178 res->hdmi = clk_get(dev, "hdmi"); ··· 2204 2204 clk_set_parent(res->sclk_hdmi, res->sclk_pixel); 2205 2205 2206 2206 res->regul_bulk = kzalloc(ARRAY_SIZE(supply) * 2207 - sizeof res->regul_bulk[0], GFP_KERNEL); 2207 + sizeof(res->regul_bulk[0]), GFP_KERNEL); 2208 2208 if (!res->regul_bulk) { 2209 2209 DRM_ERROR("failed to get memory for regulators\n"); 2210 2210 goto fail; ··· 2243 2243 clk_put(res->sclk_hdmi); 2244 2244 if (!IS_ERR_OR_NULL(res->hdmi)) 2245 2245 clk_put(res->hdmi); 2246 - memset(res, 0, sizeof *res); 2246 + memset(res, 0, sizeof(*res)); 2247 2247 2248 2248 return 0; 2249 2249 } ··· 2312 2312 } 2313 2313 2314 2314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2315 - if (!res) { 2316 - DRM_ERROR("failed to find registers\n"); 2317 - ret = -ENOENT; 2318 - goto err_resource; 2319 - } 2320 2315 2321 2316 hdata->regs = devm_request_and_ioremap(&pdev->dev, res); 2322 2317 if (!hdata->regs) {
+3 -3
drivers/gpu/drm/exynos/exynos_mixer.c
··· 236 236 static void vp_default_filter(struct mixer_resources *res) 237 237 { 238 238 vp_filter_set(res, VP_POLY8_Y0_LL, 239 - filter_y_horiz_tap8, sizeof filter_y_horiz_tap8); 239 + filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); 240 240 vp_filter_set(res, VP_POLY4_Y0_LL, 241 - filter_y_vert_tap4, sizeof filter_y_vert_tap4); 241 + filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); 242 242 vp_filter_set(res, VP_POLY4_C0_LL, 243 - filter_cr_horiz_tap4, sizeof filter_cr_horiz_tap4); 243 + filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); 244 244 } 245 245 246 246 static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
+2
drivers/gpu/drm/gma500/oaktrail_device.c
··· 476 476 .pos = DSPAPOS, 477 477 .surf = DSPASURF, 478 478 .addr = MRST_DSPABASE, 479 + .base = MRST_DSPABASE, 479 480 .status = PIPEASTAT, 480 481 .linoff = DSPALINOFF, 481 482 .tileoff = DSPATILEOFF, ··· 500 499 .pos = DSPBPOS, 501 500 .surf = DSPBSURF, 502 501 .addr = DSPBBASE, 502 + .base = DSPBBASE, 503 503 .status = PIPEBSTAT, 504 504 .linoff = DSPBLINOFF, 505 505 .tileoff = DSPBTILEOFF,
+1
drivers/gpu/drm/i915/i915_dma.c
··· 1587 1587 spin_lock_init(&dev_priv->irq_lock); 1588 1588 spin_lock_init(&dev_priv->error_lock); 1589 1589 spin_lock_init(&dev_priv->rps_lock); 1590 + spin_lock_init(&dev_priv->dpio_lock); 1590 1591 1591 1592 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1592 1593 dev_priv->num_pipe = 3;
-3
drivers/gpu/drm/i915/i915_irq.c
··· 2700 2700 dev->driver->irq_handler = i8xx_irq_handler; 2701 2701 dev->driver->irq_uninstall = i8xx_irq_uninstall; 2702 2702 } else if (INTEL_INFO(dev)->gen == 3) { 2703 - /* IIR "flip pending" means done if this bit is set */ 2704 - I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 2705 - 2706 2703 dev->driver->irq_preinstall = i915_irq_preinstall; 2707 2704 dev->driver->irq_postinstall = i915_irq_postinstall; 2708 2705 dev->driver->irq_uninstall = i915_irq_uninstall;
+4 -2
drivers/gpu/drm/i915/intel_display.c
··· 1376 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1377 1377 reg, pipe_name(pipe)); 1378 1378 1379 - WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1379 + WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 1380 + && (val & DP_PIPEB_SELECT), 1380 1381 "IBX PCH dp port still using transcoder B\n"); 1381 1382 } 1382 1383 ··· 1389 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1390 1389 reg, pipe_name(pipe)); 1391 1390 1392 - WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1391 + WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 1392 + && (val & SDVO_PIPE_B_SELECT), 1393 1393 "IBX PCH hdmi port still using transcoder B\n"); 1394 1394 } 1395 1395
+7 -4
drivers/gpu/drm/i915/intel_dp.c
··· 2533 2533 break; 2534 2534 } 2535 2535 2536 - intel_dp_i2c_init(intel_dp, intel_connector, name); 2537 - 2538 2536 /* Cache some DPCD data in the eDP case */ 2539 2537 if (is_edp(intel_dp)) { 2540 - bool ret; 2541 2538 struct edp_power_seq cur, vbt; 2542 2539 u32 pp_on, pp_off, pp_div; 2543 - struct edid *edid; 2544 2540 2545 2541 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2546 2542 pp_off = I915_READ(PCH_PP_OFF_DELAYS); ··· 2587 2591 2588 2592 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2589 2593 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2594 + } 2595 + 2596 + intel_dp_i2c_init(intel_dp, intel_connector, name); 2597 + 2598 + if (is_edp(intel_dp)) { 2599 + bool ret; 2600 + struct edid *edid; 2590 2601 2591 2602 ironlake_edp_panel_vdd_on(intel_dp); 2592 2603 ret = intel_dp_get_dpcd(intel_dp);
+22 -9
drivers/gpu/drm/i915/intel_panel.c
··· 162 162 return val; 163 163 } 164 164 165 - u32 intel_panel_get_max_backlight(struct drm_device *dev) 165 + static u32 _intel_panel_get_max_backlight(struct drm_device *dev) 166 166 { 167 167 struct drm_i915_private *dev_priv = dev->dev_private; 168 168 u32 max; 169 169 170 170 max = i915_read_blc_pwm_ctl(dev_priv); 171 - if (max == 0) { 172 - /* XXX add code here to query mode clock or hardware clock 173 - * and program max PWM appropriately. 174 - */ 175 - pr_warn_once("fixme: max PWM is zero\n"); 176 - return 1; 177 - } 178 171 179 172 if (HAS_PCH_SPLIT(dev)) { 180 173 max >>= 16; ··· 179 186 180 187 if (is_backlight_combination_mode(dev)) 181 188 max *= 0xff; 189 + } 190 + 191 + return max; 192 + } 193 + 194 + u32 intel_panel_get_max_backlight(struct drm_device *dev) 195 + { 196 + u32 max; 197 + 198 + max = _intel_panel_get_max_backlight(dev); 199 + if (max == 0) { 200 + /* XXX add code here to query mode clock or hardware clock 201 + * and program max PWM appropriately. 202 + */ 203 + pr_warn_once("fixme: max PWM is zero\n"); 204 + return 1; 182 205 } 183 206 184 207 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); ··· 433 424 434 425 memset(&props, 0, sizeof(props)); 435 426 props.type = BACKLIGHT_RAW; 436 - props.max_brightness = intel_panel_get_max_backlight(dev); 427 + props.max_brightness = _intel_panel_get_max_backlight(dev); 428 + if (props.max_brightness == 0) { 429 + DRM_ERROR("Failed to get maximum backlight value\n"); 430 + return -ENODEV; 431 + } 437 432 dev_priv->backlight = 438 433 backlight_device_register("intel_backlight", 439 434 &connector->kdev, dev,
+3
drivers/gpu/drm/i915/intel_pm.c
··· 3672 3672 3673 3673 if (IS_PINEVIEW(dev)) 3674 3674 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 3675 + 3676 + /* IIR "flip pending" means done if this bit is set */ 3677 + I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 3675 3678 } 3676 3679 3677 3680 static void i85x_init_clock_gating(struct drm_device *dev)
+6 -9
drivers/gpu/drm/i915/intel_sdvo.c
··· 2573 2573 hotplug_mask = intel_sdvo->is_sdvob ? 2574 2574 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; 2575 2575 } 2576 - dev_priv->hotplug_supported_mask |= hotplug_mask; 2577 2576 2578 2577 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); 2579 2578 ··· 2580 2581 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2581 2582 goto err; 2582 2583 2583 - /* Set up hotplug command - note paranoia about contents of reply. 2584 - * We assume that the hardware is in a sane state, and only touch 2585 - * the bits we think we understand. 2586 - */ 2587 - intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, 2588 - &intel_sdvo->hotplug_active, 2); 2589 - intel_sdvo->hotplug_active[0] &= ~0x3; 2590 - 2591 2584 if (intel_sdvo_output_setup(intel_sdvo, 2592 2585 intel_sdvo->caps.output_flags) != true) { 2593 2586 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2594 2587 SDVO_NAME(intel_sdvo)); 2595 2588 goto err; 2596 2589 } 2590 + 2591 + /* Only enable the hotplug irq if we need it, to work around noisy 2592 + * hotplug lines. 2593 + */ 2594 + if (intel_sdvo->hotplug_active[0]) 2595 + dev_priv->hotplug_supported_mask |= hotplug_mask; 2597 2596 2598 2597 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 2599 2598
+1 -1
drivers/gpu/drm/nouveau/nouveau_display.c
··· 598 598 args->size = args->pitch * args->height; 599 599 args->size = roundup(args->size, PAGE_SIZE); 600 600 601 - ret = nouveau_gem_new(dev, args->size, 0, TTM_PL_FLAG_VRAM, 0, 0, &bo); 601 + ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo); 602 602 if (ret) 603 603 return ret; 604 604
+129 -34
drivers/gpu/drm/radeon/atombios_crtc.c
··· 1479 1479 } 1480 1480 } 1481 1481 1482 + /** 1483 + * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1484 + * 1485 + * @crtc: drm crtc 1486 + * 1487 + * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1488 + */ 1489 + static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1490 + { 1491 + struct drm_device *dev = crtc->dev; 1492 + struct drm_crtc *test_crtc; 1493 + struct radeon_crtc *radeon_test_crtc; 1494 + u32 pll_in_use = 0; 1495 + 1496 + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1497 + if (crtc == test_crtc) 1498 + continue; 1499 + 1500 + radeon_test_crtc = to_radeon_crtc(test_crtc); 1501 + if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) 1502 + pll_in_use |= (1 << radeon_test_crtc->pll_id); 1503 + } 1504 + return pll_in_use; 1505 + } 1506 + 1507 + /** 1508 + * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1509 + * 1510 + * @crtc: drm crtc 1511 + * 1512 + * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1513 + * also in DP mode. For DP, a single PPLL can be used for all DP 1514 + * crtcs/encoders. 1515 + */ 1516 + static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1517 + { 1518 + struct drm_device *dev = crtc->dev; 1519 + struct drm_encoder *test_encoder; 1520 + struct radeon_crtc *radeon_test_crtc; 1521 + 1522 + list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1523 + if (test_encoder->crtc && (test_encoder->crtc != crtc)) { 1524 + if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1525 + /* for DP use the same PLL for all */ 1526 + radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); 1527 + if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) 1528 + return radeon_test_crtc->pll_id; 1529 + } 1530 + } 1531 + } 1532 + return ATOM_PPLL_INVALID; 1533 + } 1534 + 1535 + /** 1536 + * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1537 + * 1538 + * @crtc: drm crtc 1539 + * 1540 + * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1541 + * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1542 + * monitors a dedicated PPLL must be used. If a particular board has 1543 + * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1544 + * as there is no need to program the PLL itself. If we are not able to 1545 + * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1546 + * avoid messing up an existing monitor. 1547 + * 1548 + * Asic specific PLL information 1549 + * 1550 + * DCE 6.1 1551 + * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1552 + * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1553 + * 1554 + * DCE 6.0 1555 + * - PPLL0 is available to all UNIPHY (DP only) 1556 + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1557 + * 1558 + * DCE 5.0 1559 + * - DCPLL is available to all UNIPHY (DP only) 1560 + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1561 + * 1562 + * DCE 3.0/4.0/4.1 1563 + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1564 + * 1565 + */ 1482 1566 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1483 1567 { 1484 1568 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1485 1569 struct drm_device *dev = crtc->dev; 1486 1570 struct radeon_device *rdev = dev->dev_private; 1487 1571 struct drm_encoder *test_encoder; 1488 - struct drm_crtc *test_crtc; 1489 - uint32_t pll_in_use = 0; 1572 + u32 pll_in_use; 1573 + int pll; 1490 1574 1491 1575 if (ASIC_IS_DCE61(rdev)) { 1492 1576 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { ··· 1582 1498 1583 1499 if ((test_radeon_encoder->encoder_id == 1584 1500 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1585 - (dig->linkb == false)) /* UNIPHY A uses PPLL2 */ 1501 + (dig->linkb == false)) 1502 + /* UNIPHY A uses PPLL2 */ 1586 1503 return ATOM_PPLL2; 1504 + else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1505 + /* UNIPHY B/C/D/E/F */ 1506 + if (rdev->clock.dp_extclk) 1507 + /* skip PPLL programming if using ext clock */ 1508 + return ATOM_PPLL_INVALID; 1509 + else { 1510 + /* use the same PPLL for all DP monitors */ 1511 + pll = radeon_get_shared_dp_ppll(crtc); 1512 + if (pll != ATOM_PPLL_INVALID) 1513 + return pll; 1514 + } 1515 + } 1516 + break; 1587 1517 } 1588 1518 } 1589 1519 /* UNIPHY B/C/D/E/F */ 1590 - list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1591 - struct radeon_crtc *radeon_test_crtc; 1592 - 1593 - if (crtc == test_crtc) 1594 - continue; 1595 - 1596 - radeon_test_crtc = to_radeon_crtc(test_crtc); 1597 - if ((radeon_test_crtc->pll_id == ATOM_PPLL0) || 1598 - (radeon_test_crtc->pll_id == ATOM_PPLL1)) 1599 - pll_in_use |= (1 << radeon_test_crtc->pll_id); 1600 - } 1601 - if (!(pll_in_use & 4)) 1520 + pll_in_use = radeon_get_pll_use_mask(crtc); 1521 + if (!(pll_in_use & (1 << ATOM_PPLL0))) 1602 1522 return ATOM_PPLL0; 1603 - return ATOM_PPLL1; 1523 + if (!(pll_in_use & (1 << ATOM_PPLL1))) 1524 + return ATOM_PPLL1; 1525 + DRM_ERROR("unable to allocate a PPLL\n"); 1526 + return ATOM_PPLL_INVALID; 1604 1527 } else if (ASIC_IS_DCE4(rdev)) { 1605 1528 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1606 1529 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1607 1530 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1608 1531 * depending on the asic: 1609 1532 * DCE4: PPLL or ext clock 1610 - * DCE5: DCPLL or ext clock 1533 + * DCE5: PPLL, DCPLL, or ext clock 1534 + * DCE6: PPLL, PPLL0, or ext clock 1611 1535 * 1612 1536 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1613 1537 * PPLL/DCPLL programming and only program the DP DTO for the ··· 1623 1531 */ 1624 1532 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1625 1533 if (rdev->clock.dp_extclk) 1534 + /* skip PPLL programming if using ext clock */ 1626 1535 return ATOM_PPLL_INVALID; 1627 1536 else if (ASIC_IS_DCE6(rdev)) 1537 + /* use PPLL0 for all DP */ 1628 1538 return ATOM_PPLL0; 1629 1539 else if (ASIC_IS_DCE5(rdev)) 1540 + /* use DCPLL for all DP */ 1630 1541 return ATOM_DCPLL; 1542 + else { 1543 + /* use the same PPLL for all DP monitors */ 1544 + pll = radeon_get_shared_dp_ppll(crtc); 1545 + if (pll != ATOM_PPLL_INVALID) 1546 + return pll; 1547 + } 1631 1548 } 1549 + break; 1632 1550 } 1633 1551 } 1634 - 1635 - /* otherwise, pick one of the plls */ 1636 - list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1637 - struct radeon_crtc *radeon_test_crtc; 1638 - 1639 - if (crtc == test_crtc) 1640 - continue; 1641 - 1642 - radeon_test_crtc = to_radeon_crtc(test_crtc); 1643 - if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1644 - (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1645 - pll_in_use |= (1 << radeon_test_crtc->pll_id); 1646 - } 1647 - if (!(pll_in_use & 1)) 1552 + /* all other cases */ 1553 + pll_in_use = radeon_get_pll_use_mask(crtc); 1554 + if (!(pll_in_use & (1 << ATOM_PPLL2))) 1555 + return ATOM_PPLL2; 1556 + if (!(pll_in_use & (1 << ATOM_PPLL1))) 1648 1557 return ATOM_PPLL1; 1649 - return ATOM_PPLL2; 1558 + DRM_ERROR("unable to allocate a PPLL\n"); 1559 + return ATOM_PPLL_INVALID; 1650 1560 } else 1561 + /* use PPLL1 or PPLL2 */ 1651 1562 return radeon_crtc->crtc_id; 1652 1563 1653 1564 } ··· 1792 1697 break; 1793 1698 } 1794 1699 done: 1795 - radeon_crtc->pll_id = -1; 1700 + radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1796 1701 } 1797 1702 1798 1703 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { ··· 1841 1746 else 1842 1747 radeon_crtc->crtc_offset = 0; 1843 1748 } 1844 - radeon_crtc->pll_id = -1; 1749 + radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1845 1750 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1846 1751 }
+5 -3
drivers/gpu/drm/radeon/radeon_fence.c
··· 131 131 */ 132 132 void radeon_fence_process(struct radeon_device *rdev, int ring) 133 133 { 134 - uint64_t seq, last_seq; 134 + uint64_t seq, last_seq, last_emitted; 135 135 unsigned count_loop = 0; 136 136 bool wake = false; 137 137 ··· 158 158 */ 159 159 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq); 160 160 do { 161 + last_emitted = rdev->fence_drv[ring].sync_seq[ring]; 161 162 seq = radeon_fence_read(rdev, ring); 162 163 seq |= last_seq & 0xffffffff00000000LL; 163 164 if (seq < last_seq) { 164 - seq += 0x100000000LL; 165 + seq &= 0xffffffff; 166 + seq |= last_emitted & 0xffffffff00000000LL; 165 167 } 166 168 167 - if (seq == last_seq) { 169 + if (seq <= last_seq || seq > last_emitted) { 168 170 break; 169 171 } 170 172 /* If we loop over we don't want to return without
+5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
··· 1155 1155 .open = vmw_driver_open, 1156 1156 .preclose = vmw_preclose, 1157 1157 .postclose = vmw_postclose, 1158 + 1159 + .dumb_create = vmw_dumb_create, 1160 + .dumb_map_offset = vmw_dumb_map_offset, 1161 + .dumb_destroy = vmw_dumb_destroy, 1162 + 1158 1163 .fops = &vmwgfx_driver_fops, 1159 1164 .name = VMWGFX_DRIVER_NAME, 1160 1165 .desc = VMWGFX_DRIVER_DESC,
+10
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
··· 645 645 int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data, 646 646 struct drm_file *file_priv); 647 647 648 + int vmw_dumb_create(struct drm_file *file_priv, 649 + struct drm_device *dev, 650 + struct drm_mode_create_dumb *args); 651 + 652 + int vmw_dumb_map_offset(struct drm_file *file_priv, 653 + struct drm_device *dev, uint32_t handle, 654 + uint64_t *offset); 655 + int vmw_dumb_destroy(struct drm_file *file_priv, 656 + struct drm_device *dev, 657 + uint32_t handle); 648 658 /** 649 659 * Overlay control - vmwgfx_overlay.c 650 660 */
+73
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
··· 1917 1917 vmw_resource_unreference(&res); 1918 1918 return ret; 1919 1919 } 1920 + 1921 + 1922 + int vmw_dumb_create(struct drm_file *file_priv, 1923 + struct drm_device *dev, 1924 + struct drm_mode_create_dumb *args) 1925 + { 1926 + struct vmw_private *dev_priv = vmw_priv(dev); 1927 + struct vmw_master *vmaster = vmw_master(file_priv->master); 1928 + struct vmw_user_dma_buffer *vmw_user_bo; 1929 + struct ttm_buffer_object *tmp; 1930 + int ret; 1931 + 1932 + args->pitch = args->width * ((args->bpp + 7) / 8); 1933 + args->size = args->pitch * args->height; 1934 + 1935 + vmw_user_bo = kzalloc(sizeof(*vmw_user_bo), GFP_KERNEL); 1936 + if (vmw_user_bo == NULL) 1937 + return -ENOMEM; 1938 + 1939 + ret = ttm_read_lock(&vmaster->lock, true); 1940 + if (ret != 0) { 1941 + kfree(vmw_user_bo); 1942 + return ret; 1943 + } 1944 + 1945 + ret = vmw_dmabuf_init(dev_priv, &vmw_user_bo->dma, args->size, 1946 + &vmw_vram_sys_placement, true, 1947 + &vmw_user_dmabuf_destroy); 1948 + if (ret != 0) 1949 + goto out_no_dmabuf; 1950 + 1951 + tmp = ttm_bo_reference(&vmw_user_bo->dma.base); 1952 + ret = ttm_base_object_init(vmw_fpriv(file_priv)->tfile, 1953 + &vmw_user_bo->base, 1954 + false, 1955 + ttm_buffer_type, 1956 + &vmw_user_dmabuf_release, NULL); 1957 + if (unlikely(ret != 0)) 1958 + goto out_no_base_object; 1959 + 1960 + args->handle = vmw_user_bo->base.hash.key; 1961 + 1962 + out_no_base_object: 1963 + ttm_bo_unref(&tmp); 1964 + out_no_dmabuf: 1965 + ttm_read_unlock(&vmaster->lock); 1966 + return ret; 1967 + } 1968 + 1969 + int vmw_dumb_map_offset(struct drm_file *file_priv, 1970 + struct drm_device *dev, uint32_t handle, 1971 + uint64_t *offset) 1972 + { 1973 + struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 1974 + struct vmw_dma_buffer *out_buf; 1975 + int ret; 1976 + 1977 + ret = vmw_user_dmabuf_lookup(tfile, handle, &out_buf); 1978 + if (ret != 0) 1979 + return -EINVAL; 1980 + 1981 + *offset = out_buf->base.addr_space_offset; 1982 + vmw_dmabuf_unreference(&out_buf); 1983 + return 0; 1984 + } 1985 + 1986 + int vmw_dumb_destroy(struct drm_file *file_priv, 1987 + struct drm_device *dev, 1988 + uint32_t handle) 1989 + { 1990 + return ttm_ref_object_base_unref(vmw_fpriv(file_priv)->tfile, 1991 + handle, TTM_REF_USAGE); 1992 + }
+1 -5
include/drm/drm_fourcc.h
··· 107 107 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 108 108 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 109 109 110 - /* 2 non contiguous plane YCbCr */ 111 - #define DRM_FORMAT_NV12M fourcc_code('N', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 110 + /* special NV12 tiled format */ 112 111 #define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */ 113 112 114 113 /* ··· 129 130 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 130 131 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 131 132 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 132 - 133 - /* 3 non contiguous plane YCbCr */ 134 - #define DRM_FORMAT_YUV420M fourcc_code('Y', 'M', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 135 133 136 134 #endif /* DRM_FOURCC_H */