tjh.dev / kernel
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drm/rcar-du: dsi: Respect DSI mode flags

Cache DSI mode flags in new mode_flags member of struct rcar_mipi_dsi .
Configure TXVMSETR register based on the content of DSI mode flags in
case the controller operates in video mode.

Rename TXVMSETR_H..BPEN_EN to TXVMSETR_H..BPEN and drop TXVMSETR_H..BPEN_DIS
which resolves to 0. Update TXVMSETR_VSEN in the same manner. Replace
TXVMSETR_SYNSEQ_PULSES with a code comment next to TXVMSETR_SYNSEQ_EVENTS
because TXVMSETR_SYNSEQ_PULSES resolves to 0.

Do not convert bits and bitfields to BIT() and GENMASK() yet, to be
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-9-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

authored by

Marek Vasut and committed by
Tomi Valkeinen dd3957e0 7d9949a8

+20 -13
+15 -3
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
··· 72 72 } clocks; 73 73 74 74 enum mipi_dsi_pixel_format format; 75 + unsigned long mode_flags; 75 76 unsigned int num_data_lanes; 76 77 unsigned int lanes; 77 78 }; ··· 475 474 } 476 475 477 476 /* Configuration for Blanking sequence and Input Pixel */ 478 - setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN 479 - | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES 480 - | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM; 477 + setr = TXVMSETR_PIXWDTH | TXVMSETR_VSTPM; 478 + 479 + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 480 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) 481 + setr |= TXVMSETR_SYNSEQ_EVENTS; 482 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)) 483 + setr |= TXVMSETR_HFPBPEN; 484 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)) 485 + setr |= TXVMSETR_HBPBPEN; 486 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)) 487 + setr |= TXVMSETR_HSABPEN; 488 + } 489 + 481 490 rcar_mipi_dsi_write(dsi, TXVMSETR, setr); 482 491 483 492 /* Configuration for Video Parameters */ ··· 928 917 929 918 dsi->lanes = device->lanes; 930 919 dsi->format = device->format; 920 + dsi->mode_flags = device->mode_flags; 931 921 932 922 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 933 923 1, 0);
+5 -10
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
··· 140 140 * Video Mode Register 141 141 */ 142 142 #define TXVMSETR 0x180 143 - #define TXVMSETR_SYNSEQ_PULSES (0 << 16) 144 - #define TXVMSETR_SYNSEQ_EVENTS (1 << 16) 143 + #define TXVMSETR_SYNSEQ_EVENTS (1 << 16) /* 0:Pulses 1:Events */ 145 144 #define TXVMSETR_VSTPM (1 << 15) 146 145 #define TXVMSETR_PIXWDTH_MASK (7 << 8) 147 146 #define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */ 148 - #define TXVMSETR_VSEN_EN (1 << 4) 149 - #define TXVMSETR_VSEN_DIS (0 << 4) 150 - #define TXVMSETR_HFPBPEN_EN (1 << 2) 151 - #define TXVMSETR_HFPBPEN_DIS (0 << 2) 152 - #define TXVMSETR_HBPBPEN_EN (1 << 1) 153 - #define TXVMSETR_HBPBPEN_DIS (0 << 1) 154 - #define TXVMSETR_HSABPEN_EN (1 << 0) 155 - #define TXVMSETR_HSABPEN_DIS (0 << 0) 147 + #define TXVMSETR_VSEN (1 << 4) 148 + #define TXVMSETR_HFPBPEN (1 << 2) 149 + #define TXVMSETR_HBPBPEN (1 << 1) 150 + #define TXVMSETR_HSABPEN (1 << 0) 156 151 157 152 #define TXVMCR 0x190 158 153 #define TXVMCR_VFCLR (1 << 12)