Merge tag 'mmc-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

+2

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml

··· 21 21 - items: 22 22 - enum: 23 23 - brcm,bcm2712-sdhci 24 + - brcm,bcm72116-sdhci 24 25 - brcm,bcm74165b0-sdhci 25 26 - brcm,bcm7445-sdhci 26 27 - brcm,bcm7425-sdhci 28 + - brcm,bcm74371-sdhci 27 29 - const: brcm,sdhci-brcmstb 28 30 29 31 reg:

-32

Documentation/devicetree/bindings/mmc/davinci_mmc.txt

··· 1 - * TI Highspeed MMC host controller for DaVinci 2 - 3 - The Highspeed MMC Host Controller on TI DaVinci family 4 - provides an interface for MMC, SD and SDIO types of memory cards. 5 - 6 - This file documents the properties used by the davinci_mmc driver. 7 - 8 - Required properties: 9 - - compatible: 10 - Should be "ti,da830-mmc": for da830, da850, dm365 11 - Should be "ti,dm355-mmc": for dm355, dm644x 12 - 13 - Optional properties: 14 - - bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1> 15 - - max-frequency: Maximum operating clock frequency, default 25MHz. 16 - - dmas: List of DMA specifiers with the controller specific format 17 - as described in the generic DMA client binding. A tx and rx 18 - specifier is required. 19 - - dma-names: RX and TX DMA request names. These strings correspond 20 - 1:1 with the DMA specifiers listed in dmas. 21 - 22 - Example: 23 - mmc0: mmc@1c40000 { 24 - compatible = "ti,da830-mmc", 25 - reg = <0x40000 0x1000>; 26 - interrupts = <16>; 27 - bus-width = <4>; 28 - max-frequency = <50000000>; 29 - dmas = <&edma 16 30 - &edma 17>; 31 - dma-names = "rx", "tx"; 32 - };

+1

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml

··· 38 38 - rockchip,rk3328-dw-mshc 39 39 - rockchip,rk3368-dw-mshc 40 40 - rockchip,rk3399-dw-mshc 41 + - rockchip,rk3506-dw-mshc 41 42 - rockchip,rk3528-dw-mshc 42 43 - rockchip,rk3562-dw-mshc 43 44 - rockchip,rk3568-dw-mshc

+1 -2

Documentation/devicetree/bindings/mmc/sdhci-am654.yaml

··· 50 50 - const: clk_ahb 51 51 - const: clk_xin 52 52 53 - dma-coherent: 54 - type: boolean 53 + dma-coherent: true 55 54 56 55 # PHY output tap delays: 57 56 # Used to delay the data valid window and align it to the sampling clock.

-30

Documentation/devicetree/bindings/mmc/sdhci-milbeaut.txt

··· 1 - * SOCIONEXT Milbeaut SDHCI controller 2 - 3 - This file documents differences between the core properties in mmc.txt 4 - and the properties used by the sdhci_milbeaut driver. 5 - 6 - Required properties: 7 - - compatible: "socionext,milbeaut-m10v-sdhci-3.0" 8 - - clocks: Must contain an entry for each entry in clock-names. It is a 9 - list of phandles and clock-specifier pairs. 10 - See ../clocks/clock-bindings.txt for details. 11 - - clock-names: Should contain the following two entries: 12 - "iface" - clock used for sdhci interface 13 - "core" - core clock for sdhci controller 14 - 15 - Optional properties: 16 - - fujitsu,cmd-dat-delay-select: boolean property indicating that this host 17 - requires the CMD_DAT_DELAY control to be enabled. 18 - 19 - Example: 20 - sdhci3: mmc@1b010000 { 21 - compatible = "socionext,milbeaut-m10v-sdhci-3.0"; 22 - reg = <0x1b010000 0x10000>; 23 - interrupts = <0 265 0x4>; 24 - voltage-ranges = <3300 3300>; 25 - bus-width = <4>; 26 - clocks = <&clk 7>, <&ahb_clk>; 27 - clock-names = "core", "iface"; 28 - cap-sdio-irq; 29 - fujitsu,cmd-dat-delay-select; 30 - };

+2

Documentation/devicetree/bindings/mmc/sdhci-msm.yaml

··· 42 42 - qcom,ipq5424-sdhci 43 43 - qcom,ipq6018-sdhci 44 44 - qcom,ipq9574-sdhci 45 + - qcom,kaanapali-sdhci 45 46 - qcom,milos-sdhci 46 47 - qcom,qcm2290-sdhci 47 48 - qcom,qcs404-sdhci ··· 71 70 - qcom,sm8450-sdhci 72 71 - qcom,sm8550-sdhci 73 72 - qcom,sm8650-sdhci 73 + - qcom,sm8750-sdhci 74 74 - qcom,x1e80100-sdhci 75 75 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 76 76

+51 -6

Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml

··· 30 30 - sophgo,sg2002-dwcmshc 31 31 - sophgo,sg2042-dwcmshc 32 32 - thead,th1520-dwcmshc 33 + - eswin,eic7700-dwcmshc 33 34 34 35 reg: 35 36 maxItems: 1 ··· 53 52 maxItems: 5 54 53 55 54 reset-names: 56 - items: 57 - - const: core 58 - - const: bus 59 - - const: axi 60 - - const: block 61 - - const: timer 55 + maxItems: 5 62 56 63 57 rockchip,txclk-tapnum: 64 58 description: Specify the number of delay for tx sampling. 65 59 $ref: /schemas/types.yaml#/definitions/uint8 60 + 61 + eswin,hsp-sp-csr: 62 + $ref: /schemas/types.yaml#/definitions/phandle-array 63 + items: 64 + - items: 65 + - description: Phandle to HSP(High-Speed Peripheral) device 66 + - description: Offset of the stability status register for internal 67 + clock. 68 + - description: Offset of the stability register for host regulator 69 + voltage. 70 + description: 71 + HSP CSR is to control and get status of different high-speed peripherals 72 + (such as Ethernet, USB, SATA, etc.) via register, which can tune 73 + board-level's parameters of PHY, etc. 74 + 75 + eswin,drive-impedance-ohms: 76 + description: Specifies the drive impedance in Ohm. 77 + enum: [33, 40, 50, 66, 100] 66 78 67 79 required: 68 80 - compatible ··· 117 103 - description: timer clock for rockchip specified 118 104 clock-names: 119 105 minItems: 1 106 + items: 107 + - const: core 108 + - const: bus 109 + - const: axi 110 + - const: block 111 + - const: timer 112 + 113 + - if: 114 + properties: 115 + compatible: 116 + contains: 117 + const: eswin,eic7700-dwcmshc 118 + then: 119 + properties: 120 + resets: 121 + minItems: 4 122 + maxItems: 4 123 + reset-names: 124 + items: 125 + - const: axi 126 + - const: phy 127 + - const: prstn 128 + - const: txrx 129 + required: 130 + - eswin,hsp-sp-csr 131 + - eswin,drive-impedance-ohms 132 + else: 133 + properties: 134 + resets: 135 + maxItems: 5 136 + reset-names: 120 137 items: 121 138 - const: core 122 139 - const: bus

+79

Documentation/devicetree/bindings/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: SOCIONEXT Milbeaut SDHCI controller 8 + 9 + maintainers: 10 + - Taichi Sugaya <sugaya.taichi@socionext.com> 11 + - Takao Orito <orito.takao@socionext.com> 12 + 13 + description: 14 + The SOCIONEXT Milbeaut SDHCI controller is a specialized SD Host 15 + Controller found in some of Socionext's Milbeaut image processing SoCs. 16 + It features a dedicated "bridge controller." This bridge controller 17 + implements special functions like reset control, clock management for 18 + various SDR modes (SDR12, SDR25, SDR50) and physical pin property settings. 19 + 20 + allOf: 21 + - $ref: sdhci-common.yaml# 22 + 23 + properties: 24 + compatible: 25 + const: socionext,milbeaut-m10v-sdhci-3.0 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + interrupts: 31 + maxItems: 1 32 + 33 + clocks: 34 + maxItems: 2 35 + 36 + clock-names: 37 + items: 38 + - const: core 39 + - const: iface 40 + 41 + fujitsu,cmd-dat-delay-select: 42 + description: 43 + Its presence indicates that the controller requires a specific command 44 + and data line delay selection mechanism for proper operation, particularly 45 + when dealing with high-speed SD/eMMC modes. 46 + type: boolean 47 + 48 + voltage-ranges: 49 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 50 + items: 51 + items: 52 + - description: minimum slot voltage (mV). 53 + - description: maximum slot voltage (mV). 54 + maxItems: 1 55 + 56 + required: 57 + - compatible 58 + - reg 59 + - interrupts 60 + - clocks 61 + - clock-names 62 + 63 + unevaluatedProperties: false 64 + 65 + examples: 66 + - | 67 + #include <dt-bindings/interrupt-controller/arm-gic.h> 68 + mmc@1b010000 { 69 + compatible = "socionext,milbeaut-m10v-sdhci-3.0"; 70 + reg = <0x1b010000 0x10000>; 71 + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 72 + voltage-ranges = <3300 3300>; 73 + bus-width = <4>; 74 + clocks = <&clk 7>, <&ahb_clk>; 75 + clock-names = "core", "iface"; 76 + cap-sdio-irq; 77 + fujitsu,cmd-dat-delay-select; 78 + }; 79 + ...

+61

Documentation/devicetree/bindings/mmc/ti,da830-mmc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/ti,da830-mmc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TI Highspeed MMC host controller for DaVinci 8 + 9 + description: 10 + The Highspeed MMC Host Controller on TI DaVinci family 11 + provides an interface for MMC, SD and SDIO types of memory cards. 12 + 13 + allOf: 14 + - $ref: mmc-controller.yaml 15 + 16 + maintainers: 17 + - Kishon Vijay Abraham I <kishon@kernel.org> 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - ti,da830-mmc 23 + - ti,dm355-mmc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + clocks: 29 + maxItems: 1 30 + 31 + interrupts: 32 + maxItems: 2 33 + 34 + dmas: 35 + maxItems: 2 36 + 37 + dma-names: 38 + items: 39 + - const: rx 40 + - const: tx 41 + 42 + required: 43 + - compatible 44 + - reg 45 + 46 + unevaluatedProperties: false 47 + 48 + examples: 49 + - | 50 + #include <dt-bindings/interrupt-controller/irq.h> 51 + mmc@1c40000 { 52 + compatible = "ti,da830-mmc"; 53 + reg = <0x40000 0x1000>; 54 + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, 55 + <17 IRQ_TYPE_LEVEL_HIGH>; 56 + bus-width = <4>; 57 + max-frequency = <50000000>; 58 + dmas = <&edma 16>, <&edma 17>; 59 + dma-names = "rx", "tx"; 60 + }; 61 + ...

+1

MAINTAINERS

··· 25119 25119 25120 25120 SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER 25121 25121 M: Jaehoon Chung <jh80.chung@samsung.com> 25122 + M: Shawn Lin <shawn.lin@rock-chips.com> 25122 25123 L: linux-mmc@vger.kernel.org 25123 25124 S: Maintained 25124 25125 F: drivers/mmc/host/dw_mmc*

+6 -8

drivers/mmc/core/block.c

··· 349 349 if (a == &dev_attr_ro_lock_until_next_power_on.attr && 350 350 (md->area_type & MMC_BLK_DATA_AREA_BOOT) && 351 351 md->queue.card->ext_csd.boot_ro_lockable) { 352 - mode = S_IRUGO; 352 + mode = 0444; 353 353 if (!(md->queue.card->ext_csd.boot_ro_lock & 354 354 EXT_CSD_BOOT_WP_B_PWR_WP_DIS)) 355 - mode |= S_IWUSR; 355 + mode |= 0200; 356 356 } 357 357 358 358 mmc_blk_put(md); ··· 957 957 u32 result; 958 958 __be32 *blocks; 959 959 u8 resp_sz = mmc_card_ult_capacity(card) ? 8 : 4; 960 - unsigned int noio_flag; 961 960 962 961 struct mmc_request mrq = {}; 963 962 struct mmc_command cmd = {}; ··· 981 982 mrq.cmd = &cmd; 982 983 mrq.data = &data; 983 984 984 - noio_flag = memalloc_noio_save(); 985 - blocks = kmalloc(resp_sz, GFP_KERNEL); 986 - memalloc_noio_restore(noio_flag); 985 + blocks = kmalloc(resp_sz, GFP_NOIO); 987 986 if (!blocks) 988 987 return -ENOMEM; 989 988 ··· 3191 3194 3192 3195 if (mmc_card_mmc(card)) { 3193 3196 md->ext_csd_dentry = 3194 - debugfs_create_file("ext_csd", S_IRUSR, root, card, 3197 + debugfs_create_file("ext_csd", 0400, root, card, 3195 3198 &mmc_dbg_ext_csd_fops); 3196 3199 } 3197 3200 } ··· 3272 3275 mmc_fixup_device(card, mmc_blk_fixups); 3273 3276 3274 3277 card->complete_wq = alloc_workqueue("mmc_complete", 3275 - WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); 3278 + WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_PERCPU, 3279 + 0); 3276 3280 if (!card->complete_wq) { 3277 3281 pr_err("Failed to create mmc completion workqueue"); 3278 3282 return -ENOMEM;

+1 -1

drivers/mmc/core/bus.h

··· 20 20 struct mmc_card *card = mmc_dev_to_card(dev); \ 21 21 return sysfs_emit(buf, fmt, args); \ 22 22 } \ 23 - static DEVICE_ATTR(name, S_IRUGO, mmc_##name##_show, NULL) 23 + static DEVICE_ATTR(name, 0444, mmc_##name##_show, NULL) 24 24 25 25 struct mmc_card *mmc_alloc_card(struct mmc_host *host, 26 26 const struct device_type *type);

+8 -2

drivers/mmc/core/debugfs.c

··· 315 315 MMC_CAP_SD_HIGHSPEED | 316 316 MMC_CAP_MMC_HIGHSPEED | 317 317 MMC_CAP_UHS | 318 - MMC_CAP_DDR; 318 + MMC_CAP_DDR | 319 + MMC_CAP_4_BIT_DATA | 320 + MMC_CAP_8_BIT_DATA | 321 + MMC_CAP_CMD23; 319 322 320 323 if (diff & ~allowed) 321 324 return -EINVAL; ··· 330 327 331 328 static int mmc_caps2_set(void *data, u64 val) 332 329 { 333 - u32 allowed = MMC_CAP2_HSX00_1_8V | MMC_CAP2_HSX00_1_2V; 330 + u32 allowed = MMC_CAP2_HSX00_1_8V | 331 + MMC_CAP2_HSX00_1_2V | 332 + MMC_CAP2_CQE | 333 + MMC_CAP2_CQE_DCMD; 334 334 u32 *caps = data; 335 335 u32 diff = *caps ^ val; 336 336

+2 -2

drivers/mmc/core/mmc.c

··· 831 831 card->ext_csd.fwrev); 832 832 } 833 833 834 - static DEVICE_ATTR(fwrev, S_IRUGO, mmc_fwrev_show, NULL); 834 + static DEVICE_ATTR(fwrev, 0444, mmc_fwrev_show, NULL); 835 835 836 836 static ssize_t mmc_dsr_show(struct device *dev, 837 837 struct device_attribute *attr, ··· 847 847 return sysfs_emit(buf, "0x%x\n", 0x404); 848 848 } 849 849 850 - static DEVICE_ATTR(dsr, S_IRUGO, mmc_dsr_show, NULL); 850 + static DEVICE_ATTR(dsr, 0444, mmc_dsr_show, NULL); 851 851 852 852 static struct attribute *mmc_std_attrs[] = { 853 853 &dev_attr_cid.attr,

+2 -2

drivers/mmc/core/mmc_test.c

··· 3208 3208 3209 3209 mutex_lock(&mmc_test_lock); 3210 3210 3211 - ret = __mmc_test_register_dbgfs_file(card, "test", S_IWUSR | S_IRUGO, 3211 + ret = __mmc_test_register_dbgfs_file(card, "test", 0644, 3212 3212 &mmc_test_fops_test); 3213 3213 if (ret) 3214 3214 goto err; 3215 3215 3216 - ret = __mmc_test_register_dbgfs_file(card, "testlist", S_IRUGO, 3216 + ret = __mmc_test_register_dbgfs_file(card, "testlist", 0444, 3217 3217 &mtf_testlist_fops); 3218 3218 if (ret) 3219 3219 goto err;

+3 -6

drivers/mmc/core/sd.c

··· 554 554 555 555 static int sd_set_current_limit(struct mmc_card *card, u8 *status) 556 556 { 557 - int current_limit = SD_SET_CURRENT_NO_CHANGE; 557 + int current_limit = SD_SET_CURRENT_LIMIT_200; 558 558 int err; 559 559 u32 max_current; 560 560 ··· 598 598 else if (max_current >= 400 && 599 599 card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_400) 600 600 current_limit = SD_SET_CURRENT_LIMIT_400; 601 - else if (max_current >= 200 && 602 - card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_200) 603 - current_limit = SD_SET_CURRENT_LIMIT_200; 604 601 605 - if (current_limit != SD_SET_CURRENT_NO_CHANGE) { 602 + if (current_limit != SD_SET_CURRENT_LIMIT_200) { 606 603 err = mmc_sd_switch(card, SD_SWITCH_SET, 3, 607 604 current_limit, status); 608 605 if (err) ··· 741 744 return sysfs_emit(buf, "0x%x\n", 0x404); 742 745 } 743 746 744 - static DEVICE_ATTR(dsr, S_IRUGO, mmc_dsr_show, NULL); 747 + static DEVICE_ATTR(dsr, 0444, mmc_dsr_show, NULL); 745 748 746 749 MMC_DEV_ATTR(vendor, "0x%04x\n", card->cis.vendor); 747 750 MMC_DEV_ATTR(device, "0x%04x\n", card->cis.device);

+1

drivers/mmc/host/Kconfig

··· 504 504 depends on ARCH_MESON || COMPILE_TEST 505 505 depends on COMMON_CLK 506 506 depends on OF_ADDRESS 507 + select REGMAP_MMIO 507 508 help 508 509 This selects support for the SD/MMC Host Controller on 509 510 Amlogic Meson6, Meson8 and Meson8b SoCs.

+5 -5

drivers/mmc/host/atmel-mci.c

··· 609 609 if (!root) 610 610 return; 611 611 612 - debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops); 613 - debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 614 - debugfs_create_u32("state", S_IRUSR, root, &host->state); 615 - debugfs_create_xul("pending_events", S_IRUSR, root, 612 + debugfs_create_file("regs", 0400, root, host, &atmci_regs_fops); 613 + debugfs_create_file("req", 0400, root, slot, &atmci_req_fops); 614 + debugfs_create_u32("state", 0400, root, &host->state); 615 + debugfs_create_xul("pending_events", 0400, root, 616 616 &host->pending_events); 617 - debugfs_create_xul("completed_events", S_IRUSR, root, 617 + debugfs_create_xul("completed_events", 0400, root, 618 618 &host->completed_events); 619 619 } 620 620

+1

drivers/mmc/host/cqhci.h

··· 93 93 /* send status config 1 */ 94 94 #define CQHCI_SSC1 0x40 95 95 #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) 96 + #define CQHCI_SSC1_CIT_MASK GENMASK(15, 0) 96 97 97 98 /* send status config 2 */ 98 99 #define CQHCI_SSC2 0x44

+3 -3

drivers/mmc/host/davinci_mmc.c

··· 145 145 #define MAX_NR_SG 16 146 146 147 147 static unsigned rw_threshold = 32; 148 - module_param(rw_threshold, uint, S_IRUGO); 148 + module_param(rw_threshold, uint, 0444); 149 149 MODULE_PARM_DESC(rw_threshold, 150 150 "Read/Write threshold. Default = 32"); 151 151 152 152 static unsigned poll_threshold = 128; 153 - module_param(poll_threshold, uint, S_IRUGO); 153 + module_param(poll_threshold, uint, 0444); 154 154 MODULE_PARM_DESC(poll_threshold, 155 155 "Polling transaction size threshold. Default = 128"); 156 156 157 157 static unsigned poll_loopcount = 32; 158 - module_param(poll_loopcount, uint, S_IRUGO); 158 + module_param(poll_loopcount, uint, 0444); 159 159 MODULE_PARM_DESC(poll_loopcount, 160 160 "Maximum polling loop count. Default = 32"); 161 161

+6

drivers/mmc/host/dw_mmc-rockchip.c

··· 19 19 #define RK3288_CLKGEN_DIV 2 20 20 #define SDMMC_TIMING_CON0 0x130 21 21 #define SDMMC_TIMING_CON1 0x134 22 + #define SDMMC_MISC_CON 0x138 23 + #define MEM_CLK_AUTOGATE_ENABLE BIT(5) 22 24 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 23 25 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 24 26 #define ROCKCHIP_MMC_DEGREE_OFFSET 1 ··· 472 470 473 471 static int dw_mci_rockchip_init(struct dw_mci *host) 474 472 { 473 + struct dw_mci_rockchip_priv_data *priv = host->priv; 475 474 int ret, i; 476 475 477 476 /* It is slot 8 on Rockchip SoCs */ ··· 496 493 if (ret < 0) 497 494 dev_warn(host->dev, "no valid minimum freq: %d\n", ret); 498 495 } 496 + 497 + if (priv->internal_phase) 498 + mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); 499 499 500 500 return 0; 501 501 }

+7 -8

drivers/mmc/host/dw_mmc.c

··· 175 175 if (!root) 176 176 return; 177 177 178 - debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops); 179 - debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops); 180 - debugfs_create_u32("state", S_IRUSR, root, &host->state); 181 - debugfs_create_xul("pending_events", S_IRUSR, root, 178 + debugfs_create_file("regs", 0400, root, host, &dw_mci_regs_fops); 179 + debugfs_create_file("req", 0400, root, slot, &dw_mci_req_fops); 180 + debugfs_create_u32("state", 0400, root, &host->state); 181 + debugfs_create_xul("pending_events", 0400, root, 182 182 &host->pending_events); 183 - debugfs_create_xul("completed_events", S_IRUSR, root, 183 + debugfs_create_xul("completed_events", 0400, root, 184 184 &host->completed_events); 185 185 #ifdef CONFIG_FAULT_INJECTION 186 186 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); ··· 3120 3120 host->dma_64bit_address = 1; 3121 3121 dev_info(host->dev, 3122 3122 "IDMAC supports 64-bit address mode.\n"); 3123 - if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 3124 - dma_set_coherent_mask(host->dev, 3125 - DMA_BIT_MASK(64)); 3123 + if (dma_set_mask_and_coherent(host->dev, DMA_BIT_MASK(64))) 3124 + dev_info(host->dev, "Fail to set 64-bit DMA mask"); 3126 3125 } else { 3127 3126 /* host supports IDMAC in 32-bit address mode */ 3128 3127 host->dma_64bit_address = 0;

+168 -169

drivers/mmc/host/meson-mx-sdio.c

··· 19 19 #include <linux/ioport.h> 20 20 #include <linux/platform_device.h> 21 21 #include <linux/of_platform.h> 22 + #include <linux/regmap.h> 22 23 #include <linux/timer.h> 23 24 #include <linux/types.h> 24 25 ··· 99 98 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) 100 99 #define MESON_MX_SDIO_MAX_SLOTS 3 101 100 101 + struct meson_mx_mmc_host_clkc { 102 + struct clk_divider cfg_div; 103 + struct clk_fixed_factor fixed_div2; 104 + }; 105 + 102 106 struct meson_mx_mmc_host { 103 107 struct device *controller_dev; 104 108 105 - struct clk *parent_clk; 106 - struct clk *core_clk; 107 - struct clk_divider cfg_div; 108 109 struct clk *cfg_div_clk; 109 - struct clk_fixed_factor fixed_factor; 110 - struct clk *fixed_factor_clk; 111 - 112 - void __iomem *base; 110 + struct regmap *regmap; 113 111 int irq; 114 112 spinlock_t irq_lock; 115 113 ··· 122 122 int error; 123 123 }; 124 124 125 - static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, 126 - u32 val) 127 - { 128 - struct meson_mx_mmc_host *host = mmc_priv(mmc); 129 - u32 regval; 130 - 131 - regval = readl(host->base + reg); 132 - regval &= ~mask; 133 - regval |= (val & mask); 134 - 135 - writel(regval, host->base + reg); 136 - } 137 - 138 125 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host) 139 126 { 140 - writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); 127 + regmap_write(host->regmap, MESON_MX_SDIO_IRQC, 128 + MESON_MX_SDIO_IRQC_SOFT_RESET); 141 129 udelay(2); 142 130 } 143 131 ··· 146 158 struct meson_mx_mmc_host *host = mmc_priv(mmc); 147 159 unsigned int pack_size; 148 160 unsigned long irqflags, timeout; 149 - u32 mult, send = 0, ext = 0; 161 + u32 send = 0, ext = 0; 150 162 151 163 host->cmd = cmd; 152 164 ··· 203 215 204 216 spin_lock_irqsave(&host->irq_lock, irqflags); 205 217 206 - mult = readl(host->base + MESON_MX_SDIO_MULT); 207 - mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK; 208 - mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id); 209 - mult |= BIT(31); 210 - writel(mult, host->base + MESON_MX_SDIO_MULT); 218 + regmap_update_bits(host->regmap, MESON_MX_SDIO_MULT, 219 + MESON_MX_SDIO_MULT_PORT_SEL_MASK | BIT(31), 220 + FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, 221 + host->slot_id) | BIT(31)); 211 222 212 223 /* enable the CMD done interrupt */ 213 - meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC, 214 - MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN, 215 - MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); 224 + regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQC, 225 + MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); 216 226 217 227 /* clear pending interrupts */ 218 - meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS, 219 - MESON_MX_SDIO_IRQS_CMD_INT, 220 - MESON_MX_SDIO_IRQS_CMD_INT); 228 + regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQS, 229 + MESON_MX_SDIO_IRQS_CMD_INT); 221 230 222 - writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); 223 - writel(ext, host->base + MESON_MX_SDIO_EXT); 224 - writel(send, host->base + MESON_MX_SDIO_SEND); 231 + regmap_write(host->regmap, MESON_MX_SDIO_ARGU, cmd->arg); 232 + regmap_write(host->regmap, MESON_MX_SDIO_EXT, ext); 233 + regmap_write(host->regmap, MESON_MX_SDIO_SEND, send); 225 234 226 235 spin_unlock_irqrestore(&host->irq_lock, irqflags); 227 236 ··· 248 263 249 264 switch (ios->bus_width) { 250 265 case MMC_BUS_WIDTH_1: 251 - meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 252 - MESON_MX_SDIO_CONF_BUS_WIDTH, 0); 266 + regmap_clear_bits(host->regmap, MESON_MX_SDIO_CONF, 267 + MESON_MX_SDIO_CONF_BUS_WIDTH); 253 268 break; 254 269 255 270 case MMC_BUS_WIDTH_4: 256 - meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 257 - MESON_MX_SDIO_CONF_BUS_WIDTH, 258 - MESON_MX_SDIO_CONF_BUS_WIDTH); 271 + regmap_set_bits(host->regmap, MESON_MX_SDIO_CONF, 272 + MESON_MX_SDIO_CONF_BUS_WIDTH); 259 273 break; 260 274 261 275 case MMC_BUS_WIDTH_8: ··· 335 351 host->mrq = mrq; 336 352 337 353 if (mrq->data) 338 - writel(sg_dma_address(mrq->data->sg), 339 - host->base + MESON_MX_SDIO_ADDR); 354 + regmap_write(host->regmap, MESON_MX_SDIO_ADDR, 355 + sg_dma_address(mrq->data->sg)); 340 356 341 357 if (mrq->sbc) 342 358 meson_mx_mmc_start_cmd(mmc, mrq->sbc); ··· 348 364 struct mmc_command *cmd) 349 365 { 350 366 struct meson_mx_mmc_host *host = mmc_priv(mmc); 351 - u32 mult; 352 - int i, resp[4]; 367 + unsigned int i, resp[4]; 353 368 354 - mult = readl(host->base + MESON_MX_SDIO_MULT); 355 - mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX; 356 - mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK; 357 - mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0); 358 - writel(mult, host->base + MESON_MX_SDIO_MULT); 369 + regmap_update_bits(host->regmap, MESON_MX_SDIO_MULT, 370 + MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX | 371 + MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 372 + MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX | 373 + FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 374 + 0)); 359 375 360 376 if (cmd->flags & MMC_RSP_136) { 361 377 for (i = 0; i <= 3; i++) 362 - resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); 378 + regmap_read(host->regmap, MESON_MX_SDIO_ARGU, 379 + &resp[3 - i]); 380 + 363 381 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff); 364 382 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff); 365 383 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff); 366 384 cmd->resp[3] = (resp[3] << 8); 367 385 } else if (cmd->flags & MMC_RSP_PRESENT) { 368 - cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); 386 + regmap_read(host->regmap, MESON_MX_SDIO_ARGU, &cmd->resp[0]); 369 387 } 370 388 } 371 389 ··· 408 422 409 423 spin_lock(&host->irq_lock); 410 424 411 - irqs = readl(host->base + MESON_MX_SDIO_IRQS); 412 - send = readl(host->base + MESON_MX_SDIO_SEND); 425 + regmap_read(host->regmap, MESON_MX_SDIO_IRQS, &irqs); 426 + regmap_read(host->regmap, MESON_MX_SDIO_SEND, &send); 413 427 414 428 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT) 415 429 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send); ··· 417 431 ret = IRQ_HANDLED; 418 432 419 433 /* finally ACK all pending interrupts */ 420 - writel(irqs, host->base + MESON_MX_SDIO_IRQS); 434 + regmap_write(host->regmap, MESON_MX_SDIO_IRQS, irqs); 421 435 422 436 spin_unlock(&host->irq_lock); 423 437 ··· 436 450 437 451 if (cmd->data) { 438 452 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, 439 - cmd->data->sg_len, 440 - mmc_get_dma_dir(cmd->data)); 453 + cmd->data->sg_len, mmc_get_dma_dir(cmd->data)); 441 454 442 455 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; 443 456 } ··· 455 470 struct meson_mx_mmc_host *host = timer_container_of(host, t, 456 471 cmd_timeout); 457 472 unsigned long irqflags; 458 - u32 irqc; 473 + u32 irqs, argu; 459 474 460 475 spin_lock_irqsave(&host->irq_lock, irqflags); 461 476 462 477 /* disable the CMD interrupt */ 463 - irqc = readl(host->base + MESON_MX_SDIO_IRQC); 464 - irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN; 465 - writel(irqc, host->base + MESON_MX_SDIO_IRQC); 478 + regmap_clear_bits(host->regmap, MESON_MX_SDIO_IRQC, 479 + MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); 466 480 467 481 spin_unlock_irqrestore(&host->irq_lock, irqflags); 468 482 ··· 472 488 if (!host->cmd) 473 489 return; 474 490 491 + regmap_read(host->regmap, MESON_MX_SDIO_IRQS, &irqs); 492 + regmap_read(host->regmap, MESON_MX_SDIO_ARGU, &argu); 493 + 475 494 dev_dbg(mmc_dev(host->mmc), 476 495 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n", 477 - host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), 478 - readl(host->base + MESON_MX_SDIO_ARGU)); 496 + host->cmd->opcode, irqs, argu); 479 497 480 498 host->cmd->error = -ETIMEDOUT; 481 499 ··· 493 507 494 508 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent) 495 509 { 496 - struct device_node *slot_node; 497 - struct platform_device *pdev; 510 + struct platform_device *pdev = NULL; 498 511 499 - /* 500 - * TODO: the MMC core framework currently does not support 501 - * controllers with multiple slots properly. So we only register 502 - * the first slot for now 503 - */ 504 - slot_node = of_get_compatible_child(parent->of_node, "mmc-slot"); 505 - if (!slot_node) { 506 - dev_warn(parent, "no 'mmc-slot' sub-node found\n"); 507 - return ERR_PTR(-ENOENT); 512 + for_each_available_child_of_node_scoped(parent->of_node, slot_node) { 513 + if (!of_device_is_compatible(slot_node, "mmc-slot")) 514 + continue; 515 + 516 + /* 517 + * TODO: the MMC core framework currently does not support 518 + * controllers with multiple slots properly. So we only 519 + * register the first slot for now. 520 + */ 521 + if (pdev) { 522 + dev_warn(parent, 523 + "more than one 'mmc-slot' compatible child found - using the first one and ignoring all subsequent ones\n"); 524 + break; 525 + } 526 + 527 + pdev = of_platform_device_create(slot_node, NULL, parent); 528 + if (!pdev) 529 + dev_err(parent, 530 + "Failed to create platform device for mmc-slot node '%pOF'\n", 531 + slot_node); 508 532 } 509 - 510 - pdev = of_platform_device_create(slot_node, NULL, parent); 511 - of_node_put(slot_node); 512 533 513 534 return pdev; 514 535 } ··· 526 533 struct device *slot_dev = mmc_dev(mmc); 527 534 int ret; 528 535 529 - if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) { 530 - dev_err(slot_dev, "missing 'reg' property\n"); 531 - return -EINVAL; 532 - } 536 + if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) 537 + return dev_err_probe(slot_dev, -EINVAL, 538 + "missing 'reg' property\n"); 533 539 534 - if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) { 535 - dev_err(slot_dev, "invalid 'reg' property value %d\n", 536 - host->slot_id); 537 - return -EINVAL; 538 - } 540 + if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) 541 + return dev_err_probe(slot_dev, -EINVAL, 542 + "invalid 'reg' property value %d\n", 543 + host->slot_id); 539 544 540 545 /* Get regulators and the supported OCR mask */ 541 546 ret = mmc_regulator_get_supply(mmc); ··· 552 561 553 562 /* Get the min and max supported clock rates */ 554 563 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1); 555 - mmc->f_max = clk_round_rate(host->cfg_div_clk, 556 - clk_get_rate(host->parent_clk)); 564 + mmc->f_max = clk_round_rate(host->cfg_div_clk, ULONG_MAX); 557 565 558 566 mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY; 559 567 mmc->ops = &meson_mx_mmc_ops; ··· 568 578 return 0; 569 579 } 570 580 571 - static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host) 581 + static struct clk *meson_mx_mmc_register_clk(struct device *dev, 582 + void __iomem *base) 572 583 { 573 - struct clk_init_data init; 574 - const char *clk_div_parent, *clk_fixed_factor_parent; 584 + const char *fixed_div2_name, *cfg_div_name; 585 + struct meson_mx_mmc_host_clkc *host_clkc; 586 + struct clk *clk; 587 + int ret; 575 588 576 - clk_fixed_factor_parent = __clk_get_name(host->parent_clk); 577 - init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 578 - "%s#fixed_factor", 579 - dev_name(host->controller_dev)); 580 - if (!init.name) 581 - return -ENOMEM; 589 + /* use a dedicated memory allocation for the clock controller to 590 + * prevent use-after-free as meson_mx_mmc_host is free'd before 591 + * dev (controller dev, not mmc_host->dev) is free'd. 592 + */ 593 + host_clkc = devm_kzalloc(dev, sizeof(*host_clkc), GFP_KERNEL); 594 + if (!host_clkc) 595 + return ERR_PTR(-ENOMEM); 582 596 583 - init.ops = &clk_fixed_factor_ops; 584 - init.flags = 0; 585 - init.parent_names = &clk_fixed_factor_parent; 586 - init.num_parents = 1; 587 - host->fixed_factor.div = 2; 588 - host->fixed_factor.mult = 1; 589 - host->fixed_factor.hw.init = &init; 597 + fixed_div2_name = devm_kasprintf(dev, GFP_KERNEL, "%s#fixed_div2", 598 + dev_name(dev)); 599 + if (!fixed_div2_name) 600 + return ERR_PTR(-ENOMEM); 590 601 591 - host->fixed_factor_clk = devm_clk_register(host->controller_dev, 592 - &host->fixed_factor.hw); 593 - if (WARN_ON(IS_ERR(host->fixed_factor_clk))) 594 - return PTR_ERR(host->fixed_factor_clk); 602 + host_clkc->fixed_div2.div = 2; 603 + host_clkc->fixed_div2.mult = 1; 604 + host_clkc->fixed_div2.hw.init = CLK_HW_INIT_FW_NAME(fixed_div2_name, 605 + "clkin", 606 + &clk_fixed_factor_ops, 607 + 0); 608 + ret = devm_clk_hw_register(dev, &host_clkc->fixed_div2.hw); 609 + if (ret) 610 + return dev_err_ptr_probe(dev, ret, 611 + "Failed to register %s clock\n", 612 + fixed_div2_name); 595 613 596 - clk_div_parent = __clk_get_name(host->fixed_factor_clk); 597 - init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 598 - "%s#div", dev_name(host->controller_dev)); 599 - if (!init.name) 600 - return -ENOMEM; 614 + cfg_div_name = devm_kasprintf(dev, GFP_KERNEL, "%s#div", dev_name(dev)); 615 + if (!cfg_div_name) 616 + return ERR_PTR(-ENOMEM); 601 617 602 - init.ops = &clk_divider_ops; 603 - init.flags = CLK_SET_RATE_PARENT; 604 - init.parent_names = &clk_div_parent; 605 - init.num_parents = 1; 606 - host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; 607 - host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; 608 - host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; 609 - host->cfg_div.hw.init = &init; 610 - host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO; 618 + host_clkc->cfg_div.reg = base + MESON_MX_SDIO_CONF; 619 + host_clkc->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; 620 + host_clkc->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; 621 + host_clkc->cfg_div.hw.init = CLK_HW_INIT_HW(cfg_div_name, 622 + &host_clkc->fixed_div2.hw, 623 + &clk_divider_ops, 624 + CLK_DIVIDER_ALLOW_ZERO); 625 + ret = devm_clk_hw_register(dev, &host_clkc->cfg_div.hw); 626 + if (ret) 627 + return dev_err_ptr_probe(dev, ret, 628 + "Failed to register %s clock\n", 629 + cfg_div_name); 611 630 612 - host->cfg_div_clk = devm_clk_register(host->controller_dev, 613 - &host->cfg_div.hw); 614 - if (WARN_ON(IS_ERR(host->cfg_div_clk))) 615 - return PTR_ERR(host->cfg_div_clk); 631 + clk = devm_clk_hw_get_clk(dev, &host_clkc->cfg_div.hw, "cfg_div_clk"); 632 + if (IS_ERR(clk)) 633 + return dev_err_ptr_probe(dev, PTR_ERR(clk), 634 + "Failed to get the cfg_div clock\n"); 616 635 617 - return 0; 636 + return clk; 618 637 } 619 638 620 639 static int meson_mx_mmc_probe(struct platform_device *pdev) 621 640 { 641 + const struct regmap_config meson_mx_sdio_regmap_config = { 642 + .reg_bits = 8, 643 + .val_bits = 32, 644 + .reg_stride = 4, 645 + .max_register = MESON_MX_SDIO_EXT, 646 + }; 622 647 struct platform_device *slot_pdev; 623 648 struct mmc_host *mmc; 624 649 struct meson_mx_mmc_host *host; 650 + struct clk *core_clk; 651 + void __iomem *base; 625 652 int ret, irq; 626 653 u32 conf; 654 + 655 + base = devm_platform_ioremap_resource(pdev, 0); 656 + if (IS_ERR(base)) 657 + return PTR_ERR(base); 627 658 628 659 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev); 629 660 if (!slot_pdev) 630 661 return -ENODEV; 631 - else if (IS_ERR(slot_pdev)) 632 - return PTR_ERR(slot_pdev); 633 662 634 - mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev); 663 + mmc = devm_mmc_alloc_host(&slot_pdev->dev, sizeof(*host)); 635 664 if (!mmc) { 636 665 ret = -ENOMEM; 637 666 goto error_unregister_slot_pdev; ··· 665 656 666 657 platform_set_drvdata(pdev, host); 667 658 668 - host->base = devm_platform_ioremap_resource(pdev, 0); 669 - if (IS_ERR(host->base)) { 670 - ret = PTR_ERR(host->base); 671 - goto error_free_mmc; 659 + host->regmap = devm_regmap_init_mmio(&pdev->dev, base, 660 + &meson_mx_sdio_regmap_config); 661 + if (IS_ERR(host->regmap)) { 662 + ret = dev_err_probe(host->controller_dev, PTR_ERR(host->regmap), 663 + "Failed to initialize regmap\n"); 664 + goto error_unregister_slot_pdev; 672 665 } 673 666 674 667 irq = platform_get_irq(pdev, 0); 675 668 if (irq < 0) { 676 669 ret = irq; 677 - goto error_free_mmc; 670 + goto error_unregister_slot_pdev; 678 671 } 679 672 680 673 ret = devm_request_threaded_irq(host->controller_dev, irq, 681 674 meson_mx_mmc_irq, 682 675 meson_mx_mmc_irq_thread, IRQF_ONESHOT, 683 676 NULL, host); 684 - if (ret) 685 - goto error_free_mmc; 686 - 687 - host->core_clk = devm_clk_get(host->controller_dev, "core"); 688 - if (IS_ERR(host->core_clk)) { 689 - ret = PTR_ERR(host->core_clk); 690 - goto error_free_mmc; 691 - } 692 - 693 - host->parent_clk = devm_clk_get(host->controller_dev, "clkin"); 694 - if (IS_ERR(host->parent_clk)) { 695 - ret = PTR_ERR(host->parent_clk); 696 - goto error_free_mmc; 697 - } 698 - 699 - ret = meson_mx_mmc_register_clks(host); 700 - if (ret) 701 - goto error_free_mmc; 702 - 703 - ret = clk_prepare_enable(host->core_clk); 704 677 if (ret) { 705 - dev_err(host->controller_dev, "Failed to enable core clock\n"); 706 - goto error_free_mmc; 678 + dev_err_probe(host->controller_dev, ret, 679 + "Failed to request IRQ\n"); 680 + goto error_unregister_slot_pdev; 681 + } 682 + 683 + core_clk = devm_clk_get_enabled(host->controller_dev, "core"); 684 + if (IS_ERR(core_clk)) { 685 + ret = dev_err_probe(host->controller_dev, PTR_ERR(core_clk), 686 + "Failed to get and enable 'core' clock\n"); 687 + goto error_unregister_slot_pdev; 688 + } 689 + 690 + host->cfg_div_clk = meson_mx_mmc_register_clk(&pdev->dev, base); 691 + if (IS_ERR(host->cfg_div_clk)) { 692 + ret = PTR_ERR(host->cfg_div_clk); 693 + goto error_unregister_slot_pdev; 707 694 } 708 695 709 696 ret = clk_prepare_enable(host->cfg_div_clk); 710 697 if (ret) { 711 - dev_err(host->controller_dev, "Failed to enable MMC clock\n"); 712 - goto error_disable_core_clk; 698 + dev_err_probe(host->controller_dev, ret, 699 + "Failed to enable MMC (cfg div) clock\n"); 700 + goto error_unregister_slot_pdev; 713 701 } 714 702 715 703 conf = 0; ··· 714 708 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3); 715 709 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2); 716 710 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2); 717 - writel(conf, host->base + MESON_MX_SDIO_CONF); 711 + regmap_write(host->regmap, MESON_MX_SDIO_CONF, conf); 718 712 719 713 meson_mx_mmc_soft_reset(host); 720 714 721 715 ret = meson_mx_mmc_add_host(host); 722 716 if (ret) 723 - goto error_disable_clks; 717 + goto error_disable_div_clk; 724 718 725 719 return 0; 726 720 727 - error_disable_clks: 721 + error_disable_div_clk: 728 722 clk_disable_unprepare(host->cfg_div_clk); 729 - error_disable_core_clk: 730 - clk_disable_unprepare(host->core_clk); 731 - error_free_mmc: 732 - mmc_free_host(mmc); 733 723 error_unregister_slot_pdev: 734 724 of_platform_device_destroy(&slot_pdev->dev, NULL); 735 725 return ret; ··· 743 741 of_platform_device_destroy(slot_dev, NULL); 744 742 745 743 clk_disable_unprepare(host->cfg_div_clk); 746 - clk_disable_unprepare(host->core_clk); 747 - 748 - mmc_free_host(host->mmc); 749 744 } 750 745 751 746 static const struct of_device_id meson_mx_mmc_of_match[] = {

+2 -2

drivers/mmc/host/mtk-sd.c

··· 1214 1214 host->data = data; 1215 1215 read = data->flags & MMC_DATA_READ; 1216 1216 1217 - mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1217 + mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT); 1218 1218 msdc_dma_setup(host, &host->dma, data); 1219 1219 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1220 1220 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); ··· 1444 1444 WARN_ON(host->cmd); 1445 1445 host->cmd = cmd; 1446 1446 1447 - mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1447 + mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT); 1448 1448 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1449 1449 return; 1450 1450

+3 -3

drivers/mmc/host/omap.c

··· 326 326 "closed"); 327 327 } 328 328 329 - static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 329 + static DEVICE_ATTR(cover_switch, 0444, mmc_omap_show_cover_switch, NULL); 330 330 331 331 static ssize_t 332 332 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, ··· 338 338 return sprintf(buf, "%s\n", slot->pdata->name); 339 339 } 340 340 341 - static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 341 + static DEVICE_ATTR(slot_name, 0444, mmc_omap_show_slot_name, NULL); 342 342 343 343 static void 344 344 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) ··· 1477 1477 host->nr_slots = pdata->nr_slots; 1478 1478 host->reg_shift = (mmc_omap7xx() ? 1 : 2); 1479 1479 1480 - host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); 1480 + host->mmc_omap_wq = alloc_workqueue("mmc_omap", WQ_PERCPU, 0); 1481 1481 if (!host->mmc_omap_wq) { 1482 1482 ret = -ENOMEM; 1483 1483 goto err_plat_cleanup;

+2 -2

drivers/mmc/host/omap_hsmmc.c

··· 746 746 return sprintf(buf, "%s\n", mmc_pdata(host)->name); 747 747 } 748 748 749 - static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 749 + static DEVICE_ATTR(slot_name, 0444, omap_hsmmc_show_slot_name, NULL); 750 750 751 751 /* 752 752 * Configure the response type and send the cmd. ··· 1672 1672 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1673 1673 { 1674 1674 if (mmc->debugfs_root) 1675 - debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1675 + debugfs_create_file("regs", 0400, mmc->debugfs_root, 1676 1676 mmc, &mmc_regs_fops); 1677 1677 } 1678 1678

+3

drivers/mmc/host/renesas_sdhi.h

··· 9 9 #ifndef RENESAS_SDHI_H 10 10 #define RENESAS_SDHI_H 11 11 12 + #include <linux/device.h> 12 13 #include <linux/dmaengine.h> 13 14 #include <linux/platform_device.h> 14 15 #include <linux/workqueue.h> ··· 108 107 const struct renesas_sdhi_of_data *of_data, 109 108 const struct renesas_sdhi_quirks *quirks); 110 109 void renesas_sdhi_remove(struct platform_device *pdev); 110 + int renesas_sdhi_suspend(struct device *dev); 111 + int renesas_sdhi_resume(struct device *dev); 111 112 #endif

+38 -1

drivers/mmc/host/renesas_sdhi_core.c

··· 31 31 #include <linux/platform_data/tmio.h> 32 32 #include <linux/platform_device.h> 33 33 #include <linux/pm_domain.h> 34 + #include <linux/pm_runtime.h> 34 35 #include <linux/regulator/consumer.h> 35 36 #include <linux/regulator/driver.h> 36 37 #include <linux/regulator/of_regulator.h> ··· 1104 1103 if (IS_ERR(priv->clk_cd)) 1105 1104 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 1106 1105 1107 - priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1106 + priv->rstc = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); 1108 1107 if (IS_ERR(priv->rstc)) 1109 1108 return PTR_ERR(priv->rstc); 1110 1109 ··· 1317 1316 renesas_sdhi_clk_disable(host); 1318 1317 } 1319 1318 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1319 + 1320 + int renesas_sdhi_suspend(struct device *dev) 1321 + { 1322 + struct tmio_mmc_host *host = dev_get_drvdata(dev); 1323 + struct renesas_sdhi *priv = host_to_priv(host); 1324 + int ret; 1325 + 1326 + ret = pm_runtime_force_suspend(dev); 1327 + if (ret) 1328 + return ret; 1329 + 1330 + ret = reset_control_assert(priv->rstc); 1331 + if (ret) 1332 + pm_runtime_force_resume(dev); 1333 + 1334 + return ret; 1335 + } 1336 + EXPORT_SYMBOL_GPL(renesas_sdhi_suspend); 1337 + 1338 + int renesas_sdhi_resume(struct device *dev) 1339 + { 1340 + struct tmio_mmc_host *host = dev_get_drvdata(dev); 1341 + struct renesas_sdhi *priv = host_to_priv(host); 1342 + int ret; 1343 + 1344 + ret = reset_control_deassert(priv->rstc); 1345 + if (ret) 1346 + return ret; 1347 + 1348 + ret = pm_runtime_force_resume(dev); 1349 + if (ret) 1350 + reset_control_assert(priv->rstc); 1351 + 1352 + return ret; 1353 + } 1354 + EXPORT_SYMBOL_GPL(renesas_sdhi_resume); 1320 1355 1321 1356 MODULE_DESCRIPTION("Renesas SDHI core driver"); 1322 1357 MODULE_LICENSE("GPL v2");

+7 -8

drivers/mmc/host/renesas_sdhi_internal_dmac.c

··· 18 18 #include <linux/pagemap.h> 19 19 #include <linux/platform_data/tmio.h> 20 20 #include <linux/platform_device.h> 21 - #include <linux/pm_runtime.h> 22 21 #include <linux/scatterlist.h> 23 22 #include <linux/sys_soc.h> 24 23 ··· 123 124 124 125 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 125 126 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 126 - TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 127 + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 128 + TMIO_MMC_64BIT_DATA_PORT, 127 129 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 128 130 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 129 131 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, ··· 599 599 } 600 600 601 601 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 602 - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 603 - pm_runtime_force_resume) 604 - SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 605 - tmio_mmc_host_runtime_resume, 606 - NULL) 602 + SYSTEM_SLEEP_PM_OPS(renesas_sdhi_suspend, renesas_sdhi_resume) 603 + RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 604 + tmio_mmc_host_runtime_resume, 605 + NULL) 607 606 }; 608 607 609 608 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 610 609 .driver = { 611 610 .name = "renesas_sdhi_internal_dmac", 612 611 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 613 - .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 612 + .pm = pm_ptr(&renesas_sdhi_internal_dmac_dev_pm_ops), 614 613 .of_match_table = renesas_sdhi_internal_dmac_of_match, 615 614 }, 616 615 .probe = renesas_sdhi_internal_dmac_probe,

+2 -1

drivers/mmc/host/renesas_sdhi_sys_dmac.c

··· 60 60 61 61 static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = { 62 62 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 63 - TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 63 + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 64 + TMIO_MMC_32BIT_DATA_PORT, 64 65 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 65 66 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 66 67 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,

+146 -10

drivers/mmc/host/sdhci-brcmstb.c

··· 31 31 32 32 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 33 33 34 - #define SDIO_CFG_CQ_CAPABILITY 0x4c 35 - #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) 36 - 37 34 #define SDIO_CFG_CTRL 0x0 38 35 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) 39 36 #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) 40 - 37 + #define SDIO_CFG_OP_DLY 0x34 38 + #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 39 + #define SDIO_CFG_CQ_CAPABILITY 0x4c 40 + #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) 41 + #define SDIO_CFG_SD_PIN_SEL 0x44 42 + #define SDIO_CFG_V1_SD_PIN_SEL 0x54 43 + #define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C 41 44 #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac 42 45 #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) 43 46 #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) 47 + 48 + #define SDIO_BOOT_MAIN_CTL 0x0 44 49 45 50 #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) 46 51 /* Select all SD UHS type I SDR speed above 50MB/s */ 47 52 #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) 48 53 49 - struct sdhci_brcmstb_priv { 50 - void __iomem *cfg_regs; 51 - unsigned int flags; 52 - struct clk *base_clk; 53 - u32 base_freq_hz; 54 + enum cfg_core_ver { 55 + SDIO_CFG_CORE_V1 = 1, 56 + SDIO_CFG_CORE_V2, 57 + }; 58 + 59 + struct sdhci_brcmstb_saved_regs { 60 + u32 sd_pin_sel; 61 + u32 phy_sw_mode0_rxctrl; 62 + u32 max_50mhz_mode; 63 + u32 boot_main_ctl; 54 64 }; 55 65 56 66 struct brcmstb_match_priv { 57 67 void (*cfginit)(struct sdhci_host *host); 58 68 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 69 + void (*save_restore_regs)(struct mmc_host *mmc, int save); 59 70 struct sdhci_ops *ops; 60 71 const unsigned int flags; 61 72 }; 73 + 74 + struct sdhci_brcmstb_priv { 75 + void __iomem *cfg_regs; 76 + void __iomem *boot_regs; 77 + struct sdhci_brcmstb_saved_regs saved_regs; 78 + unsigned int flags; 79 + struct clk *base_clk; 80 + u32 base_freq_hz; 81 + const struct brcmstb_match_priv *match_priv; 82 + }; 83 + 84 + static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver) 85 + { 86 + struct sdhci_host *host = mmc_priv(mmc); 87 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 88 + struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 89 + struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs; 90 + void __iomem *cr = priv->cfg_regs; 91 + bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE; 92 + 93 + if (is_emmc && priv->boot_regs) 94 + sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); 95 + 96 + if (ver == SDIO_CFG_CORE_V1) { 97 + sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL); 98 + return; 99 + } 100 + 101 + sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL); 102 + sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); 103 + sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE); 104 + } 105 + 106 + static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver) 107 + { 108 + struct sdhci_host *host = mmc_priv(mmc); 109 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 110 + struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 111 + struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs; 112 + void __iomem *cr = priv->cfg_regs; 113 + bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE; 114 + 115 + if (is_emmc && priv->boot_regs) 116 + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); 117 + 118 + if (ver == SDIO_CFG_CORE_V1) { 119 + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); 120 + return; 121 + } 122 + 123 + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); 124 + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); 125 + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); 126 + } 127 + 128 + static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save) 129 + { 130 + if (save) 131 + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); 132 + else 133 + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); 134 + } 135 + 136 + static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save) 137 + { 138 + if (save) 139 + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); 140 + else 141 + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); 142 + } 62 143 63 144 static inline void enable_clock_gating(struct sdhci_host *host) 64 145 { ··· 293 212 } 294 213 } 295 214 215 + static void sdhci_brcmstb_set_72116_uhs_signaling(struct sdhci_host *host, unsigned int timing) 216 + { 217 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 218 + struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 219 + u32 reg; 220 + 221 + /* no change to SDIO_CFG_OP_DLY_DEFAULT when using preset clk rate */ 222 + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 223 + return; 224 + 225 + reg = (timing == MMC_TIMING_MMC_HS200) ? 0 : SDIO_CFG_OP_DLY_DEFAULT; 226 + writel(reg, priv->cfg_regs + SDIO_CFG_OP_DLY); 227 + sdhci_set_uhs_signaling(host, timing); 228 + } 229 + 296 230 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 297 231 { 298 232 sdhci_dumpregs(mmc_priv(mmc)); ··· 348 252 .set_uhs_signaling = sdhci_set_uhs_signaling, 349 253 }; 350 254 255 + static struct sdhci_ops sdhci_brcmstb_ops_72116 = { 256 + .set_clock = sdhci_set_clock, 257 + .set_bus_width = sdhci_set_bus_width, 258 + .reset = sdhci_reset, 259 + .set_uhs_signaling = sdhci_brcmstb_set_72116_uhs_signaling, 260 + }; 261 + 351 262 static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 352 263 .set_clock = sdhci_brcmstb_set_clock, 353 264 .set_bus_width = sdhci_set_bus_width, ··· 380 277 .ops = &sdhci_brcmstb_ops, 381 278 }; 382 279 383 - static struct brcmstb_match_priv match_priv_7445 = { 280 + static struct brcmstb_match_priv match_priv_74371 = { 384 281 .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 385 282 .ops = &sdhci_brcmstb_ops, 386 283 }; 387 284 285 + static struct brcmstb_match_priv match_priv_7445 = { 286 + .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 287 + .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1, 288 + .ops = &sdhci_brcmstb_ops, 289 + }; 290 + 291 + static struct brcmstb_match_priv match_priv_72116 = { 292 + .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 293 + .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1, 294 + .ops = &sdhci_brcmstb_ops_72116, 295 + }; 296 + 388 297 static const struct brcmstb_match_priv match_priv_7216 = { 389 298 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 299 + .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2, 390 300 .hs400es = sdhci_brcmstb_hs400es, 391 301 .ops = &sdhci_brcmstb_ops_7216, 392 302 }; 393 303 394 304 static struct brcmstb_match_priv match_priv_74165b0 = { 395 305 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 306 + .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2, 396 307 .hs400es = sdhci_brcmstb_hs400es, 397 308 .ops = &sdhci_brcmstb_ops_74165b0, 398 309 }; ··· 414 297 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { 415 298 { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, 416 299 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 300 + { .compatible = "brcm,bcm74371-sdhci", .data = &match_priv_74371 }, 417 301 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 302 + { .compatible = "brcm,bcm72116-sdhci", .data = &match_priv_72116 }, 418 303 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 419 304 { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 }, 420 305 {}, ··· 514 395 515 396 pltfm_host = sdhci_priv(host); 516 397 priv = sdhci_pltfm_priv(pltfm_host); 398 + priv->match_priv = match->data; 517 399 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 518 400 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 519 401 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; ··· 531 411 res = mmc_of_parse(host->mmc); 532 412 if (res) 533 413 goto err; 414 + 415 + /* map non-standard BOOT registers if present */ 416 + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { 417 + priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL); 418 + if (IS_ERR(priv->boot_regs)) 419 + priv->boot_regs = NULL; 420 + } 534 421 535 422 /* 536 423 * Automatic clock gating does not work for SD cards that may ··· 628 501 struct sdhci_host *host = dev_get_drvdata(dev); 629 502 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 630 503 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 504 + const struct brcmstb_match_priv *match_priv = priv->match_priv; 505 + 631 506 int ret; 507 + 508 + if (match_priv->save_restore_regs) 509 + match_priv->save_restore_regs(host->mmc, 1); 632 510 633 511 clk_disable_unprepare(priv->base_clk); 634 512 if (host->mmc->caps2 & MMC_CAP2_CQE) { ··· 650 518 struct sdhci_host *host = dev_get_drvdata(dev); 651 519 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 652 520 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 521 + const struct brcmstb_match_priv *match_priv = priv->match_priv; 653 522 int ret; 654 523 655 524 ret = sdhci_pltfm_resume(dev); ··· 666 533 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 667 534 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 668 535 } 536 + 537 + if (match_priv->save_restore_regs) 538 + match_priv->save_restore_regs(host->mmc, 0); 669 539 670 540 if (host->mmc->caps2 & MMC_CAP2_CQE) 671 541 ret = cqhci_resume(host->mmc);

+15 -12

drivers/mmc/host/sdhci-msm.c

··· 344 344 writel_relaxed(val, host->ioaddr + offset); 345 345 } 346 346 347 - static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host) 347 + static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host, 348 + unsigned int clock, 349 + unsigned int timing) 348 350 { 349 - struct mmc_ios ios = host->mmc->ios; 350 351 /* 351 352 * The SDHC requires internal clock frequency to be double the 352 353 * actual clock that will be set for DDR mode. The controller 353 354 * uses the faster clock(100/400MHz) for some of its parts and 354 355 * send the actual required clock (50/200MHz) to the card. 355 356 */ 356 - if (ios.timing == MMC_TIMING_UHS_DDR50 || 357 - ios.timing == MMC_TIMING_MMC_DDR52 || 358 - ios.timing == MMC_TIMING_MMC_HS400 || 357 + if (timing == MMC_TIMING_UHS_DDR50 || 358 + timing == MMC_TIMING_MMC_DDR52 || 359 + (timing == MMC_TIMING_MMC_HS400 && 360 + clock == MMC_HS200_MAX_DTR) || 359 361 host->flags & SDHCI_HS400_TUNING) 360 362 return 2; 361 363 return 1; 362 364 } 363 365 364 366 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, 365 - unsigned int clock) 367 + unsigned int clock, 368 + unsigned int timing) 366 369 { 367 370 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 368 371 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 369 - struct mmc_ios curr_ios = host->mmc->ios; 370 372 struct clk *core_clk = msm_host->bulk_clks[0].clk; 371 373 unsigned long achieved_rate; 372 374 unsigned int desired_rate; 373 375 unsigned int mult; 374 376 int rc; 375 377 376 - mult = msm_get_clock_mult_for_bus_mode(host); 378 + mult = msm_get_clock_mult_for_bus_mode(host, clock, timing); 377 379 desired_rate = clock * mult; 378 380 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); 379 381 if (rc) { 380 382 pr_err("%s: Failed to set clock at rate %u at timing %d\n", 381 - mmc_hostname(host->mmc), desired_rate, curr_ios.timing); 383 + mmc_hostname(host->mmc), desired_rate, timing); 382 384 return; 383 385 } 384 386 ··· 399 397 msm_host->clk_rate = desired_rate; 400 398 401 399 pr_debug("%s: Setting clock at rate %lu at timing %d\n", 402 - mmc_hostname(host->mmc), achieved_rate, curr_ios.timing); 400 + mmc_hostname(host->mmc), achieved_rate, timing); 403 401 } 404 402 405 403 /* Platform specific tuning */ ··· 1241 1239 */ 1242 1240 if (host->flags & SDHCI_HS400_TUNING) { 1243 1241 sdhci_msm_hc_select_mode(host); 1244 - msm_set_clock_rate_for_bus_mode(host, ios.clock); 1242 + msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing); 1245 1243 host->flags &= ~SDHCI_HS400_TUNING; 1246 1244 } 1247 1245 ··· 1866 1864 { 1867 1865 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1868 1866 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 1867 + struct mmc_ios ios = host->mmc->ios; 1869 1868 1870 1869 if (!clock) { 1871 1870 host->mmc->actual_clock = msm_host->clk_rate = 0; ··· 1875 1872 1876 1873 sdhci_msm_hc_select_mode(host); 1877 1874 1878 - msm_set_clock_rate_for_bus_mode(host, clock); 1875 + msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing); 1879 1876 out: 1880 1877 __sdhci_msm_set_clock(host, clock); 1881 1878 }

+1 -1

drivers/mmc/host/sdhci-of-arasan.c

··· 1991 1991 1992 1992 ret = mmc_of_parse(host->mmc); 1993 1993 if (ret) { 1994 - ret = dev_err_probe(dev, ret, "parsing dt failed.\n"); 1994 + dev_err_probe(dev, ret, "parsing dt failed.\n"); 1995 1995 goto unreg_clk; 1996 1996 } 1997 1997

+589 -15

drivers/mmc/host/sdhci-of-dwcmshc.c

··· 11 11 #include <linux/arm-smccc.h> 12 12 #include <linux/bitfield.h> 13 13 #include <linux/clk.h> 14 + #include <linux/clk-provider.h> 14 15 #include <linux/dma-mapping.h> 15 16 #include <linux/iopoll.h> 16 17 #include <linux/kernel.h> ··· 20 19 #include <linux/platform_device.h> 21 20 #include <linux/pm_domain.h> 22 21 #include <linux/pm_runtime.h> 22 + #include <linux/regmap.h> 23 23 #include <linux/reset.h> 24 24 #include <linux/sizes.h> 25 + #include <linux/mfd/syscon.h> 26 + #include <linux/units.h> 25 27 26 28 #include "sdhci-pltfm.h" 27 29 #include "cqhci.h" 30 + #include "sdhci-cqhci.h" 28 31 29 32 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 30 33 ··· 44 39 #define DWCMSHC_CARD_IS_EMMC BIT(0) 45 40 #define DWCMSHC_ENHANCED_STROBE BIT(8) 46 41 #define DWCMSHC_EMMC_ATCTRL 0x40 42 + #define DWCMSHC_AT_STAT 0x44 47 43 /* Tuning and auto-tuning fields in AT_CTRL_R control register */ 48 44 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ 49 45 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ ··· 88 82 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 89 83 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 90 84 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 85 + #define DECMSHC_EMMC_MISC_CON 0x81C 86 + #define MISC_INTCLK_EN BIT(1) 91 87 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 92 88 #define DWCMSHC_EMMC_DLL_START BIT(0) 93 89 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) ··· 202 194 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ 203 195 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 204 196 197 + /* PHY DLL offset setting register */ 198 + #define PHY_DLL_OFFST_R (DWC_MSHC_PTR_PHY_R + 0x29) 199 + /* DLL LBT setting register */ 200 + #define PHY_DLLBT_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x2c) 201 + /* DLL Status register */ 202 + #define PHY_DLL_STATUS_R (DWC_MSHC_PTR_PHY_R + 0x2e) 203 + #define DLL_LOCK_STS BIT(0)/* DLL is locked and ready */ 204 + /* 205 + * Captures the value of DLL's lock error status information. Value is valid 206 + * only when LOCK_STS is set. 207 + */ 208 + #define DLL_ERROR_STS BIT(1) 209 + 205 210 #define FLAG_IO_FIXED_1V8 BIT(0) 206 211 207 212 #define BOUNDARY_OK(addr, len) \ ··· 227 206 /* SMC call for BlueField-3 eMMC RST_N */ 228 207 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 229 208 209 + /* Eswin specific Registers */ 210 + #define EIC7700_CARD_CLK_STABLE BIT(28) 211 + #define EIC7700_INT_BCLK_STABLE BIT(16) 212 + #define EIC7700_INT_ACLK_STABLE BIT(8) 213 + #define EIC7700_INT_TMCLK_STABLE BIT(0) 214 + #define EIC7700_INT_CLK_STABLE (EIC7700_CARD_CLK_STABLE | \ 215 + EIC7700_INT_ACLK_STABLE | \ 216 + EIC7700_INT_BCLK_STABLE | \ 217 + EIC7700_INT_TMCLK_STABLE) 218 + #define EIC7700_HOST_VAL_STABLE BIT(0) 219 + 220 + /* strength definition */ 221 + #define PHYCTRL_DR_33OHM 0xee 222 + #define PHYCTRL_DR_40OHM 0xcc 223 + #define PHYCTRL_DR_50OHM 0x88 224 + #define PHYCTRL_DR_66OHM 0x44 225 + #define PHYCTRL_DR_100OHM 0x00 226 + 227 + #define MAX_PHASE_CODE 0xff 228 + #define TUNING_RANGE_THRESHOLD 40 229 + #define PHY_CLK_MAX_DELAY_MASK 0x7f 230 + #define PHY_DELAY_CODE_MAX 0x7f 231 + #define PHY_DELAY_CODE_EMMC 0x17 232 + #define PHY_DELAY_CODE_SD 0x55 233 + 230 234 enum dwcmshc_rk_type { 231 235 DWCMSHC_RK3568, 232 236 DWCMSHC_RK3588, ··· 261 215 struct reset_control *reset; 262 216 enum dwcmshc_rk_type devtype; 263 217 u8 txclk_tapnum; 218 + }; 219 + 220 + struct eic7700_priv { 221 + struct reset_control *reset; 222 + unsigned int drive_impedance; 264 223 }; 265 224 266 225 #define DWCMSHC_MAX_OTHER_CLKS 3 ··· 285 234 286 235 struct dwcmshc_pltfm_data { 287 236 const struct sdhci_pltfm_data pdata; 237 + const struct cqhci_host_ops *cqhci_host_ops; 288 238 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 289 239 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 290 240 }; 241 + 242 + static void dwcmshc_enable_card_clk(struct sdhci_host *host) 243 + { 244 + u16 ctrl; 245 + 246 + ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 247 + if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 248 + ctrl |= SDHCI_CLOCK_CARD_EN; 249 + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 250 + } 251 + } 291 252 292 253 static int dwcmshc_get_enable_other_clks(struct device *dev, 293 254 struct dwcmshc_priv *priv, ··· 637 574 sdhci_dumpregs(mmc_priv(mmc)); 638 575 } 639 576 577 + static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc) 578 + { 579 + struct sdhci_host *host = mmc_priv(mmc); 580 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 581 + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 582 + u32 reg; 583 + 584 + /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */ 585 + reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1); 586 + reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100; 587 + sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1); 588 + 589 + reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG); 590 + reg |= CQHCI_ENABLE; 591 + sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG); 592 + } 593 + 594 + static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc) 595 + { 596 + struct sdhci_host *host = mmc_priv(mmc); 597 + u32 reg; 598 + 599 + reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 600 + while (reg & SDHCI_DATA_AVAILABLE) { 601 + sdhci_readl(host, SDHCI_BUFFER); 602 + reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 603 + } 604 + 605 + sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 606 + 607 + sdhci_cqe_enable(mmc); 608 + } 609 + 610 + static void rk35xx_sdhci_cqe_disable(struct mmc_host *mmc, bool recovery) 611 + { 612 + struct sdhci_host *host = mmc_priv(mmc); 613 + unsigned long flags; 614 + u32 ctrl; 615 + 616 + /* 617 + * During CQE command transfers, command complete bit gets latched. 618 + * So s/w should clear command complete interrupt status when CQE is 619 + * either halted or disabled. Otherwise unexpected SDCHI legacy 620 + * interrupt gets triggered when CQE is halted/disabled. 621 + */ 622 + spin_lock_irqsave(&host->lock, flags); 623 + ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); 624 + ctrl |= SDHCI_INT_RESPONSE; 625 + sdhci_writel(host, ctrl, SDHCI_INT_ENABLE); 626 + sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); 627 + spin_unlock_irqrestore(&host->lock, flags); 628 + 629 + sdhci_cqe_disable(mmc, recovery); 630 + } 631 + 632 + static void rk35xx_sdhci_cqe_post_disable(struct mmc_host *mmc) 633 + { 634 + struct sdhci_host *host = mmc_priv(mmc); 635 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 636 + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 637 + u32 ctrl; 638 + 639 + ctrl = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG); 640 + ctrl &= ~CQHCI_ENABLE; 641 + sdhci_writel(host, ctrl, dwc_priv->vendor_specific_area2 + CQHCI_CFG); 642 + } 643 + 640 644 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 641 645 { 642 646 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ··· 731 601 732 602 sdhci_set_clock(host, clock); 733 603 734 - /* Disable cmd conflict check */ 604 + /* Disable cmd conflict check and internal clock gate */ 735 605 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 736 606 extra = sdhci_readl(host, reg); 737 607 extra &= ~BIT(0); 608 + extra |= BIT(4); 738 609 sdhci_writel(host, extra, reg); 739 610 740 611 if (clock <= 52000000) { ··· 823 692 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 824 693 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 825 694 struct rk35xx_priv *priv = dwc_priv->priv; 695 + u32 extra = sdhci_readl(host, DECMSHC_EMMC_MISC_CON); 696 + 697 + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) 698 + cqhci_deactivate(host->mmc); 826 699 827 700 if (mask & SDHCI_RESET_ALL && priv->reset) { 828 701 reset_control_assert(priv->reset); ··· 835 700 } 836 701 837 702 sdhci_reset(host, mask); 703 + 704 + /* Enable INTERNAL CLOCK */ 705 + sdhci_writel(host, MISC_INTCLK_EN | extra, DECMSHC_EMMC_MISC_CON); 838 706 } 839 707 840 708 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, ··· 1238 1100 ARRAY_SIZE(clk_ids), clk_ids); 1239 1101 } 1240 1102 1103 + static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int clock) 1104 + { 1105 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1106 + u16 clk; 1107 + 1108 + host->mmc->actual_clock = clock; 1109 + 1110 + if (clock == 0) { 1111 + sdhci_set_clock(host, clock); 1112 + return; 1113 + } 1114 + 1115 + clk_set_rate(pltfm_host->clk, clock); 1116 + 1117 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1118 + clk |= SDHCI_CLOCK_INT_EN; 1119 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1120 + 1121 + dwcmshc_enable_card_clk(host); 1122 + } 1123 + 1124 + static void sdhci_eic7700_config_phy_delay(struct sdhci_host *host, int delay) 1125 + { 1126 + delay &= PHY_CLK_MAX_DELAY_MASK; 1127 + 1128 + /* phy clk delay line config */ 1129 + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 1130 + sdhci_writeb(host, delay, PHY_SDCLKDL_DC_R); 1131 + sdhci_writeb(host, 0x0, PHY_SDCLKDL_CNFG_R); 1132 + } 1133 + 1134 + static void sdhci_eic7700_config_phy(struct sdhci_host *host) 1135 + { 1136 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1137 + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 1138 + u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1139 + struct eic7700_priv *priv = dwc_priv->priv; 1140 + unsigned int val, drv; 1141 + 1142 + drv = FIELD_PREP(PHY_CNFG_PAD_SP_MASK, priv->drive_impedance & 0xF); 1143 + drv |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, (priv->drive_impedance >> 4) & 0xF); 1144 + 1145 + if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 1146 + val = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 1147 + val |= DWCMSHC_CARD_IS_EMMC; 1148 + sdhci_writew(host, val, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 1149 + } 1150 + 1151 + /* reset phy, config phy's pad */ 1152 + sdhci_writel(host, drv | ~PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); 1153 + 1154 + /* configure phy pads */ 1155 + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1156 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1157 + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 1158 + val |= PHY_PAD_RXSEL_1V8; 1159 + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 1160 + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 1161 + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 1162 + 1163 + /* Clock PAD Setting */ 1164 + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1165 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1166 + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 1167 + 1168 + /* PHY strobe PAD setting (EMMC only) */ 1169 + if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 1170 + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1171 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1172 + val |= PHY_PAD_RXSEL_1V8; 1173 + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 1174 + } 1175 + usleep_range(2000, 3000); 1176 + sdhci_writel(host, drv | PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); 1177 + sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); 1178 + } 1179 + 1180 + static void sdhci_eic7700_reset(struct sdhci_host *host, u8 mask) 1181 + { 1182 + sdhci_reset(host, mask); 1183 + 1184 + /* after reset all, the phy's config will be clear */ 1185 + if (mask == SDHCI_RESET_ALL) 1186 + sdhci_eic7700_config_phy(host); 1187 + } 1188 + 1189 + static int sdhci_eic7700_reset_init(struct device *dev, struct eic7700_priv *priv) 1190 + { 1191 + int ret; 1192 + 1193 + priv->reset = devm_reset_control_array_get_optional_exclusive(dev); 1194 + if (IS_ERR(priv->reset)) { 1195 + ret = PTR_ERR(priv->reset); 1196 + dev_err(dev, "failed to get reset control %d\n", ret); 1197 + return ret; 1198 + } 1199 + 1200 + ret = reset_control_assert(priv->reset); 1201 + if (ret) { 1202 + dev_err(dev, "Failed to assert reset signals: %d\n", ret); 1203 + return ret; 1204 + } 1205 + usleep_range(2000, 2100); 1206 + ret = reset_control_deassert(priv->reset); 1207 + if (ret) { 1208 + dev_err(dev, "Failed to deassert reset signals: %d\n", ret); 1209 + return ret; 1210 + } 1211 + 1212 + return ret; 1213 + } 1214 + 1215 + static unsigned int eic7700_convert_drive_impedance_ohm(struct device *dev, unsigned int dr_ohm) 1216 + { 1217 + switch (dr_ohm) { 1218 + case 100: 1219 + return PHYCTRL_DR_100OHM; 1220 + case 66: 1221 + return PHYCTRL_DR_66OHM; 1222 + case 50: 1223 + return PHYCTRL_DR_50OHM; 1224 + case 40: 1225 + return PHYCTRL_DR_40OHM; 1226 + case 33: 1227 + return PHYCTRL_DR_33OHM; 1228 + } 1229 + 1230 + dev_warn(dev, "Invalid value %u for drive-impedance-ohms.\n", dr_ohm); 1231 + return PHYCTRL_DR_50OHM; 1232 + } 1233 + 1234 + static int sdhci_eic7700_delay_tuning(struct sdhci_host *host, u32 opcode) 1235 + { 1236 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1237 + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 1238 + int delay_min = -1; 1239 + int delay_max = -1; 1240 + int cmd_error = 0; 1241 + int delay = 0; 1242 + int i = 0; 1243 + int ret; 1244 + 1245 + for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) { 1246 + sdhci_eic7700_config_phy_delay(host, i); 1247 + ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); 1248 + if (ret) { 1249 + host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1250 + usleep_range(200, 210); 1251 + if (delay_min != -1 && delay_max != -1) 1252 + break; 1253 + } else { 1254 + if (delay_min == -1) { 1255 + delay_min = i; 1256 + continue; 1257 + } else { 1258 + delay_max = i; 1259 + continue; 1260 + } 1261 + } 1262 + } 1263 + if (delay_min == -1 && delay_max == -1) { 1264 + pr_err("%s: delay code tuning failed!\n", mmc_hostname(host->mmc)); 1265 + sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); 1266 + return ret; 1267 + } 1268 + 1269 + delay = (delay_min + delay_max) / 2; 1270 + sdhci_eic7700_config_phy_delay(host, delay); 1271 + 1272 + return 0; 1273 + } 1274 + 1275 + static int sdhci_eic7700_phase_code_tuning(struct sdhci_host *host, u32 opcode) 1276 + { 1277 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1278 + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1279 + u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; 1280 + int phase_code = -1; 1281 + int code_range = -1; 1282 + bool is_sd = false; 1283 + int code_min = -1; 1284 + int code_max = -1; 1285 + int cmd_error = 0; 1286 + int ret = 0; 1287 + int i = 0; 1288 + 1289 + if ((host->mmc->caps2 & sd_caps) == sd_caps) 1290 + is_sd = true; 1291 + 1292 + for (i = 0; i <= MAX_PHASE_CODE; i++) { 1293 + /* Centered Phase code */ 1294 + sdhci_writew(host, i, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); 1295 + ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); 1296 + host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1297 + 1298 + if (ret) { 1299 + /* SD specific range tracking */ 1300 + if (is_sd && code_min != -1 && code_max != -1) { 1301 + if (code_max - code_min > code_range) { 1302 + code_range = code_max - code_min; 1303 + phase_code = (code_min + code_max) / 2; 1304 + if (code_range > TUNING_RANGE_THRESHOLD) 1305 + break; 1306 + } 1307 + code_min = -1; 1308 + code_max = -1; 1309 + } 1310 + /* EMMC breaks after first valid range */ 1311 + if (!is_sd && code_min != -1 && code_max != -1) 1312 + break; 1313 + } else { 1314 + /* Track valid phase code range */ 1315 + if (code_min == -1) { 1316 + code_min = i; 1317 + if (!is_sd) 1318 + continue; 1319 + } 1320 + code_max = i; 1321 + if (is_sd && i == MAX_PHASE_CODE) { 1322 + if (code_max - code_min > code_range) { 1323 + code_range = code_max - code_min; 1324 + phase_code = (code_min + code_max) / 2; 1325 + } 1326 + } 1327 + } 1328 + } 1329 + 1330 + /* Handle tuning failure case */ 1331 + if ((is_sd && phase_code == -1) || 1332 + (!is_sd && code_min == -1 && code_max == -1)) { 1333 + pr_err("%s: phase code tuning failed!\n", mmc_hostname(host->mmc)); 1334 + sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); 1335 + return -EIO; 1336 + } 1337 + if (!is_sd) 1338 + phase_code = (code_min + code_max) / 2; 1339 + 1340 + sdhci_writew(host, phase_code, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); 1341 + 1342 + /* SD specific final verification */ 1343 + if (is_sd) { 1344 + ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); 1345 + host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1346 + if (ret) { 1347 + pr_err("%s: Final phase code 0x%x verification failed!\n", 1348 + mmc_hostname(host->mmc), phase_code); 1349 + return ret; 1350 + } 1351 + } 1352 + 1353 + return 0; 1354 + } 1355 + 1356 + static int sdhci_eic7700_executing_tuning(struct sdhci_host *host, u32 opcode) 1357 + { 1358 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1359 + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1360 + u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1361 + int ret = 0; 1362 + u16 ctrl; 1363 + u32 val; 1364 + 1365 + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1366 + ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1367 + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1368 + 1369 + val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 1370 + val |= AT_CTRL_SW_TUNE_EN; 1371 + sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 1372 + 1373 + sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); 1374 + sdhci_writew(host, 0x0, SDHCI_CMD_DATA); 1375 + 1376 + if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 1377 + ret = sdhci_eic7700_delay_tuning(host, opcode); 1378 + if (ret) 1379 + return ret; 1380 + } 1381 + 1382 + ret = sdhci_eic7700_phase_code_tuning(host, opcode); 1383 + if (ret) 1384 + return ret; 1385 + 1386 + return 0; 1387 + } 1388 + 1389 + static void sdhci_eic7700_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) 1390 + { 1391 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1392 + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1393 + u8 status; 1394 + u32 val; 1395 + int ret; 1396 + 1397 + dwcmshc_set_uhs_signaling(host, timing); 1398 + 1399 + /* here need make dll locked when in hs400 at 200MHz */ 1400 + if (timing == MMC_TIMING_MMC_HS400 && host->clock == 200000000) { 1401 + val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 1402 + val &= ~(FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY)); 1403 + /* 2-cycle latency */ 1404 + val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, 0x2); 1405 + sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 1406 + 1407 + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | 1408 + 0x3, PHY_DLL_CNFG1_R);/* DLL wait cycle input */ 1409 + /* DLL jump step input */ 1410 + sdhci_writeb(host, 0x02, PHY_DLL_CNFG2_R); 1411 + sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, 1412 + PHY_DLLDL_CNFG_SLV_INPSEL), PHY_DLLDL_CNFG_R); 1413 + /* Sets the value of DLL's offset input */ 1414 + sdhci_writeb(host, 0x00, PHY_DLL_OFFST_R); 1415 + /* 1416 + * Sets the value of DLL's olbt loadval input. Controls the Ibt 1417 + * timer's timeout value at which DLL runs a revalidation cycle. 1418 + */ 1419 + sdhci_writew(host, 0xffff, PHY_DLLBT_CNFG_R); 1420 + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 1421 + usleep_range(100, 110); 1422 + 1423 + ret = read_poll_timeout(sdhci_readb, status, status & DLL_LOCK_STS, 100, 1000000, 1424 + false, host, PHY_DLL_STATUS_R); 1425 + if (ret) { 1426 + pr_err("%s: DLL lock timeout! status: 0x%x\n", 1427 + mmc_hostname(host->mmc), status); 1428 + return; 1429 + } 1430 + 1431 + status = sdhci_readb(host, PHY_DLL_STATUS_R); 1432 + if (status & DLL_ERROR_STS) { 1433 + pr_err("%s: DLL lock failed!err_status:0x%x\n", 1434 + mmc_hostname(host->mmc), status); 1435 + } 1436 + } 1437 + } 1438 + 1439 + static void sdhci_eic7700_set_uhs_wrapper(struct sdhci_host *host, unsigned int timing) 1440 + { 1441 + u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; 1442 + 1443 + if ((host->mmc->caps2 & sd_caps) == sd_caps) 1444 + sdhci_set_uhs_signaling(host, timing); 1445 + else 1446 + sdhci_eic7700_set_uhs_signaling(host, timing); 1447 + } 1448 + 1449 + static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 1450 + { 1451 + u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1452 + unsigned int val, hsp_int_status, hsp_pwr_ctrl; 1453 + struct of_phandle_args args; 1454 + struct eic7700_priv *priv; 1455 + struct regmap *hsp_regmap; 1456 + int ret; 1457 + 1458 + priv = devm_kzalloc(dev, sizeof(struct eic7700_priv), GFP_KERNEL); 1459 + if (!priv) 1460 + return -ENOMEM; 1461 + 1462 + dwc_priv->priv = priv; 1463 + 1464 + ret = sdhci_eic7700_reset_init(dev, dwc_priv->priv); 1465 + if (ret) { 1466 + dev_err(dev, "failed to reset\n"); 1467 + return ret; 1468 + } 1469 + 1470 + ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args); 1471 + if (ret) { 1472 + dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret); 1473 + return ret; 1474 + } 1475 + 1476 + hsp_regmap = syscon_node_to_regmap(args.np); 1477 + if (IS_ERR(hsp_regmap)) { 1478 + dev_err(dev, "Failed to get regmap for 'eswin,hsp-sp-csr'\n"); 1479 + of_node_put(args.np); 1480 + return PTR_ERR(hsp_regmap); 1481 + } 1482 + hsp_int_status = args.args[0]; 1483 + hsp_pwr_ctrl = args.args[1]; 1484 + of_node_put(args.np); 1485 + /* 1486 + * Assert clock stability: write EIC7700_INT_CLK_STABLE to hsp_int_status. 1487 + * This signals to the eMMC controller that platform clocks (card, ACLK, 1488 + * BCLK, TMCLK) are enabled and stable. 1489 + */ 1490 + regmap_write(hsp_regmap, hsp_int_status, EIC7700_INT_CLK_STABLE); 1491 + /* 1492 + * Assert voltage stability: write EIC7700_HOST_VAL_STABLE to hsp_pwr_ctrl. 1493 + * This signals that VDD is stable and permits transition to high-speed 1494 + * modes (e.g., UHS-I). 1495 + */ 1496 + regmap_write(hsp_regmap, hsp_pwr_ctrl, EIC7700_HOST_VAL_STABLE); 1497 + 1498 + if ((host->mmc->caps2 & emmc_caps) == emmc_caps) 1499 + dwc_priv->delay_line = PHY_DELAY_CODE_EMMC; 1500 + else 1501 + dwc_priv->delay_line = PHY_DELAY_CODE_SD; 1502 + 1503 + if (!of_property_read_u32(dev->of_node, "eswin,drive-impedance-ohms", &val)) 1504 + priv->drive_impedance = eic7700_convert_drive_impedance_ohm(dev, val); 1505 + return 0; 1506 + } 1507 + 1241 1508 static const struct sdhci_ops sdhci_dwcmshc_ops = { 1242 1509 .set_clock = sdhci_set_clock, 1243 1510 .set_bus_width = sdhci_set_bus_width, ··· 1717 1174 .platform_execute_tuning = th1520_execute_tuning, 1718 1175 }; 1719 1176 1177 + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { 1178 + .set_clock = sdhci_eic7700_set_clock, 1179 + .get_max_clock = sdhci_pltfm_clk_get_max_clock, 1180 + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 1181 + .set_bus_width = sdhci_set_bus_width, 1182 + .reset = sdhci_eic7700_reset, 1183 + .set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper, 1184 + .set_power = sdhci_set_power_and_bus_voltage, 1185 + .irq = dwcmshc_cqe_irq_handler, 1186 + .platform_execute_tuning = sdhci_eic7700_executing_tuning, 1187 + }; 1188 + 1720 1189 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { 1721 1190 .pdata = { 1722 1191 .ops = &sdhci_dwcmshc_ops, ··· 1748 1193 }; 1749 1194 #endif 1750 1195 1196 + static const struct cqhci_host_ops rk35xx_cqhci_ops = { 1197 + .pre_enable = rk35xx_sdhci_cqe_pre_enable, 1198 + .enable = rk35xx_sdhci_cqe_enable, 1199 + .disable = rk35xx_sdhci_cqe_disable, 1200 + .post_disable = rk35xx_sdhci_cqe_post_disable, 1201 + .dumpregs = dwcmshc_cqhci_dumpregs, 1202 + .set_tran_desc = dwcmshc_set_tran_desc, 1203 + }; 1204 + 1751 1205 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 1752 1206 .pdata = { 1753 1207 .ops = &sdhci_dwcmshc_rk35xx_ops, ··· 1765 1201 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1766 1202 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1767 1203 }, 1204 + .cqhci_host_ops = &rk35xx_cqhci_ops, 1768 1205 .init = dwcmshc_rk35xx_init, 1769 1206 .postinit = dwcmshc_rk35xx_postinit, 1770 1207 }; ··· 1778 1213 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1779 1214 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1780 1215 }, 1216 + .cqhci_host_ops = &rk35xx_cqhci_ops, 1781 1217 .init = dwcmshc_rk35xx_init, 1782 1218 .postinit = dwcmshc_rk3576_postinit, 1783 1219 }; ··· 1809 1243 .init = sg2042_init, 1810 1244 }; 1811 1245 1246 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { 1247 + .pdata = { 1248 + .ops = &sdhci_dwcmshc_eic7700_ops, 1249 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1250 + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1251 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1252 + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1253 + }, 1254 + .init = eic7700_init, 1255 + }; 1256 + 1812 1257 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 1813 1258 .enable = dwcmshc_sdhci_cqe_enable, 1814 1259 .disable = sdhci_cqe_disable, ··· 1827 1250 .set_tran_desc = dwcmshc_set_tran_desc, 1828 1251 }; 1829 1252 1830 - static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 1253 + static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev, 1254 + const struct dwcmshc_pltfm_data *pltfm_data) 1831 1255 { 1832 1256 struct cqhci_host *cq_host; 1833 1257 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ··· 1858 1280 } 1859 1281 1860 1282 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 1861 - cq_host->ops = &dwcmshc_cqhci_ops; 1283 + if (pltfm_data->cqhci_host_ops) 1284 + cq_host->ops = pltfm_data->cqhci_host_ops; 1285 + else 1286 + cq_host->ops = &dwcmshc_cqhci_ops; 1862 1287 1863 1288 /* Enable using of 128-bit task descriptors */ 1864 1289 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; ··· 1923 1342 { 1924 1343 .compatible = "sophgo,sg2042-dwcmshc", 1925 1344 .data = &sdhci_dwcmshc_sg2042_pdata, 1345 + }, 1346 + { 1347 + .compatible = "eswin,eic7700-dwcmshc", 1348 + .data = &sdhci_dwcmshc_eic7700_pdata, 1926 1349 }, 1927 1350 {}, 1928 1351 }; ··· 2033 1448 priv->vendor_specific_area2 = 2034 1449 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 2035 1450 2036 - dwcmshc_cqhci_init(host, pdev); 1451 + dwcmshc_cqhci_init(host, pdev, pltfm_data); 2037 1452 } 2038 1453 2039 1454 if (pltfm_data->postinit) ··· 2158 1573 disable_clk: 2159 1574 clk_disable_unprepare(pltfm_host->clk); 2160 1575 return ret; 2161 - } 2162 - 2163 - static void dwcmshc_enable_card_clk(struct sdhci_host *host) 2164 - { 2165 - u16 ctrl; 2166 - 2167 - ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 2168 - if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 2169 - ctrl |= SDHCI_CLOCK_CARD_EN; 2170 - sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 2171 - } 2172 1576 } 2173 1577 2174 1578 static int dwcmshc_runtime_suspend(struct device *dev)

-2

drivers/mmc/host/tmio_mmc.h

··· 209 209 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 210 210 irqreturn_t tmio_mmc_irq(int irq, void *devid); 211 211 212 - #ifdef CONFIG_PM 213 212 int tmio_mmc_host_runtime_suspend(struct device *dev); 214 213 int tmio_mmc_host_runtime_resume(struct device *dev); 215 - #endif 216 214 217 215 static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) 218 216 {

-1

include/linux/mmc/card.h

··· 182 182 #define SD_SET_CURRENT_LIMIT_400 1 183 183 #define SD_SET_CURRENT_LIMIT_600 2 184 184 #define SD_SET_CURRENT_LIMIT_800 3 185 - #define SD_SET_CURRENT_NO_CHANGE (-1) 186 185 187 186 #define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200) 188 187 #define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)

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