Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-misc-next-2025-08-14' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.18:
UAPI Changes:
- Add DRM_IOCTL_GEM_CHANGE_HANDLE for reassigning GEM handles
- Document DRM_MODE_PAGE_FLIP_EVENT
Cross-subsystem Changes:
fbcon:
- Add missing declarations in fbcon.h
Core Changes:
bridge:
- Fix ref counting
panel:
- Replace and remove mipi_dsi_generic_write_{seq/_chatty}()
sched:
- Fixes
Rust:
- Drop Opaque<> from ioctl arguments
Driver Changes:
amdxdma:
- Support buffers allocated by user space
- Streamline PM interfaces
- Fixes
bridge:
- cdns-dsi: Various improvements to mode setting
- Support Solomon SSD2825 plus DT bindings
- Support Waveshare DSI2DPI plus DT bindings
gud:
- Fixes
ivpu:
- Fixes
nouveau:
- Use GSP firmware by default
- Fixes
panel:
- panel-edp: Support mt8189 Chromebooks; Support BOE NV140WUM-N64;
Support SHP LQ134Z1; Fixes
- panel-simple: Support Olimex LCD-OLinuXino-5CTS plus DT bindings
- Support Samsung AMS561RA01
- Support Hydis HV101HD1 plus DT bindings
panthor:
- Print task/pid on errors
- Fixes
renesas:
- convert to RUNTIME_PM_OPS
repaper:
- Use shadow-plane helpers
rocket:
- Add driver for Rockchip NPU plus DT bindings
sharp-memory:
- Use shadow-plane helpers
simpledrm:
- Use of_reserved_mem_region_to_resource() helper
tidss:
- Use crtc_ fields for programming display mode
- Remove other drivers from aperture
v3d:
- Support querying nubmer of GPU resets for KHR_robustness
vmwgfx:
- Fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://lore.kernel.org/r/20250814072454.GA18104@linux.fritz.box
+10399
-1183
+2
.mailmap
+2
.mailmap
···
164
164
Casey Connolly <casey.connolly@linaro.org> <caleb@postmarketos.org>
165
165
Can Guo <quic_cang@quicinc.com> <cang@codeaurora.org>
166
166
Carl Huang <quic_cjhuang@quicinc.com> <cjhuang@codeaurora.org>
167
+
Carl Vanderlip <carl.vanderlip@oss.qualcomm.com> <carlv@codeaurora.org>
168
+
Carl Vanderlip <carl.vanderlip@oss.qualcomm.com> <quic_carlv@quicinc.com>
167
169
Carlos Bilbao <carlos.bilbao@kernel.org> <carlos.bilbao@amd.com>
168
170
Carlos Bilbao <carlos.bilbao@kernel.org> <carlos.bilbao.osdev@gmail.com>
169
171
Carlos Bilbao <carlos.bilbao@kernel.org> <bilbao@vt.edu>
+1
Documentation/accel/index.rst
+1
Documentation/accel/index.rst
+19
Documentation/accel/rocket/index.rst
+19
Documentation/accel/rocket/index.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
=====================================
4
+
accel/rocket Rockchip NPU driver
5
+
=====================================
6
+
7
+
The accel/rocket driver supports the Neural Processing Units (NPUs) inside some
8
+
Rockchip SoCs such as the RK3588. Rockchip calls it RKNN and sometimes RKNPU.
9
+
10
+
The hardware is described in chapter 36 in the RK3588 TRM.
11
+
12
+
This driver just powers the hardware on and off, allocates and maps buffers to
13
+
the device and submits jobs to the frontend unit. Everything else is done in
14
+
userspace, as a Gallium driver (also called rocket) that is part of the Mesa3D
15
+
project.
16
+
17
+
Hardware currently supported:
18
+
19
+
* RK3588
+141
Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml
+141
Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/bridge/solomon,ssd2825.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Solomon SSD2825 RGB to MIPI-DSI bridge
8
+
9
+
maintainers:
10
+
- Svyatoslav Ryhel <clamor95@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: solomon,ssd2825
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
reset-gpios: true
23
+
24
+
dvdd-supply:
25
+
description: Regulator for 1.2V digital power supply.
26
+
27
+
avdd-supply:
28
+
description: Regulator for 1.2V analog power supply.
29
+
30
+
vddio-supply:
31
+
description: Regulator for 1.8V IO power supply.
32
+
33
+
spi-max-frequency:
34
+
maximum: 1000000
35
+
36
+
spi-cpha: true
37
+
spi-cpol: true
38
+
39
+
clocks:
40
+
maxItems: 1
41
+
description: Reference TX_CLK used before PLL is locked.
42
+
43
+
solomon,hs-zero-delay-ns:
44
+
description:
45
+
HS zero delay period
46
+
minimum: 0
47
+
maximum: 1700
48
+
default: 133
49
+
50
+
solomon,hs-prep-delay-ns:
51
+
description:
52
+
HS prep delay period
53
+
minimum: 0
54
+
maximum: 1728
55
+
default: 40
56
+
57
+
ports:
58
+
$ref: /schemas/graph.yaml#/properties/ports
59
+
60
+
properties:
61
+
port@0:
62
+
$ref: /schemas/graph.yaml#/$defs/port-base
63
+
unevaluatedProperties: false
64
+
description:
65
+
Video port for RGB input
66
+
67
+
properties:
68
+
endpoint:
69
+
$ref: /schemas/graph.yaml#/$defs/endpoint-base
70
+
unevaluatedProperties: false
71
+
72
+
properties:
73
+
bus-width:
74
+
enum: [ 16, 18, 24 ]
75
+
76
+
port@1:
77
+
$ref: /schemas/graph.yaml#/properties/port
78
+
description:
79
+
Video port for DSI output (panel or connector)
80
+
81
+
required:
82
+
- port@0
83
+
- port@1
84
+
85
+
required:
86
+
- compatible
87
+
- ports
88
+
89
+
additionalProperties: false
90
+
91
+
examples:
92
+
- |
93
+
#include <dt-bindings/gpio/gpio.h>
94
+
95
+
spi {
96
+
#address-cells = <1>;
97
+
#size-cells = <0>;
98
+
99
+
dsi@2 {
100
+
compatible = "solomon,ssd2825";
101
+
reg = <2>;
102
+
103
+
spi-max-frequency = <1000000>;
104
+
105
+
spi-cpha;
106
+
spi-cpol;
107
+
108
+
reset-gpios = <&gpio 114 GPIO_ACTIVE_LOW>;
109
+
110
+
dvdd-supply = <&vdd_1v2>;
111
+
avdd-supply = <&vdd_1v2>;
112
+
vddio-supply = <&vdd_1v8_io>;
113
+
114
+
solomon,hs-zero-delay-ns = <300>;
115
+
solomon,hs-prep-delay-ns = <65>;
116
+
117
+
clocks = <&ssd2825_tx_clk>;
118
+
119
+
ports {
120
+
#address-cells = <1>;
121
+
#size-cells = <0>;
122
+
123
+
port@0 {
124
+
reg = <0>;
125
+
126
+
bridge_input: endpoint {
127
+
remote-endpoint = <&dpi_output>;
128
+
bus-width = <24>;
129
+
};
130
+
};
131
+
132
+
port@1 {
133
+
reg = <1>;
134
+
135
+
bridge_output: endpoint {
136
+
remote-endpoint = <&panel_input>;
137
+
};
138
+
};
139
+
};
140
+
};
141
+
};
+60
Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml
+60
Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/panel/hydis,hv101hd1.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Hydis HV101HD1 DSI Display Panel
8
+
9
+
maintainers:
10
+
- Svyatoslav Ryhel <clamor95@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: panel-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: hydis,hv101hd1
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
vdd-supply: true
23
+
vio-supply: true
24
+
25
+
backlight: true
26
+
port: true
27
+
28
+
required:
29
+
- compatible
30
+
- vdd-supply
31
+
- vio-supply
32
+
- backlight
33
+
34
+
additionalProperties: false
35
+
36
+
examples:
37
+
- |
38
+
#include <dt-bindings/gpio/gpio.h>
39
+
40
+
dsi {
41
+
#address-cells = <1>;
42
+
#size-cells = <0>;
43
+
44
+
panel@0 {
45
+
compatible = "hydis,hv101hd1";
46
+
reg = <0>;
47
+
48
+
vdd-supply = <&vdd_lcd>;
49
+
vio-supply = <&vddio_lcd>;
50
+
51
+
backlight = <&backlight>;
52
+
53
+
port {
54
+
panel_in: endpoint {
55
+
remote-endpoint = <&dsi_out>;
56
+
};
57
+
};
58
+
};
59
+
};
60
+
...
+6
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+6
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
···
236
236
- okaya,rs800480t-7x0gp
237
237
# Olimex 4.3" TFT LCD panel
238
238
- olimex,lcd-olinuxino-43-ts
239
+
# Olimex 5.0" TFT LCD panel
240
+
- olimex,lcd-olinuxino-5-cts
239
241
# On Tat Industrial Company 5" DPI TFT panel.
240
242
- ontat,kd50g21-40nt-a1
241
243
# On Tat Industrial Company 7" DPI TFT panel.
···
323
321
- vivax,tpc9150-panel
324
322
# VXT 800x480 color TFT LCD panel
325
323
- vxt,vl050-8048nt-c01
324
+
# Waveshare 13.3" FHD (1920x1080) LCD panel
325
+
- waveshare,13.3inch-panel
326
+
# Waveshare 7.0" WSVGA (1024x600) LCD panel
327
+
- waveshare,7.0inch-c-panel
326
328
# Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
327
329
- winstar,wf35ltiacd
328
330
# Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel
+4
Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
+4
Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
···
21
21
- enum:
22
22
# Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel
23
23
- samsung,atna30dw01
24
+
# Samsung 14" FHD+ (1920x1200 pixels) eDP AMOLED panel
25
+
- samsung,atna40ct06
26
+
# Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
27
+
- samsung,atna40cu11
24
28
# Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel
25
29
- samsung,atna40yk20
26
30
# Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
+55
Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml
+55
Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung AMS561RA01 panel with S6E8AA5X01 controller
8
+
9
+
maintainers:
10
+
- Kaustabh Chakraborty <kauschluss@disroot.org>
11
+
12
+
allOf:
13
+
- $ref: panel-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: samsung,s6e8aa5x01-ams561ra01
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
vdd-supply:
23
+
description: core voltage supply
24
+
25
+
vci-supply:
26
+
description: voltage supply for analog circuits
27
+
28
+
reset-gpios: true
29
+
30
+
required:
31
+
- compatible
32
+
- reg
33
+
34
+
additionalProperties: false
35
+
36
+
examples:
37
+
- |
38
+
#include <dt-bindings/gpio/gpio.h>
39
+
40
+
dsi {
41
+
#address-cells = <1>;
42
+
#size-cells = <0>;
43
+
44
+
panel@0 {
45
+
compatible = "samsung,s6e8aa5x01-ams561ra01";
46
+
reg = <0>;
47
+
48
+
vdd-supply = <&panel_vdd_reg>;
49
+
vci-supply = <&panel_vci_reg>;
50
+
51
+
reset-gpios = <&gpd3 4 GPIO_ACTIVE_HIGH>;
52
+
};
53
+
};
54
+
55
+
...
+112
Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
+112
Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Neural Processing Unit IP from Rockchip
8
+
9
+
maintainers:
10
+
- Tomeu Vizoso <tomeu@tomeuvizoso.net>
11
+
12
+
description:
13
+
Rockchip IP for accelerating inference of neural networks.
14
+
15
+
There is to be a node per each NPU core in the SoC, and each core should reference all the
16
+
resources that it needs to function, such as clocks, power domains, and resets.
17
+
18
+
properties:
19
+
$nodename:
20
+
pattern: '^npu@[a-f0-9]+$'
21
+
22
+
compatible:
23
+
enum:
24
+
- rockchip,rk3588-rknn-core
25
+
26
+
reg:
27
+
maxItems: 3
28
+
29
+
reg-names:
30
+
items:
31
+
- const: pc # Program Control-related registers
32
+
- const: cna # Convolution Neural Network Accelerator registers
33
+
- const: core # Main NPU core processing unit registers
34
+
35
+
clocks:
36
+
maxItems: 4
37
+
38
+
clock-names:
39
+
items:
40
+
- const: aclk
41
+
- const: hclk
42
+
- const: npu
43
+
- const: pclk
44
+
45
+
interrupts:
46
+
maxItems: 1
47
+
48
+
iommus:
49
+
maxItems: 1
50
+
51
+
npu-supply: true
52
+
53
+
power-domains:
54
+
maxItems: 1
55
+
56
+
resets:
57
+
maxItems: 2
58
+
59
+
reset-names:
60
+
items:
61
+
- const: srst_a
62
+
- const: srst_h
63
+
64
+
sram-supply: true
65
+
66
+
required:
67
+
- compatible
68
+
- reg
69
+
- reg-names
70
+
- clocks
71
+
- clock-names
72
+
- interrupts
73
+
- iommus
74
+
- power-domains
75
+
- resets
76
+
- reset-names
77
+
- npu-supply
78
+
- sram-supply
79
+
80
+
additionalProperties: false
81
+
82
+
examples:
83
+
- |
84
+
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
85
+
#include <dt-bindings/interrupt-controller/irq.h>
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
#include <dt-bindings/power/rk3588-power.h>
88
+
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
89
+
90
+
bus {
91
+
#address-cells = <2>;
92
+
#size-cells = <2>;
93
+
94
+
npu@fdab0000 {
95
+
compatible = "rockchip,rk3588-rknn-core";
96
+
reg = <0x0 0xfdab0000 0x0 0x1000>,
97
+
<0x0 0xfdab1000 0x0 0x1000>,
98
+
<0x0 0xfdab3000 0x0 0x1000>;
99
+
reg-names = "pc", "cna", "core";
100
+
clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
101
+
<&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
102
+
clock-names = "aclk", "hclk", "npu", "pclk";
103
+
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
104
+
iommus = <&rknn_mmu_0>;
105
+
npu-supply = <&vdd_npu_s0>;
106
+
power-domains = <&power RK3588_PD_NPUTOP>;
107
+
resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
108
+
reset-names = "srst_a", "srst_h";
109
+
sram-supply = <&vdd_npu_mem_s0>;
110
+
};
111
+
};
112
+
...
+11
-11
Documentation/gpu/todo.rst
+11
-11
Documentation/gpu/todo.rst
···
497
497
498
498
Level: Intermediate
499
499
500
-
Transition away from using mipi_dsi_*_write_seq()
501
-
-------------------------------------------------
500
+
Transition away from using deprecated MIPI DSI functions
501
+
--------------------------------------------------------
502
502
503
-
The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are
504
-
non-intuitive because, if there are errors, they return out of the *caller's*
505
-
function. We should move all callers to use mipi_dsi_generic_write_seq_multi()
506
-
and mipi_dsi_dcs_write_seq_multi() macros instead.
503
+
There are many functions defined in ``drm_mipi_dsi.c`` which have been
504
+
deprecated. Each deprecated function was deprecated in favor of its `multi`
505
+
variant (e.g. `mipi_dsi_generic_write()` and `mipi_dsi_generic_write_multi()`).
506
+
The `multi` variant of a function includes improved error handling and logic
507
+
which makes it more convenient to make several calls in a row, as most MIPI
508
+
drivers do.
507
509
508
-
Once all callers are transitioned, the macros and the functions that they call,
509
-
mipi_dsi_generic_write_chatty() and mipi_dsi_dcs_write_buffer_chatty(), can
510
-
probably be removed. Alternatively, if people feel like the _multi() variants
511
-
are overkill for some use cases, we could keep the mipi_dsi_*_write_seq()
512
-
variants but change them not to return out of the caller.
510
+
Drivers should be updated to use undeprecated functions. Once all usages of the
511
+
deprecated MIPI DSI functions have been removed, their definitions may be
512
+
removed from ``drm_mipi_dsi.c``.
513
513
514
514
Contact: Douglas Anderson <dianders@chromium.org>
515
515
+12
-1
MAINTAINERS
+12
-1
MAINTAINERS
···
7492
7492
DRM ACCEL DRIVERS FOR INTEL VPU
7493
7493
M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
7494
7494
M: Maciej Falkowski <maciej.falkowski@linux.intel.com>
7495
+
M: Karol Wachowski <karol.wachowski@linux.intel.com>
7495
7496
L: dri-devel@lists.freedesktop.org
7496
7497
S: Supported
7497
7498
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7498
7499
F: drivers/accel/ivpu/
7499
7500
F: include/uapi/drm/ivpu_accel.h
7501
+
7502
+
DRM ACCEL DRIVER FOR ROCKCHIP NPU
7503
+
M: Tomeu Vizoso <tomeu@tomeuvizoso.net>
7504
+
L: dri-devel@lists.freedesktop.org
7505
+
S: Supported
7506
+
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7507
+
F: Documentation/accel/rocket/
7508
+
F: Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
7509
+
F: drivers/accel/rocket/
7510
+
F: include/uapi/drm/rocket_accel.h
7500
7511
7501
7512
DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
7502
7513
M: Oded Gabbay <ogabbay@kernel.org>
···
20672
20661
20673
20662
QUALCOMM CLOUD AI (QAIC) DRIVER
20674
20663
M: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
20675
-
R: Carl Vanderlip <quic_carlv@quicinc.com>
20664
+
R: Carl Vanderlip <carl.vanderlip@oss.qualcomm.com>
20676
20665
L: linux-arm-msm@vger.kernel.org
20677
20666
L: dri-devel@lists.freedesktop.org
20678
20667
S: Supported
+1
drivers/accel/Kconfig
+1
drivers/accel/Kconfig
+1
drivers/accel/Makefile
+1
drivers/accel/Makefile
+1
drivers/accel/amdxdna/Makefile
+1
drivers/accel/amdxdna/Makefile
+30
-29
drivers/accel/amdxdna/aie2_ctx.c
+30
-29
drivers/accel/amdxdna/aie2_ctx.c
···
46
46
kref_put(&job->refcnt, aie2_job_release);
47
47
}
48
48
49
+
static void aie2_hwctx_status_shift_stop(struct amdxdna_hwctx *hwctx)
50
+
{
51
+
hwctx->old_status = hwctx->status;
52
+
hwctx->status = HWCTX_STAT_STOP;
53
+
}
54
+
55
+
static void aie2_hwctx_status_restore(struct amdxdna_hwctx *hwctx)
56
+
{
57
+
hwctx->status = hwctx->old_status;
58
+
}
59
+
49
60
/* The bad_job is used in aie2_sched_job_timedout, otherwise, set it to NULL */
50
61
static void aie2_hwctx_stop(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hwctx,
51
62
struct drm_sched_job *bad_job)
···
100
89
return ret;
101
90
}
102
91
103
-
void aie2_restart_ctx(struct amdxdna_client *client)
104
-
{
105
-
struct amdxdna_dev *xdna = client->xdna;
106
-
struct amdxdna_hwctx *hwctx;
107
-
unsigned long hwctx_id;
108
-
109
-
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
110
-
mutex_lock(&client->hwctx_lock);
111
-
amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
112
-
if (hwctx->status != HWCTX_STAT_STOP)
113
-
continue;
114
-
115
-
hwctx->status = hwctx->old_status;
116
-
XDNA_DBG(xdna, "Resetting %s", hwctx->name);
117
-
aie2_hwctx_restart(xdna, hwctx);
118
-
}
119
-
mutex_unlock(&client->hwctx_lock);
120
-
}
121
-
122
92
static struct dma_fence *aie2_cmd_get_out_fence(struct amdxdna_hwctx *hwctx, u64 seq)
123
93
{
124
94
struct dma_fence *fence, *out_fence = NULL;
···
133
141
dma_fence_put(fence);
134
142
}
135
143
136
-
void aie2_hwctx_suspend(struct amdxdna_hwctx *hwctx)
144
+
void aie2_hwctx_suspend(struct amdxdna_client *client)
137
145
{
138
-
struct amdxdna_dev *xdna = hwctx->client->xdna;
146
+
struct amdxdna_dev *xdna = client->xdna;
147
+
struct amdxdna_hwctx *hwctx;
148
+
unsigned long hwctx_id;
139
149
140
150
/*
141
151
* Command timeout is unlikely. But if it happens, it doesn't
···
145
151
* and abort all commands.
146
152
*/
147
153
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
148
-
aie2_hwctx_wait_for_idle(hwctx);
149
-
aie2_hwctx_stop(xdna, hwctx, NULL);
150
-
hwctx->old_status = hwctx->status;
151
-
hwctx->status = HWCTX_STAT_STOP;
154
+
guard(mutex)(&client->hwctx_lock);
155
+
amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
156
+
aie2_hwctx_wait_for_idle(hwctx);
157
+
aie2_hwctx_stop(xdna, hwctx, NULL);
158
+
aie2_hwctx_status_shift_stop(hwctx);
159
+
}
152
160
}
153
161
154
-
void aie2_hwctx_resume(struct amdxdna_hwctx *hwctx)
162
+
void aie2_hwctx_resume(struct amdxdna_client *client)
155
163
{
156
-
struct amdxdna_dev *xdna = hwctx->client->xdna;
164
+
struct amdxdna_dev *xdna = client->xdna;
165
+
struct amdxdna_hwctx *hwctx;
166
+
unsigned long hwctx_id;
157
167
158
168
/*
159
169
* The resume path cannot guarantee that mailbox channel can be
···
165
167
* mailbox channel, error will return.
166
168
*/
167
169
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
168
-
hwctx->status = hwctx->old_status;
169
-
aie2_hwctx_restart(xdna, hwctx);
170
+
guard(mutex)(&client->hwctx_lock);
171
+
amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
172
+
aie2_hwctx_status_restore(hwctx);
173
+
aie2_hwctx_restart(xdna, hwctx);
174
+
}
170
175
}
171
176
172
177
static void
+35
-10
drivers/accel/amdxdna/aie2_pci.c
+35
-10
drivers/accel/amdxdna/aie2_pci.c
···
440
440
return ret;
441
441
}
442
442
443
+
static int aie2_hw_suspend(struct amdxdna_dev *xdna)
444
+
{
445
+
struct amdxdna_client *client;
446
+
447
+
guard(mutex)(&xdna->dev_lock);
448
+
list_for_each_entry(client, &xdna->client_list, node)
449
+
aie2_hwctx_suspend(client);
450
+
451
+
aie2_hw_stop(xdna);
452
+
453
+
return 0;
454
+
}
455
+
456
+
static int aie2_hw_resume(struct amdxdna_dev *xdna)
457
+
{
458
+
struct amdxdna_client *client;
459
+
int ret;
460
+
461
+
guard(mutex)(&xdna->dev_lock);
462
+
ret = aie2_hw_start(xdna);
463
+
if (ret) {
464
+
XDNA_ERR(xdna, "Start hardware failed, %d", ret);
465
+
return ret;
466
+
}
467
+
468
+
list_for_each_entry(client, &xdna->client_list, node)
469
+
aie2_hwctx_resume(client);
470
+
471
+
return ret;
472
+
}
473
+
443
474
static int aie2_init(struct amdxdna_dev *xdna)
444
475
{
445
476
struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
···
551
520
if (!ndev->psp_hdl) {
552
521
XDNA_ERR(xdna, "failed to create psp");
553
522
ret = -ENOMEM;
554
-
goto free_irq;
523
+
goto release_fw;
555
524
}
556
525
xdna->dev_handle = ndev;
557
526
558
527
ret = aie2_hw_start(xdna);
559
528
if (ret) {
560
529
XDNA_ERR(xdna, "start npu failed, ret %d", ret);
561
-
goto free_irq;
530
+
goto release_fw;
562
531
}
563
532
564
533
ret = aie2_mgmt_fw_query(ndev);
···
609
578
aie2_error_async_events_free(ndev);
610
579
stop_hw:
611
580
aie2_hw_stop(xdna);
612
-
free_irq:
613
-
pci_free_irq_vectors(pdev);
614
581
release_fw:
615
582
release_firmware(fw);
616
583
···
617
588
618
589
static void aie2_fini(struct amdxdna_dev *xdna)
619
590
{
620
-
struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
621
591
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
622
592
623
593
aie2_hw_stop(xdna);
624
594
aie2_error_async_events_free(ndev);
625
-
pci_free_irq_vectors(pdev);
626
595
}
627
596
628
597
static int aie2_get_aie_status(struct amdxdna_client *client,
···
932
905
const struct amdxdna_dev_ops aie2_ops = {
933
906
.init = aie2_init,
934
907
.fini = aie2_fini,
935
-
.resume = aie2_hw_start,
936
-
.suspend = aie2_hw_stop,
908
+
.resume = aie2_hw_resume,
909
+
.suspend = aie2_hw_suspend,
937
910
.get_aie_info = aie2_get_info,
938
911
.set_aie_state = aie2_set_state,
939
912
.hwctx_init = aie2_hwctx_init,
···
941
914
.hwctx_config = aie2_hwctx_config,
942
915
.cmd_submit = aie2_cmd_submit,
943
916
.hmm_invalidate = aie2_hmm_invalidate,
944
-
.hwctx_suspend = aie2_hwctx_suspend,
945
-
.hwctx_resume = aie2_hwctx_resume,
946
917
};
+2
-3
drivers/accel/amdxdna/aie2_pci.h
+2
-3
drivers/accel/amdxdna/aie2_pci.h
···
288
288
int aie2_hwctx_init(struct amdxdna_hwctx *hwctx);
289
289
void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx);
290
290
int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
291
-
void aie2_hwctx_suspend(struct amdxdna_hwctx *hwctx);
292
-
void aie2_hwctx_resume(struct amdxdna_hwctx *hwctx);
291
+
void aie2_hwctx_suspend(struct amdxdna_client *client);
292
+
void aie2_hwctx_resume(struct amdxdna_client *client);
293
293
int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
294
294
void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
295
-
void aie2_restart_ctx(struct amdxdna_client *client);
296
295
297
296
#endif /* _AIE2_PCI_H_ */
-26
drivers/accel/amdxdna/amdxdna_ctx.c
-26
drivers/accel/amdxdna/amdxdna_ctx.c
···
60
60
return &fence->base;
61
61
}
62
62
63
-
void amdxdna_hwctx_suspend(struct amdxdna_client *client)
64
-
{
65
-
struct amdxdna_dev *xdna = client->xdna;
66
-
struct amdxdna_hwctx *hwctx;
67
-
unsigned long hwctx_id;
68
-
69
-
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
70
-
mutex_lock(&client->hwctx_lock);
71
-
amdxdna_for_each_hwctx(client, hwctx_id, hwctx)
72
-
xdna->dev_info->ops->hwctx_suspend(hwctx);
73
-
mutex_unlock(&client->hwctx_lock);
74
-
}
75
-
76
-
void amdxdna_hwctx_resume(struct amdxdna_client *client)
77
-
{
78
-
struct amdxdna_dev *xdna = client->xdna;
79
-
struct amdxdna_hwctx *hwctx;
80
-
unsigned long hwctx_id;
81
-
82
-
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
83
-
mutex_lock(&client->hwctx_lock);
84
-
amdxdna_for_each_hwctx(client, hwctx_id, hwctx)
85
-
xdna->dev_info->ops->hwctx_resume(hwctx);
86
-
mutex_unlock(&client->hwctx_lock);
87
-
}
88
-
89
63
static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx,
90
64
struct srcu_struct *ss)
91
65
{
-2
drivers/accel/amdxdna/amdxdna_ctx.h
-2
drivers/accel/amdxdna/amdxdna_ctx.h
···
147
147
148
148
void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job);
149
149
void amdxdna_hwctx_remove_all(struct amdxdna_client *client);
150
-
void amdxdna_hwctx_suspend(struct amdxdna_client *client);
151
-
void amdxdna_hwctx_resume(struct amdxdna_client *client);
152
150
153
151
int amdxdna_cmd_submit(struct amdxdna_client *client,
154
152
u32 cmd_bo_hdls, u32 *arg_bo_hdls, u32 arg_bo_cnt,
+114
-25
drivers/accel/amdxdna/amdxdna_gem.c
+114
-25
drivers/accel/amdxdna/amdxdna_gem.c
···
18
18
#include "amdxdna_ctx.h"
19
19
#include "amdxdna_gem.h"
20
20
#include "amdxdna_pci_drv.h"
21
+
#include "amdxdna_ubuf.h"
21
22
22
23
#define XDNA_MAX_CMD_BO_SIZE SZ_32K
23
24
···
297
296
298
297
vma->vm_private_data = NULL;
299
298
vma->vm_ops = NULL;
300
-
ret = dma_buf_mmap(to_gobj(abo)->dma_buf, vma, 0);
299
+
ret = dma_buf_mmap(abo->dma_buf, vma, 0);
301
300
if (ret) {
302
301
XDNA_ERR(xdna, "Failed to mmap dma buf %d", ret);
303
302
return ret;
···
392
391
.vunmap = drm_gem_dmabuf_vunmap,
393
392
};
394
393
394
+
static int amdxdna_gem_obj_vmap(struct drm_gem_object *obj, struct iosys_map *map)
395
+
{
396
+
struct amdxdna_gem_obj *abo = to_xdna_obj(obj);
397
+
398
+
iosys_map_clear(map);
399
+
400
+
dma_resv_assert_held(obj->resv);
401
+
402
+
if (is_import_bo(abo))
403
+
dma_buf_vmap(abo->dma_buf, map);
404
+
else
405
+
drm_gem_shmem_object_vmap(obj, map);
406
+
407
+
if (!map->vaddr)
408
+
return -ENOMEM;
409
+
410
+
return 0;
411
+
}
412
+
413
+
static void amdxdna_gem_obj_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
414
+
{
415
+
struct amdxdna_gem_obj *abo = to_xdna_obj(obj);
416
+
417
+
dma_resv_assert_held(obj->resv);
418
+
419
+
if (is_import_bo(abo))
420
+
dma_buf_vunmap(abo->dma_buf, map);
421
+
else
422
+
drm_gem_shmem_object_vunmap(obj, map);
423
+
}
424
+
395
425
static struct dma_buf *amdxdna_gem_prime_export(struct drm_gem_object *gobj, int flags)
396
426
{
427
+
struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
397
428
DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
429
+
430
+
if (abo->dma_buf) {
431
+
get_dma_buf(abo->dma_buf);
432
+
return abo->dma_buf;
433
+
}
398
434
399
435
exp_info.ops = &amdxdna_dmabuf_ops;
400
436
exp_info.size = gobj->size;
···
489
451
.pin = drm_gem_shmem_object_pin,
490
452
.unpin = drm_gem_shmem_object_unpin,
491
453
.get_sg_table = drm_gem_shmem_object_get_sg_table,
492
-
.vmap = drm_gem_shmem_object_vmap,
493
-
.vunmap = drm_gem_shmem_object_vunmap,
454
+
.vmap = amdxdna_gem_obj_vmap,
455
+
.vunmap = amdxdna_gem_obj_vunmap,
494
456
.mmap = amdxdna_gem_obj_mmap,
495
457
.vm_ops = &drm_gem_shmem_vm_ops,
496
458
.export = amdxdna_gem_prime_export,
···
530
492
to_gobj(abo)->funcs = &amdxdna_gem_shmem_funcs;
531
493
532
494
return to_gobj(abo);
495
+
}
496
+
497
+
static struct amdxdna_gem_obj *
498
+
amdxdna_gem_create_shmem_object(struct drm_device *dev, size_t size)
499
+
{
500
+
struct drm_gem_shmem_object *shmem = drm_gem_shmem_create(dev, size);
501
+
502
+
if (IS_ERR(shmem))
503
+
return ERR_CAST(shmem);
504
+
505
+
shmem->map_wc = false;
506
+
return to_xdna_obj(&shmem->base);
507
+
}
508
+
509
+
static struct amdxdna_gem_obj *
510
+
amdxdna_gem_create_ubuf_object(struct drm_device *dev, struct amdxdna_drm_create_bo *args)
511
+
{
512
+
struct amdxdna_dev *xdna = to_xdna_dev(dev);
513
+
enum amdxdna_ubuf_flag flags = 0;
514
+
struct amdxdna_drm_va_tbl va_tbl;
515
+
struct drm_gem_object *gobj;
516
+
struct dma_buf *dma_buf;
517
+
518
+
if (copy_from_user(&va_tbl, u64_to_user_ptr(args->vaddr), sizeof(va_tbl))) {
519
+
XDNA_DBG(xdna, "Access va table failed");
520
+
return ERR_PTR(-EINVAL);
521
+
}
522
+
523
+
if (va_tbl.num_entries) {
524
+
if (args->type == AMDXDNA_BO_CMD)
525
+
flags |= AMDXDNA_UBUF_FLAG_MAP_DMA;
526
+
527
+
dma_buf = amdxdna_get_ubuf(dev, flags, va_tbl.num_entries,
528
+
u64_to_user_ptr(args->vaddr + sizeof(va_tbl)));
529
+
} else {
530
+
dma_buf = dma_buf_get(va_tbl.dmabuf_fd);
531
+
}
532
+
533
+
if (IS_ERR(dma_buf))
534
+
return ERR_CAST(dma_buf);
535
+
536
+
gobj = amdxdna_gem_prime_import(dev, dma_buf);
537
+
if (IS_ERR(gobj)) {
538
+
dma_buf_put(dma_buf);
539
+
return ERR_CAST(gobj);
540
+
}
541
+
542
+
dma_buf_put(dma_buf);
543
+
544
+
return to_xdna_obj(gobj);
545
+
}
546
+
547
+
static struct amdxdna_gem_obj *
548
+
amdxdna_gem_create_object(struct drm_device *dev,
549
+
struct amdxdna_drm_create_bo *args)
550
+
{
551
+
size_t aligned_sz = PAGE_ALIGN(args->size);
552
+
553
+
if (args->vaddr)
554
+
return amdxdna_gem_create_ubuf_object(dev, args);
555
+
556
+
return amdxdna_gem_create_shmem_object(dev, aligned_sz);
533
557
}
534
558
535
559
struct drm_gem_object *
···
645
545
struct drm_file *filp)
646
546
{
647
547
struct amdxdna_client *client = filp->driver_priv;
648
-
struct drm_gem_shmem_object *shmem;
649
548
struct amdxdna_gem_obj *abo;
650
549
651
-
shmem = drm_gem_shmem_create(dev, args->size);
652
-
if (IS_ERR(shmem))
653
-
return ERR_CAST(shmem);
550
+
abo = amdxdna_gem_create_object(dev, args);
551
+
if (IS_ERR(abo))
552
+
return ERR_CAST(abo);
654
553
655
-
shmem->map_wc = false;
656
-
657
-
abo = to_xdna_obj(&shmem->base);
658
554
abo->client = client;
659
555
abo->type = AMDXDNA_BO_SHMEM;
660
556
···
665
569
struct amdxdna_client *client = filp->driver_priv;
666
570
struct iosys_map map = IOSYS_MAP_INIT_VADDR(NULL);
667
571
struct amdxdna_dev *xdna = to_xdna_dev(dev);
668
-
struct drm_gem_shmem_object *shmem;
669
572
struct amdxdna_gem_obj *abo;
670
573
int ret;
671
574
···
681
586
goto mm_unlock;
682
587
}
683
588
684
-
shmem = drm_gem_shmem_create(dev, args->size);
685
-
if (IS_ERR(shmem)) {
686
-
ret = PTR_ERR(shmem);
589
+
abo = amdxdna_gem_create_object(dev, args);
590
+
if (IS_ERR(abo)) {
591
+
ret = PTR_ERR(abo);
687
592
goto mm_unlock;
688
593
}
689
594
690
-
shmem->map_wc = false;
691
-
abo = to_xdna_obj(&shmem->base);
692
595
abo->type = AMDXDNA_BO_DEV_HEAP;
693
596
abo->client = client;
694
597
abo->mem.dev_addr = client->xdna->dev_info->dev_mem_base;
···
750
657
{
751
658
struct iosys_map map = IOSYS_MAP_INIT_VADDR(NULL);
752
659
struct amdxdna_dev *xdna = to_xdna_dev(dev);
753
-
struct drm_gem_shmem_object *shmem;
754
660
struct amdxdna_gem_obj *abo;
755
661
int ret;
756
662
···
763
671
return ERR_PTR(-EINVAL);
764
672
}
765
673
766
-
shmem = drm_gem_shmem_create(dev, args->size);
767
-
if (IS_ERR(shmem))
768
-
return ERR_CAST(shmem);
769
-
770
-
shmem->map_wc = false;
771
-
abo = to_xdna_obj(&shmem->base);
674
+
abo = amdxdna_gem_create_object(dev, args);
675
+
if (IS_ERR(abo))
676
+
return ERR_CAST(abo);
772
677
773
678
abo->type = AMDXDNA_BO_CMD;
774
679
abo->client = filp->driver_priv;
···
780
691
return abo;
781
692
782
693
release_obj:
783
-
drm_gem_shmem_free(shmem);
694
+
drm_gem_object_put(to_gobj(abo));
784
695
return ERR_PTR(ret);
785
696
}
786
697
···
791
702
struct amdxdna_gem_obj *abo;
792
703
int ret;
793
704
794
-
if (args->flags || args->vaddr || !args->size)
705
+
if (args->flags)
795
706
return -EINVAL;
796
707
797
708
XDNA_DBG(xdna, "BO arg type %d vaddr 0x%llx size 0x%llx flags 0x%llx",
+7
-67
drivers/accel/amdxdna/amdxdna_pci_drv.c
+7
-67
drivers/accel/amdxdna/amdxdna_pci_drv.c
···
343
343
mutex_unlock(&xdna->dev_lock);
344
344
}
345
345
346
-
static int amdxdna_dev_suspend_nolock(struct amdxdna_dev *xdna)
347
-
{
348
-
if (xdna->dev_info->ops->suspend)
349
-
xdna->dev_info->ops->suspend(xdna);
350
-
351
-
return 0;
352
-
}
353
-
354
-
static int amdxdna_dev_resume_nolock(struct amdxdna_dev *xdna)
355
-
{
356
-
if (xdna->dev_info->ops->resume)
357
-
return xdna->dev_info->ops->resume(xdna);
358
-
359
-
return 0;
360
-
}
361
-
362
346
static int amdxdna_pmops_suspend(struct device *dev)
363
347
{
364
348
struct amdxdna_dev *xdna = pci_get_drvdata(to_pci_dev(dev));
365
-
struct amdxdna_client *client;
366
349
367
-
mutex_lock(&xdna->dev_lock);
368
-
list_for_each_entry(client, &xdna->client_list, node)
369
-
amdxdna_hwctx_suspend(client);
350
+
if (!xdna->dev_info->ops->suspend)
351
+
return -EOPNOTSUPP;
370
352
371
-
amdxdna_dev_suspend_nolock(xdna);
372
-
mutex_unlock(&xdna->dev_lock);
373
-
374
-
return 0;
353
+
return xdna->dev_info->ops->suspend(xdna);
375
354
}
376
355
377
356
static int amdxdna_pmops_resume(struct device *dev)
378
357
{
379
358
struct amdxdna_dev *xdna = pci_get_drvdata(to_pci_dev(dev));
380
-
struct amdxdna_client *client;
381
-
int ret;
382
359
383
-
XDNA_INFO(xdna, "firmware resuming...");
384
-
mutex_lock(&xdna->dev_lock);
385
-
ret = amdxdna_dev_resume_nolock(xdna);
386
-
if (ret) {
387
-
XDNA_ERR(xdna, "resume NPU firmware failed");
388
-
mutex_unlock(&xdna->dev_lock);
389
-
return ret;
390
-
}
360
+
if (!xdna->dev_info->ops->resume)
361
+
return -EOPNOTSUPP;
391
362
392
-
XDNA_INFO(xdna, "hardware context resuming...");
393
-
list_for_each_entry(client, &xdna->client_list, node)
394
-
amdxdna_hwctx_resume(client);
395
-
mutex_unlock(&xdna->dev_lock);
396
-
397
-
return 0;
398
-
}
399
-
400
-
static int amdxdna_rpmops_suspend(struct device *dev)
401
-
{
402
-
struct amdxdna_dev *xdna = pci_get_drvdata(to_pci_dev(dev));
403
-
int ret;
404
-
405
-
mutex_lock(&xdna->dev_lock);
406
-
ret = amdxdna_dev_suspend_nolock(xdna);
407
-
mutex_unlock(&xdna->dev_lock);
408
-
409
-
XDNA_DBG(xdna, "Runtime suspend done ret: %d", ret);
410
-
return ret;
411
-
}
412
-
413
-
static int amdxdna_rpmops_resume(struct device *dev)
414
-
{
415
-
struct amdxdna_dev *xdna = pci_get_drvdata(to_pci_dev(dev));
416
-
int ret;
417
-
418
-
mutex_lock(&xdna->dev_lock);
419
-
ret = amdxdna_dev_resume_nolock(xdna);
420
-
mutex_unlock(&xdna->dev_lock);
421
-
422
-
XDNA_DBG(xdna, "Runtime resume done ret: %d", ret);
423
-
return ret;
363
+
return xdna->dev_info->ops->resume(xdna);
424
364
}
425
365
426
366
static const struct dev_pm_ops amdxdna_pm_ops = {
427
367
SYSTEM_SLEEP_PM_OPS(amdxdna_pmops_suspend, amdxdna_pmops_resume)
428
-
RUNTIME_PM_OPS(amdxdna_rpmops_suspend, amdxdna_rpmops_resume, NULL)
368
+
RUNTIME_PM_OPS(amdxdna_pmops_suspend, amdxdna_pmops_resume, NULL)
429
369
};
430
370
431
371
static struct pci_driver amdxdna_pci_driver = {
+1
-3
drivers/accel/amdxdna/amdxdna_pci_drv.h
+1
-3
drivers/accel/amdxdna/amdxdna_pci_drv.h
···
50
50
int (*init)(struct amdxdna_dev *xdna);
51
51
void (*fini)(struct amdxdna_dev *xdna);
52
52
int (*resume)(struct amdxdna_dev *xdna);
53
-
void (*suspend)(struct amdxdna_dev *xdna);
53
+
int (*suspend)(struct amdxdna_dev *xdna);
54
54
int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
55
55
void (*hwctx_fini)(struct amdxdna_hwctx *hwctx);
56
56
int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
57
57
void (*hmm_invalidate)(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
58
-
void (*hwctx_suspend)(struct amdxdna_hwctx *hwctx);
59
-
void (*hwctx_resume)(struct amdxdna_hwctx *hwctx);
60
58
int (*cmd_submit)(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
61
59
int (*get_aie_info)(struct amdxdna_client *client, struct amdxdna_drm_get_info *args);
62
60
int (*set_aie_state)(struct amdxdna_client *client, struct amdxdna_drm_set_state *args);
+232
drivers/accel/amdxdna/amdxdna_ubuf.c
+232
drivers/accel/amdxdna/amdxdna_ubuf.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2025, Advanced Micro Devices, Inc.
4
+
*/
5
+
6
+
#include <drm/amdxdna_accel.h>
7
+
#include <drm/drm_device.h>
8
+
#include <drm/drm_print.h>
9
+
#include <linux/dma-buf.h>
10
+
#include <linux/pagemap.h>
11
+
#include <linux/vmalloc.h>
12
+
13
+
#include "amdxdna_pci_drv.h"
14
+
#include "amdxdna_ubuf.h"
15
+
16
+
struct amdxdna_ubuf_priv {
17
+
struct page **pages;
18
+
u64 nr_pages;
19
+
enum amdxdna_ubuf_flag flags;
20
+
struct mm_struct *mm;
21
+
};
22
+
23
+
static struct sg_table *amdxdna_ubuf_map(struct dma_buf_attachment *attach,
24
+
enum dma_data_direction direction)
25
+
{
26
+
struct amdxdna_ubuf_priv *ubuf = attach->dmabuf->priv;
27
+
struct sg_table *sg;
28
+
int ret;
29
+
30
+
sg = kzalloc(sizeof(*sg), GFP_KERNEL);
31
+
if (!sg)
32
+
return ERR_PTR(-ENOMEM);
33
+
34
+
ret = sg_alloc_table_from_pages(sg, ubuf->pages, ubuf->nr_pages, 0,
35
+
ubuf->nr_pages << PAGE_SHIFT, GFP_KERNEL);
36
+
if (ret)
37
+
return ERR_PTR(ret);
38
+
39
+
if (ubuf->flags & AMDXDNA_UBUF_FLAG_MAP_DMA) {
40
+
ret = dma_map_sgtable(attach->dev, sg, direction, 0);
41
+
if (ret)
42
+
return ERR_PTR(ret);
43
+
}
44
+
45
+
return sg;
46
+
}
47
+
48
+
static void amdxdna_ubuf_unmap(struct dma_buf_attachment *attach,
49
+
struct sg_table *sg,
50
+
enum dma_data_direction direction)
51
+
{
52
+
struct amdxdna_ubuf_priv *ubuf = attach->dmabuf->priv;
53
+
54
+
if (ubuf->flags & AMDXDNA_UBUF_FLAG_MAP_DMA)
55
+
dma_unmap_sgtable(attach->dev, sg, direction, 0);
56
+
57
+
sg_free_table(sg);
58
+
kfree(sg);
59
+
}
60
+
61
+
static void amdxdna_ubuf_release(struct dma_buf *dbuf)
62
+
{
63
+
struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
64
+
65
+
unpin_user_pages(ubuf->pages, ubuf->nr_pages);
66
+
kvfree(ubuf->pages);
67
+
atomic64_sub(ubuf->nr_pages, &ubuf->mm->pinned_vm);
68
+
mmdrop(ubuf->mm);
69
+
kfree(ubuf);
70
+
}
71
+
72
+
static vm_fault_t amdxdna_ubuf_vm_fault(struct vm_fault *vmf)
73
+
{
74
+
struct vm_area_struct *vma = vmf->vma;
75
+
struct amdxdna_ubuf_priv *ubuf;
76
+
unsigned long pfn;
77
+
pgoff_t pgoff;
78
+
79
+
ubuf = vma->vm_private_data;
80
+
pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
81
+
82
+
pfn = page_to_pfn(ubuf->pages[pgoff]);
83
+
return vmf_insert_pfn(vma, vmf->address, pfn);
84
+
}
85
+
86
+
static const struct vm_operations_struct amdxdna_ubuf_vm_ops = {
87
+
.fault = amdxdna_ubuf_vm_fault,
88
+
};
89
+
90
+
static int amdxdna_ubuf_mmap(struct dma_buf *dbuf, struct vm_area_struct *vma)
91
+
{
92
+
struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
93
+
94
+
vma->vm_ops = &amdxdna_ubuf_vm_ops;
95
+
vma->vm_private_data = ubuf;
96
+
vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP);
97
+
98
+
return 0;
99
+
}
100
+
101
+
static int amdxdna_ubuf_vmap(struct dma_buf *dbuf, struct iosys_map *map)
102
+
{
103
+
struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
104
+
void *kva;
105
+
106
+
kva = vmap(ubuf->pages, ubuf->nr_pages, VM_MAP, PAGE_KERNEL);
107
+
if (!kva)
108
+
return -EINVAL;
109
+
110
+
iosys_map_set_vaddr(map, kva);
111
+
return 0;
112
+
}
113
+
114
+
static void amdxdna_ubuf_vunmap(struct dma_buf *dbuf, struct iosys_map *map)
115
+
{
116
+
vunmap(map->vaddr);
117
+
}
118
+
119
+
static const struct dma_buf_ops amdxdna_ubuf_dmabuf_ops = {
120
+
.map_dma_buf = amdxdna_ubuf_map,
121
+
.unmap_dma_buf = amdxdna_ubuf_unmap,
122
+
.release = amdxdna_ubuf_release,
123
+
.mmap = amdxdna_ubuf_mmap,
124
+
.vmap = amdxdna_ubuf_vmap,
125
+
.vunmap = amdxdna_ubuf_vunmap,
126
+
};
127
+
128
+
struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev,
129
+
enum amdxdna_ubuf_flag flags,
130
+
u32 num_entries, void __user *va_entries)
131
+
{
132
+
struct amdxdna_dev *xdna = to_xdna_dev(dev);
133
+
unsigned long lock_limit, new_pinned;
134
+
struct amdxdna_drm_va_entry *va_ent;
135
+
struct amdxdna_ubuf_priv *ubuf;
136
+
u32 npages, start = 0;
137
+
struct dma_buf *dbuf;
138
+
int i, ret;
139
+
DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
140
+
141
+
if (!can_do_mlock())
142
+
return ERR_PTR(-EPERM);
143
+
144
+
ubuf = kzalloc(sizeof(*ubuf), GFP_KERNEL);
145
+
if (!ubuf)
146
+
return ERR_PTR(-ENOMEM);
147
+
148
+
ubuf->flags = flags;
149
+
ubuf->mm = current->mm;
150
+
mmgrab(ubuf->mm);
151
+
152
+
va_ent = kvcalloc(num_entries, sizeof(*va_ent), GFP_KERNEL);
153
+
if (!va_ent) {
154
+
ret = -ENOMEM;
155
+
goto free_ubuf;
156
+
}
157
+
158
+
if (copy_from_user(va_ent, va_entries, sizeof(*va_ent) * num_entries)) {
159
+
XDNA_DBG(xdna, "Access va entries failed");
160
+
ret = -EINVAL;
161
+
goto free_ent;
162
+
}
163
+
164
+
for (i = 0, exp_info.size = 0; i < num_entries; i++) {
165
+
if (!IS_ALIGNED(va_ent[i].vaddr, PAGE_SIZE) ||
166
+
!IS_ALIGNED(va_ent[i].len, PAGE_SIZE)) {
167
+
XDNA_ERR(xdna, "Invalid address or len %llx, %llx",
168
+
va_ent[i].vaddr, va_ent[i].len);
169
+
ret = -EINVAL;
170
+
goto free_ent;
171
+
}
172
+
173
+
exp_info.size += va_ent[i].len;
174
+
}
175
+
176
+
ubuf->nr_pages = exp_info.size >> PAGE_SHIFT;
177
+
lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
178
+
new_pinned = atomic64_add_return(ubuf->nr_pages, &ubuf->mm->pinned_vm);
179
+
if (new_pinned > lock_limit && !capable(CAP_IPC_LOCK)) {
180
+
XDNA_DBG(xdna, "New pin %ld, limit %ld, cap %d",
181
+
new_pinned, lock_limit, capable(CAP_IPC_LOCK));
182
+
ret = -ENOMEM;
183
+
goto sub_pin_cnt;
184
+
}
185
+
186
+
ubuf->pages = kvmalloc_array(ubuf->nr_pages, sizeof(*ubuf->pages), GFP_KERNEL);
187
+
if (!ubuf->pages) {
188
+
ret = -ENOMEM;
189
+
goto sub_pin_cnt;
190
+
}
191
+
192
+
for (i = 0; i < num_entries; i++) {
193
+
npages = va_ent[i].len >> PAGE_SHIFT;
194
+
195
+
ret = pin_user_pages_fast(va_ent[i].vaddr, npages,
196
+
FOLL_WRITE | FOLL_LONGTERM,
197
+
&ubuf->pages[start]);
198
+
if (ret < 0 || ret != npages) {
199
+
ret = -ENOMEM;
200
+
XDNA_ERR(xdna, "Failed to pin pages ret %d", ret);
201
+
goto destroy_pages;
202
+
}
203
+
204
+
start += ret;
205
+
}
206
+
207
+
exp_info.ops = &amdxdna_ubuf_dmabuf_ops;
208
+
exp_info.priv = ubuf;
209
+
exp_info.flags = O_RDWR | O_CLOEXEC;
210
+
211
+
dbuf = dma_buf_export(&exp_info);
212
+
if (IS_ERR(dbuf)) {
213
+
ret = PTR_ERR(dbuf);
214
+
goto destroy_pages;
215
+
}
216
+
kvfree(va_ent);
217
+
218
+
return dbuf;
219
+
220
+
destroy_pages:
221
+
if (start)
222
+
unpin_user_pages(ubuf->pages, start);
223
+
kvfree(ubuf->pages);
224
+
sub_pin_cnt:
225
+
atomic64_sub(ubuf->nr_pages, &ubuf->mm->pinned_vm);
226
+
free_ent:
227
+
kvfree(va_ent);
228
+
free_ubuf:
229
+
mmdrop(ubuf->mm);
230
+
kfree(ubuf);
231
+
return ERR_PTR(ret);
232
+
}
+19
drivers/accel/amdxdna/amdxdna_ubuf.h
+19
drivers/accel/amdxdna/amdxdna_ubuf.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2025, Advanced Micro Devices, Inc.
4
+
*/
5
+
#ifndef _AMDXDNA_UBUF_H_
6
+
#define _AMDXDNA_UBUF_H_
7
+
8
+
#include <drm/drm_device.h>
9
+
#include <linux/dma-buf.h>
10
+
11
+
enum amdxdna_ubuf_flag {
12
+
AMDXDNA_UBUF_FLAG_MAP_DMA = 1,
13
+
};
14
+
15
+
struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev,
16
+
enum amdxdna_ubuf_flag flags,
17
+
u32 num_entries, void __user *va_entries);
18
+
19
+
#endif /* _AMDXDNA_UBUF_H_ */
-1
drivers/accel/ivpu/ivpu_ipc.c
-1
drivers/accel/ivpu/ivpu_ipc.c
+24
drivers/accel/rocket/Kconfig
+24
drivers/accel/rocket/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config DRM_ACCEL_ROCKET
4
+
tristate "Rocket (support for Rockchip NPUs)"
5
+
depends on DRM
6
+
depends on (ARCH_ROCKCHIP && ARM64) || COMPILE_TEST
7
+
depends on ROCKCHIP_IOMMU || COMPILE_TEST
8
+
depends on MMU
9
+
select DRM_SCHED
10
+
select DRM_GEM_SHMEM_HELPER
11
+
help
12
+
Choose this option if you have a Rockchip SoC that contains a
13
+
compatible Neural Processing Unit (NPU), such as the RK3588. Called by
14
+
Rockchip either RKNN or RKNPU, it accelerates inference of neural
15
+
networks.
16
+
17
+
The interface exposed to userspace is described in
18
+
include/uapi/drm/rocket_accel.h and is used by the Rocket userspace
19
+
driver in Mesa3D.
20
+
21
+
If unsure, say N.
22
+
23
+
To compile this driver as a module, choose M here: the
24
+
module will be called rocket.
+10
drivers/accel/rocket/Makefile
+10
drivers/accel/rocket/Makefile
+110
drivers/accel/rocket/rocket_core.c
+110
drivers/accel/rocket/rocket_core.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#include <linux/clk.h>
5
+
#include <linux/delay.h>
6
+
#include <linux/dev_printk.h>
7
+
#include <linux/dma-mapping.h>
8
+
#include <linux/err.h>
9
+
#include <linux/iommu.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/pm_runtime.h>
12
+
#include <linux/reset.h>
13
+
14
+
#include "rocket_core.h"
15
+
#include "rocket_job.h"
16
+
17
+
int rocket_core_init(struct rocket_core *core)
18
+
{
19
+
struct device *dev = core->dev;
20
+
struct platform_device *pdev = to_platform_device(dev);
21
+
u32 version;
22
+
int err = 0;
23
+
24
+
core->resets[0].id = "srst_a";
25
+
core->resets[1].id = "srst_h";
26
+
err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
27
+
core->resets);
28
+
if (err)
29
+
return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
30
+
31
+
err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
32
+
if (err)
33
+
return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
34
+
35
+
core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc");
36
+
if (IS_ERR(core->pc_iomem)) {
37
+
dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem));
38
+
return PTR_ERR(core->pc_iomem);
39
+
}
40
+
41
+
core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna");
42
+
if (IS_ERR(core->cna_iomem)) {
43
+
dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem));
44
+
return PTR_ERR(core->cna_iomem);
45
+
}
46
+
47
+
core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core");
48
+
if (IS_ERR(core->core_iomem)) {
49
+
dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem));
50
+
return PTR_ERR(core->core_iomem);
51
+
}
52
+
53
+
dma_set_max_seg_size(dev, UINT_MAX);
54
+
55
+
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
56
+
if (err)
57
+
return err;
58
+
59
+
core->iommu_group = iommu_group_get(dev);
60
+
61
+
err = rocket_job_init(core);
62
+
if (err)
63
+
return err;
64
+
65
+
pm_runtime_use_autosuspend(dev);
66
+
67
+
/*
68
+
* As this NPU will be most often used as part of a media pipeline that
69
+
* ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an
70
+
* autosuspend delay as that will keep the device powered up while the
71
+
* pipeline is running.
72
+
*/
73
+
pm_runtime_set_autosuspend_delay(dev, 50);
74
+
75
+
pm_runtime_enable(dev);
76
+
77
+
err = pm_runtime_get_sync(dev);
78
+
if (err) {
79
+
rocket_job_fini(core);
80
+
return err;
81
+
}
82
+
83
+
version = rocket_pc_readl(core, VERSION);
84
+
version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
85
+
86
+
pm_runtime_mark_last_busy(dev);
87
+
pm_runtime_put_autosuspend(dev);
88
+
89
+
dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
90
+
91
+
return 0;
92
+
}
93
+
94
+
void rocket_core_fini(struct rocket_core *core)
95
+
{
96
+
pm_runtime_dont_use_autosuspend(core->dev);
97
+
pm_runtime_disable(core->dev);
98
+
iommu_group_put(core->iommu_group);
99
+
core->iommu_group = NULL;
100
+
rocket_job_fini(core);
101
+
}
102
+
103
+
void rocket_core_reset(struct rocket_core *core)
104
+
{
105
+
reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
106
+
107
+
udelay(10);
108
+
109
+
reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
110
+
}
+64
drivers/accel/rocket/rocket_core.h
+64
drivers/accel/rocket/rocket_core.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#ifndef __ROCKET_CORE_H__
5
+
#define __ROCKET_CORE_H__
6
+
7
+
#include <drm/gpu_scheduler.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/io.h>
10
+
#include <linux/mutex_types.h>
11
+
#include <linux/reset.h>
12
+
13
+
#include "rocket_registers.h"
14
+
15
+
#define rocket_pc_readl(core, reg) \
16
+
readl((core)->pc_iomem + (REG_PC_##reg))
17
+
#define rocket_pc_writel(core, reg, value) \
18
+
writel(value, (core)->pc_iomem + (REG_PC_##reg))
19
+
20
+
#define rocket_cna_readl(core, reg) \
21
+
readl((core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
22
+
#define rocket_cna_writel(core, reg, value) \
23
+
writel(value, (core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
24
+
25
+
#define rocket_core_readl(core, reg) \
26
+
readl((core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
27
+
#define rocket_core_writel(core, reg, value) \
28
+
writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
29
+
30
+
struct rocket_core {
31
+
struct device *dev;
32
+
struct rocket_device *rdev;
33
+
unsigned int index;
34
+
35
+
int irq;
36
+
void __iomem *pc_iomem;
37
+
void __iomem *cna_iomem;
38
+
void __iomem *core_iomem;
39
+
struct clk_bulk_data clks[4];
40
+
struct reset_control_bulk_data resets[2];
41
+
42
+
struct iommu_group *iommu_group;
43
+
44
+
struct mutex job_lock;
45
+
struct rocket_job *in_flight_job;
46
+
47
+
spinlock_t fence_lock;
48
+
49
+
struct {
50
+
struct workqueue_struct *wq;
51
+
struct work_struct work;
52
+
atomic_t pending;
53
+
} reset;
54
+
55
+
struct drm_gpu_scheduler sched;
56
+
u64 fence_context;
57
+
u64 emit_seqno;
58
+
};
59
+
60
+
int rocket_core_init(struct rocket_core *core);
61
+
void rocket_core_fini(struct rocket_core *core);
62
+
void rocket_core_reset(struct rocket_core *core);
63
+
64
+
#endif
+60
drivers/accel/rocket/rocket_device.c
+60
drivers/accel/rocket/rocket_device.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#include <drm/drm_drv.h>
5
+
#include <linux/array_size.h>
6
+
#include <linux/clk.h>
7
+
#include <linux/dma-mapping.h>
8
+
#include <linux/platform_device.h>
9
+
#include <linux/of.h>
10
+
11
+
#include "rocket_device.h"
12
+
13
+
struct rocket_device *rocket_device_init(struct platform_device *pdev,
14
+
const struct drm_driver *rocket_drm_driver)
15
+
{
16
+
struct device *dev = &pdev->dev;
17
+
struct device_node *core_node;
18
+
struct rocket_device *rdev;
19
+
struct drm_device *ddev;
20
+
unsigned int num_cores = 0;
21
+
int err;
22
+
23
+
rdev = devm_drm_dev_alloc(dev, rocket_drm_driver, struct rocket_device, ddev);
24
+
if (IS_ERR(rdev))
25
+
return rdev;
26
+
27
+
ddev = &rdev->ddev;
28
+
dev_set_drvdata(dev, rdev);
29
+
30
+
for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
31
+
if (of_device_is_available(core_node))
32
+
num_cores++;
33
+
34
+
rdev->cores = devm_kcalloc(dev, num_cores, sizeof(*rdev->cores), GFP_KERNEL);
35
+
if (!rdev->cores)
36
+
return ERR_PTR(-ENOMEM);
37
+
38
+
dma_set_max_seg_size(dev, UINT_MAX);
39
+
40
+
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
41
+
if (err)
42
+
return ERR_PTR(err);
43
+
44
+
err = devm_mutex_init(dev, &rdev->sched_lock);
45
+
if (err)
46
+
return ERR_PTR(-ENOMEM);
47
+
48
+
err = drm_dev_register(ddev, 0);
49
+
if (err)
50
+
return ERR_PTR(err);
51
+
52
+
return rdev;
53
+
}
54
+
55
+
void rocket_device_fini(struct rocket_device *rdev)
56
+
{
57
+
WARN_ON(rdev->num_cores > 0);
58
+
59
+
drm_dev_unregister(&rdev->ddev);
60
+
}
+30
drivers/accel/rocket/rocket_device.h
+30
drivers/accel/rocket/rocket_device.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#ifndef __ROCKET_DEVICE_H__
5
+
#define __ROCKET_DEVICE_H__
6
+
7
+
#include <drm/drm_device.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/container_of.h>
10
+
#include <linux/iommu.h>
11
+
#include <linux/platform_device.h>
12
+
13
+
#include "rocket_core.h"
14
+
15
+
struct rocket_device {
16
+
struct drm_device ddev;
17
+
18
+
struct mutex sched_lock;
19
+
20
+
struct rocket_core *cores;
21
+
unsigned int num_cores;
22
+
};
23
+
24
+
struct rocket_device *rocket_device_init(struct platform_device *pdev,
25
+
const struct drm_driver *rocket_drm_driver);
26
+
void rocket_device_fini(struct rocket_device *rdev);
27
+
#define to_rocket_device(drm_dev) \
28
+
((struct rocket_device *)(container_of((drm_dev), struct rocket_device, ddev)))
29
+
30
+
#endif /* __ROCKET_DEVICE_H__ */
+290
drivers/accel/rocket/rocket_drv.c
+290
drivers/accel/rocket/rocket_drv.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#include <drm/drm_accel.h>
5
+
#include <drm/drm_drv.h>
6
+
#include <drm/drm_gem.h>
7
+
#include <drm/drm_ioctl.h>
8
+
#include <drm/rocket_accel.h>
9
+
#include <linux/clk.h>
10
+
#include <linux/err.h>
11
+
#include <linux/iommu.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/pm_runtime.h>
15
+
16
+
#include "rocket_drv.h"
17
+
#include "rocket_gem.h"
18
+
#include "rocket_job.h"
19
+
20
+
/*
21
+
* Facade device, used to expose a single DRM device to userspace, that
22
+
* schedules jobs to any RKNN cores in the system.
23
+
*/
24
+
static struct platform_device *drm_dev;
25
+
static struct rocket_device *rdev;
26
+
27
+
static void
28
+
rocket_iommu_domain_destroy(struct kref *kref)
29
+
{
30
+
struct rocket_iommu_domain *domain = container_of(kref, struct rocket_iommu_domain, kref);
31
+
32
+
iommu_domain_free(domain->domain);
33
+
domain->domain = NULL;
34
+
kfree(domain);
35
+
}
36
+
37
+
static struct rocket_iommu_domain*
38
+
rocket_iommu_domain_create(struct device *dev)
39
+
{
40
+
struct rocket_iommu_domain *domain = kmalloc(sizeof(*domain), GFP_KERNEL);
41
+
void *err;
42
+
43
+
if (!domain)
44
+
return ERR_PTR(-ENOMEM);
45
+
46
+
domain->domain = iommu_paging_domain_alloc(dev);
47
+
if (IS_ERR(domain->domain)) {
48
+
err = ERR_CAST(domain->domain);
49
+
kfree(domain);
50
+
return err;
51
+
}
52
+
kref_init(&domain->kref);
53
+
54
+
return domain;
55
+
}
56
+
57
+
struct rocket_iommu_domain *
58
+
rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv)
59
+
{
60
+
kref_get(&rocket_priv->domain->kref);
61
+
return rocket_priv->domain;
62
+
}
63
+
64
+
void
65
+
rocket_iommu_domain_put(struct rocket_iommu_domain *domain)
66
+
{
67
+
kref_put(&domain->kref, rocket_iommu_domain_destroy);
68
+
}
69
+
70
+
static int
71
+
rocket_open(struct drm_device *dev, struct drm_file *file)
72
+
{
73
+
struct rocket_device *rdev = to_rocket_device(dev);
74
+
struct rocket_file_priv *rocket_priv;
75
+
u64 start, end;
76
+
int ret;
77
+
78
+
if (!try_module_get(THIS_MODULE))
79
+
return -EINVAL;
80
+
81
+
rocket_priv = kzalloc(sizeof(*rocket_priv), GFP_KERNEL);
82
+
if (!rocket_priv) {
83
+
ret = -ENOMEM;
84
+
goto err_put_mod;
85
+
}
86
+
87
+
rocket_priv->rdev = rdev;
88
+
rocket_priv->domain = rocket_iommu_domain_create(rdev->cores[0].dev);
89
+
if (IS_ERR(rocket_priv->domain)) {
90
+
ret = PTR_ERR(rocket_priv->domain);
91
+
goto err_free;
92
+
}
93
+
94
+
file->driver_priv = rocket_priv;
95
+
96
+
start = rocket_priv->domain->domain->geometry.aperture_start;
97
+
end = rocket_priv->domain->domain->geometry.aperture_end;
98
+
drm_mm_init(&rocket_priv->mm, start, end - start + 1);
99
+
mutex_init(&rocket_priv->mm_lock);
100
+
101
+
ret = rocket_job_open(rocket_priv);
102
+
if (ret)
103
+
goto err_mm_takedown;
104
+
105
+
return 0;
106
+
107
+
err_mm_takedown:
108
+
mutex_destroy(&rocket_priv->mm_lock);
109
+
drm_mm_takedown(&rocket_priv->mm);
110
+
rocket_iommu_domain_put(rocket_priv->domain);
111
+
err_free:
112
+
kfree(rocket_priv);
113
+
err_put_mod:
114
+
module_put(THIS_MODULE);
115
+
return ret;
116
+
}
117
+
118
+
static void
119
+
rocket_postclose(struct drm_device *dev, struct drm_file *file)
120
+
{
121
+
struct rocket_file_priv *rocket_priv = file->driver_priv;
122
+
123
+
rocket_job_close(rocket_priv);
124
+
mutex_destroy(&rocket_priv->mm_lock);
125
+
drm_mm_takedown(&rocket_priv->mm);
126
+
rocket_iommu_domain_put(rocket_priv->domain);
127
+
kfree(rocket_priv);
128
+
module_put(THIS_MODULE);
129
+
}
130
+
131
+
static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
132
+
#define ROCKET_IOCTL(n, func) \
133
+
DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
134
+
135
+
ROCKET_IOCTL(CREATE_BO, create_bo),
136
+
ROCKET_IOCTL(SUBMIT, submit),
137
+
ROCKET_IOCTL(PREP_BO, prep_bo),
138
+
ROCKET_IOCTL(FINI_BO, fini_bo),
139
+
};
140
+
141
+
DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
142
+
143
+
/*
144
+
* Rocket driver version:
145
+
* - 1.0 - initial interface
146
+
*/
147
+
static const struct drm_driver rocket_drm_driver = {
148
+
.driver_features = DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
149
+
.open = rocket_open,
150
+
.postclose = rocket_postclose,
151
+
.gem_create_object = rocket_gem_create_object,
152
+
.ioctls = rocket_drm_driver_ioctls,
153
+
.num_ioctls = ARRAY_SIZE(rocket_drm_driver_ioctls),
154
+
.fops = &rocket_accel_driver_fops,
155
+
.name = "rocket",
156
+
.desc = "rocket DRM",
157
+
};
158
+
159
+
static int rocket_probe(struct platform_device *pdev)
160
+
{
161
+
if (rdev == NULL) {
162
+
/* First core probing, initialize DRM device. */
163
+
rdev = rocket_device_init(drm_dev, &rocket_drm_driver);
164
+
if (IS_ERR(rdev)) {
165
+
dev_err(&pdev->dev, "failed to initialize rocket device\n");
166
+
return PTR_ERR(rdev);
167
+
}
168
+
}
169
+
170
+
unsigned int core = rdev->num_cores;
171
+
172
+
dev_set_drvdata(&pdev->dev, rdev);
173
+
174
+
rdev->cores[core].rdev = rdev;
175
+
rdev->cores[core].dev = &pdev->dev;
176
+
rdev->cores[core].index = core;
177
+
178
+
rdev->num_cores++;
179
+
180
+
return rocket_core_init(&rdev->cores[core]);
181
+
}
182
+
183
+
static void rocket_remove(struct platform_device *pdev)
184
+
{
185
+
struct device *dev = &pdev->dev;
186
+
187
+
for (unsigned int core = 0; core < rdev->num_cores; core++) {
188
+
if (rdev->cores[core].dev == dev) {
189
+
rocket_core_fini(&rdev->cores[core]);
190
+
rdev->num_cores--;
191
+
break;
192
+
}
193
+
}
194
+
195
+
if (rdev->num_cores == 0) {
196
+
/* Last core removed, deinitialize DRM device. */
197
+
rocket_device_fini(rdev);
198
+
rdev = NULL;
199
+
}
200
+
}
201
+
202
+
static const struct of_device_id dt_match[] = {
203
+
{ .compatible = "rockchip,rk3588-rknn-core" },
204
+
{}
205
+
};
206
+
MODULE_DEVICE_TABLE(of, dt_match);
207
+
208
+
static int find_core_for_dev(struct device *dev)
209
+
{
210
+
struct rocket_device *rdev = dev_get_drvdata(dev);
211
+
212
+
for (unsigned int core = 0; core < rdev->num_cores; core++) {
213
+
if (dev == rdev->cores[core].dev)
214
+
return core;
215
+
}
216
+
217
+
return -1;
218
+
}
219
+
220
+
static int rocket_device_runtime_resume(struct device *dev)
221
+
{
222
+
struct rocket_device *rdev = dev_get_drvdata(dev);
223
+
int core = find_core_for_dev(dev);
224
+
int err = 0;
225
+
226
+
if (core < 0)
227
+
return -ENODEV;
228
+
229
+
err = clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
230
+
if (err) {
231
+
dev_err(dev, "failed to enable (%d) clocks for core %d\n", err, core);
232
+
return err;
233
+
}
234
+
235
+
return 0;
236
+
}
237
+
238
+
static int rocket_device_runtime_suspend(struct device *dev)
239
+
{
240
+
struct rocket_device *rdev = dev_get_drvdata(dev);
241
+
int core = find_core_for_dev(dev);
242
+
243
+
if (core < 0)
244
+
return -ENODEV;
245
+
246
+
if (!rocket_job_is_idle(&rdev->cores[core]))
247
+
return -EBUSY;
248
+
249
+
clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
250
+
251
+
return 0;
252
+
}
253
+
254
+
EXPORT_GPL_DEV_PM_OPS(rocket_pm_ops) = {
255
+
RUNTIME_PM_OPS(rocket_device_runtime_suspend, rocket_device_runtime_resume, NULL)
256
+
SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
257
+
};
258
+
259
+
static struct platform_driver rocket_driver = {
260
+
.probe = rocket_probe,
261
+
.remove = rocket_remove,
262
+
.driver = {
263
+
.name = "rocket",
264
+
.pm = pm_ptr(&rocket_pm_ops),
265
+
.of_match_table = dt_match,
266
+
},
267
+
};
268
+
269
+
static int __init rocket_register(void)
270
+
{
271
+
drm_dev = platform_device_register_simple("rknn", -1, NULL, 0);
272
+
if (IS_ERR(drm_dev))
273
+
return PTR_ERR(drm_dev);
274
+
275
+
return platform_driver_register(&rocket_driver);
276
+
}
277
+
278
+
static void __exit rocket_unregister(void)
279
+
{
280
+
platform_driver_unregister(&rocket_driver);
281
+
282
+
platform_device_unregister(drm_dev);
283
+
}
284
+
285
+
module_init(rocket_register);
286
+
module_exit(rocket_unregister);
287
+
288
+
MODULE_LICENSE("GPL");
289
+
MODULE_DESCRIPTION("DRM driver for the Rockchip NPU IP");
290
+
MODULE_AUTHOR("Tomeu Vizoso");
+32
drivers/accel/rocket/rocket_drv.h
+32
drivers/accel/rocket/rocket_drv.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#ifndef __ROCKET_DRV_H__
5
+
#define __ROCKET_DRV_H__
6
+
7
+
#include <drm/drm_mm.h>
8
+
#include <drm/gpu_scheduler.h>
9
+
10
+
#include "rocket_device.h"
11
+
12
+
extern const struct dev_pm_ops rocket_pm_ops;
13
+
14
+
struct rocket_iommu_domain {
15
+
struct iommu_domain *domain;
16
+
struct kref kref;
17
+
};
18
+
19
+
struct rocket_file_priv {
20
+
struct rocket_device *rdev;
21
+
22
+
struct rocket_iommu_domain *domain;
23
+
struct drm_mm mm;
24
+
struct mutex mm_lock;
25
+
26
+
struct drm_sched_entity sched_entity;
27
+
};
28
+
29
+
struct rocket_iommu_domain *rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv);
30
+
void rocket_iommu_domain_put(struct rocket_iommu_domain *domain);
31
+
32
+
#endif
+181
drivers/accel/rocket/rocket_gem.c
+181
drivers/accel/rocket/rocket_gem.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#include <drm/drm_device.h>
5
+
#include <drm/drm_utils.h>
6
+
#include <drm/rocket_accel.h>
7
+
#include <linux/dma-mapping.h>
8
+
#include <linux/iommu.h>
9
+
10
+
#include "rocket_drv.h"
11
+
#include "rocket_gem.h"
12
+
13
+
static void rocket_gem_bo_free(struct drm_gem_object *obj)
14
+
{
15
+
struct rocket_gem_object *bo = to_rocket_bo(obj);
16
+
struct rocket_file_priv *rocket_priv = bo->driver_priv;
17
+
size_t unmapped;
18
+
19
+
drm_WARN_ON(obj->dev, refcount_read(&bo->base.pages_use_count) > 1);
20
+
21
+
unmapped = iommu_unmap(bo->domain->domain, bo->mm.start, bo->size);
22
+
drm_WARN_ON(obj->dev, unmapped != bo->size);
23
+
24
+
mutex_lock(&rocket_priv->mm_lock);
25
+
drm_mm_remove_node(&bo->mm);
26
+
mutex_unlock(&rocket_priv->mm_lock);
27
+
28
+
rocket_iommu_domain_put(bo->domain);
29
+
bo->domain = NULL;
30
+
31
+
drm_gem_shmem_free(&bo->base);
32
+
}
33
+
34
+
static const struct drm_gem_object_funcs rocket_gem_funcs = {
35
+
.free = rocket_gem_bo_free,
36
+
.print_info = drm_gem_shmem_object_print_info,
37
+
.pin = drm_gem_shmem_object_pin,
38
+
.unpin = drm_gem_shmem_object_unpin,
39
+
.get_sg_table = drm_gem_shmem_object_get_sg_table,
40
+
.vmap = drm_gem_shmem_object_vmap,
41
+
.vunmap = drm_gem_shmem_object_vunmap,
42
+
.mmap = drm_gem_shmem_object_mmap,
43
+
.vm_ops = &drm_gem_shmem_vm_ops,
44
+
};
45
+
46
+
struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size)
47
+
{
48
+
struct rocket_gem_object *obj;
49
+
50
+
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
51
+
if (!obj)
52
+
return ERR_PTR(-ENOMEM);
53
+
54
+
obj->base.base.funcs = &rocket_gem_funcs;
55
+
56
+
return &obj->base.base;
57
+
}
58
+
59
+
int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file)
60
+
{
61
+
struct rocket_file_priv *rocket_priv = file->driver_priv;
62
+
struct drm_rocket_create_bo *args = data;
63
+
struct drm_gem_shmem_object *shmem_obj;
64
+
struct rocket_gem_object *rkt_obj;
65
+
struct drm_gem_object *gem_obj;
66
+
struct sg_table *sgt;
67
+
int ret;
68
+
69
+
shmem_obj = drm_gem_shmem_create(dev, args->size);
70
+
if (IS_ERR(shmem_obj))
71
+
return PTR_ERR(shmem_obj);
72
+
73
+
gem_obj = &shmem_obj->base;
74
+
rkt_obj = to_rocket_bo(gem_obj);
75
+
76
+
rkt_obj->driver_priv = rocket_priv;
77
+
rkt_obj->domain = rocket_iommu_domain_get(rocket_priv);
78
+
rkt_obj->size = args->size;
79
+
rkt_obj->offset = 0;
80
+
81
+
ret = drm_gem_handle_create(file, gem_obj, &args->handle);
82
+
drm_gem_object_put(gem_obj);
83
+
if (ret)
84
+
goto err;
85
+
86
+
sgt = drm_gem_shmem_get_pages_sgt(shmem_obj);
87
+
if (IS_ERR(sgt)) {
88
+
ret = PTR_ERR(sgt);
89
+
goto err;
90
+
}
91
+
92
+
mutex_lock(&rocket_priv->mm_lock);
93
+
ret = drm_mm_insert_node_generic(&rocket_priv->mm, &rkt_obj->mm,
94
+
rkt_obj->size, PAGE_SIZE,
95
+
0, 0);
96
+
mutex_unlock(&rocket_priv->mm_lock);
97
+
98
+
ret = iommu_map_sgtable(rocket_priv->domain->domain,
99
+
rkt_obj->mm.start,
100
+
shmem_obj->sgt,
101
+
IOMMU_READ | IOMMU_WRITE);
102
+
if (ret < 0 || ret < args->size) {
103
+
drm_err(dev, "failed to map buffer: size=%d request_size=%u\n",
104
+
ret, args->size);
105
+
ret = -ENOMEM;
106
+
goto err_remove_node;
107
+
}
108
+
109
+
/* iommu_map_sgtable might have aligned the size */
110
+
rkt_obj->size = ret;
111
+
args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
112
+
args->dma_address = rkt_obj->mm.start;
113
+
114
+
return 0;
115
+
116
+
err_remove_node:
117
+
mutex_lock(&rocket_priv->mm_lock);
118
+
drm_mm_remove_node(&rkt_obj->mm);
119
+
mutex_unlock(&rocket_priv->mm_lock);
120
+
121
+
err:
122
+
drm_gem_shmem_object_free(gem_obj);
123
+
124
+
return ret;
125
+
}
126
+
127
+
int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file)
128
+
{
129
+
struct drm_rocket_prep_bo *args = data;
130
+
unsigned long timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
131
+
struct drm_gem_object *gem_obj;
132
+
struct drm_gem_shmem_object *shmem_obj;
133
+
long ret = 0;
134
+
135
+
if (args->reserved != 0) {
136
+
drm_dbg(dev, "Reserved field in drm_rocket_prep_bo struct should be 0.\n");
137
+
return -EINVAL;
138
+
}
139
+
140
+
gem_obj = drm_gem_object_lookup(file, args->handle);
141
+
if (!gem_obj)
142
+
return -ENOENT;
143
+
144
+
ret = dma_resv_wait_timeout(gem_obj->resv, DMA_RESV_USAGE_WRITE, true, timeout);
145
+
if (!ret)
146
+
ret = timeout ? -ETIMEDOUT : -EBUSY;
147
+
148
+
shmem_obj = &to_rocket_bo(gem_obj)->base;
149
+
150
+
dma_sync_sgtable_for_cpu(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
151
+
152
+
drm_gem_object_put(gem_obj);
153
+
154
+
return ret;
155
+
}
156
+
157
+
int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file)
158
+
{
159
+
struct drm_rocket_fini_bo *args = data;
160
+
struct drm_gem_shmem_object *shmem_obj;
161
+
struct rocket_gem_object *rkt_obj;
162
+
struct drm_gem_object *gem_obj;
163
+
164
+
if (args->reserved != 0) {
165
+
drm_dbg(dev, "Reserved field in drm_rocket_fini_bo struct should be 0.\n");
166
+
return -EINVAL;
167
+
}
168
+
169
+
gem_obj = drm_gem_object_lookup(file, args->handle);
170
+
if (!gem_obj)
171
+
return -ENOENT;
172
+
173
+
rkt_obj = to_rocket_bo(gem_obj);
174
+
shmem_obj = &rkt_obj->base;
175
+
176
+
dma_sync_sgtable_for_device(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
177
+
178
+
drm_gem_object_put(gem_obj);
179
+
180
+
return 0;
181
+
}
+34
drivers/accel/rocket/rocket_gem.h
+34
drivers/accel/rocket/rocket_gem.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#ifndef __ROCKET_GEM_H__
5
+
#define __ROCKET_GEM_H__
6
+
7
+
#include <drm/drm_gem_shmem_helper.h>
8
+
9
+
struct rocket_gem_object {
10
+
struct drm_gem_shmem_object base;
11
+
12
+
struct rocket_file_priv *driver_priv;
13
+
14
+
struct rocket_iommu_domain *domain;
15
+
struct drm_mm_node mm;
16
+
size_t size;
17
+
u32 offset;
18
+
};
19
+
20
+
struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size);
21
+
22
+
int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
23
+
24
+
int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file);
25
+
26
+
int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file);
27
+
28
+
static inline
29
+
struct rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
30
+
{
31
+
return container_of(to_drm_gem_shmem_obj(obj), struct rocket_gem_object, base);
32
+
}
33
+
34
+
#endif
+636
drivers/accel/rocket/rocket_job.c
+636
drivers/accel/rocket/rocket_job.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
3
+
/* Copyright 2019 Collabora ltd. */
4
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
5
+
6
+
#include <drm/drm_print.h>
7
+
#include <drm/drm_file.h>
8
+
#include <drm/drm_gem.h>
9
+
#include <drm/rocket_accel.h>
10
+
#include <linux/interrupt.h>
11
+
#include <linux/iommu.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/pm_runtime.h>
14
+
15
+
#include "rocket_core.h"
16
+
#include "rocket_device.h"
17
+
#include "rocket_drv.h"
18
+
#include "rocket_job.h"
19
+
#include "rocket_registers.h"
20
+
21
+
#define JOB_TIMEOUT_MS 500
22
+
23
+
static struct rocket_job *
24
+
to_rocket_job(struct drm_sched_job *sched_job)
25
+
{
26
+
return container_of(sched_job, struct rocket_job, base);
27
+
}
28
+
29
+
static const char *rocket_fence_get_driver_name(struct dma_fence *fence)
30
+
{
31
+
return "rocket";
32
+
}
33
+
34
+
static const char *rocket_fence_get_timeline_name(struct dma_fence *fence)
35
+
{
36
+
return "rockchip-npu";
37
+
}
38
+
39
+
static const struct dma_fence_ops rocket_fence_ops = {
40
+
.get_driver_name = rocket_fence_get_driver_name,
41
+
.get_timeline_name = rocket_fence_get_timeline_name,
42
+
};
43
+
44
+
static struct dma_fence *rocket_fence_create(struct rocket_core *core)
45
+
{
46
+
struct dma_fence *fence;
47
+
48
+
fence = kzalloc(sizeof(*fence), GFP_KERNEL);
49
+
if (!fence)
50
+
return ERR_PTR(-ENOMEM);
51
+
52
+
dma_fence_init(fence, &rocket_fence_ops, &core->fence_lock,
53
+
core->fence_context, ++core->emit_seqno);
54
+
55
+
return fence;
56
+
}
57
+
58
+
static int
59
+
rocket_copy_tasks(struct drm_device *dev,
60
+
struct drm_file *file_priv,
61
+
struct drm_rocket_job *job,
62
+
struct rocket_job *rjob)
63
+
{
64
+
int ret = 0;
65
+
66
+
if (job->task_struct_size < sizeof(struct drm_rocket_task))
67
+
return -EINVAL;
68
+
69
+
rjob->task_count = job->task_count;
70
+
71
+
if (!rjob->task_count)
72
+
return 0;
73
+
74
+
rjob->tasks = kvmalloc_array(job->task_count, sizeof(*rjob->tasks), GFP_KERNEL);
75
+
if (!rjob->tasks) {
76
+
drm_dbg(dev, "Failed to allocate task array\n");
77
+
return -ENOMEM;
78
+
}
79
+
80
+
for (int i = 0; i < rjob->task_count; i++) {
81
+
struct drm_rocket_task task = {0};
82
+
83
+
if (copy_from_user(&task,
84
+
u64_to_user_ptr(job->tasks) + i * job->task_struct_size,
85
+
sizeof(task))) {
86
+
drm_dbg(dev, "Failed to copy incoming tasks\n");
87
+
ret = -EFAULT;
88
+
goto fail;
89
+
}
90
+
91
+
if (task.regcmd_count == 0) {
92
+
drm_dbg(dev, "regcmd_count field in drm_rocket_task should be > 0.\n");
93
+
ret = -EINVAL;
94
+
goto fail;
95
+
}
96
+
97
+
rjob->tasks[i].regcmd = task.regcmd;
98
+
rjob->tasks[i].regcmd_count = task.regcmd_count;
99
+
}
100
+
101
+
return 0;
102
+
103
+
fail:
104
+
kvfree(rjob->tasks);
105
+
return ret;
106
+
}
107
+
108
+
static void rocket_job_hw_submit(struct rocket_core *core, struct rocket_job *job)
109
+
{
110
+
struct rocket_task *task;
111
+
unsigned int extra_bit;
112
+
113
+
/* Don't queue the job if a reset is in progress */
114
+
if (atomic_read(&core->reset.pending))
115
+
return;
116
+
117
+
/* GO ! */
118
+
119
+
task = &job->tasks[job->next_task_idx];
120
+
job->next_task_idx++;
121
+
122
+
rocket_pc_writel(core, BASE_ADDRESS, 0x1);
123
+
124
+
/* From rknpu, in the TRM this bit is marked as reserved */
125
+
extra_bit = 0x10000000 * core->index;
126
+
rocket_cna_writel(core, S_POINTER, CNA_S_POINTER_POINTER_PP_EN(1) |
127
+
CNA_S_POINTER_EXECUTER_PP_EN(1) |
128
+
CNA_S_POINTER_POINTER_PP_MODE(1) |
129
+
extra_bit);
130
+
131
+
rocket_core_writel(core, S_POINTER, CORE_S_POINTER_POINTER_PP_EN(1) |
132
+
CORE_S_POINTER_EXECUTER_PP_EN(1) |
133
+
CORE_S_POINTER_POINTER_PP_MODE(1) |
134
+
extra_bit);
135
+
136
+
rocket_pc_writel(core, BASE_ADDRESS, task->regcmd);
137
+
rocket_pc_writel(core, REGISTER_AMOUNTS,
138
+
PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT((task->regcmd_count + 1) / 2 - 1));
139
+
140
+
rocket_pc_writel(core, INTERRUPT_MASK, PC_INTERRUPT_MASK_DPU_0 | PC_INTERRUPT_MASK_DPU_1);
141
+
rocket_pc_writel(core, INTERRUPT_CLEAR, PC_INTERRUPT_CLEAR_DPU_0 | PC_INTERRUPT_CLEAR_DPU_1);
142
+
143
+
rocket_pc_writel(core, TASK_CON, PC_TASK_CON_RESERVED_0(1) |
144
+
PC_TASK_CON_TASK_COUNT_CLEAR(1) |
145
+
PC_TASK_CON_TASK_NUMBER(1) |
146
+
PC_TASK_CON_TASK_PP_EN(1));
147
+
148
+
rocket_pc_writel(core, TASK_DMA_BASE_ADDR, PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(0x0));
149
+
150
+
rocket_pc_writel(core, OPERATION_ENABLE, PC_OPERATION_ENABLE_OP_EN(1));
151
+
152
+
dev_dbg(core->dev, "Submitted regcmd at 0x%llx to core %d", task->regcmd, core->index);
153
+
}
154
+
155
+
static int rocket_acquire_object_fences(struct drm_gem_object **bos,
156
+
int bo_count,
157
+
struct drm_sched_job *job,
158
+
bool is_write)
159
+
{
160
+
int i, ret;
161
+
162
+
for (i = 0; i < bo_count; i++) {
163
+
ret = dma_resv_reserve_fences(bos[i]->resv, 1);
164
+
if (ret)
165
+
return ret;
166
+
167
+
ret = drm_sched_job_add_implicit_dependencies(job, bos[i],
168
+
is_write);
169
+
if (ret)
170
+
return ret;
171
+
}
172
+
173
+
return 0;
174
+
}
175
+
176
+
static void rocket_attach_object_fences(struct drm_gem_object **bos,
177
+
int bo_count,
178
+
struct dma_fence *fence)
179
+
{
180
+
int i;
181
+
182
+
for (i = 0; i < bo_count; i++)
183
+
dma_resv_add_fence(bos[i]->resv, fence, DMA_RESV_USAGE_WRITE);
184
+
}
185
+
186
+
static int rocket_job_push(struct rocket_job *job)
187
+
{
188
+
struct rocket_device *rdev = job->rdev;
189
+
struct drm_gem_object **bos;
190
+
struct ww_acquire_ctx acquire_ctx;
191
+
int ret = 0;
192
+
193
+
bos = kvmalloc_array(job->in_bo_count + job->out_bo_count, sizeof(void *),
194
+
GFP_KERNEL);
195
+
memcpy(bos, job->in_bos, job->in_bo_count * sizeof(void *));
196
+
memcpy(&bos[job->in_bo_count], job->out_bos, job->out_bo_count * sizeof(void *));
197
+
198
+
ret = drm_gem_lock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
199
+
if (ret)
200
+
goto err;
201
+
202
+
scoped_guard(mutex, &rdev->sched_lock) {
203
+
drm_sched_job_arm(&job->base);
204
+
205
+
job->inference_done_fence = dma_fence_get(&job->base.s_fence->finished);
206
+
207
+
ret = rocket_acquire_object_fences(job->in_bos, job->in_bo_count, &job->base, false);
208
+
if (ret)
209
+
goto err_unlock;
210
+
211
+
ret = rocket_acquire_object_fences(job->out_bos, job->out_bo_count, &job->base, true);
212
+
if (ret)
213
+
goto err_unlock;
214
+
215
+
kref_get(&job->refcount); /* put by scheduler job completion */
216
+
217
+
drm_sched_entity_push_job(&job->base);
218
+
}
219
+
220
+
rocket_attach_object_fences(job->out_bos, job->out_bo_count, job->inference_done_fence);
221
+
222
+
err_unlock:
223
+
drm_gem_unlock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
224
+
err:
225
+
kfree(bos);
226
+
227
+
return ret;
228
+
}
229
+
230
+
static void rocket_job_cleanup(struct kref *ref)
231
+
{
232
+
struct rocket_job *job = container_of(ref, struct rocket_job,
233
+
refcount);
234
+
unsigned int i;
235
+
236
+
rocket_iommu_domain_put(job->domain);
237
+
238
+
dma_fence_put(job->done_fence);
239
+
dma_fence_put(job->inference_done_fence);
240
+
241
+
if (job->in_bos) {
242
+
for (i = 0; i < job->in_bo_count; i++)
243
+
drm_gem_object_put(job->in_bos[i]);
244
+
245
+
kvfree(job->in_bos);
246
+
}
247
+
248
+
if (job->out_bos) {
249
+
for (i = 0; i < job->out_bo_count; i++)
250
+
drm_gem_object_put(job->out_bos[i]);
251
+
252
+
kvfree(job->out_bos);
253
+
}
254
+
255
+
kvfree(job->tasks);
256
+
257
+
kfree(job);
258
+
}
259
+
260
+
static void rocket_job_put(struct rocket_job *job)
261
+
{
262
+
kref_put(&job->refcount, rocket_job_cleanup);
263
+
}
264
+
265
+
static void rocket_job_free(struct drm_sched_job *sched_job)
266
+
{
267
+
struct rocket_job *job = to_rocket_job(sched_job);
268
+
269
+
drm_sched_job_cleanup(sched_job);
270
+
271
+
rocket_job_put(job);
272
+
}
273
+
274
+
static struct rocket_core *sched_to_core(struct rocket_device *rdev,
275
+
struct drm_gpu_scheduler *sched)
276
+
{
277
+
unsigned int core;
278
+
279
+
for (core = 0; core < rdev->num_cores; core++) {
280
+
if (&rdev->cores[core].sched == sched)
281
+
return &rdev->cores[core];
282
+
}
283
+
284
+
return NULL;
285
+
}
286
+
287
+
static struct dma_fence *rocket_job_run(struct drm_sched_job *sched_job)
288
+
{
289
+
struct rocket_job *job = to_rocket_job(sched_job);
290
+
struct rocket_device *rdev = job->rdev;
291
+
struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
292
+
struct dma_fence *fence = NULL;
293
+
int ret;
294
+
295
+
if (unlikely(job->base.s_fence->finished.error))
296
+
return NULL;
297
+
298
+
/*
299
+
* Nothing to execute: can happen if the job has finished while
300
+
* we were resetting the NPU.
301
+
*/
302
+
if (job->next_task_idx == job->task_count)
303
+
return NULL;
304
+
305
+
fence = rocket_fence_create(core);
306
+
if (IS_ERR(fence))
307
+
return fence;
308
+
309
+
if (job->done_fence)
310
+
dma_fence_put(job->done_fence);
311
+
job->done_fence = dma_fence_get(fence);
312
+
313
+
ret = pm_runtime_get_sync(core->dev);
314
+
if (ret < 0)
315
+
return fence;
316
+
317
+
ret = iommu_attach_group(job->domain->domain, core->iommu_group);
318
+
if (ret < 0)
319
+
return fence;
320
+
321
+
scoped_guard(mutex, &core->job_lock) {
322
+
core->in_flight_job = job;
323
+
rocket_job_hw_submit(core, job);
324
+
}
325
+
326
+
return fence;
327
+
}
328
+
329
+
static void rocket_job_handle_irq(struct rocket_core *core)
330
+
{
331
+
pm_runtime_mark_last_busy(core->dev);
332
+
333
+
rocket_pc_writel(core, OPERATION_ENABLE, 0x0);
334
+
rocket_pc_writel(core, INTERRUPT_CLEAR, 0x1ffff);
335
+
336
+
scoped_guard(mutex, &core->job_lock)
337
+
if (core->in_flight_job) {
338
+
if (core->in_flight_job->next_task_idx < core->in_flight_job->task_count) {
339
+
rocket_job_hw_submit(core, core->in_flight_job);
340
+
return;
341
+
}
342
+
343
+
iommu_detach_group(NULL, iommu_group_get(core->dev));
344
+
dma_fence_signal(core->in_flight_job->done_fence);
345
+
pm_runtime_put_autosuspend(core->dev);
346
+
core->in_flight_job = NULL;
347
+
}
348
+
}
349
+
350
+
static void
351
+
rocket_reset(struct rocket_core *core, struct drm_sched_job *bad)
352
+
{
353
+
if (!atomic_read(&core->reset.pending))
354
+
return;
355
+
356
+
drm_sched_stop(&core->sched, bad);
357
+
358
+
/*
359
+
* Remaining interrupts have been handled, but we might still have
360
+
* stuck jobs. Let's make sure the PM counters stay balanced by
361
+
* manually calling pm_runtime_put_noidle().
362
+
*/
363
+
scoped_guard(mutex, &core->job_lock) {
364
+
if (core->in_flight_job)
365
+
pm_runtime_put_noidle(core->dev);
366
+
367
+
iommu_detach_group(NULL, core->iommu_group);
368
+
369
+
core->in_flight_job = NULL;
370
+
}
371
+
372
+
/* Proceed with reset now. */
373
+
rocket_core_reset(core);
374
+
375
+
/* NPU has been reset, we can clear the reset pending bit. */
376
+
atomic_set(&core->reset.pending, 0);
377
+
378
+
/* Restart the scheduler */
379
+
drm_sched_start(&core->sched, 0);
380
+
}
381
+
382
+
static enum drm_gpu_sched_stat rocket_job_timedout(struct drm_sched_job *sched_job)
383
+
{
384
+
struct rocket_job *job = to_rocket_job(sched_job);
385
+
struct rocket_device *rdev = job->rdev;
386
+
struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
387
+
388
+
dev_err(core->dev, "NPU job timed out");
389
+
390
+
atomic_set(&core->reset.pending, 1);
391
+
rocket_reset(core, sched_job);
392
+
393
+
return DRM_GPU_SCHED_STAT_RESET;
394
+
}
395
+
396
+
static void rocket_reset_work(struct work_struct *work)
397
+
{
398
+
struct rocket_core *core;
399
+
400
+
core = container_of(work, struct rocket_core, reset.work);
401
+
rocket_reset(core, NULL);
402
+
}
403
+
404
+
static const struct drm_sched_backend_ops rocket_sched_ops = {
405
+
.run_job = rocket_job_run,
406
+
.timedout_job = rocket_job_timedout,
407
+
.free_job = rocket_job_free
408
+
};
409
+
410
+
static irqreturn_t rocket_job_irq_handler_thread(int irq, void *data)
411
+
{
412
+
struct rocket_core *core = data;
413
+
414
+
rocket_job_handle_irq(core);
415
+
416
+
return IRQ_HANDLED;
417
+
}
418
+
419
+
static irqreturn_t rocket_job_irq_handler(int irq, void *data)
420
+
{
421
+
struct rocket_core *core = data;
422
+
u32 raw_status = rocket_pc_readl(core, INTERRUPT_RAW_STATUS);
423
+
424
+
WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR);
425
+
WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR);
426
+
427
+
if (!(raw_status & PC_INTERRUPT_RAW_STATUS_DPU_0 ||
428
+
raw_status & PC_INTERRUPT_RAW_STATUS_DPU_1))
429
+
return IRQ_NONE;
430
+
431
+
rocket_pc_writel(core, INTERRUPT_MASK, 0x0);
432
+
433
+
return IRQ_WAKE_THREAD;
434
+
}
435
+
436
+
int rocket_job_init(struct rocket_core *core)
437
+
{
438
+
struct drm_sched_init_args args = {
439
+
.ops = &rocket_sched_ops,
440
+
.num_rqs = DRM_SCHED_PRIORITY_COUNT,
441
+
.credit_limit = 1,
442
+
.timeout = msecs_to_jiffies(JOB_TIMEOUT_MS),
443
+
.name = dev_name(core->dev),
444
+
.dev = core->dev,
445
+
};
446
+
int ret;
447
+
448
+
INIT_WORK(&core->reset.work, rocket_reset_work);
449
+
spin_lock_init(&core->fence_lock);
450
+
mutex_init(&core->job_lock);
451
+
452
+
core->irq = platform_get_irq(to_platform_device(core->dev), 0);
453
+
if (core->irq < 0)
454
+
return core->irq;
455
+
456
+
ret = devm_request_threaded_irq(core->dev, core->irq,
457
+
rocket_job_irq_handler,
458
+
rocket_job_irq_handler_thread,
459
+
IRQF_SHARED, dev_name(core->dev),
460
+
core);
461
+
if (ret) {
462
+
dev_err(core->dev, "failed to request job irq");
463
+
return ret;
464
+
}
465
+
466
+
core->reset.wq = alloc_ordered_workqueue("rocket-reset-%d", 0, core->index);
467
+
if (!core->reset.wq)
468
+
return -ENOMEM;
469
+
470
+
core->fence_context = dma_fence_context_alloc(1);
471
+
472
+
args.timeout_wq = core->reset.wq;
473
+
ret = drm_sched_init(&core->sched, &args);
474
+
if (ret) {
475
+
dev_err(core->dev, "Failed to create scheduler: %d.", ret);
476
+
goto err_sched;
477
+
}
478
+
479
+
return 0;
480
+
481
+
err_sched:
482
+
drm_sched_fini(&core->sched);
483
+
484
+
destroy_workqueue(core->reset.wq);
485
+
return ret;
486
+
}
487
+
488
+
void rocket_job_fini(struct rocket_core *core)
489
+
{
490
+
drm_sched_fini(&core->sched);
491
+
492
+
cancel_work_sync(&core->reset.work);
493
+
destroy_workqueue(core->reset.wq);
494
+
}
495
+
496
+
int rocket_job_open(struct rocket_file_priv *rocket_priv)
497
+
{
498
+
struct rocket_device *rdev = rocket_priv->rdev;
499
+
struct drm_gpu_scheduler **scheds = kmalloc_array(rdev->num_cores, sizeof(scheds),
500
+
GFP_KERNEL);
501
+
unsigned int core;
502
+
int ret;
503
+
504
+
for (core = 0; core < rdev->num_cores; core++)
505
+
scheds[core] = &rdev->cores[core].sched;
506
+
507
+
ret = drm_sched_entity_init(&rocket_priv->sched_entity,
508
+
DRM_SCHED_PRIORITY_NORMAL,
509
+
scheds,
510
+
rdev->num_cores, NULL);
511
+
if (WARN_ON(ret))
512
+
return ret;
513
+
514
+
return 0;
515
+
}
516
+
517
+
void rocket_job_close(struct rocket_file_priv *rocket_priv)
518
+
{
519
+
struct drm_sched_entity *entity = &rocket_priv->sched_entity;
520
+
521
+
kfree(entity->sched_list);
522
+
drm_sched_entity_destroy(entity);
523
+
}
524
+
525
+
int rocket_job_is_idle(struct rocket_core *core)
526
+
{
527
+
/* If there are any jobs in this HW queue, we're not idle */
528
+
if (atomic_read(&core->sched.credit_count))
529
+
return false;
530
+
531
+
return true;
532
+
}
533
+
534
+
static int rocket_ioctl_submit_job(struct drm_device *dev, struct drm_file *file,
535
+
struct drm_rocket_job *job)
536
+
{
537
+
struct rocket_device *rdev = to_rocket_device(dev);
538
+
struct rocket_file_priv *file_priv = file->driver_priv;
539
+
struct rocket_job *rjob = NULL;
540
+
int ret = 0;
541
+
542
+
if (job->task_count == 0)
543
+
return -EINVAL;
544
+
545
+
rjob = kzalloc(sizeof(*rjob), GFP_KERNEL);
546
+
if (!rjob)
547
+
return -ENOMEM;
548
+
549
+
kref_init(&rjob->refcount);
550
+
551
+
rjob->rdev = rdev;
552
+
553
+
ret = drm_sched_job_init(&rjob->base,
554
+
&file_priv->sched_entity,
555
+
1, NULL, file->client_id);
556
+
if (ret)
557
+
goto out_put_job;
558
+
559
+
ret = rocket_copy_tasks(dev, file, job, rjob);
560
+
if (ret)
561
+
goto out_cleanup_job;
562
+
563
+
ret = drm_gem_objects_lookup(file, u64_to_user_ptr(job->in_bo_handles),
564
+
job->in_bo_handle_count, &rjob->in_bos);
565
+
if (ret)
566
+
goto out_cleanup_job;
567
+
568
+
rjob->in_bo_count = job->in_bo_handle_count;
569
+
570
+
ret = drm_gem_objects_lookup(file, u64_to_user_ptr(job->out_bo_handles),
571
+
job->out_bo_handle_count, &rjob->out_bos);
572
+
if (ret)
573
+
goto out_cleanup_job;
574
+
575
+
rjob->out_bo_count = job->out_bo_handle_count;
576
+
577
+
rjob->domain = rocket_iommu_domain_get(file_priv);
578
+
579
+
ret = rocket_job_push(rjob);
580
+
if (ret)
581
+
goto out_cleanup_job;
582
+
583
+
out_cleanup_job:
584
+
if (ret)
585
+
drm_sched_job_cleanup(&rjob->base);
586
+
out_put_job:
587
+
rocket_job_put(rjob);
588
+
589
+
return ret;
590
+
}
591
+
592
+
int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file)
593
+
{
594
+
struct drm_rocket_submit *args = data;
595
+
struct drm_rocket_job *jobs;
596
+
int ret = 0;
597
+
unsigned int i = 0;
598
+
599
+
if (args->job_count == 0)
600
+
return 0;
601
+
602
+
if (args->job_struct_size < sizeof(struct drm_rocket_job)) {
603
+
drm_dbg(dev, "job_struct_size field in drm_rocket_submit struct is too small.\n");
604
+
return -EINVAL;
605
+
}
606
+
607
+
if (args->reserved != 0) {
608
+
drm_dbg(dev, "Reserved field in drm_rocket_submit struct should be 0.\n");
609
+
return -EINVAL;
610
+
}
611
+
612
+
jobs = kvmalloc_array(args->job_count, sizeof(*jobs), GFP_KERNEL);
613
+
if (!jobs) {
614
+
drm_dbg(dev, "Failed to allocate incoming job array\n");
615
+
return -ENOMEM;
616
+
}
617
+
618
+
for (i = 0; i < args->job_count; i++) {
619
+
if (copy_from_user(&jobs[i],
620
+
u64_to_user_ptr(args->jobs) + i * args->job_struct_size,
621
+
sizeof(*jobs))) {
622
+
ret = -EFAULT;
623
+
drm_dbg(dev, "Failed to copy incoming job array\n");
624
+
goto exit;
625
+
}
626
+
}
627
+
628
+
629
+
for (i = 0; i < args->job_count; i++)
630
+
rocket_ioctl_submit_job(dev, file, &jobs[i]);
631
+
632
+
exit:
633
+
kfree(jobs);
634
+
635
+
return ret;
636
+
}
+52
drivers/accel/rocket/rocket_job.h
+52
drivers/accel/rocket/rocket_job.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
3
+
4
+
#ifndef __ROCKET_JOB_H__
5
+
#define __ROCKET_JOB_H__
6
+
7
+
#include <drm/drm_drv.h>
8
+
#include <drm/gpu_scheduler.h>
9
+
10
+
#include "rocket_core.h"
11
+
#include "rocket_drv.h"
12
+
13
+
struct rocket_task {
14
+
u64 regcmd;
15
+
u32 regcmd_count;
16
+
};
17
+
18
+
struct rocket_job {
19
+
struct drm_sched_job base;
20
+
21
+
struct rocket_device *rdev;
22
+
23
+
struct drm_gem_object **in_bos;
24
+
struct drm_gem_object **out_bos;
25
+
26
+
u32 in_bo_count;
27
+
u32 out_bo_count;
28
+
29
+
struct rocket_task *tasks;
30
+
u32 task_count;
31
+
u32 next_task_idx;
32
+
33
+
/* Fence to be signaled by drm-sched once its done with the job */
34
+
struct dma_fence *inference_done_fence;
35
+
36
+
/* Fence to be signaled by IRQ handler when the job is complete. */
37
+
struct dma_fence *done_fence;
38
+
39
+
struct rocket_iommu_domain *domain;
40
+
41
+
struct kref refcount;
42
+
};
43
+
44
+
int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file);
45
+
46
+
int rocket_job_init(struct rocket_core *core);
47
+
void rocket_job_fini(struct rocket_core *core);
48
+
int rocket_job_open(struct rocket_file_priv *rocket_priv);
49
+
void rocket_job_close(struct rocket_file_priv *rocket_priv);
50
+
int rocket_job_is_idle(struct rocket_core *core);
51
+
52
+
#endif
+4404
drivers/accel/rocket/rocket_registers.h
+4404
drivers/accel/rocket/rocket_registers.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2
+
3
+
#ifndef __ROCKET_REGISTERS_XML__
4
+
#define __ROCKET_REGISTERS_XML__
5
+
6
+
/* Autogenerated file, DO NOT EDIT manually!
7
+
8
+
This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
9
+
http://gitlab.freedesktop.org/mesa/mesa/
10
+
git clone https://gitlab.freedesktop.org/mesa/mesa.git
11
+
12
+
The rules-ng-ng source files this header was generated from are:
13
+
14
+
- /home/tomeu/src/mesa/src/gallium/drivers/rocket/registers.xml ( 60076 bytes, from Wed Jun 12 10:02:25 2024)
15
+
16
+
Copyright (C) 2024-2025 by the following authors:
17
+
- Tomeu Vizoso <tomeu@tomeuvizoso.net>
18
+
*/
19
+
20
+
#define REG_PC_VERSION 0x00000000
21
+
#define PC_VERSION_VERSION__MASK 0xffffffff
22
+
#define PC_VERSION_VERSION__SHIFT 0
23
+
static inline uint32_t PC_VERSION_VERSION(uint32_t val)
24
+
{
25
+
return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK;
26
+
}
27
+
28
+
#define REG_PC_VERSION_NUM 0x00000004
29
+
#define PC_VERSION_NUM_VERSION_NUM__MASK 0xffffffff
30
+
#define PC_VERSION_NUM_VERSION_NUM__SHIFT 0
31
+
static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val)
32
+
{
33
+
return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK;
34
+
}
35
+
36
+
#define REG_PC_OPERATION_ENABLE 0x00000008
37
+
#define PC_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
38
+
#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT 1
39
+
static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val)
40
+
{
41
+
return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK;
42
+
}
43
+
#define PC_OPERATION_ENABLE_OP_EN__MASK 0x00000001
44
+
#define PC_OPERATION_ENABLE_OP_EN__SHIFT 0
45
+
static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val)
46
+
{
47
+
return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK;
48
+
}
49
+
50
+
#define REG_PC_BASE_ADDRESS 0x00000010
51
+
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK 0xfffffff0
52
+
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT 4
53
+
static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val)
54
+
{
55
+
return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK;
56
+
}
57
+
#define PC_BASE_ADDRESS_RESERVED_0__MASK 0x0000000e
58
+
#define PC_BASE_ADDRESS_RESERVED_0__SHIFT 1
59
+
static inline uint32_t PC_BASE_ADDRESS_RESERVED_0(uint32_t val)
60
+
{
61
+
return ((val) << PC_BASE_ADDRESS_RESERVED_0__SHIFT) & PC_BASE_ADDRESS_RESERVED_0__MASK;
62
+
}
63
+
#define PC_BASE_ADDRESS_PC_SEL__MASK 0x00000001
64
+
#define PC_BASE_ADDRESS_PC_SEL__SHIFT 0
65
+
static inline uint32_t PC_BASE_ADDRESS_PC_SEL(uint32_t val)
66
+
{
67
+
return ((val) << PC_BASE_ADDRESS_PC_SEL__SHIFT) & PC_BASE_ADDRESS_PC_SEL__MASK;
68
+
}
69
+
70
+
#define REG_PC_REGISTER_AMOUNTS 0x00000014
71
+
#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK 0xffff0000
72
+
#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT 16
73
+
static inline uint32_t PC_REGISTER_AMOUNTS_RESERVED_0(uint32_t val)
74
+
{
75
+
return ((val) << PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT) & PC_REGISTER_AMOUNTS_RESERVED_0__MASK;
76
+
}
77
+
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK 0x0000ffff
78
+
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT 0
79
+
static inline uint32_t PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT(uint32_t val)
80
+
{
81
+
return ((val) << PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT) & PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK;
82
+
}
83
+
84
+
#define REG_PC_INTERRUPT_MASK 0x00000020
85
+
#define PC_INTERRUPT_MASK_RESERVED_0__MASK 0xffffc000
86
+
#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT 14
87
+
static inline uint32_t PC_INTERRUPT_MASK_RESERVED_0(uint32_t val)
88
+
{
89
+
return ((val) << PC_INTERRUPT_MASK_RESERVED_0__SHIFT) & PC_INTERRUPT_MASK_RESERVED_0__MASK;
90
+
}
91
+
#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR 0x00002000
92
+
#define PC_INTERRUPT_MASK_DMA_READ_ERROR 0x00001000
93
+
#define PC_INTERRUPT_MASK_PPU_1 0x00000800
94
+
#define PC_INTERRUPT_MASK_PPU_0 0x00000400
95
+
#define PC_INTERRUPT_MASK_DPU_1 0x00000200
96
+
#define PC_INTERRUPT_MASK_DPU_0 0x00000100
97
+
#define PC_INTERRUPT_MASK_CORE_1 0x00000080
98
+
#define PC_INTERRUPT_MASK_CORE_0 0x00000040
99
+
#define PC_INTERRUPT_MASK_CNA_CSC_1 0x00000020
100
+
#define PC_INTERRUPT_MASK_CNA_CSC_0 0x00000010
101
+
#define PC_INTERRUPT_MASK_CNA_WEIGHT_1 0x00000008
102
+
#define PC_INTERRUPT_MASK_CNA_WEIGHT_0 0x00000004
103
+
#define PC_INTERRUPT_MASK_CNA_FEATURE_1 0x00000002
104
+
#define PC_INTERRUPT_MASK_CNA_FEATURE_0 0x00000001
105
+
106
+
#define REG_PC_INTERRUPT_CLEAR 0x00000024
107
+
#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK 0xffffc000
108
+
#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT 14
109
+
static inline uint32_t PC_INTERRUPT_CLEAR_RESERVED_0(uint32_t val)
110
+
{
111
+
return ((val) << PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT) & PC_INTERRUPT_CLEAR_RESERVED_0__MASK;
112
+
}
113
+
#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR 0x00002000
114
+
#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR 0x00001000
115
+
#define PC_INTERRUPT_CLEAR_PPU_1 0x00000800
116
+
#define PC_INTERRUPT_CLEAR_PPU_0 0x00000400
117
+
#define PC_INTERRUPT_CLEAR_DPU_1 0x00000200
118
+
#define PC_INTERRUPT_CLEAR_DPU_0 0x00000100
119
+
#define PC_INTERRUPT_CLEAR_CORE_1 0x00000080
120
+
#define PC_INTERRUPT_CLEAR_CORE_0 0x00000040
121
+
#define PC_INTERRUPT_CLEAR_CNA_CSC_1 0x00000020
122
+
#define PC_INTERRUPT_CLEAR_CNA_CSC_0 0x00000010
123
+
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1 0x00000008
124
+
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0 0x00000004
125
+
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1 0x00000002
126
+
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0 0x00000001
127
+
128
+
#define REG_PC_INTERRUPT_STATUS 0x00000028
129
+
#define PC_INTERRUPT_STATUS_RESERVED_0__MASK 0xffffc000
130
+
#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT 14
131
+
static inline uint32_t PC_INTERRUPT_STATUS_RESERVED_0(uint32_t val)
132
+
{
133
+
return ((val) << PC_INTERRUPT_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_STATUS_RESERVED_0__MASK;
134
+
}
135
+
#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR 0x00002000
136
+
#define PC_INTERRUPT_STATUS_DMA_READ_ERROR 0x00001000
137
+
#define PC_INTERRUPT_STATUS_PPU_1 0x00000800
138
+
#define PC_INTERRUPT_STATUS_PPU_0 0x00000400
139
+
#define PC_INTERRUPT_STATUS_DPU_1 0x00000200
140
+
#define PC_INTERRUPT_STATUS_DPU_0 0x00000100
141
+
#define PC_INTERRUPT_STATUS_CORE_1 0x00000080
142
+
#define PC_INTERRUPT_STATUS_CORE_0 0x00000040
143
+
#define PC_INTERRUPT_STATUS_CNA_CSC_1 0x00000020
144
+
#define PC_INTERRUPT_STATUS_CNA_CSC_0 0x00000010
145
+
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1 0x00000008
146
+
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0 0x00000004
147
+
#define PC_INTERRUPT_STATUS_CNA_FEATURE_1 0x00000002
148
+
#define PC_INTERRUPT_STATUS_CNA_FEATURE_0 0x00000001
149
+
150
+
#define REG_PC_INTERRUPT_RAW_STATUS 0x0000002c
151
+
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK 0xffffc000
152
+
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT 14
153
+
static inline uint32_t PC_INTERRUPT_RAW_STATUS_RESERVED_0(uint32_t val)
154
+
{
155
+
return ((val) << PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK;
156
+
}
157
+
#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR 0x00002000
158
+
#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR 0x00001000
159
+
#define PC_INTERRUPT_RAW_STATUS_PPU_1 0x00000800
160
+
#define PC_INTERRUPT_RAW_STATUS_PPU_0 0x00000400
161
+
#define PC_INTERRUPT_RAW_STATUS_DPU_1 0x00000200
162
+
#define PC_INTERRUPT_RAW_STATUS_DPU_0 0x00000100
163
+
#define PC_INTERRUPT_RAW_STATUS_CORE_1 0x00000080
164
+
#define PC_INTERRUPT_RAW_STATUS_CORE_0 0x00000040
165
+
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1 0x00000020
166
+
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0 0x00000010
167
+
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1 0x00000008
168
+
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0 0x00000004
169
+
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1 0x00000002
170
+
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0 0x00000001
171
+
172
+
#define REG_PC_TASK_CON 0x00000030
173
+
#define PC_TASK_CON_RESERVED_0__MASK 0xffffc000
174
+
#define PC_TASK_CON_RESERVED_0__SHIFT 14
175
+
static inline uint32_t PC_TASK_CON_RESERVED_0(uint32_t val)
176
+
{
177
+
return ((val) << PC_TASK_CON_RESERVED_0__SHIFT) & PC_TASK_CON_RESERVED_0__MASK;
178
+
}
179
+
#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK 0x00002000
180
+
#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT 13
181
+
static inline uint32_t PC_TASK_CON_TASK_COUNT_CLEAR(uint32_t val)
182
+
{
183
+
return ((val) << PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT) & PC_TASK_CON_TASK_COUNT_CLEAR__MASK;
184
+
}
185
+
#define PC_TASK_CON_TASK_PP_EN__MASK 0x00001000
186
+
#define PC_TASK_CON_TASK_PP_EN__SHIFT 12
187
+
static inline uint32_t PC_TASK_CON_TASK_PP_EN(uint32_t val)
188
+
{
189
+
return ((val) << PC_TASK_CON_TASK_PP_EN__SHIFT) & PC_TASK_CON_TASK_PP_EN__MASK;
190
+
}
191
+
#define PC_TASK_CON_TASK_NUMBER__MASK 0x00000fff
192
+
#define PC_TASK_CON_TASK_NUMBER__SHIFT 0
193
+
static inline uint32_t PC_TASK_CON_TASK_NUMBER(uint32_t val)
194
+
{
195
+
return ((val) << PC_TASK_CON_TASK_NUMBER__SHIFT) & PC_TASK_CON_TASK_NUMBER__MASK;
196
+
}
197
+
198
+
#define REG_PC_TASK_DMA_BASE_ADDR 0x00000034
199
+
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK 0xfffffff0
200
+
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT 4
201
+
static inline uint32_t PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(uint32_t val)
202
+
{
203
+
return ((val) << PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT) & PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK;
204
+
}
205
+
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK 0x0000000f
206
+
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT 0
207
+
static inline uint32_t PC_TASK_DMA_BASE_ADDR_RESERVED_0(uint32_t val)
208
+
{
209
+
return ((val) << PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT) & PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK;
210
+
}
211
+
212
+
#define REG_PC_TASK_STATUS 0x0000003c
213
+
#define PC_TASK_STATUS_RESERVED_0__MASK 0xf0000000
214
+
#define PC_TASK_STATUS_RESERVED_0__SHIFT 28
215
+
static inline uint32_t PC_TASK_STATUS_RESERVED_0(uint32_t val)
216
+
{
217
+
return ((val) << PC_TASK_STATUS_RESERVED_0__SHIFT) & PC_TASK_STATUS_RESERVED_0__MASK;
218
+
}
219
+
#define PC_TASK_STATUS_TASK_STATUS__MASK 0x0fffffff
220
+
#define PC_TASK_STATUS_TASK_STATUS__SHIFT 0
221
+
static inline uint32_t PC_TASK_STATUS_TASK_STATUS(uint32_t val)
222
+
{
223
+
return ((val) << PC_TASK_STATUS_TASK_STATUS__SHIFT) & PC_TASK_STATUS_TASK_STATUS__MASK;
224
+
}
225
+
226
+
#define REG_CNA_S_STATUS 0x00001000
227
+
#define CNA_S_STATUS_RESERVED_0__MASK 0xfffc0000
228
+
#define CNA_S_STATUS_RESERVED_0__SHIFT 18
229
+
static inline uint32_t CNA_S_STATUS_RESERVED_0(uint32_t val)
230
+
{
231
+
return ((val) << CNA_S_STATUS_RESERVED_0__SHIFT) & CNA_S_STATUS_RESERVED_0__MASK;
232
+
}
233
+
#define CNA_S_STATUS_STATUS_1__MASK 0x00030000
234
+
#define CNA_S_STATUS_STATUS_1__SHIFT 16
235
+
static inline uint32_t CNA_S_STATUS_STATUS_1(uint32_t val)
236
+
{
237
+
return ((val) << CNA_S_STATUS_STATUS_1__SHIFT) & CNA_S_STATUS_STATUS_1__MASK;
238
+
}
239
+
#define CNA_S_STATUS_RESERVED_1__MASK 0x0000fffc
240
+
#define CNA_S_STATUS_RESERVED_1__SHIFT 2
241
+
static inline uint32_t CNA_S_STATUS_RESERVED_1(uint32_t val)
242
+
{
243
+
return ((val) << CNA_S_STATUS_RESERVED_1__SHIFT) & CNA_S_STATUS_RESERVED_1__MASK;
244
+
}
245
+
#define CNA_S_STATUS_STATUS_0__MASK 0x00000003
246
+
#define CNA_S_STATUS_STATUS_0__SHIFT 0
247
+
static inline uint32_t CNA_S_STATUS_STATUS_0(uint32_t val)
248
+
{
249
+
return ((val) << CNA_S_STATUS_STATUS_0__SHIFT) & CNA_S_STATUS_STATUS_0__MASK;
250
+
}
251
+
252
+
#define REG_CNA_S_POINTER 0x00001004
253
+
#define CNA_S_POINTER_RESERVED_0__MASK 0xfffe0000
254
+
#define CNA_S_POINTER_RESERVED_0__SHIFT 17
255
+
static inline uint32_t CNA_S_POINTER_RESERVED_0(uint32_t val)
256
+
{
257
+
return ((val) << CNA_S_POINTER_RESERVED_0__SHIFT) & CNA_S_POINTER_RESERVED_0__MASK;
258
+
}
259
+
#define CNA_S_POINTER_EXECUTER__MASK 0x00010000
260
+
#define CNA_S_POINTER_EXECUTER__SHIFT 16
261
+
static inline uint32_t CNA_S_POINTER_EXECUTER(uint32_t val)
262
+
{
263
+
return ((val) << CNA_S_POINTER_EXECUTER__SHIFT) & CNA_S_POINTER_EXECUTER__MASK;
264
+
}
265
+
#define CNA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
266
+
#define CNA_S_POINTER_RESERVED_1__SHIFT 6
267
+
static inline uint32_t CNA_S_POINTER_RESERVED_1(uint32_t val)
268
+
{
269
+
return ((val) << CNA_S_POINTER_RESERVED_1__SHIFT) & CNA_S_POINTER_RESERVED_1__MASK;
270
+
}
271
+
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
272
+
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
273
+
static inline uint32_t CNA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
274
+
{
275
+
return ((val) << CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
276
+
}
277
+
#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
278
+
#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
279
+
static inline uint32_t CNA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
280
+
{
281
+
return ((val) << CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_POINTER_PP_CLEAR__MASK;
282
+
}
283
+
#define CNA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
284
+
#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT 3
285
+
static inline uint32_t CNA_S_POINTER_POINTER_PP_MODE(uint32_t val)
286
+
{
287
+
return ((val) << CNA_S_POINTER_POINTER_PP_MODE__SHIFT) & CNA_S_POINTER_POINTER_PP_MODE__MASK;
288
+
}
289
+
#define CNA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
290
+
#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
291
+
static inline uint32_t CNA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
292
+
{
293
+
return ((val) << CNA_S_POINTER_EXECUTER_PP_EN__SHIFT) & CNA_S_POINTER_EXECUTER_PP_EN__MASK;
294
+
}
295
+
#define CNA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
296
+
#define CNA_S_POINTER_POINTER_PP_EN__SHIFT 1
297
+
static inline uint32_t CNA_S_POINTER_POINTER_PP_EN(uint32_t val)
298
+
{
299
+
return ((val) << CNA_S_POINTER_POINTER_PP_EN__SHIFT) & CNA_S_POINTER_POINTER_PP_EN__MASK;
300
+
}
301
+
#define CNA_S_POINTER_POINTER__MASK 0x00000001
302
+
#define CNA_S_POINTER_POINTER__SHIFT 0
303
+
static inline uint32_t CNA_S_POINTER_POINTER(uint32_t val)
304
+
{
305
+
return ((val) << CNA_S_POINTER_POINTER__SHIFT) & CNA_S_POINTER_POINTER__MASK;
306
+
}
307
+
308
+
#define REG_CNA_OPERATION_ENABLE 0x00001008
309
+
#define CNA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
310
+
#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
311
+
static inline uint32_t CNA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
312
+
{
313
+
return ((val) << CNA_OPERATION_ENABLE_RESERVED_0__SHIFT) & CNA_OPERATION_ENABLE_RESERVED_0__MASK;
314
+
}
315
+
#define CNA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
316
+
#define CNA_OPERATION_ENABLE_OP_EN__SHIFT 0
317
+
static inline uint32_t CNA_OPERATION_ENABLE_OP_EN(uint32_t val)
318
+
{
319
+
return ((val) << CNA_OPERATION_ENABLE_OP_EN__SHIFT) & CNA_OPERATION_ENABLE_OP_EN__MASK;
320
+
}
321
+
322
+
#define REG_CNA_CONV_CON1 0x0000100c
323
+
#define CNA_CONV_CON1_RESERVED_0__MASK 0x80000000
324
+
#define CNA_CONV_CON1_RESERVED_0__SHIFT 31
325
+
static inline uint32_t CNA_CONV_CON1_RESERVED_0(uint32_t val)
326
+
{
327
+
return ((val) << CNA_CONV_CON1_RESERVED_0__SHIFT) & CNA_CONV_CON1_RESERVED_0__MASK;
328
+
}
329
+
#define CNA_CONV_CON1_NONALIGN_DMA__MASK 0x40000000
330
+
#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT 30
331
+
static inline uint32_t CNA_CONV_CON1_NONALIGN_DMA(uint32_t val)
332
+
{
333
+
return ((val) << CNA_CONV_CON1_NONALIGN_DMA__SHIFT) & CNA_CONV_CON1_NONALIGN_DMA__MASK;
334
+
}
335
+
#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK 0x20000000
336
+
#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT 29
337
+
static inline uint32_t CNA_CONV_CON1_GROUP_LINE_OFF(uint32_t val)
338
+
{
339
+
return ((val) << CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT) & CNA_CONV_CON1_GROUP_LINE_OFF__MASK;
340
+
}
341
+
#define CNA_CONV_CON1_RESERVED_1__MASK 0x1ffe0000
342
+
#define CNA_CONV_CON1_RESERVED_1__SHIFT 17
343
+
static inline uint32_t CNA_CONV_CON1_RESERVED_1(uint32_t val)
344
+
{
345
+
return ((val) << CNA_CONV_CON1_RESERVED_1__SHIFT) & CNA_CONV_CON1_RESERVED_1__MASK;
346
+
}
347
+
#define CNA_CONV_CON1_DECONV__MASK 0x00010000
348
+
#define CNA_CONV_CON1_DECONV__SHIFT 16
349
+
static inline uint32_t CNA_CONV_CON1_DECONV(uint32_t val)
350
+
{
351
+
return ((val) << CNA_CONV_CON1_DECONV__SHIFT) & CNA_CONV_CON1_DECONV__MASK;
352
+
}
353
+
#define CNA_CONV_CON1_ARGB_IN__MASK 0x0000f000
354
+
#define CNA_CONV_CON1_ARGB_IN__SHIFT 12
355
+
static inline uint32_t CNA_CONV_CON1_ARGB_IN(uint32_t val)
356
+
{
357
+
return ((val) << CNA_CONV_CON1_ARGB_IN__SHIFT) & CNA_CONV_CON1_ARGB_IN__MASK;
358
+
}
359
+
#define CNA_CONV_CON1_RESERVED_2__MASK 0x00000c00
360
+
#define CNA_CONV_CON1_RESERVED_2__SHIFT 10
361
+
static inline uint32_t CNA_CONV_CON1_RESERVED_2(uint32_t val)
362
+
{
363
+
return ((val) << CNA_CONV_CON1_RESERVED_2__SHIFT) & CNA_CONV_CON1_RESERVED_2__MASK;
364
+
}
365
+
#define CNA_CONV_CON1_PROC_PRECISION__MASK 0x00000380
366
+
#define CNA_CONV_CON1_PROC_PRECISION__SHIFT 7
367
+
static inline uint32_t CNA_CONV_CON1_PROC_PRECISION(uint32_t val)
368
+
{
369
+
return ((val) << CNA_CONV_CON1_PROC_PRECISION__SHIFT) & CNA_CONV_CON1_PROC_PRECISION__MASK;
370
+
}
371
+
#define CNA_CONV_CON1_IN_PRECISION__MASK 0x00000070
372
+
#define CNA_CONV_CON1_IN_PRECISION__SHIFT 4
373
+
static inline uint32_t CNA_CONV_CON1_IN_PRECISION(uint32_t val)
374
+
{
375
+
return ((val) << CNA_CONV_CON1_IN_PRECISION__SHIFT) & CNA_CONV_CON1_IN_PRECISION__MASK;
376
+
}
377
+
#define CNA_CONV_CON1_CONV_MODE__MASK 0x0000000f
378
+
#define CNA_CONV_CON1_CONV_MODE__SHIFT 0
379
+
static inline uint32_t CNA_CONV_CON1_CONV_MODE(uint32_t val)
380
+
{
381
+
return ((val) << CNA_CONV_CON1_CONV_MODE__SHIFT) & CNA_CONV_CON1_CONV_MODE__MASK;
382
+
}
383
+
384
+
#define REG_CNA_CONV_CON2 0x00001010
385
+
#define CNA_CONV_CON2_RESERVED_0__MASK 0xff000000
386
+
#define CNA_CONV_CON2_RESERVED_0__SHIFT 24
387
+
static inline uint32_t CNA_CONV_CON2_RESERVED_0(uint32_t val)
388
+
{
389
+
return ((val) << CNA_CONV_CON2_RESERVED_0__SHIFT) & CNA_CONV_CON2_RESERVED_0__MASK;
390
+
}
391
+
#define CNA_CONV_CON2_KERNEL_GROUP__MASK 0x00ff0000
392
+
#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT 16
393
+
static inline uint32_t CNA_CONV_CON2_KERNEL_GROUP(uint32_t val)
394
+
{
395
+
return ((val) << CNA_CONV_CON2_KERNEL_GROUP__SHIFT) & CNA_CONV_CON2_KERNEL_GROUP__MASK;
396
+
}
397
+
#define CNA_CONV_CON2_RESERVED_1__MASK 0x0000c000
398
+
#define CNA_CONV_CON2_RESERVED_1__SHIFT 14
399
+
static inline uint32_t CNA_CONV_CON2_RESERVED_1(uint32_t val)
400
+
{
401
+
return ((val) << CNA_CONV_CON2_RESERVED_1__SHIFT) & CNA_CONV_CON2_RESERVED_1__MASK;
402
+
}
403
+
#define CNA_CONV_CON2_FEATURE_GRAINS__MASK 0x00003ff0
404
+
#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT 4
405
+
static inline uint32_t CNA_CONV_CON2_FEATURE_GRAINS(uint32_t val)
406
+
{
407
+
return ((val) << CNA_CONV_CON2_FEATURE_GRAINS__SHIFT) & CNA_CONV_CON2_FEATURE_GRAINS__MASK;
408
+
}
409
+
#define CNA_CONV_CON2_RESERVED_2__MASK 0x00000008
410
+
#define CNA_CONV_CON2_RESERVED_2__SHIFT 3
411
+
static inline uint32_t CNA_CONV_CON2_RESERVED_2(uint32_t val)
412
+
{
413
+
return ((val) << CNA_CONV_CON2_RESERVED_2__SHIFT) & CNA_CONV_CON2_RESERVED_2__MASK;
414
+
}
415
+
#define CNA_CONV_CON2_CSC_WO_EN__MASK 0x00000004
416
+
#define CNA_CONV_CON2_CSC_WO_EN__SHIFT 2
417
+
static inline uint32_t CNA_CONV_CON2_CSC_WO_EN(uint32_t val)
418
+
{
419
+
return ((val) << CNA_CONV_CON2_CSC_WO_EN__SHIFT) & CNA_CONV_CON2_CSC_WO_EN__MASK;
420
+
}
421
+
#define CNA_CONV_CON2_CSC_DO_EN__MASK 0x00000002
422
+
#define CNA_CONV_CON2_CSC_DO_EN__SHIFT 1
423
+
static inline uint32_t CNA_CONV_CON2_CSC_DO_EN(uint32_t val)
424
+
{
425
+
return ((val) << CNA_CONV_CON2_CSC_DO_EN__SHIFT) & CNA_CONV_CON2_CSC_DO_EN__MASK;
426
+
}
427
+
#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK 0x00000001
428
+
#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT 0
429
+
static inline uint32_t CNA_CONV_CON2_CMD_FIFO_SRST(uint32_t val)
430
+
{
431
+
return ((val) << CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT) & CNA_CONV_CON2_CMD_FIFO_SRST__MASK;
432
+
}
433
+
434
+
#define REG_CNA_CONV_CON3 0x00001014
435
+
#define CNA_CONV_CON3_RESERVED_0__MASK 0x80000000
436
+
#define CNA_CONV_CON3_RESERVED_0__SHIFT 31
437
+
static inline uint32_t CNA_CONV_CON3_RESERVED_0(uint32_t val)
438
+
{
439
+
return ((val) << CNA_CONV_CON3_RESERVED_0__SHIFT) & CNA_CONV_CON3_RESERVED_0__MASK;
440
+
}
441
+
#define CNA_CONV_CON3_NN_MODE__MASK 0x70000000
442
+
#define CNA_CONV_CON3_NN_MODE__SHIFT 28
443
+
static inline uint32_t CNA_CONV_CON3_NN_MODE(uint32_t val)
444
+
{
445
+
return ((val) << CNA_CONV_CON3_NN_MODE__SHIFT) & CNA_CONV_CON3_NN_MODE__MASK;
446
+
}
447
+
#define CNA_CONV_CON3_RESERVED_1__MASK 0x0c000000
448
+
#define CNA_CONV_CON3_RESERVED_1__SHIFT 26
449
+
static inline uint32_t CNA_CONV_CON3_RESERVED_1(uint32_t val)
450
+
{
451
+
return ((val) << CNA_CONV_CON3_RESERVED_1__SHIFT) & CNA_CONV_CON3_RESERVED_1__MASK;
452
+
}
453
+
#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK 0x03e00000
454
+
#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT 21
455
+
static inline uint32_t CNA_CONV_CON3_ATROUS_Y_DILATION(uint32_t val)
456
+
{
457
+
return ((val) << CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_Y_DILATION__MASK;
458
+
}
459
+
#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK 0x001f0000
460
+
#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT 16
461
+
static inline uint32_t CNA_CONV_CON3_ATROUS_X_DILATION(uint32_t val)
462
+
{
463
+
return ((val) << CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_X_DILATION__MASK;
464
+
}
465
+
#define CNA_CONV_CON3_RESERVED_2__MASK 0x0000c000
466
+
#define CNA_CONV_CON3_RESERVED_2__SHIFT 14
467
+
static inline uint32_t CNA_CONV_CON3_RESERVED_2(uint32_t val)
468
+
{
469
+
return ((val) << CNA_CONV_CON3_RESERVED_2__SHIFT) & CNA_CONV_CON3_RESERVED_2__MASK;
470
+
}
471
+
#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK 0x00003800
472
+
#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT 11
473
+
static inline uint32_t CNA_CONV_CON3_DECONV_Y_STRIDE(uint32_t val)
474
+
{
475
+
return ((val) << CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_Y_STRIDE__MASK;
476
+
}
477
+
#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK 0x00000700
478
+
#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT 8
479
+
static inline uint32_t CNA_CONV_CON3_DECONV_X_STRIDE(uint32_t val)
480
+
{
481
+
return ((val) << CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_X_STRIDE__MASK;
482
+
}
483
+
#define CNA_CONV_CON3_RESERVED_3__MASK 0x000000c0
484
+
#define CNA_CONV_CON3_RESERVED_3__SHIFT 6
485
+
static inline uint32_t CNA_CONV_CON3_RESERVED_3(uint32_t val)
486
+
{
487
+
return ((val) << CNA_CONV_CON3_RESERVED_3__SHIFT) & CNA_CONV_CON3_RESERVED_3__MASK;
488
+
}
489
+
#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK 0x00000038
490
+
#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT 3
491
+
static inline uint32_t CNA_CONV_CON3_CONV_Y_STRIDE(uint32_t val)
492
+
{
493
+
return ((val) << CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_Y_STRIDE__MASK;
494
+
}
495
+
#define CNA_CONV_CON3_CONV_X_STRIDE__MASK 0x00000007
496
+
#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT 0
497
+
static inline uint32_t CNA_CONV_CON3_CONV_X_STRIDE(uint32_t val)
498
+
{
499
+
return ((val) << CNA_CONV_CON3_CONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_X_STRIDE__MASK;
500
+
}
501
+
502
+
#define REG_CNA_DATA_SIZE0 0x00001020
503
+
#define CNA_DATA_SIZE0_RESERVED_0__MASK 0xf8000000
504
+
#define CNA_DATA_SIZE0_RESERVED_0__SHIFT 27
505
+
static inline uint32_t CNA_DATA_SIZE0_RESERVED_0(uint32_t val)
506
+
{
507
+
return ((val) << CNA_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_DATA_SIZE0_RESERVED_0__MASK;
508
+
}
509
+
#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK 0x07ff0000
510
+
#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT 16
511
+
static inline uint32_t CNA_DATA_SIZE0_DATAIN_WIDTH(uint32_t val)
512
+
{
513
+
return ((val) << CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT) & CNA_DATA_SIZE0_DATAIN_WIDTH__MASK;
514
+
}
515
+
#define CNA_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
516
+
#define CNA_DATA_SIZE0_RESERVED_1__SHIFT 11
517
+
static inline uint32_t CNA_DATA_SIZE0_RESERVED_1(uint32_t val)
518
+
{
519
+
return ((val) << CNA_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_DATA_SIZE0_RESERVED_1__MASK;
520
+
}
521
+
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK 0x000007ff
522
+
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT 0
523
+
static inline uint32_t CNA_DATA_SIZE0_DATAIN_HEIGHT(uint32_t val)
524
+
{
525
+
return ((val) << CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT) & CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK;
526
+
}
527
+
528
+
#define REG_CNA_DATA_SIZE1 0x00001024
529
+
#define CNA_DATA_SIZE1_RESERVED_0__MASK 0xc0000000
530
+
#define CNA_DATA_SIZE1_RESERVED_0__SHIFT 30
531
+
static inline uint32_t CNA_DATA_SIZE1_RESERVED_0(uint32_t val)
532
+
{
533
+
return ((val) << CNA_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_DATA_SIZE1_RESERVED_0__MASK;
534
+
}
535
+
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK 0x3fff0000
536
+
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT 16
537
+
static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(uint32_t val)
538
+
{
539
+
return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK;
540
+
}
541
+
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK 0x0000ffff
542
+
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT 0
543
+
static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL(uint32_t val)
544
+
{
545
+
return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK;
546
+
}
547
+
548
+
#define REG_CNA_DATA_SIZE2 0x00001028
549
+
#define CNA_DATA_SIZE2_RESERVED_0__MASK 0xfffff800
550
+
#define CNA_DATA_SIZE2_RESERVED_0__SHIFT 11
551
+
static inline uint32_t CNA_DATA_SIZE2_RESERVED_0(uint32_t val)
552
+
{
553
+
return ((val) << CNA_DATA_SIZE2_RESERVED_0__SHIFT) & CNA_DATA_SIZE2_RESERVED_0__MASK;
554
+
}
555
+
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK 0x000007ff
556
+
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT 0
557
+
static inline uint32_t CNA_DATA_SIZE2_DATAOUT_WIDTH(uint32_t val)
558
+
{
559
+
return ((val) << CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT) & CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK;
560
+
}
561
+
562
+
#define REG_CNA_DATA_SIZE3 0x0000102c
563
+
#define CNA_DATA_SIZE3_RESERVED_0__MASK 0xff000000
564
+
#define CNA_DATA_SIZE3_RESERVED_0__SHIFT 24
565
+
static inline uint32_t CNA_DATA_SIZE3_RESERVED_0(uint32_t val)
566
+
{
567
+
return ((val) << CNA_DATA_SIZE3_RESERVED_0__SHIFT) & CNA_DATA_SIZE3_RESERVED_0__MASK;
568
+
}
569
+
#define CNA_DATA_SIZE3_SURF_MODE__MASK 0x00c00000
570
+
#define CNA_DATA_SIZE3_SURF_MODE__SHIFT 22
571
+
static inline uint32_t CNA_DATA_SIZE3_SURF_MODE(uint32_t val)
572
+
{
573
+
return ((val) << CNA_DATA_SIZE3_SURF_MODE__SHIFT) & CNA_DATA_SIZE3_SURF_MODE__MASK;
574
+
}
575
+
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK 0x003fffff
576
+
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT 0
577
+
static inline uint32_t CNA_DATA_SIZE3_DATAOUT_ATOMICS(uint32_t val)
578
+
{
579
+
return ((val) << CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT) & CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK;
580
+
}
581
+
582
+
#define REG_CNA_WEIGHT_SIZE0 0x00001030
583
+
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK 0xffffffff
584
+
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT 0
585
+
static inline uint32_t CNA_WEIGHT_SIZE0_WEIGHT_BYTES(uint32_t val)
586
+
{
587
+
return ((val) << CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT) & CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK;
588
+
}
589
+
590
+
#define REG_CNA_WEIGHT_SIZE1 0x00001034
591
+
#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK 0xfff80000
592
+
#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT 19
593
+
static inline uint32_t CNA_WEIGHT_SIZE1_RESERVED_0(uint32_t val)
594
+
{
595
+
return ((val) << CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE1_RESERVED_0__MASK;
596
+
}
597
+
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK 0x0007ffff
598
+
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT 0
599
+
static inline uint32_t CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL(uint32_t val)
600
+
{
601
+
return ((val) << CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT) & CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK;
602
+
}
603
+
604
+
#define REG_CNA_WEIGHT_SIZE2 0x00001038
605
+
#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK 0xe0000000
606
+
#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT 29
607
+
static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_0(uint32_t val)
608
+
{
609
+
return ((val) << CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_0__MASK;
610
+
}
611
+
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK 0x1f000000
612
+
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT 24
613
+
static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(uint32_t val)
614
+
{
615
+
return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK;
616
+
}
617
+
#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK 0x00e00000
618
+
#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT 21
619
+
static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_1(uint32_t val)
620
+
{
621
+
return ((val) << CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_1__MASK;
622
+
}
623
+
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK 0x001f0000
624
+
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT 16
625
+
static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(uint32_t val)
626
+
{
627
+
return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK;
628
+
}
629
+
#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK 0x0000c000
630
+
#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT 14
631
+
static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_2(uint32_t val)
632
+
{
633
+
return ((val) << CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_2__MASK;
634
+
}
635
+
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK 0x00003fff
636
+
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT 0
637
+
static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(uint32_t val)
638
+
{
639
+
return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK;
640
+
}
641
+
642
+
#define REG_CNA_CBUF_CON0 0x00001040
643
+
#define CNA_CBUF_CON0_RESERVED_0__MASK 0xffffc000
644
+
#define CNA_CBUF_CON0_RESERVED_0__SHIFT 14
645
+
static inline uint32_t CNA_CBUF_CON0_RESERVED_0(uint32_t val)
646
+
{
647
+
return ((val) << CNA_CBUF_CON0_RESERVED_0__SHIFT) & CNA_CBUF_CON0_RESERVED_0__MASK;
648
+
}
649
+
#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK 0x00002000
650
+
#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT 13
651
+
static inline uint32_t CNA_CBUF_CON0_WEIGHT_REUSE(uint32_t val)
652
+
{
653
+
return ((val) << CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT) & CNA_CBUF_CON0_WEIGHT_REUSE__MASK;
654
+
}
655
+
#define CNA_CBUF_CON0_DATA_REUSE__MASK 0x00001000
656
+
#define CNA_CBUF_CON0_DATA_REUSE__SHIFT 12
657
+
static inline uint32_t CNA_CBUF_CON0_DATA_REUSE(uint32_t val)
658
+
{
659
+
return ((val) << CNA_CBUF_CON0_DATA_REUSE__SHIFT) & CNA_CBUF_CON0_DATA_REUSE__MASK;
660
+
}
661
+
#define CNA_CBUF_CON0_RESERVED_1__MASK 0x00000800
662
+
#define CNA_CBUF_CON0_RESERVED_1__SHIFT 11
663
+
static inline uint32_t CNA_CBUF_CON0_RESERVED_1(uint32_t val)
664
+
{
665
+
return ((val) << CNA_CBUF_CON0_RESERVED_1__SHIFT) & CNA_CBUF_CON0_RESERVED_1__MASK;
666
+
}
667
+
#define CNA_CBUF_CON0_FC_DATA_BANK__MASK 0x00000700
668
+
#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT 8
669
+
static inline uint32_t CNA_CBUF_CON0_FC_DATA_BANK(uint32_t val)
670
+
{
671
+
return ((val) << CNA_CBUF_CON0_FC_DATA_BANK__SHIFT) & CNA_CBUF_CON0_FC_DATA_BANK__MASK;
672
+
}
673
+
#define CNA_CBUF_CON0_WEIGHT_BANK__MASK 0x000000f0
674
+
#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT 4
675
+
static inline uint32_t CNA_CBUF_CON0_WEIGHT_BANK(uint32_t val)
676
+
{
677
+
return ((val) << CNA_CBUF_CON0_WEIGHT_BANK__SHIFT) & CNA_CBUF_CON0_WEIGHT_BANK__MASK;
678
+
}
679
+
#define CNA_CBUF_CON0_DATA_BANK__MASK 0x0000000f
680
+
#define CNA_CBUF_CON0_DATA_BANK__SHIFT 0
681
+
static inline uint32_t CNA_CBUF_CON0_DATA_BANK(uint32_t val)
682
+
{
683
+
return ((val) << CNA_CBUF_CON0_DATA_BANK__SHIFT) & CNA_CBUF_CON0_DATA_BANK__MASK;
684
+
}
685
+
686
+
#define REG_CNA_CBUF_CON1 0x00001044
687
+
#define CNA_CBUF_CON1_RESERVED_0__MASK 0xffffc000
688
+
#define CNA_CBUF_CON1_RESERVED_0__SHIFT 14
689
+
static inline uint32_t CNA_CBUF_CON1_RESERVED_0(uint32_t val)
690
+
{
691
+
return ((val) << CNA_CBUF_CON1_RESERVED_0__SHIFT) & CNA_CBUF_CON1_RESERVED_0__MASK;
692
+
}
693
+
#define CNA_CBUF_CON1_DATA_ENTRIES__MASK 0x00003fff
694
+
#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT 0
695
+
static inline uint32_t CNA_CBUF_CON1_DATA_ENTRIES(uint32_t val)
696
+
{
697
+
return ((val) << CNA_CBUF_CON1_DATA_ENTRIES__SHIFT) & CNA_CBUF_CON1_DATA_ENTRIES__MASK;
698
+
}
699
+
700
+
#define REG_CNA_CVT_CON0 0x0000104c
701
+
#define CNA_CVT_CON0_RESERVED_0__MASK 0xf0000000
702
+
#define CNA_CVT_CON0_RESERVED_0__SHIFT 28
703
+
static inline uint32_t CNA_CVT_CON0_RESERVED_0(uint32_t val)
704
+
{
705
+
return ((val) << CNA_CVT_CON0_RESERVED_0__SHIFT) & CNA_CVT_CON0_RESERVED_0__MASK;
706
+
}
707
+
#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK 0x0fc00000
708
+
#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT 22
709
+
static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_3(uint32_t val)
710
+
{
711
+
return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_3__MASK;
712
+
}
713
+
#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK 0x003f0000
714
+
#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT 16
715
+
static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_2(uint32_t val)
716
+
{
717
+
return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_2__MASK;
718
+
}
719
+
#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK 0x0000fc00
720
+
#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT 10
721
+
static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_1(uint32_t val)
722
+
{
723
+
return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_1__MASK;
724
+
}
725
+
#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK 0x000003f0
726
+
#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT 4
727
+
static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_0(uint32_t val)
728
+
{
729
+
return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_0__MASK;
730
+
}
731
+
#define CNA_CVT_CON0_DATA_SIGN__MASK 0x00000008
732
+
#define CNA_CVT_CON0_DATA_SIGN__SHIFT 3
733
+
static inline uint32_t CNA_CVT_CON0_DATA_SIGN(uint32_t val)
734
+
{
735
+
return ((val) << CNA_CVT_CON0_DATA_SIGN__SHIFT) & CNA_CVT_CON0_DATA_SIGN__MASK;
736
+
}
737
+
#define CNA_CVT_CON0_ROUND_TYPE__MASK 0x00000004
738
+
#define CNA_CVT_CON0_ROUND_TYPE__SHIFT 2
739
+
static inline uint32_t CNA_CVT_CON0_ROUND_TYPE(uint32_t val)
740
+
{
741
+
return ((val) << CNA_CVT_CON0_ROUND_TYPE__SHIFT) & CNA_CVT_CON0_ROUND_TYPE__MASK;
742
+
}
743
+
#define CNA_CVT_CON0_CVT_TYPE__MASK 0x00000002
744
+
#define CNA_CVT_CON0_CVT_TYPE__SHIFT 1
745
+
static inline uint32_t CNA_CVT_CON0_CVT_TYPE(uint32_t val)
746
+
{
747
+
return ((val) << CNA_CVT_CON0_CVT_TYPE__SHIFT) & CNA_CVT_CON0_CVT_TYPE__MASK;
748
+
}
749
+
#define CNA_CVT_CON0_CVT_BYPASS__MASK 0x00000001
750
+
#define CNA_CVT_CON0_CVT_BYPASS__SHIFT 0
751
+
static inline uint32_t CNA_CVT_CON0_CVT_BYPASS(uint32_t val)
752
+
{
753
+
return ((val) << CNA_CVT_CON0_CVT_BYPASS__SHIFT) & CNA_CVT_CON0_CVT_BYPASS__MASK;
754
+
}
755
+
756
+
#define REG_CNA_CVT_CON1 0x00001050
757
+
#define CNA_CVT_CON1_CVT_SCALE0__MASK 0xffff0000
758
+
#define CNA_CVT_CON1_CVT_SCALE0__SHIFT 16
759
+
static inline uint32_t CNA_CVT_CON1_CVT_SCALE0(uint32_t val)
760
+
{
761
+
return ((val) << CNA_CVT_CON1_CVT_SCALE0__SHIFT) & CNA_CVT_CON1_CVT_SCALE0__MASK;
762
+
}
763
+
#define CNA_CVT_CON1_CVT_OFFSET0__MASK 0x0000ffff
764
+
#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT 0
765
+
static inline uint32_t CNA_CVT_CON1_CVT_OFFSET0(uint32_t val)
766
+
{
767
+
return ((val) << CNA_CVT_CON1_CVT_OFFSET0__SHIFT) & CNA_CVT_CON1_CVT_OFFSET0__MASK;
768
+
}
769
+
770
+
#define REG_CNA_CVT_CON2 0x00001054
771
+
#define CNA_CVT_CON2_CVT_SCALE1__MASK 0xffff0000
772
+
#define CNA_CVT_CON2_CVT_SCALE1__SHIFT 16
773
+
static inline uint32_t CNA_CVT_CON2_CVT_SCALE1(uint32_t val)
774
+
{
775
+
return ((val) << CNA_CVT_CON2_CVT_SCALE1__SHIFT) & CNA_CVT_CON2_CVT_SCALE1__MASK;
776
+
}
777
+
#define CNA_CVT_CON2_CVT_OFFSET1__MASK 0x0000ffff
778
+
#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT 0
779
+
static inline uint32_t CNA_CVT_CON2_CVT_OFFSET1(uint32_t val)
780
+
{
781
+
return ((val) << CNA_CVT_CON2_CVT_OFFSET1__SHIFT) & CNA_CVT_CON2_CVT_OFFSET1__MASK;
782
+
}
783
+
784
+
#define REG_CNA_CVT_CON3 0x00001058
785
+
#define CNA_CVT_CON3_CVT_SCALE2__MASK 0xffff0000
786
+
#define CNA_CVT_CON3_CVT_SCALE2__SHIFT 16
787
+
static inline uint32_t CNA_CVT_CON3_CVT_SCALE2(uint32_t val)
788
+
{
789
+
return ((val) << CNA_CVT_CON3_CVT_SCALE2__SHIFT) & CNA_CVT_CON3_CVT_SCALE2__MASK;
790
+
}
791
+
#define CNA_CVT_CON3_CVT_OFFSET2__MASK 0x0000ffff
792
+
#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT 0
793
+
static inline uint32_t CNA_CVT_CON3_CVT_OFFSET2(uint32_t val)
794
+
{
795
+
return ((val) << CNA_CVT_CON3_CVT_OFFSET2__SHIFT) & CNA_CVT_CON3_CVT_OFFSET2__MASK;
796
+
}
797
+
798
+
#define REG_CNA_CVT_CON4 0x0000105c
799
+
#define CNA_CVT_CON4_CVT_SCALE3__MASK 0xffff0000
800
+
#define CNA_CVT_CON4_CVT_SCALE3__SHIFT 16
801
+
static inline uint32_t CNA_CVT_CON4_CVT_SCALE3(uint32_t val)
802
+
{
803
+
return ((val) << CNA_CVT_CON4_CVT_SCALE3__SHIFT) & CNA_CVT_CON4_CVT_SCALE3__MASK;
804
+
}
805
+
#define CNA_CVT_CON4_CVT_OFFSET3__MASK 0x0000ffff
806
+
#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT 0
807
+
static inline uint32_t CNA_CVT_CON4_CVT_OFFSET3(uint32_t val)
808
+
{
809
+
return ((val) << CNA_CVT_CON4_CVT_OFFSET3__SHIFT) & CNA_CVT_CON4_CVT_OFFSET3__MASK;
810
+
}
811
+
812
+
#define REG_CNA_FC_CON0 0x00001060
813
+
#define CNA_FC_CON0_FC_SKIP_DATA__MASK 0xffff0000
814
+
#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT 16
815
+
static inline uint32_t CNA_FC_CON0_FC_SKIP_DATA(uint32_t val)
816
+
{
817
+
return ((val) << CNA_FC_CON0_FC_SKIP_DATA__SHIFT) & CNA_FC_CON0_FC_SKIP_DATA__MASK;
818
+
}
819
+
#define CNA_FC_CON0_RESERVED_0__MASK 0x0000fffe
820
+
#define CNA_FC_CON0_RESERVED_0__SHIFT 1
821
+
static inline uint32_t CNA_FC_CON0_RESERVED_0(uint32_t val)
822
+
{
823
+
return ((val) << CNA_FC_CON0_RESERVED_0__SHIFT) & CNA_FC_CON0_RESERVED_0__MASK;
824
+
}
825
+
#define CNA_FC_CON0_FC_SKIP_EN__MASK 0x00000001
826
+
#define CNA_FC_CON0_FC_SKIP_EN__SHIFT 0
827
+
static inline uint32_t CNA_FC_CON0_FC_SKIP_EN(uint32_t val)
828
+
{
829
+
return ((val) << CNA_FC_CON0_FC_SKIP_EN__SHIFT) & CNA_FC_CON0_FC_SKIP_EN__MASK;
830
+
}
831
+
832
+
#define REG_CNA_FC_CON1 0x00001064
833
+
#define CNA_FC_CON1_RESERVED_0__MASK 0xfffe0000
834
+
#define CNA_FC_CON1_RESERVED_0__SHIFT 17
835
+
static inline uint32_t CNA_FC_CON1_RESERVED_0(uint32_t val)
836
+
{
837
+
return ((val) << CNA_FC_CON1_RESERVED_0__SHIFT) & CNA_FC_CON1_RESERVED_0__MASK;
838
+
}
839
+
#define CNA_FC_CON1_DATA_OFFSET__MASK 0x0001ffff
840
+
#define CNA_FC_CON1_DATA_OFFSET__SHIFT 0
841
+
static inline uint32_t CNA_FC_CON1_DATA_OFFSET(uint32_t val)
842
+
{
843
+
return ((val) << CNA_FC_CON1_DATA_OFFSET__SHIFT) & CNA_FC_CON1_DATA_OFFSET__MASK;
844
+
}
845
+
846
+
#define REG_CNA_PAD_CON0 0x00001068
847
+
#define CNA_PAD_CON0_RESERVED_0__MASK 0xffffff00
848
+
#define CNA_PAD_CON0_RESERVED_0__SHIFT 8
849
+
static inline uint32_t CNA_PAD_CON0_RESERVED_0(uint32_t val)
850
+
{
851
+
return ((val) << CNA_PAD_CON0_RESERVED_0__SHIFT) & CNA_PAD_CON0_RESERVED_0__MASK;
852
+
}
853
+
#define CNA_PAD_CON0_PAD_LEFT__MASK 0x000000f0
854
+
#define CNA_PAD_CON0_PAD_LEFT__SHIFT 4
855
+
static inline uint32_t CNA_PAD_CON0_PAD_LEFT(uint32_t val)
856
+
{
857
+
return ((val) << CNA_PAD_CON0_PAD_LEFT__SHIFT) & CNA_PAD_CON0_PAD_LEFT__MASK;
858
+
}
859
+
#define CNA_PAD_CON0_PAD_TOP__MASK 0x0000000f
860
+
#define CNA_PAD_CON0_PAD_TOP__SHIFT 0
861
+
static inline uint32_t CNA_PAD_CON0_PAD_TOP(uint32_t val)
862
+
{
863
+
return ((val) << CNA_PAD_CON0_PAD_TOP__SHIFT) & CNA_PAD_CON0_PAD_TOP__MASK;
864
+
}
865
+
866
+
#define REG_CNA_FEATURE_DATA_ADDR 0x00001070
867
+
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK 0xffffffff
868
+
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT 0
869
+
static inline uint32_t CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR(uint32_t val)
870
+
{
871
+
return ((val) << CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT) & CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK;
872
+
}
873
+
874
+
#define REG_CNA_FC_CON2 0x00001074
875
+
#define CNA_FC_CON2_RESERVED_0__MASK 0xfffe0000
876
+
#define CNA_FC_CON2_RESERVED_0__SHIFT 17
877
+
static inline uint32_t CNA_FC_CON2_RESERVED_0(uint32_t val)
878
+
{
879
+
return ((val) << CNA_FC_CON2_RESERVED_0__SHIFT) & CNA_FC_CON2_RESERVED_0__MASK;
880
+
}
881
+
#define CNA_FC_CON2_WEIGHT_OFFSET__MASK 0x0001ffff
882
+
#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT 0
883
+
static inline uint32_t CNA_FC_CON2_WEIGHT_OFFSET(uint32_t val)
884
+
{
885
+
return ((val) << CNA_FC_CON2_WEIGHT_OFFSET__SHIFT) & CNA_FC_CON2_WEIGHT_OFFSET__MASK;
886
+
}
887
+
888
+
#define REG_CNA_DMA_CON0 0x00001078
889
+
#define CNA_DMA_CON0_OV4K_BYPASS__MASK 0x80000000
890
+
#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT 31
891
+
static inline uint32_t CNA_DMA_CON0_OV4K_BYPASS(uint32_t val)
892
+
{
893
+
return ((val) << CNA_DMA_CON0_OV4K_BYPASS__SHIFT) & CNA_DMA_CON0_OV4K_BYPASS__MASK;
894
+
}
895
+
#define CNA_DMA_CON0_RESERVED_0__MASK 0x7ff00000
896
+
#define CNA_DMA_CON0_RESERVED_0__SHIFT 20
897
+
static inline uint32_t CNA_DMA_CON0_RESERVED_0(uint32_t val)
898
+
{
899
+
return ((val) << CNA_DMA_CON0_RESERVED_0__SHIFT) & CNA_DMA_CON0_RESERVED_0__MASK;
900
+
}
901
+
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK 0x000f0000
902
+
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT 16
903
+
static inline uint32_t CNA_DMA_CON0_WEIGHT_BURST_LEN(uint32_t val)
904
+
{
905
+
return ((val) << CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT) & CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK;
906
+
}
907
+
#define CNA_DMA_CON0_RESERVED_1__MASK 0x0000fff0
908
+
#define CNA_DMA_CON0_RESERVED_1__SHIFT 4
909
+
static inline uint32_t CNA_DMA_CON0_RESERVED_1(uint32_t val)
910
+
{
911
+
return ((val) << CNA_DMA_CON0_RESERVED_1__SHIFT) & CNA_DMA_CON0_RESERVED_1__MASK;
912
+
}
913
+
#define CNA_DMA_CON0_DATA_BURST_LEN__MASK 0x0000000f
914
+
#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT 0
915
+
static inline uint32_t CNA_DMA_CON0_DATA_BURST_LEN(uint32_t val)
916
+
{
917
+
return ((val) << CNA_DMA_CON0_DATA_BURST_LEN__SHIFT) & CNA_DMA_CON0_DATA_BURST_LEN__MASK;
918
+
}
919
+
920
+
#define REG_CNA_DMA_CON1 0x0000107c
921
+
#define CNA_DMA_CON1_RESERVED_0__MASK 0xf0000000
922
+
#define CNA_DMA_CON1_RESERVED_0__SHIFT 28
923
+
static inline uint32_t CNA_DMA_CON1_RESERVED_0(uint32_t val)
924
+
{
925
+
return ((val) << CNA_DMA_CON1_RESERVED_0__SHIFT) & CNA_DMA_CON1_RESERVED_0__MASK;
926
+
}
927
+
#define CNA_DMA_CON1_LINE_STRIDE__MASK 0x0fffffff
928
+
#define CNA_DMA_CON1_LINE_STRIDE__SHIFT 0
929
+
static inline uint32_t CNA_DMA_CON1_LINE_STRIDE(uint32_t val)
930
+
{
931
+
return ((val) << CNA_DMA_CON1_LINE_STRIDE__SHIFT) & CNA_DMA_CON1_LINE_STRIDE__MASK;
932
+
}
933
+
934
+
#define REG_CNA_DMA_CON2 0x00001080
935
+
#define CNA_DMA_CON2_RESERVED_0__MASK 0xf0000000
936
+
#define CNA_DMA_CON2_RESERVED_0__SHIFT 28
937
+
static inline uint32_t CNA_DMA_CON2_RESERVED_0(uint32_t val)
938
+
{
939
+
return ((val) << CNA_DMA_CON2_RESERVED_0__SHIFT) & CNA_DMA_CON2_RESERVED_0__MASK;
940
+
}
941
+
#define CNA_DMA_CON2_SURF_STRIDE__MASK 0x0fffffff
942
+
#define CNA_DMA_CON2_SURF_STRIDE__SHIFT 0
943
+
static inline uint32_t CNA_DMA_CON2_SURF_STRIDE(uint32_t val)
944
+
{
945
+
return ((val) << CNA_DMA_CON2_SURF_STRIDE__SHIFT) & CNA_DMA_CON2_SURF_STRIDE__MASK;
946
+
}
947
+
948
+
#define REG_CNA_FC_DATA_SIZE0 0x00001084
949
+
#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK 0xc0000000
950
+
#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT 30
951
+
static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_0(uint32_t val)
952
+
{
953
+
return ((val) << CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_0__MASK;
954
+
}
955
+
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK 0x3fff0000
956
+
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT 16
957
+
static inline uint32_t CNA_FC_DATA_SIZE0_DMA_WIDTH(uint32_t val)
958
+
{
959
+
return ((val) << CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT) & CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK;
960
+
}
961
+
#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
962
+
#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT 11
963
+
static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_1(uint32_t val)
964
+
{
965
+
return ((val) << CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_1__MASK;
966
+
}
967
+
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK 0x000007ff
968
+
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT 0
969
+
static inline uint32_t CNA_FC_DATA_SIZE0_DMA_HEIGHT(uint32_t val)
970
+
{
971
+
return ((val) << CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT) & CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK;
972
+
}
973
+
974
+
#define REG_CNA_FC_DATA_SIZE1 0x00001088
975
+
#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK 0xffff0000
976
+
#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT 16
977
+
static inline uint32_t CNA_FC_DATA_SIZE1_RESERVED_0(uint32_t val)
978
+
{
979
+
return ((val) << CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE1_RESERVED_0__MASK;
980
+
}
981
+
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK 0x0000ffff
982
+
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT 0
983
+
static inline uint32_t CNA_FC_DATA_SIZE1_DMA_CHANNEL(uint32_t val)
984
+
{
985
+
return ((val) << CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT) & CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK;
986
+
}
987
+
988
+
#define REG_CNA_CLK_GATE 0x00001090
989
+
#define CNA_CLK_GATE_RESERVED_0__MASK 0xffffffe0
990
+
#define CNA_CLK_GATE_RESERVED_0__SHIFT 5
991
+
static inline uint32_t CNA_CLK_GATE_RESERVED_0(uint32_t val)
992
+
{
993
+
return ((val) << CNA_CLK_GATE_RESERVED_0__SHIFT) & CNA_CLK_GATE_RESERVED_0__MASK;
994
+
}
995
+
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK 0x00000010
996
+
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT 4
997
+
static inline uint32_t CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE(uint32_t val)
998
+
{
999
+
return ((val) << CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK;
1000
+
}
1001
+
#define CNA_CLK_GATE_RESERVED_1__MASK 0x00000008
1002
+
#define CNA_CLK_GATE_RESERVED_1__SHIFT 3
1003
+
static inline uint32_t CNA_CLK_GATE_RESERVED_1(uint32_t val)
1004
+
{
1005
+
return ((val) << CNA_CLK_GATE_RESERVED_1__SHIFT) & CNA_CLK_GATE_RESERVED_1__MASK;
1006
+
}
1007
+
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK 0x00000004
1008
+
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT 2
1009
+
static inline uint32_t CNA_CLK_GATE_CSC_DISABLE_CLKGATE(uint32_t val)
1010
+
{
1011
+
return ((val) << CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK;
1012
+
}
1013
+
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK 0x00000002
1014
+
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT 1
1015
+
static inline uint32_t CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE(uint32_t val)
1016
+
{
1017
+
return ((val) << CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK;
1018
+
}
1019
+
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK 0x00000001
1020
+
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT 0
1021
+
static inline uint32_t CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE(uint32_t val)
1022
+
{
1023
+
return ((val) << CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK;
1024
+
}
1025
+
1026
+
#define REG_CNA_DCOMP_CTRL 0x00001100
1027
+
#define CNA_DCOMP_CTRL_RESERVED_0__MASK 0xfffffff0
1028
+
#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT 4
1029
+
static inline uint32_t CNA_DCOMP_CTRL_RESERVED_0(uint32_t val)
1030
+
{
1031
+
return ((val) << CNA_DCOMP_CTRL_RESERVED_0__SHIFT) & CNA_DCOMP_CTRL_RESERVED_0__MASK;
1032
+
}
1033
+
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK 0x00000008
1034
+
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT 3
1035
+
static inline uint32_t CNA_DCOMP_CTRL_WT_DEC_BYPASS(uint32_t val)
1036
+
{
1037
+
return ((val) << CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT) & CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK;
1038
+
}
1039
+
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK 0x00000007
1040
+
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT 0
1041
+
static inline uint32_t CNA_DCOMP_CTRL_DECOMP_CONTROL(uint32_t val)
1042
+
{
1043
+
return ((val) << CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT) & CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK;
1044
+
}
1045
+
1046
+
#define REG_CNA_DCOMP_REGNUM 0x00001104
1047
+
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK 0xffffffff
1048
+
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT 0
1049
+
static inline uint32_t CNA_DCOMP_REGNUM_DCOMP_REGNUM(uint32_t val)
1050
+
{
1051
+
return ((val) << CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT) & CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK;
1052
+
}
1053
+
1054
+
#define REG_CNA_DCOMP_ADDR0 0x00001110
1055
+
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK 0xffffffff
1056
+
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT 0
1057
+
static inline uint32_t CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0(uint32_t val)
1058
+
{
1059
+
return ((val) << CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT) & CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK;
1060
+
}
1061
+
1062
+
#define REG_CNA_DCOMP_AMOUNT0 0x00001140
1063
+
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK 0xffffffff
1064
+
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT 0
1065
+
static inline uint32_t CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0(uint32_t val)
1066
+
{
1067
+
return ((val) << CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT) & CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK;
1068
+
}
1069
+
1070
+
#define REG_CNA_DCOMP_AMOUNT1 0x00001144
1071
+
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK 0xffffffff
1072
+
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT 0
1073
+
static inline uint32_t CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1(uint32_t val)
1074
+
{
1075
+
return ((val) << CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT) & CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK;
1076
+
}
1077
+
1078
+
#define REG_CNA_DCOMP_AMOUNT2 0x00001148
1079
+
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK 0xffffffff
1080
+
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT 0
1081
+
static inline uint32_t CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2(uint32_t val)
1082
+
{
1083
+
return ((val) << CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT) & CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK;
1084
+
}
1085
+
1086
+
#define REG_CNA_DCOMP_AMOUNT3 0x0000114c
1087
+
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK 0xffffffff
1088
+
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT 0
1089
+
static inline uint32_t CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3(uint32_t val)
1090
+
{
1091
+
return ((val) << CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT) & CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK;
1092
+
}
1093
+
1094
+
#define REG_CNA_DCOMP_AMOUNT4 0x00001150
1095
+
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK 0xffffffff
1096
+
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT 0
1097
+
static inline uint32_t CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4(uint32_t val)
1098
+
{
1099
+
return ((val) << CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT) & CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK;
1100
+
}
1101
+
1102
+
#define REG_CNA_DCOMP_AMOUNT5 0x00001154
1103
+
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK 0xffffffff
1104
+
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT 0
1105
+
static inline uint32_t CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5(uint32_t val)
1106
+
{
1107
+
return ((val) << CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT) & CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK;
1108
+
}
1109
+
1110
+
#define REG_CNA_DCOMP_AMOUNT6 0x00001158
1111
+
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK 0xffffffff
1112
+
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT 0
1113
+
static inline uint32_t CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6(uint32_t val)
1114
+
{
1115
+
return ((val) << CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT) & CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK;
1116
+
}
1117
+
1118
+
#define REG_CNA_DCOMP_AMOUNT7 0x0000115c
1119
+
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK 0xffffffff
1120
+
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT 0
1121
+
static inline uint32_t CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7(uint32_t val)
1122
+
{
1123
+
return ((val) << CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT) & CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK;
1124
+
}
1125
+
1126
+
#define REG_CNA_DCOMP_AMOUNT8 0x00001160
1127
+
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK 0xffffffff
1128
+
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT 0
1129
+
static inline uint32_t CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8(uint32_t val)
1130
+
{
1131
+
return ((val) << CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT) & CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK;
1132
+
}
1133
+
1134
+
#define REG_CNA_DCOMP_AMOUNT9 0x00001164
1135
+
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK 0xffffffff
1136
+
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT 0
1137
+
static inline uint32_t CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9(uint32_t val)
1138
+
{
1139
+
return ((val) << CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT) & CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK;
1140
+
}
1141
+
1142
+
#define REG_CNA_DCOMP_AMOUNT10 0x00001168
1143
+
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK 0xffffffff
1144
+
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT 0
1145
+
static inline uint32_t CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10(uint32_t val)
1146
+
{
1147
+
return ((val) << CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT) & CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK;
1148
+
}
1149
+
1150
+
#define REG_CNA_DCOMP_AMOUNT11 0x0000116c
1151
+
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK 0xffffffff
1152
+
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT 0
1153
+
static inline uint32_t CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11(uint32_t val)
1154
+
{
1155
+
return ((val) << CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT) & CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK;
1156
+
}
1157
+
1158
+
#define REG_CNA_DCOMP_AMOUNT12 0x00001170
1159
+
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK 0xffffffff
1160
+
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT 0
1161
+
static inline uint32_t CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12(uint32_t val)
1162
+
{
1163
+
return ((val) << CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT) & CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK;
1164
+
}
1165
+
1166
+
#define REG_CNA_DCOMP_AMOUNT13 0x00001174
1167
+
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK 0xffffffff
1168
+
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT 0
1169
+
static inline uint32_t CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13(uint32_t val)
1170
+
{
1171
+
return ((val) << CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT) & CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK;
1172
+
}
1173
+
1174
+
#define REG_CNA_DCOMP_AMOUNT14 0x00001178
1175
+
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK 0xffffffff
1176
+
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT 0
1177
+
static inline uint32_t CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14(uint32_t val)
1178
+
{
1179
+
return ((val) << CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT) & CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK;
1180
+
}
1181
+
1182
+
#define REG_CNA_DCOMP_AMOUNT15 0x0000117c
1183
+
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK 0xffffffff
1184
+
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT 0
1185
+
static inline uint32_t CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15(uint32_t val)
1186
+
{
1187
+
return ((val) << CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT) & CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK;
1188
+
}
1189
+
1190
+
#define REG_CNA_CVT_CON5 0x00001180
1191
+
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK 0xffffffff
1192
+
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT 0
1193
+
static inline uint32_t CNA_CVT_CON5_PER_CHANNEL_CVT_EN(uint32_t val)
1194
+
{
1195
+
return ((val) << CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT) & CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK;
1196
+
}
1197
+
1198
+
#define REG_CNA_PAD_CON1 0x00001184
1199
+
#define CNA_PAD_CON1_PAD_VALUE__MASK 0xffffffff
1200
+
#define CNA_PAD_CON1_PAD_VALUE__SHIFT 0
1201
+
static inline uint32_t CNA_PAD_CON1_PAD_VALUE(uint32_t val)
1202
+
{
1203
+
return ((val) << CNA_PAD_CON1_PAD_VALUE__SHIFT) & CNA_PAD_CON1_PAD_VALUE__MASK;
1204
+
}
1205
+
1206
+
#define REG_CORE_S_STATUS 0x00003000
1207
+
#define CORE_S_STATUS_RESERVED_0__MASK 0xfffc0000
1208
+
#define CORE_S_STATUS_RESERVED_0__SHIFT 18
1209
+
static inline uint32_t CORE_S_STATUS_RESERVED_0(uint32_t val)
1210
+
{
1211
+
return ((val) << CORE_S_STATUS_RESERVED_0__SHIFT) & CORE_S_STATUS_RESERVED_0__MASK;
1212
+
}
1213
+
#define CORE_S_STATUS_STATUS_1__MASK 0x00030000
1214
+
#define CORE_S_STATUS_STATUS_1__SHIFT 16
1215
+
static inline uint32_t CORE_S_STATUS_STATUS_1(uint32_t val)
1216
+
{
1217
+
return ((val) << CORE_S_STATUS_STATUS_1__SHIFT) & CORE_S_STATUS_STATUS_1__MASK;
1218
+
}
1219
+
#define CORE_S_STATUS_RESERVED_1__MASK 0x0000fffc
1220
+
#define CORE_S_STATUS_RESERVED_1__SHIFT 2
1221
+
static inline uint32_t CORE_S_STATUS_RESERVED_1(uint32_t val)
1222
+
{
1223
+
return ((val) << CORE_S_STATUS_RESERVED_1__SHIFT) & CORE_S_STATUS_RESERVED_1__MASK;
1224
+
}
1225
+
#define CORE_S_STATUS_STATUS_0__MASK 0x00000003
1226
+
#define CORE_S_STATUS_STATUS_0__SHIFT 0
1227
+
static inline uint32_t CORE_S_STATUS_STATUS_0(uint32_t val)
1228
+
{
1229
+
return ((val) << CORE_S_STATUS_STATUS_0__SHIFT) & CORE_S_STATUS_STATUS_0__MASK;
1230
+
}
1231
+
1232
+
#define REG_CORE_S_POINTER 0x00003004
1233
+
#define CORE_S_POINTER_RESERVED_0__MASK 0xfffe0000
1234
+
#define CORE_S_POINTER_RESERVED_0__SHIFT 17
1235
+
static inline uint32_t CORE_S_POINTER_RESERVED_0(uint32_t val)
1236
+
{
1237
+
return ((val) << CORE_S_POINTER_RESERVED_0__SHIFT) & CORE_S_POINTER_RESERVED_0__MASK;
1238
+
}
1239
+
#define CORE_S_POINTER_EXECUTER__MASK 0x00010000
1240
+
#define CORE_S_POINTER_EXECUTER__SHIFT 16
1241
+
static inline uint32_t CORE_S_POINTER_EXECUTER(uint32_t val)
1242
+
{
1243
+
return ((val) << CORE_S_POINTER_EXECUTER__SHIFT) & CORE_S_POINTER_EXECUTER__MASK;
1244
+
}
1245
+
#define CORE_S_POINTER_RESERVED_1__MASK 0x0000ffc0
1246
+
#define CORE_S_POINTER_RESERVED_1__SHIFT 6
1247
+
static inline uint32_t CORE_S_POINTER_RESERVED_1(uint32_t val)
1248
+
{
1249
+
return ((val) << CORE_S_POINTER_RESERVED_1__SHIFT) & CORE_S_POINTER_RESERVED_1__MASK;
1250
+
}
1251
+
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
1252
+
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
1253
+
static inline uint32_t CORE_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
1254
+
{
1255
+
return ((val) << CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK;
1256
+
}
1257
+
#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
1258
+
#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
1259
+
static inline uint32_t CORE_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
1260
+
{
1261
+
return ((val) << CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_POINTER_PP_CLEAR__MASK;
1262
+
}
1263
+
#define CORE_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
1264
+
#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT 3
1265
+
static inline uint32_t CORE_S_POINTER_POINTER_PP_MODE(uint32_t val)
1266
+
{
1267
+
return ((val) << CORE_S_POINTER_POINTER_PP_MODE__SHIFT) & CORE_S_POINTER_POINTER_PP_MODE__MASK;
1268
+
}
1269
+
#define CORE_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
1270
+
#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT 2
1271
+
static inline uint32_t CORE_S_POINTER_EXECUTER_PP_EN(uint32_t val)
1272
+
{
1273
+
return ((val) << CORE_S_POINTER_EXECUTER_PP_EN__SHIFT) & CORE_S_POINTER_EXECUTER_PP_EN__MASK;
1274
+
}
1275
+
#define CORE_S_POINTER_POINTER_PP_EN__MASK 0x00000002
1276
+
#define CORE_S_POINTER_POINTER_PP_EN__SHIFT 1
1277
+
static inline uint32_t CORE_S_POINTER_POINTER_PP_EN(uint32_t val)
1278
+
{
1279
+
return ((val) << CORE_S_POINTER_POINTER_PP_EN__SHIFT) & CORE_S_POINTER_POINTER_PP_EN__MASK;
1280
+
}
1281
+
#define CORE_S_POINTER_POINTER__MASK 0x00000001
1282
+
#define CORE_S_POINTER_POINTER__SHIFT 0
1283
+
static inline uint32_t CORE_S_POINTER_POINTER(uint32_t val)
1284
+
{
1285
+
return ((val) << CORE_S_POINTER_POINTER__SHIFT) & CORE_S_POINTER_POINTER__MASK;
1286
+
}
1287
+
1288
+
#define REG_CORE_OPERATION_ENABLE 0x00003008
1289
+
#define CORE_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
1290
+
#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT 1
1291
+
static inline uint32_t CORE_OPERATION_ENABLE_RESERVED_0(uint32_t val)
1292
+
{
1293
+
return ((val) << CORE_OPERATION_ENABLE_RESERVED_0__SHIFT) & CORE_OPERATION_ENABLE_RESERVED_0__MASK;
1294
+
}
1295
+
#define CORE_OPERATION_ENABLE_OP_EN__MASK 0x00000001
1296
+
#define CORE_OPERATION_ENABLE_OP_EN__SHIFT 0
1297
+
static inline uint32_t CORE_OPERATION_ENABLE_OP_EN(uint32_t val)
1298
+
{
1299
+
return ((val) << CORE_OPERATION_ENABLE_OP_EN__SHIFT) & CORE_OPERATION_ENABLE_OP_EN__MASK;
1300
+
}
1301
+
1302
+
#define REG_CORE_MAC_GATING 0x0000300c
1303
+
#define CORE_MAC_GATING_RESERVED_0__MASK 0xf8000000
1304
+
#define CORE_MAC_GATING_RESERVED_0__SHIFT 27
1305
+
static inline uint32_t CORE_MAC_GATING_RESERVED_0(uint32_t val)
1306
+
{
1307
+
return ((val) << CORE_MAC_GATING_RESERVED_0__SHIFT) & CORE_MAC_GATING_RESERVED_0__MASK;
1308
+
}
1309
+
#define CORE_MAC_GATING_SLCG_OP_EN__MASK 0x07ffffff
1310
+
#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT 0
1311
+
static inline uint32_t CORE_MAC_GATING_SLCG_OP_EN(uint32_t val)
1312
+
{
1313
+
return ((val) << CORE_MAC_GATING_SLCG_OP_EN__SHIFT) & CORE_MAC_GATING_SLCG_OP_EN__MASK;
1314
+
}
1315
+
1316
+
#define REG_CORE_MISC_CFG 0x00003010
1317
+
#define CORE_MISC_CFG_RESERVED_0__MASK 0xfff00000
1318
+
#define CORE_MISC_CFG_RESERVED_0__SHIFT 20
1319
+
static inline uint32_t CORE_MISC_CFG_RESERVED_0(uint32_t val)
1320
+
{
1321
+
return ((val) << CORE_MISC_CFG_RESERVED_0__SHIFT) & CORE_MISC_CFG_RESERVED_0__MASK;
1322
+
}
1323
+
#define CORE_MISC_CFG_SOFT_GATING__MASK 0x000fc000
1324
+
#define CORE_MISC_CFG_SOFT_GATING__SHIFT 14
1325
+
static inline uint32_t CORE_MISC_CFG_SOFT_GATING(uint32_t val)
1326
+
{
1327
+
return ((val) << CORE_MISC_CFG_SOFT_GATING__SHIFT) & CORE_MISC_CFG_SOFT_GATING__MASK;
1328
+
}
1329
+
#define CORE_MISC_CFG_RESERVED_1__MASK 0x00003800
1330
+
#define CORE_MISC_CFG_RESERVED_1__SHIFT 11
1331
+
static inline uint32_t CORE_MISC_CFG_RESERVED_1(uint32_t val)
1332
+
{
1333
+
return ((val) << CORE_MISC_CFG_RESERVED_1__SHIFT) & CORE_MISC_CFG_RESERVED_1__MASK;
1334
+
}
1335
+
#define CORE_MISC_CFG_PROC_PRECISION__MASK 0x00000700
1336
+
#define CORE_MISC_CFG_PROC_PRECISION__SHIFT 8
1337
+
static inline uint32_t CORE_MISC_CFG_PROC_PRECISION(uint32_t val)
1338
+
{
1339
+
return ((val) << CORE_MISC_CFG_PROC_PRECISION__SHIFT) & CORE_MISC_CFG_PROC_PRECISION__MASK;
1340
+
}
1341
+
#define CORE_MISC_CFG_RESERVED_2__MASK 0x000000fc
1342
+
#define CORE_MISC_CFG_RESERVED_2__SHIFT 2
1343
+
static inline uint32_t CORE_MISC_CFG_RESERVED_2(uint32_t val)
1344
+
{
1345
+
return ((val) << CORE_MISC_CFG_RESERVED_2__SHIFT) & CORE_MISC_CFG_RESERVED_2__MASK;
1346
+
}
1347
+
#define CORE_MISC_CFG_DW_EN__MASK 0x00000002
1348
+
#define CORE_MISC_CFG_DW_EN__SHIFT 1
1349
+
static inline uint32_t CORE_MISC_CFG_DW_EN(uint32_t val)
1350
+
{
1351
+
return ((val) << CORE_MISC_CFG_DW_EN__SHIFT) & CORE_MISC_CFG_DW_EN__MASK;
1352
+
}
1353
+
#define CORE_MISC_CFG_QD_EN__MASK 0x00000001
1354
+
#define CORE_MISC_CFG_QD_EN__SHIFT 0
1355
+
static inline uint32_t CORE_MISC_CFG_QD_EN(uint32_t val)
1356
+
{
1357
+
return ((val) << CORE_MISC_CFG_QD_EN__SHIFT) & CORE_MISC_CFG_QD_EN__MASK;
1358
+
}
1359
+
1360
+
#define REG_CORE_DATAOUT_SIZE_0 0x00003014
1361
+
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK 0xffff0000
1362
+
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT 16
1363
+
static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT(uint32_t val)
1364
+
{
1365
+
return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK;
1366
+
}
1367
+
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK 0x0000ffff
1368
+
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT 0
1369
+
static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH(uint32_t val)
1370
+
{
1371
+
return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK;
1372
+
}
1373
+
1374
+
#define REG_CORE_DATAOUT_SIZE_1 0x00003018
1375
+
#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK 0xffff0000
1376
+
#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT 16
1377
+
static inline uint32_t CORE_DATAOUT_SIZE_1_RESERVED_0(uint32_t val)
1378
+
{
1379
+
return ((val) << CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT) & CORE_DATAOUT_SIZE_1_RESERVED_0__MASK;
1380
+
}
1381
+
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK 0x0000ffff
1382
+
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT 0
1383
+
static inline uint32_t CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL(uint32_t val)
1384
+
{
1385
+
return ((val) << CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT) & CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK;
1386
+
}
1387
+
1388
+
#define REG_CORE_CLIP_TRUNCATE 0x0000301c
1389
+
#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK 0xffffff80
1390
+
#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT 7
1391
+
static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_0(uint32_t val)
1392
+
{
1393
+
return ((val) << CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_0__MASK;
1394
+
}
1395
+
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK 0x00000040
1396
+
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT 6
1397
+
static inline uint32_t CORE_CLIP_TRUNCATE_ROUND_TYPE(uint32_t val)
1398
+
{
1399
+
return ((val) << CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT) & CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK;
1400
+
}
1401
+
#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK 0x00000020
1402
+
#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT 5
1403
+
static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_1(uint32_t val)
1404
+
{
1405
+
return ((val) << CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_1__MASK;
1406
+
}
1407
+
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK 0x0000001f
1408
+
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT 0
1409
+
static inline uint32_t CORE_CLIP_TRUNCATE_CLIP_TRUNCATE(uint32_t val)
1410
+
{
1411
+
return ((val) << CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT) & CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK;
1412
+
}
1413
+
1414
+
#define REG_DPU_S_STATUS 0x00004000
1415
+
#define DPU_S_STATUS_RESERVED_0__MASK 0xfffc0000
1416
+
#define DPU_S_STATUS_RESERVED_0__SHIFT 18
1417
+
static inline uint32_t DPU_S_STATUS_RESERVED_0(uint32_t val)
1418
+
{
1419
+
return ((val) << DPU_S_STATUS_RESERVED_0__SHIFT) & DPU_S_STATUS_RESERVED_0__MASK;
1420
+
}
1421
+
#define DPU_S_STATUS_STATUS_1__MASK 0x00030000
1422
+
#define DPU_S_STATUS_STATUS_1__SHIFT 16
1423
+
static inline uint32_t DPU_S_STATUS_STATUS_1(uint32_t val)
1424
+
{
1425
+
return ((val) << DPU_S_STATUS_STATUS_1__SHIFT) & DPU_S_STATUS_STATUS_1__MASK;
1426
+
}
1427
+
#define DPU_S_STATUS_RESERVED_1__MASK 0x0000fffc
1428
+
#define DPU_S_STATUS_RESERVED_1__SHIFT 2
1429
+
static inline uint32_t DPU_S_STATUS_RESERVED_1(uint32_t val)
1430
+
{
1431
+
return ((val) << DPU_S_STATUS_RESERVED_1__SHIFT) & DPU_S_STATUS_RESERVED_1__MASK;
1432
+
}
1433
+
#define DPU_S_STATUS_STATUS_0__MASK 0x00000003
1434
+
#define DPU_S_STATUS_STATUS_0__SHIFT 0
1435
+
static inline uint32_t DPU_S_STATUS_STATUS_0(uint32_t val)
1436
+
{
1437
+
return ((val) << DPU_S_STATUS_STATUS_0__SHIFT) & DPU_S_STATUS_STATUS_0__MASK;
1438
+
}
1439
+
1440
+
#define REG_DPU_S_POINTER 0x00004004
1441
+
#define DPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
1442
+
#define DPU_S_POINTER_RESERVED_0__SHIFT 17
1443
+
static inline uint32_t DPU_S_POINTER_RESERVED_0(uint32_t val)
1444
+
{
1445
+
return ((val) << DPU_S_POINTER_RESERVED_0__SHIFT) & DPU_S_POINTER_RESERVED_0__MASK;
1446
+
}
1447
+
#define DPU_S_POINTER_EXECUTER__MASK 0x00010000
1448
+
#define DPU_S_POINTER_EXECUTER__SHIFT 16
1449
+
static inline uint32_t DPU_S_POINTER_EXECUTER(uint32_t val)
1450
+
{
1451
+
return ((val) << DPU_S_POINTER_EXECUTER__SHIFT) & DPU_S_POINTER_EXECUTER__MASK;
1452
+
}
1453
+
#define DPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
1454
+
#define DPU_S_POINTER_RESERVED_1__SHIFT 6
1455
+
static inline uint32_t DPU_S_POINTER_RESERVED_1(uint32_t val)
1456
+
{
1457
+
return ((val) << DPU_S_POINTER_RESERVED_1__SHIFT) & DPU_S_POINTER_RESERVED_1__MASK;
1458
+
}
1459
+
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
1460
+
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
1461
+
static inline uint32_t DPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
1462
+
{
1463
+
return ((val) << DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
1464
+
}
1465
+
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
1466
+
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
1467
+
static inline uint32_t DPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
1468
+
{
1469
+
return ((val) << DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_POINTER_PP_CLEAR__MASK;
1470
+
}
1471
+
#define DPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
1472
+
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
1473
+
static inline uint32_t DPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
1474
+
{
1475
+
return ((val) << DPU_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_S_POINTER_POINTER_PP_MODE__MASK;
1476
+
}
1477
+
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
1478
+
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
1479
+
static inline uint32_t DPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
1480
+
{
1481
+
return ((val) << DPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_S_POINTER_EXECUTER_PP_EN__MASK;
1482
+
}
1483
+
#define DPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
1484
+
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT 1
1485
+
static inline uint32_t DPU_S_POINTER_POINTER_PP_EN(uint32_t val)
1486
+
{
1487
+
return ((val) << DPU_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_S_POINTER_POINTER_PP_EN__MASK;
1488
+
}
1489
+
#define DPU_S_POINTER_POINTER__MASK 0x00000001
1490
+
#define DPU_S_POINTER_POINTER__SHIFT 0
1491
+
static inline uint32_t DPU_S_POINTER_POINTER(uint32_t val)
1492
+
{
1493
+
return ((val) << DPU_S_POINTER_POINTER__SHIFT) & DPU_S_POINTER_POINTER__MASK;
1494
+
}
1495
+
1496
+
#define REG_DPU_OPERATION_ENABLE 0x00004008
1497
+
#define DPU_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
1498
+
#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT 1
1499
+
static inline uint32_t DPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
1500
+
{
1501
+
return ((val) << DPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_OPERATION_ENABLE_RESERVED_0__MASK;
1502
+
}
1503
+
#define DPU_OPERATION_ENABLE_OP_EN__MASK 0x00000001
1504
+
#define DPU_OPERATION_ENABLE_OP_EN__SHIFT 0
1505
+
static inline uint32_t DPU_OPERATION_ENABLE_OP_EN(uint32_t val)
1506
+
{
1507
+
return ((val) << DPU_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_OPERATION_ENABLE_OP_EN__MASK;
1508
+
}
1509
+
1510
+
#define REG_DPU_FEATURE_MODE_CFG 0x0000400c
1511
+
#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK 0x80000000
1512
+
#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT 31
1513
+
static inline uint32_t DPU_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
1514
+
{
1515
+
return ((val) << DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_FEATURE_MODE_CFG_COMB_USE__MASK;
1516
+
}
1517
+
#define DPU_FEATURE_MODE_CFG_TP_EN__MASK 0x40000000
1518
+
#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT 30
1519
+
static inline uint32_t DPU_FEATURE_MODE_CFG_TP_EN(uint32_t val)
1520
+
{
1521
+
return ((val) << DPU_FEATURE_MODE_CFG_TP_EN__SHIFT) & DPU_FEATURE_MODE_CFG_TP_EN__MASK;
1522
+
}
1523
+
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK 0x3c000000
1524
+
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT 26
1525
+
static inline uint32_t DPU_FEATURE_MODE_CFG_RGP_TYPE(uint32_t val)
1526
+
{
1527
+
return ((val) << DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT) & DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK;
1528
+
}
1529
+
#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK 0x02000000
1530
+
#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT 25
1531
+
static inline uint32_t DPU_FEATURE_MODE_CFG_NONALIGN(uint32_t val)
1532
+
{
1533
+
return ((val) << DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT) & DPU_FEATURE_MODE_CFG_NONALIGN__MASK;
1534
+
}
1535
+
#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK 0x01fffe00
1536
+
#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT 9
1537
+
static inline uint32_t DPU_FEATURE_MODE_CFG_SURF_LEN(uint32_t val)
1538
+
{
1539
+
return ((val) << DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_SURF_LEN__MASK;
1540
+
}
1541
+
#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK 0x000001e0
1542
+
#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT 5
1543
+
static inline uint32_t DPU_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
1544
+
{
1545
+
return ((val) << DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_BURST_LEN__MASK;
1546
+
}
1547
+
#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000018
1548
+
#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT 3
1549
+
static inline uint32_t DPU_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
1550
+
{
1551
+
return ((val) << DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_CONV_MODE__MASK;
1552
+
}
1553
+
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK 0x00000006
1554
+
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT 1
1555
+
static inline uint32_t DPU_FEATURE_MODE_CFG_OUTPUT_MODE(uint32_t val)
1556
+
{
1557
+
return ((val) << DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK;
1558
+
}
1559
+
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
1560
+
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
1561
+
static inline uint32_t DPU_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
1562
+
{
1563
+
return ((val) << DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK;
1564
+
}
1565
+
1566
+
#define REG_DPU_DATA_FORMAT 0x00004010
1567
+
#define DPU_DATA_FORMAT_OUT_PRECISION__MASK 0xe0000000
1568
+
#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT 29
1569
+
static inline uint32_t DPU_DATA_FORMAT_OUT_PRECISION(uint32_t val)
1570
+
{
1571
+
return ((val) << DPU_DATA_FORMAT_OUT_PRECISION__SHIFT) & DPU_DATA_FORMAT_OUT_PRECISION__MASK;
1572
+
}
1573
+
#define DPU_DATA_FORMAT_IN_PRECISION__MASK 0x1c000000
1574
+
#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT 26
1575
+
static inline uint32_t DPU_DATA_FORMAT_IN_PRECISION(uint32_t val)
1576
+
{
1577
+
return ((val) << DPU_DATA_FORMAT_IN_PRECISION__SHIFT) & DPU_DATA_FORMAT_IN_PRECISION__MASK;
1578
+
}
1579
+
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK 0x03ff0000
1580
+
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT 16
1581
+
static inline uint32_t DPU_DATA_FORMAT_EW_TRUNCATE_NEG(uint32_t val)
1582
+
{
1583
+
return ((val) << DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT) & DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK;
1584
+
}
1585
+
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK 0x0000fc00
1586
+
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT 10
1587
+
static inline uint32_t DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG(uint32_t val)
1588
+
{
1589
+
return ((val) << DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK;
1590
+
}
1591
+
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK 0x000003f0
1592
+
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT 4
1593
+
static inline uint32_t DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG(uint32_t val)
1594
+
{
1595
+
return ((val) << DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK;
1596
+
}
1597
+
#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK 0x00000008
1598
+
#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT 3
1599
+
static inline uint32_t DPU_DATA_FORMAT_MC_SURF_OUT(uint32_t val)
1600
+
{
1601
+
return ((val) << DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT) & DPU_DATA_FORMAT_MC_SURF_OUT__MASK;
1602
+
}
1603
+
#define DPU_DATA_FORMAT_PROC_PRECISION__MASK 0x00000007
1604
+
#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT 0
1605
+
static inline uint32_t DPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
1606
+
{
1607
+
return ((val) << DPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & DPU_DATA_FORMAT_PROC_PRECISION__MASK;
1608
+
}
1609
+
1610
+
#define REG_DPU_OFFSET_PEND 0x00004014
1611
+
#define DPU_OFFSET_PEND_RESERVED_0__MASK 0xffff0000
1612
+
#define DPU_OFFSET_PEND_RESERVED_0__SHIFT 16
1613
+
static inline uint32_t DPU_OFFSET_PEND_RESERVED_0(uint32_t val)
1614
+
{
1615
+
return ((val) << DPU_OFFSET_PEND_RESERVED_0__SHIFT) & DPU_OFFSET_PEND_RESERVED_0__MASK;
1616
+
}
1617
+
#define DPU_OFFSET_PEND_OFFSET_PEND__MASK 0x0000ffff
1618
+
#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT 0
1619
+
static inline uint32_t DPU_OFFSET_PEND_OFFSET_PEND(uint32_t val)
1620
+
{
1621
+
return ((val) << DPU_OFFSET_PEND_OFFSET_PEND__SHIFT) & DPU_OFFSET_PEND_OFFSET_PEND__MASK;
1622
+
}
1623
+
1624
+
#define REG_DPU_DST_BASE_ADDR 0x00004020
1625
+
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK 0xffffffff
1626
+
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT 0
1627
+
static inline uint32_t DPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
1628
+
{
1629
+
return ((val) << DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
1630
+
}
1631
+
1632
+
#define REG_DPU_DST_SURF_STRIDE 0x00004024
1633
+
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK 0xfffffff0
1634
+
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT 4
1635
+
static inline uint32_t DPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
1636
+
{
1637
+
return ((val) << DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
1638
+
}
1639
+
#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
1640
+
#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT 0
1641
+
static inline uint32_t DPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
1642
+
{
1643
+
return ((val) << DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_DST_SURF_STRIDE_RESERVED_0__MASK;
1644
+
}
1645
+
1646
+
#define REG_DPU_DATA_CUBE_WIDTH 0x00004030
1647
+
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
1648
+
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
1649
+
static inline uint32_t DPU_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
1650
+
{
1651
+
return ((val) << DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK;
1652
+
}
1653
+
#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
1654
+
#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
1655
+
static inline uint32_t DPU_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
1656
+
{
1657
+
return ((val) << DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_DATA_CUBE_WIDTH_WIDTH__MASK;
1658
+
}
1659
+
1660
+
#define REG_DPU_DATA_CUBE_HEIGHT 0x00004034
1661
+
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xfe000000
1662
+
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 25
1663
+
static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
1664
+
{
1665
+
return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
1666
+
}
1667
+
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK 0x01c00000
1668
+
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT 22
1669
+
static inline uint32_t DPU_DATA_CUBE_HEIGHT_MINMAX_CTL(uint32_t val)
1670
+
{
1671
+
return ((val) << DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT) & DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK;
1672
+
}
1673
+
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x003fe000
1674
+
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
1675
+
static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
1676
+
{
1677
+
return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
1678
+
}
1679
+
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
1680
+
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
1681
+
static inline uint32_t DPU_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
1682
+
{
1683
+
return ((val) << DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK;
1684
+
}
1685
+
1686
+
#define REG_DPU_DATA_CUBE_NOTCH_ADDR 0x00004038
1687
+
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK 0xe0000000
1688
+
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT 29
1689
+
static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0(uint32_t val)
1690
+
{
1691
+
return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK;
1692
+
}
1693
+
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK 0x1fff0000
1694
+
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT 16
1695
+
static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1(uint32_t val)
1696
+
{
1697
+
return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK;
1698
+
}
1699
+
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK 0x0000e000
1700
+
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT 13
1701
+
static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1(uint32_t val)
1702
+
{
1703
+
return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK;
1704
+
}
1705
+
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK 0x00001fff
1706
+
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT 0
1707
+
static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0(uint32_t val)
1708
+
{
1709
+
return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK;
1710
+
}
1711
+
1712
+
#define REG_DPU_DATA_CUBE_CHANNEL 0x0000403c
1713
+
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xe0000000
1714
+
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 29
1715
+
static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
1716
+
{
1717
+
return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
1718
+
}
1719
+
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK 0x1fff0000
1720
+
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT 16
1721
+
static inline uint32_t DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL(uint32_t val)
1722
+
{
1723
+
return ((val) << DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK;
1724
+
}
1725
+
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK 0x0000e000
1726
+
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT 13
1727
+
static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_1(uint32_t val)
1728
+
{
1729
+
return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK;
1730
+
}
1731
+
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
1732
+
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
1733
+
static inline uint32_t DPU_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
1734
+
{
1735
+
return ((val) << DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK;
1736
+
}
1737
+
1738
+
#define REG_DPU_BS_CFG 0x00004040
1739
+
#define DPU_BS_CFG_RESERVED_0__MASK 0xfff00000
1740
+
#define DPU_BS_CFG_RESERVED_0__SHIFT 20
1741
+
static inline uint32_t DPU_BS_CFG_RESERVED_0(uint32_t val)
1742
+
{
1743
+
return ((val) << DPU_BS_CFG_RESERVED_0__SHIFT) & DPU_BS_CFG_RESERVED_0__MASK;
1744
+
}
1745
+
#define DPU_BS_CFG_BS_ALU_ALGO__MASK 0x000f0000
1746
+
#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT 16
1747
+
static inline uint32_t DPU_BS_CFG_BS_ALU_ALGO(uint32_t val)
1748
+
{
1749
+
return ((val) << DPU_BS_CFG_BS_ALU_ALGO__SHIFT) & DPU_BS_CFG_BS_ALU_ALGO__MASK;
1750
+
}
1751
+
#define DPU_BS_CFG_RESERVED_1__MASK 0x0000fe00
1752
+
#define DPU_BS_CFG_RESERVED_1__SHIFT 9
1753
+
static inline uint32_t DPU_BS_CFG_RESERVED_1(uint32_t val)
1754
+
{
1755
+
return ((val) << DPU_BS_CFG_RESERVED_1__SHIFT) & DPU_BS_CFG_RESERVED_1__MASK;
1756
+
}
1757
+
#define DPU_BS_CFG_BS_ALU_SRC__MASK 0x00000100
1758
+
#define DPU_BS_CFG_BS_ALU_SRC__SHIFT 8
1759
+
static inline uint32_t DPU_BS_CFG_BS_ALU_SRC(uint32_t val)
1760
+
{
1761
+
return ((val) << DPU_BS_CFG_BS_ALU_SRC__SHIFT) & DPU_BS_CFG_BS_ALU_SRC__MASK;
1762
+
}
1763
+
#define DPU_BS_CFG_BS_RELUX_EN__MASK 0x00000080
1764
+
#define DPU_BS_CFG_BS_RELUX_EN__SHIFT 7
1765
+
static inline uint32_t DPU_BS_CFG_BS_RELUX_EN(uint32_t val)
1766
+
{
1767
+
return ((val) << DPU_BS_CFG_BS_RELUX_EN__SHIFT) & DPU_BS_CFG_BS_RELUX_EN__MASK;
1768
+
}
1769
+
#define DPU_BS_CFG_BS_RELU_BYPASS__MASK 0x00000040
1770
+
#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT 6
1771
+
static inline uint32_t DPU_BS_CFG_BS_RELU_BYPASS(uint32_t val)
1772
+
{
1773
+
return ((val) << DPU_BS_CFG_BS_RELU_BYPASS__SHIFT) & DPU_BS_CFG_BS_RELU_BYPASS__MASK;
1774
+
}
1775
+
#define DPU_BS_CFG_BS_MUL_PRELU__MASK 0x00000020
1776
+
#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT 5
1777
+
static inline uint32_t DPU_BS_CFG_BS_MUL_PRELU(uint32_t val)
1778
+
{
1779
+
return ((val) << DPU_BS_CFG_BS_MUL_PRELU__SHIFT) & DPU_BS_CFG_BS_MUL_PRELU__MASK;
1780
+
}
1781
+
#define DPU_BS_CFG_BS_MUL_BYPASS__MASK 0x00000010
1782
+
#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT 4
1783
+
static inline uint32_t DPU_BS_CFG_BS_MUL_BYPASS(uint32_t val)
1784
+
{
1785
+
return ((val) << DPU_BS_CFG_BS_MUL_BYPASS__SHIFT) & DPU_BS_CFG_BS_MUL_BYPASS__MASK;
1786
+
}
1787
+
#define DPU_BS_CFG_RESERVED_2__MASK 0x0000000c
1788
+
#define DPU_BS_CFG_RESERVED_2__SHIFT 2
1789
+
static inline uint32_t DPU_BS_CFG_RESERVED_2(uint32_t val)
1790
+
{
1791
+
return ((val) << DPU_BS_CFG_RESERVED_2__SHIFT) & DPU_BS_CFG_RESERVED_2__MASK;
1792
+
}
1793
+
#define DPU_BS_CFG_BS_ALU_BYPASS__MASK 0x00000002
1794
+
#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT 1
1795
+
static inline uint32_t DPU_BS_CFG_BS_ALU_BYPASS(uint32_t val)
1796
+
{
1797
+
return ((val) << DPU_BS_CFG_BS_ALU_BYPASS__SHIFT) & DPU_BS_CFG_BS_ALU_BYPASS__MASK;
1798
+
}
1799
+
#define DPU_BS_CFG_BS_BYPASS__MASK 0x00000001
1800
+
#define DPU_BS_CFG_BS_BYPASS__SHIFT 0
1801
+
static inline uint32_t DPU_BS_CFG_BS_BYPASS(uint32_t val)
1802
+
{
1803
+
return ((val) << DPU_BS_CFG_BS_BYPASS__SHIFT) & DPU_BS_CFG_BS_BYPASS__MASK;
1804
+
}
1805
+
1806
+
#define REG_DPU_BS_ALU_CFG 0x00004044
1807
+
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK 0xffffffff
1808
+
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT 0
1809
+
static inline uint32_t DPU_BS_ALU_CFG_BS_ALU_OPERAND(uint32_t val)
1810
+
{
1811
+
return ((val) << DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT) & DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK;
1812
+
}
1813
+
1814
+
#define REG_DPU_BS_MUL_CFG 0x00004048
1815
+
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK 0xffff0000
1816
+
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT 16
1817
+
static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_OPERAND(uint32_t val)
1818
+
{
1819
+
return ((val) << DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK;
1820
+
}
1821
+
#define DPU_BS_MUL_CFG_RESERVED_0__MASK 0x0000c000
1822
+
#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT 14
1823
+
static inline uint32_t DPU_BS_MUL_CFG_RESERVED_0(uint32_t val)
1824
+
{
1825
+
return ((val) << DPU_BS_MUL_CFG_RESERVED_0__SHIFT) & DPU_BS_MUL_CFG_RESERVED_0__MASK;
1826
+
}
1827
+
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK 0x00003f00
1828
+
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT 8
1829
+
static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE(uint32_t val)
1830
+
{
1831
+
return ((val) << DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK;
1832
+
}
1833
+
#define DPU_BS_MUL_CFG_RESERVED_1__MASK 0x000000fc
1834
+
#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT 2
1835
+
static inline uint32_t DPU_BS_MUL_CFG_RESERVED_1(uint32_t val)
1836
+
{
1837
+
return ((val) << DPU_BS_MUL_CFG_RESERVED_1__SHIFT) & DPU_BS_MUL_CFG_RESERVED_1__MASK;
1838
+
}
1839
+
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK 0x00000002
1840
+
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT 1
1841
+
static inline uint32_t DPU_BS_MUL_CFG_BS_TRUNCATE_SRC(uint32_t val)
1842
+
{
1843
+
return ((val) << DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK;
1844
+
}
1845
+
#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK 0x00000001
1846
+
#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT 0
1847
+
static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SRC(uint32_t val)
1848
+
{
1849
+
return ((val) << DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SRC__MASK;
1850
+
}
1851
+
1852
+
#define REG_DPU_BS_RELUX_CMP_VALUE 0x0000404c
1853
+
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK 0xffffffff
1854
+
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT 0
1855
+
static inline uint32_t DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT(uint32_t val)
1856
+
{
1857
+
return ((val) << DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT) & DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK;
1858
+
}
1859
+
1860
+
#define REG_DPU_BS_OW_CFG 0x00004050
1861
+
#define DPU_BS_OW_CFG_RGP_CNTER__MASK 0xf0000000
1862
+
#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT 28
1863
+
static inline uint32_t DPU_BS_OW_CFG_RGP_CNTER(uint32_t val)
1864
+
{
1865
+
return ((val) << DPU_BS_OW_CFG_RGP_CNTER__SHIFT) & DPU_BS_OW_CFG_RGP_CNTER__MASK;
1866
+
}
1867
+
#define DPU_BS_OW_CFG_TP_ORG_EN__MASK 0x08000000
1868
+
#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT 27
1869
+
static inline uint32_t DPU_BS_OW_CFG_TP_ORG_EN(uint32_t val)
1870
+
{
1871
+
return ((val) << DPU_BS_OW_CFG_TP_ORG_EN__SHIFT) & DPU_BS_OW_CFG_TP_ORG_EN__MASK;
1872
+
}
1873
+
#define DPU_BS_OW_CFG_RESERVED_0__MASK 0x07fff800
1874
+
#define DPU_BS_OW_CFG_RESERVED_0__SHIFT 11
1875
+
static inline uint32_t DPU_BS_OW_CFG_RESERVED_0(uint32_t val)
1876
+
{
1877
+
return ((val) << DPU_BS_OW_CFG_RESERVED_0__SHIFT) & DPU_BS_OW_CFG_RESERVED_0__MASK;
1878
+
}
1879
+
#define DPU_BS_OW_CFG_SIZE_E_2__MASK 0x00000700
1880
+
#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT 8
1881
+
static inline uint32_t DPU_BS_OW_CFG_SIZE_E_2(uint32_t val)
1882
+
{
1883
+
return ((val) << DPU_BS_OW_CFG_SIZE_E_2__SHIFT) & DPU_BS_OW_CFG_SIZE_E_2__MASK;
1884
+
}
1885
+
#define DPU_BS_OW_CFG_SIZE_E_1__MASK 0x000000e0
1886
+
#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT 5
1887
+
static inline uint32_t DPU_BS_OW_CFG_SIZE_E_1(uint32_t val)
1888
+
{
1889
+
return ((val) << DPU_BS_OW_CFG_SIZE_E_1__SHIFT) & DPU_BS_OW_CFG_SIZE_E_1__MASK;
1890
+
}
1891
+
#define DPU_BS_OW_CFG_SIZE_E_0__MASK 0x0000001c
1892
+
#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT 2
1893
+
static inline uint32_t DPU_BS_OW_CFG_SIZE_E_0(uint32_t val)
1894
+
{
1895
+
return ((val) << DPU_BS_OW_CFG_SIZE_E_0__SHIFT) & DPU_BS_OW_CFG_SIZE_E_0__MASK;
1896
+
}
1897
+
#define DPU_BS_OW_CFG_OD_BYPASS__MASK 0x00000002
1898
+
#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT 1
1899
+
static inline uint32_t DPU_BS_OW_CFG_OD_BYPASS(uint32_t val)
1900
+
{
1901
+
return ((val) << DPU_BS_OW_CFG_OD_BYPASS__SHIFT) & DPU_BS_OW_CFG_OD_BYPASS__MASK;
1902
+
}
1903
+
#define DPU_BS_OW_CFG_OW_SRC__MASK 0x00000001
1904
+
#define DPU_BS_OW_CFG_OW_SRC__SHIFT 0
1905
+
static inline uint32_t DPU_BS_OW_CFG_OW_SRC(uint32_t val)
1906
+
{
1907
+
return ((val) << DPU_BS_OW_CFG_OW_SRC__SHIFT) & DPU_BS_OW_CFG_OW_SRC__MASK;
1908
+
}
1909
+
1910
+
#define REG_DPU_BS_OW_OP 0x00004054
1911
+
#define DPU_BS_OW_OP_RESERVED_0__MASK 0xffff0000
1912
+
#define DPU_BS_OW_OP_RESERVED_0__SHIFT 16
1913
+
static inline uint32_t DPU_BS_OW_OP_RESERVED_0(uint32_t val)
1914
+
{
1915
+
return ((val) << DPU_BS_OW_OP_RESERVED_0__SHIFT) & DPU_BS_OW_OP_RESERVED_0__MASK;
1916
+
}
1917
+
#define DPU_BS_OW_OP_OW_OP__MASK 0x0000ffff
1918
+
#define DPU_BS_OW_OP_OW_OP__SHIFT 0
1919
+
static inline uint32_t DPU_BS_OW_OP_OW_OP(uint32_t val)
1920
+
{
1921
+
return ((val) << DPU_BS_OW_OP_OW_OP__SHIFT) & DPU_BS_OW_OP_OW_OP__MASK;
1922
+
}
1923
+
1924
+
#define REG_DPU_WDMA_SIZE_0 0x00004058
1925
+
#define DPU_WDMA_SIZE_0_RESERVED_0__MASK 0xf0000000
1926
+
#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT 28
1927
+
static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_0(uint32_t val)
1928
+
{
1929
+
return ((val) << DPU_WDMA_SIZE_0_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_0__MASK;
1930
+
}
1931
+
#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK 0x08000000
1932
+
#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT 27
1933
+
static inline uint32_t DPU_WDMA_SIZE_0_TP_PRECISION(uint32_t val)
1934
+
{
1935
+
return ((val) << DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT) & DPU_WDMA_SIZE_0_TP_PRECISION__MASK;
1936
+
}
1937
+
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK 0x07ff0000
1938
+
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT 16
1939
+
static inline uint32_t DPU_WDMA_SIZE_0_SIZE_C_WDMA(uint32_t val)
1940
+
{
1941
+
return ((val) << DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT) & DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK;
1942
+
}
1943
+
#define DPU_WDMA_SIZE_0_RESERVED_1__MASK 0x0000e000
1944
+
#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT 13
1945
+
static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_1(uint32_t val)
1946
+
{
1947
+
return ((val) << DPU_WDMA_SIZE_0_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_1__MASK;
1948
+
}
1949
+
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK 0x00001fff
1950
+
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT 0
1951
+
static inline uint32_t DPU_WDMA_SIZE_0_CHANNEL_WDMA(uint32_t val)
1952
+
{
1953
+
return ((val) << DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT) & DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK;
1954
+
}
1955
+
1956
+
#define REG_DPU_WDMA_SIZE_1 0x0000405c
1957
+
#define DPU_WDMA_SIZE_1_RESERVED_0__MASK 0xe0000000
1958
+
#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT 29
1959
+
static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_0(uint32_t val)
1960
+
{
1961
+
return ((val) << DPU_WDMA_SIZE_1_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_0__MASK;
1962
+
}
1963
+
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK 0x1fff0000
1964
+
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT 16
1965
+
static inline uint32_t DPU_WDMA_SIZE_1_HEIGHT_WDMA(uint32_t val)
1966
+
{
1967
+
return ((val) << DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT) & DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK;
1968
+
}
1969
+
#define DPU_WDMA_SIZE_1_RESERVED_1__MASK 0x0000e000
1970
+
#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT 13
1971
+
static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_1(uint32_t val)
1972
+
{
1973
+
return ((val) << DPU_WDMA_SIZE_1_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_1__MASK;
1974
+
}
1975
+
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK 0x00001fff
1976
+
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT 0
1977
+
static inline uint32_t DPU_WDMA_SIZE_1_WIDTH_WDMA(uint32_t val)
1978
+
{
1979
+
return ((val) << DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT) & DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK;
1980
+
}
1981
+
1982
+
#define REG_DPU_BN_CFG 0x00004060
1983
+
#define DPU_BN_CFG_RESERVED_0__MASK 0xfff00000
1984
+
#define DPU_BN_CFG_RESERVED_0__SHIFT 20
1985
+
static inline uint32_t DPU_BN_CFG_RESERVED_0(uint32_t val)
1986
+
{
1987
+
return ((val) << DPU_BN_CFG_RESERVED_0__SHIFT) & DPU_BN_CFG_RESERVED_0__MASK;
1988
+
}
1989
+
#define DPU_BN_CFG_BN_ALU_ALGO__MASK 0x000f0000
1990
+
#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT 16
1991
+
static inline uint32_t DPU_BN_CFG_BN_ALU_ALGO(uint32_t val)
1992
+
{
1993
+
return ((val) << DPU_BN_CFG_BN_ALU_ALGO__SHIFT) & DPU_BN_CFG_BN_ALU_ALGO__MASK;
1994
+
}
1995
+
#define DPU_BN_CFG_RESERVED_1__MASK 0x0000fe00
1996
+
#define DPU_BN_CFG_RESERVED_1__SHIFT 9
1997
+
static inline uint32_t DPU_BN_CFG_RESERVED_1(uint32_t val)
1998
+
{
1999
+
return ((val) << DPU_BN_CFG_RESERVED_1__SHIFT) & DPU_BN_CFG_RESERVED_1__MASK;
2000
+
}
2001
+
#define DPU_BN_CFG_BN_ALU_SRC__MASK 0x00000100
2002
+
#define DPU_BN_CFG_BN_ALU_SRC__SHIFT 8
2003
+
static inline uint32_t DPU_BN_CFG_BN_ALU_SRC(uint32_t val)
2004
+
{
2005
+
return ((val) << DPU_BN_CFG_BN_ALU_SRC__SHIFT) & DPU_BN_CFG_BN_ALU_SRC__MASK;
2006
+
}
2007
+
#define DPU_BN_CFG_BN_RELUX_EN__MASK 0x00000080
2008
+
#define DPU_BN_CFG_BN_RELUX_EN__SHIFT 7
2009
+
static inline uint32_t DPU_BN_CFG_BN_RELUX_EN(uint32_t val)
2010
+
{
2011
+
return ((val) << DPU_BN_CFG_BN_RELUX_EN__SHIFT) & DPU_BN_CFG_BN_RELUX_EN__MASK;
2012
+
}
2013
+
#define DPU_BN_CFG_BN_RELU_BYPASS__MASK 0x00000040
2014
+
#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT 6
2015
+
static inline uint32_t DPU_BN_CFG_BN_RELU_BYPASS(uint32_t val)
2016
+
{
2017
+
return ((val) << DPU_BN_CFG_BN_RELU_BYPASS__SHIFT) & DPU_BN_CFG_BN_RELU_BYPASS__MASK;
2018
+
}
2019
+
#define DPU_BN_CFG_BN_MUL_PRELU__MASK 0x00000020
2020
+
#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT 5
2021
+
static inline uint32_t DPU_BN_CFG_BN_MUL_PRELU(uint32_t val)
2022
+
{
2023
+
return ((val) << DPU_BN_CFG_BN_MUL_PRELU__SHIFT) & DPU_BN_CFG_BN_MUL_PRELU__MASK;
2024
+
}
2025
+
#define DPU_BN_CFG_BN_MUL_BYPASS__MASK 0x00000010
2026
+
#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT 4
2027
+
static inline uint32_t DPU_BN_CFG_BN_MUL_BYPASS(uint32_t val)
2028
+
{
2029
+
return ((val) << DPU_BN_CFG_BN_MUL_BYPASS__SHIFT) & DPU_BN_CFG_BN_MUL_BYPASS__MASK;
2030
+
}
2031
+
#define DPU_BN_CFG_RESERVED_2__MASK 0x0000000c
2032
+
#define DPU_BN_CFG_RESERVED_2__SHIFT 2
2033
+
static inline uint32_t DPU_BN_CFG_RESERVED_2(uint32_t val)
2034
+
{
2035
+
return ((val) << DPU_BN_CFG_RESERVED_2__SHIFT) & DPU_BN_CFG_RESERVED_2__MASK;
2036
+
}
2037
+
#define DPU_BN_CFG_BN_ALU_BYPASS__MASK 0x00000002
2038
+
#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT 1
2039
+
static inline uint32_t DPU_BN_CFG_BN_ALU_BYPASS(uint32_t val)
2040
+
{
2041
+
return ((val) << DPU_BN_CFG_BN_ALU_BYPASS__SHIFT) & DPU_BN_CFG_BN_ALU_BYPASS__MASK;
2042
+
}
2043
+
#define DPU_BN_CFG_BN_BYPASS__MASK 0x00000001
2044
+
#define DPU_BN_CFG_BN_BYPASS__SHIFT 0
2045
+
static inline uint32_t DPU_BN_CFG_BN_BYPASS(uint32_t val)
2046
+
{
2047
+
return ((val) << DPU_BN_CFG_BN_BYPASS__SHIFT) & DPU_BN_CFG_BN_BYPASS__MASK;
2048
+
}
2049
+
2050
+
#define REG_DPU_BN_ALU_CFG 0x00004064
2051
+
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK 0xffffffff
2052
+
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT 0
2053
+
static inline uint32_t DPU_BN_ALU_CFG_BN_ALU_OPERAND(uint32_t val)
2054
+
{
2055
+
return ((val) << DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT) & DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK;
2056
+
}
2057
+
2058
+
#define REG_DPU_BN_MUL_CFG 0x00004068
2059
+
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK 0xffff0000
2060
+
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT 16
2061
+
static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_OPERAND(uint32_t val)
2062
+
{
2063
+
return ((val) << DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK;
2064
+
}
2065
+
#define DPU_BN_MUL_CFG_RESERVED_0__MASK 0x0000c000
2066
+
#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT 14
2067
+
static inline uint32_t DPU_BN_MUL_CFG_RESERVED_0(uint32_t val)
2068
+
{
2069
+
return ((val) << DPU_BN_MUL_CFG_RESERVED_0__SHIFT) & DPU_BN_MUL_CFG_RESERVED_0__MASK;
2070
+
}
2071
+
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK 0x00003f00
2072
+
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT 8
2073
+
static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE(uint32_t val)
2074
+
{
2075
+
return ((val) << DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK;
2076
+
}
2077
+
#define DPU_BN_MUL_CFG_RESERVED_1__MASK 0x000000fc
2078
+
#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT 2
2079
+
static inline uint32_t DPU_BN_MUL_CFG_RESERVED_1(uint32_t val)
2080
+
{
2081
+
return ((val) << DPU_BN_MUL_CFG_RESERVED_1__SHIFT) & DPU_BN_MUL_CFG_RESERVED_1__MASK;
2082
+
}
2083
+
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK 0x00000002
2084
+
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT 1
2085
+
static inline uint32_t DPU_BN_MUL_CFG_BN_TRUNCATE_SRC(uint32_t val)
2086
+
{
2087
+
return ((val) << DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK;
2088
+
}
2089
+
#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK 0x00000001
2090
+
#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT 0
2091
+
static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SRC(uint32_t val)
2092
+
{
2093
+
return ((val) << DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SRC__MASK;
2094
+
}
2095
+
2096
+
#define REG_DPU_BN_RELUX_CMP_VALUE 0x0000406c
2097
+
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK 0xffffffff
2098
+
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT 0
2099
+
static inline uint32_t DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT(uint32_t val)
2100
+
{
2101
+
return ((val) << DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT) & DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK;
2102
+
}
2103
+
2104
+
#define REG_DPU_EW_CFG 0x00004070
2105
+
#define DPU_EW_CFG_EW_CVT_TYPE__MASK 0x80000000
2106
+
#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT 31
2107
+
static inline uint32_t DPU_EW_CFG_EW_CVT_TYPE(uint32_t val)
2108
+
{
2109
+
return ((val) << DPU_EW_CFG_EW_CVT_TYPE__SHIFT) & DPU_EW_CFG_EW_CVT_TYPE__MASK;
2110
+
}
2111
+
#define DPU_EW_CFG_EW_CVT_ROUND__MASK 0x40000000
2112
+
#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT 30
2113
+
static inline uint32_t DPU_EW_CFG_EW_CVT_ROUND(uint32_t val)
2114
+
{
2115
+
return ((val) << DPU_EW_CFG_EW_CVT_ROUND__SHIFT) & DPU_EW_CFG_EW_CVT_ROUND__MASK;
2116
+
}
2117
+
#define DPU_EW_CFG_EW_DATA_MODE__MASK 0x30000000
2118
+
#define DPU_EW_CFG_EW_DATA_MODE__SHIFT 28
2119
+
static inline uint32_t DPU_EW_CFG_EW_DATA_MODE(uint32_t val)
2120
+
{
2121
+
return ((val) << DPU_EW_CFG_EW_DATA_MODE__SHIFT) & DPU_EW_CFG_EW_DATA_MODE__MASK;
2122
+
}
2123
+
#define DPU_EW_CFG_RESERVED_0__MASK 0x0f000000
2124
+
#define DPU_EW_CFG_RESERVED_0__SHIFT 24
2125
+
static inline uint32_t DPU_EW_CFG_RESERVED_0(uint32_t val)
2126
+
{
2127
+
return ((val) << DPU_EW_CFG_RESERVED_0__SHIFT) & DPU_EW_CFG_RESERVED_0__MASK;
2128
+
}
2129
+
#define DPU_EW_CFG_EDATA_SIZE__MASK 0x00c00000
2130
+
#define DPU_EW_CFG_EDATA_SIZE__SHIFT 22
2131
+
static inline uint32_t DPU_EW_CFG_EDATA_SIZE(uint32_t val)
2132
+
{
2133
+
return ((val) << DPU_EW_CFG_EDATA_SIZE__SHIFT) & DPU_EW_CFG_EDATA_SIZE__MASK;
2134
+
}
2135
+
#define DPU_EW_CFG_EW_EQUAL_EN__MASK 0x00200000
2136
+
#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT 21
2137
+
static inline uint32_t DPU_EW_CFG_EW_EQUAL_EN(uint32_t val)
2138
+
{
2139
+
return ((val) << DPU_EW_CFG_EW_EQUAL_EN__SHIFT) & DPU_EW_CFG_EW_EQUAL_EN__MASK;
2140
+
}
2141
+
#define DPU_EW_CFG_EW_BINARY_EN__MASK 0x00100000
2142
+
#define DPU_EW_CFG_EW_BINARY_EN__SHIFT 20
2143
+
static inline uint32_t DPU_EW_CFG_EW_BINARY_EN(uint32_t val)
2144
+
{
2145
+
return ((val) << DPU_EW_CFG_EW_BINARY_EN__SHIFT) & DPU_EW_CFG_EW_BINARY_EN__MASK;
2146
+
}
2147
+
#define DPU_EW_CFG_EW_ALU_ALGO__MASK 0x000f0000
2148
+
#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT 16
2149
+
static inline uint32_t DPU_EW_CFG_EW_ALU_ALGO(uint32_t val)
2150
+
{
2151
+
return ((val) << DPU_EW_CFG_EW_ALU_ALGO__SHIFT) & DPU_EW_CFG_EW_ALU_ALGO__MASK;
2152
+
}
2153
+
#define DPU_EW_CFG_RESERVED_1__MASK 0x0000f800
2154
+
#define DPU_EW_CFG_RESERVED_1__SHIFT 11
2155
+
static inline uint32_t DPU_EW_CFG_RESERVED_1(uint32_t val)
2156
+
{
2157
+
return ((val) << DPU_EW_CFG_RESERVED_1__SHIFT) & DPU_EW_CFG_RESERVED_1__MASK;
2158
+
}
2159
+
#define DPU_EW_CFG_EW_RELUX_EN__MASK 0x00000400
2160
+
#define DPU_EW_CFG_EW_RELUX_EN__SHIFT 10
2161
+
static inline uint32_t DPU_EW_CFG_EW_RELUX_EN(uint32_t val)
2162
+
{
2163
+
return ((val) << DPU_EW_CFG_EW_RELUX_EN__SHIFT) & DPU_EW_CFG_EW_RELUX_EN__MASK;
2164
+
}
2165
+
#define DPU_EW_CFG_EW_RELU_BYPASS__MASK 0x00000200
2166
+
#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT 9
2167
+
static inline uint32_t DPU_EW_CFG_EW_RELU_BYPASS(uint32_t val)
2168
+
{
2169
+
return ((val) << DPU_EW_CFG_EW_RELU_BYPASS__SHIFT) & DPU_EW_CFG_EW_RELU_BYPASS__MASK;
2170
+
}
2171
+
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK 0x00000100
2172
+
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT 8
2173
+
static inline uint32_t DPU_EW_CFG_EW_OP_CVT_BYPASS(uint32_t val)
2174
+
{
2175
+
return ((val) << DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK;
2176
+
}
2177
+
#define DPU_EW_CFG_EW_LUT_BYPASS__MASK 0x00000080
2178
+
#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT 7
2179
+
static inline uint32_t DPU_EW_CFG_EW_LUT_BYPASS(uint32_t val)
2180
+
{
2181
+
return ((val) << DPU_EW_CFG_EW_LUT_BYPASS__SHIFT) & DPU_EW_CFG_EW_LUT_BYPASS__MASK;
2182
+
}
2183
+
#define DPU_EW_CFG_EW_OP_SRC__MASK 0x00000040
2184
+
#define DPU_EW_CFG_EW_OP_SRC__SHIFT 6
2185
+
static inline uint32_t DPU_EW_CFG_EW_OP_SRC(uint32_t val)
2186
+
{
2187
+
return ((val) << DPU_EW_CFG_EW_OP_SRC__SHIFT) & DPU_EW_CFG_EW_OP_SRC__MASK;
2188
+
}
2189
+
#define DPU_EW_CFG_EW_MUL_PRELU__MASK 0x00000020
2190
+
#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT 5
2191
+
static inline uint32_t DPU_EW_CFG_EW_MUL_PRELU(uint32_t val)
2192
+
{
2193
+
return ((val) << DPU_EW_CFG_EW_MUL_PRELU__SHIFT) & DPU_EW_CFG_EW_MUL_PRELU__MASK;
2194
+
}
2195
+
#define DPU_EW_CFG_RESERVED_2__MASK 0x00000018
2196
+
#define DPU_EW_CFG_RESERVED_2__SHIFT 3
2197
+
static inline uint32_t DPU_EW_CFG_RESERVED_2(uint32_t val)
2198
+
{
2199
+
return ((val) << DPU_EW_CFG_RESERVED_2__SHIFT) & DPU_EW_CFG_RESERVED_2__MASK;
2200
+
}
2201
+
#define DPU_EW_CFG_EW_OP_TYPE__MASK 0x00000004
2202
+
#define DPU_EW_CFG_EW_OP_TYPE__SHIFT 2
2203
+
static inline uint32_t DPU_EW_CFG_EW_OP_TYPE(uint32_t val)
2204
+
{
2205
+
return ((val) << DPU_EW_CFG_EW_OP_TYPE__SHIFT) & DPU_EW_CFG_EW_OP_TYPE__MASK;
2206
+
}
2207
+
#define DPU_EW_CFG_EW_OP_BYPASS__MASK 0x00000002
2208
+
#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT 1
2209
+
static inline uint32_t DPU_EW_CFG_EW_OP_BYPASS(uint32_t val)
2210
+
{
2211
+
return ((val) << DPU_EW_CFG_EW_OP_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_BYPASS__MASK;
2212
+
}
2213
+
#define DPU_EW_CFG_EW_BYPASS__MASK 0x00000001
2214
+
#define DPU_EW_CFG_EW_BYPASS__SHIFT 0
2215
+
static inline uint32_t DPU_EW_CFG_EW_BYPASS(uint32_t val)
2216
+
{
2217
+
return ((val) << DPU_EW_CFG_EW_BYPASS__SHIFT) & DPU_EW_CFG_EW_BYPASS__MASK;
2218
+
}
2219
+
2220
+
#define REG_DPU_EW_CVT_OFFSET_VALUE 0x00004074
2221
+
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK 0xffffffff
2222
+
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT 0
2223
+
static inline uint32_t DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET(uint32_t val)
2224
+
{
2225
+
return ((val) << DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT) & DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK;
2226
+
}
2227
+
2228
+
#define REG_DPU_EW_CVT_SCALE_VALUE 0x00004078
2229
+
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK 0xffc00000
2230
+
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT 22
2231
+
static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE(uint32_t val)
2232
+
{
2233
+
return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK;
2234
+
}
2235
+
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK 0x003f0000
2236
+
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT 16
2237
+
static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT(uint32_t val)
2238
+
{
2239
+
return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK;
2240
+
}
2241
+
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK 0x0000ffff
2242
+
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT 0
2243
+
static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(uint32_t val)
2244
+
{
2245
+
return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK;
2246
+
}
2247
+
2248
+
#define REG_DPU_EW_RELUX_CMP_VALUE 0x0000407c
2249
+
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK 0xffffffff
2250
+
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT 0
2251
+
static inline uint32_t DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT(uint32_t val)
2252
+
{
2253
+
return ((val) << DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT) & DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK;
2254
+
}
2255
+
2256
+
#define REG_DPU_OUT_CVT_OFFSET 0x00004080
2257
+
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK 0xffffffff
2258
+
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT 0
2259
+
static inline uint32_t DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET(uint32_t val)
2260
+
{
2261
+
return ((val) << DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT) & DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK;
2262
+
}
2263
+
2264
+
#define REG_DPU_OUT_CVT_SCALE 0x00004084
2265
+
#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK 0xfffe0000
2266
+
#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT 17
2267
+
static inline uint32_t DPU_OUT_CVT_SCALE_RESERVED_0(uint32_t val)
2268
+
{
2269
+
return ((val) << DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT) & DPU_OUT_CVT_SCALE_RESERVED_0__MASK;
2270
+
}
2271
+
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK 0x00010000
2272
+
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT 16
2273
+
static inline uint32_t DPU_OUT_CVT_SCALE_FP32TOFP16_EN(uint32_t val)
2274
+
{
2275
+
return ((val) << DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT) & DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK;
2276
+
}
2277
+
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK 0x0000ffff
2278
+
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT 0
2279
+
static inline uint32_t DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(uint32_t val)
2280
+
{
2281
+
return ((val) << DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT) & DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK;
2282
+
}
2283
+
2284
+
#define REG_DPU_OUT_CVT_SHIFT 0x00004088
2285
+
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK 0x80000000
2286
+
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT 31
2287
+
static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_TYPE(uint32_t val)
2288
+
{
2289
+
return ((val) << DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK;
2290
+
}
2291
+
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK 0x40000000
2292
+
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT 30
2293
+
static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_ROUND(uint32_t val)
2294
+
{
2295
+
return ((val) << DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK;
2296
+
}
2297
+
#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK 0x3ff00000
2298
+
#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT 20
2299
+
static inline uint32_t DPU_OUT_CVT_SHIFT_RESERVED_0(uint32_t val)
2300
+
{
2301
+
return ((val) << DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT) & DPU_OUT_CVT_SHIFT_RESERVED_0__MASK;
2302
+
}
2303
+
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK 0x000ff000
2304
+
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT 12
2305
+
static inline uint32_t DPU_OUT_CVT_SHIFT_MINUS_EXP(uint32_t val)
2306
+
{
2307
+
return ((val) << DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT) & DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK;
2308
+
}
2309
+
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK 0x00000fff
2310
+
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT 0
2311
+
static inline uint32_t DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(uint32_t val)
2312
+
{
2313
+
return ((val) << DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT) & DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK;
2314
+
}
2315
+
2316
+
#define REG_DPU_EW_OP_VALUE_0 0x00004090
2317
+
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK 0xffffffff
2318
+
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT 0
2319
+
static inline uint32_t DPU_EW_OP_VALUE_0_EW_OPERAND_0(uint32_t val)
2320
+
{
2321
+
return ((val) << DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT) & DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK;
2322
+
}
2323
+
2324
+
#define REG_DPU_EW_OP_VALUE_1 0x00004094
2325
+
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK 0xffffffff
2326
+
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT 0
2327
+
static inline uint32_t DPU_EW_OP_VALUE_1_EW_OPERAND_1(uint32_t val)
2328
+
{
2329
+
return ((val) << DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT) & DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK;
2330
+
}
2331
+
2332
+
#define REG_DPU_EW_OP_VALUE_2 0x00004098
2333
+
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK 0xffffffff
2334
+
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT 0
2335
+
static inline uint32_t DPU_EW_OP_VALUE_2_EW_OPERAND_2(uint32_t val)
2336
+
{
2337
+
return ((val) << DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT) & DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK;
2338
+
}
2339
+
2340
+
#define REG_DPU_EW_OP_VALUE_3 0x0000409c
2341
+
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK 0xffffffff
2342
+
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT 0
2343
+
static inline uint32_t DPU_EW_OP_VALUE_3_EW_OPERAND_3(uint32_t val)
2344
+
{
2345
+
return ((val) << DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT) & DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK;
2346
+
}
2347
+
2348
+
#define REG_DPU_EW_OP_VALUE_4 0x000040a0
2349
+
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK 0xffffffff
2350
+
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT 0
2351
+
static inline uint32_t DPU_EW_OP_VALUE_4_EW_OPERAND_4(uint32_t val)
2352
+
{
2353
+
return ((val) << DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT) & DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK;
2354
+
}
2355
+
2356
+
#define REG_DPU_EW_OP_VALUE_5 0x000040a4
2357
+
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK 0xffffffff
2358
+
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT 0
2359
+
static inline uint32_t DPU_EW_OP_VALUE_5_EW_OPERAND_5(uint32_t val)
2360
+
{
2361
+
return ((val) << DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT) & DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK;
2362
+
}
2363
+
2364
+
#define REG_DPU_EW_OP_VALUE_6 0x000040a8
2365
+
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK 0xffffffff
2366
+
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT 0
2367
+
static inline uint32_t DPU_EW_OP_VALUE_6_EW_OPERAND_6(uint32_t val)
2368
+
{
2369
+
return ((val) << DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT) & DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK;
2370
+
}
2371
+
2372
+
#define REG_DPU_EW_OP_VALUE_7 0x000040ac
2373
+
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK 0xffffffff
2374
+
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT 0
2375
+
static inline uint32_t DPU_EW_OP_VALUE_7_EW_OPERAND_7(uint32_t val)
2376
+
{
2377
+
return ((val) << DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT) & DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK;
2378
+
}
2379
+
2380
+
#define REG_DPU_SURFACE_ADD 0x000040c0
2381
+
#define DPU_SURFACE_ADD_SURF_ADD__MASK 0xfffffff0
2382
+
#define DPU_SURFACE_ADD_SURF_ADD__SHIFT 4
2383
+
static inline uint32_t DPU_SURFACE_ADD_SURF_ADD(uint32_t val)
2384
+
{
2385
+
return ((val) << DPU_SURFACE_ADD_SURF_ADD__SHIFT) & DPU_SURFACE_ADD_SURF_ADD__MASK;
2386
+
}
2387
+
#define DPU_SURFACE_ADD_RESERVED_0__MASK 0x0000000f
2388
+
#define DPU_SURFACE_ADD_RESERVED_0__SHIFT 0
2389
+
static inline uint32_t DPU_SURFACE_ADD_RESERVED_0(uint32_t val)
2390
+
{
2391
+
return ((val) << DPU_SURFACE_ADD_RESERVED_0__SHIFT) & DPU_SURFACE_ADD_RESERVED_0__MASK;
2392
+
}
2393
+
2394
+
#define REG_DPU_LUT_ACCESS_CFG 0x00004100
2395
+
#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK 0xfffc0000
2396
+
#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT 18
2397
+
static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_0(uint32_t val)
2398
+
{
2399
+
return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_0__MASK;
2400
+
}
2401
+
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK 0x00020000
2402
+
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT 17
2403
+
static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE(uint32_t val)
2404
+
{
2405
+
return ((val) << DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK;
2406
+
}
2407
+
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK 0x00010000
2408
+
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT 16
2409
+
static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_TABLE_ID(uint32_t val)
2410
+
{
2411
+
return ((val) << DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK;
2412
+
}
2413
+
#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK 0x0000fc00
2414
+
#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT 10
2415
+
static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_1(uint32_t val)
2416
+
{
2417
+
return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_1__MASK;
2418
+
}
2419
+
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK 0x000003ff
2420
+
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT 0
2421
+
static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ADDR(uint32_t val)
2422
+
{
2423
+
return ((val) << DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK;
2424
+
}
2425
+
2426
+
#define REG_DPU_LUT_ACCESS_DATA 0x00004104
2427
+
#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK 0xffff0000
2428
+
#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT 16
2429
+
static inline uint32_t DPU_LUT_ACCESS_DATA_RESERVED_0(uint32_t val)
2430
+
{
2431
+
return ((val) << DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_DATA_RESERVED_0__MASK;
2432
+
}
2433
+
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK 0x0000ffff
2434
+
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT 0
2435
+
static inline uint32_t DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA(uint32_t val)
2436
+
{
2437
+
return ((val) << DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT) & DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK;
2438
+
}
2439
+
2440
+
#define REG_DPU_LUT_CFG 0x00004108
2441
+
#define DPU_LUT_CFG_RESERVED_0__MASK 0xffffff00
2442
+
#define DPU_LUT_CFG_RESERVED_0__SHIFT 8
2443
+
static inline uint32_t DPU_LUT_CFG_RESERVED_0(uint32_t val)
2444
+
{
2445
+
return ((val) << DPU_LUT_CFG_RESERVED_0__SHIFT) & DPU_LUT_CFG_RESERVED_0__MASK;
2446
+
}
2447
+
#define DPU_LUT_CFG_LUT_CAL_SEL__MASK 0x00000080
2448
+
#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT 7
2449
+
static inline uint32_t DPU_LUT_CFG_LUT_CAL_SEL(uint32_t val)
2450
+
{
2451
+
return ((val) << DPU_LUT_CFG_LUT_CAL_SEL__SHIFT) & DPU_LUT_CFG_LUT_CAL_SEL__MASK;
2452
+
}
2453
+
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK 0x00000040
2454
+
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT 6
2455
+
static inline uint32_t DPU_LUT_CFG_LUT_HYBRID_PRIORITY(uint32_t val)
2456
+
{
2457
+
return ((val) << DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK;
2458
+
}
2459
+
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK 0x00000020
2460
+
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT 5
2461
+
static inline uint32_t DPU_LUT_CFG_LUT_OFLOW_PRIORITY(uint32_t val)
2462
+
{
2463
+
return ((val) << DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK;
2464
+
}
2465
+
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK 0x00000010
2466
+
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT 4
2467
+
static inline uint32_t DPU_LUT_CFG_LUT_UFLOW_PRIORITY(uint32_t val)
2468
+
{
2469
+
return ((val) << DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK;
2470
+
}
2471
+
#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK 0x0000000c
2472
+
#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT 2
2473
+
static inline uint32_t DPU_LUT_CFG_LUT_LO_LE_MUX(uint32_t val)
2474
+
{
2475
+
return ((val) << DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT) & DPU_LUT_CFG_LUT_LO_LE_MUX__MASK;
2476
+
}
2477
+
#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK 0x00000002
2478
+
#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT 1
2479
+
static inline uint32_t DPU_LUT_CFG_LUT_EXPAND_EN(uint32_t val)
2480
+
{
2481
+
return ((val) << DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT) & DPU_LUT_CFG_LUT_EXPAND_EN__MASK;
2482
+
}
2483
+
#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK 0x00000001
2484
+
#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT 0
2485
+
static inline uint32_t DPU_LUT_CFG_LUT_ROAD_SEL(uint32_t val)
2486
+
{
2487
+
return ((val) << DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT) & DPU_LUT_CFG_LUT_ROAD_SEL__MASK;
2488
+
}
2489
+
2490
+
#define REG_DPU_LUT_INFO 0x0000410c
2491
+
#define DPU_LUT_INFO_RESERVED_0__MASK 0xff000000
2492
+
#define DPU_LUT_INFO_RESERVED_0__SHIFT 24
2493
+
static inline uint32_t DPU_LUT_INFO_RESERVED_0(uint32_t val)
2494
+
{
2495
+
return ((val) << DPU_LUT_INFO_RESERVED_0__SHIFT) & DPU_LUT_INFO_RESERVED_0__MASK;
2496
+
}
2497
+
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK 0x00ff0000
2498
+
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT 16
2499
+
static inline uint32_t DPU_LUT_INFO_LUT_LO_INDEX_SELECT(uint32_t val)
2500
+
{
2501
+
return ((val) << DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK;
2502
+
}
2503
+
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK 0x0000ff00
2504
+
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT 8
2505
+
static inline uint32_t DPU_LUT_INFO_LUT_LE_INDEX_SELECT(uint32_t val)
2506
+
{
2507
+
return ((val) << DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK;
2508
+
}
2509
+
#define DPU_LUT_INFO_RESERVED_1__MASK 0x000000ff
2510
+
#define DPU_LUT_INFO_RESERVED_1__SHIFT 0
2511
+
static inline uint32_t DPU_LUT_INFO_RESERVED_1(uint32_t val)
2512
+
{
2513
+
return ((val) << DPU_LUT_INFO_RESERVED_1__SHIFT) & DPU_LUT_INFO_RESERVED_1__MASK;
2514
+
}
2515
+
2516
+
#define REG_DPU_LUT_LE_START 0x00004110
2517
+
#define DPU_LUT_LE_START_LUT_LE_START__MASK 0xffffffff
2518
+
#define DPU_LUT_LE_START_LUT_LE_START__SHIFT 0
2519
+
static inline uint32_t DPU_LUT_LE_START_LUT_LE_START(uint32_t val)
2520
+
{
2521
+
return ((val) << DPU_LUT_LE_START_LUT_LE_START__SHIFT) & DPU_LUT_LE_START_LUT_LE_START__MASK;
2522
+
}
2523
+
2524
+
#define REG_DPU_LUT_LE_END 0x00004114
2525
+
#define DPU_LUT_LE_END_LUT_LE_END__MASK 0xffffffff
2526
+
#define DPU_LUT_LE_END_LUT_LE_END__SHIFT 0
2527
+
static inline uint32_t DPU_LUT_LE_END_LUT_LE_END(uint32_t val)
2528
+
{
2529
+
return ((val) << DPU_LUT_LE_END_LUT_LE_END__SHIFT) & DPU_LUT_LE_END_LUT_LE_END__MASK;
2530
+
}
2531
+
2532
+
#define REG_DPU_LUT_LO_START 0x00004118
2533
+
#define DPU_LUT_LO_START_LUT_LO_START__MASK 0xffffffff
2534
+
#define DPU_LUT_LO_START_LUT_LO_START__SHIFT 0
2535
+
static inline uint32_t DPU_LUT_LO_START_LUT_LO_START(uint32_t val)
2536
+
{
2537
+
return ((val) << DPU_LUT_LO_START_LUT_LO_START__SHIFT) & DPU_LUT_LO_START_LUT_LO_START__MASK;
2538
+
}
2539
+
2540
+
#define REG_DPU_LUT_LO_END 0x0000411c
2541
+
#define DPU_LUT_LO_END_LUT_LO_END__MASK 0xffffffff
2542
+
#define DPU_LUT_LO_END_LUT_LO_END__SHIFT 0
2543
+
static inline uint32_t DPU_LUT_LO_END_LUT_LO_END(uint32_t val)
2544
+
{
2545
+
return ((val) << DPU_LUT_LO_END_LUT_LO_END__SHIFT) & DPU_LUT_LO_END_LUT_LO_END__MASK;
2546
+
}
2547
+
2548
+
#define REG_DPU_LUT_LE_SLOPE_SCALE 0x00004120
2549
+
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK 0xffff0000
2550
+
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT 16
2551
+
static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE(uint32_t val)
2552
+
{
2553
+
return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK;
2554
+
}
2555
+
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
2556
+
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT 0
2557
+
static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE(uint32_t val)
2558
+
{
2559
+
return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK;
2560
+
}
2561
+
2562
+
#define REG_DPU_LUT_LE_SLOPE_SHIFT 0x00004124
2563
+
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
2564
+
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT 10
2565
+
static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0(uint32_t val)
2566
+
{
2567
+
return ((val) << DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK;
2568
+
}
2569
+
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
2570
+
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT 5
2571
+
static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT(uint32_t val)
2572
+
{
2573
+
return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK;
2574
+
}
2575
+
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
2576
+
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT 0
2577
+
static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT(uint32_t val)
2578
+
{
2579
+
return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK;
2580
+
}
2581
+
2582
+
#define REG_DPU_LUT_LO_SLOPE_SCALE 0x00004128
2583
+
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK 0xffff0000
2584
+
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT 16
2585
+
static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE(uint32_t val)
2586
+
{
2587
+
return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK;
2588
+
}
2589
+
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
2590
+
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT 0
2591
+
static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE(uint32_t val)
2592
+
{
2593
+
return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK;
2594
+
}
2595
+
2596
+
#define REG_DPU_LUT_LO_SLOPE_SHIFT 0x0000412c
2597
+
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
2598
+
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT 10
2599
+
static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0(uint32_t val)
2600
+
{
2601
+
return ((val) << DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK;
2602
+
}
2603
+
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
2604
+
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT 5
2605
+
static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT(uint32_t val)
2606
+
{
2607
+
return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK;
2608
+
}
2609
+
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
2610
+
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT 0
2611
+
static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT(uint32_t val)
2612
+
{
2613
+
return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK;
2614
+
}
2615
+
2616
+
#define REG_DPU_RDMA_RDMA_S_STATUS 0x00005000
2617
+
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
2618
+
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
2619
+
static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
2620
+
{
2621
+
return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
2622
+
}
2623
+
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
2624
+
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
2625
+
static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
2626
+
{
2627
+
return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
2628
+
}
2629
+
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
2630
+
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
2631
+
static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
2632
+
{
2633
+
return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
2634
+
}
2635
+
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
2636
+
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
2637
+
static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
2638
+
{
2639
+
return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
2640
+
}
2641
+
2642
+
#define REG_DPU_RDMA_RDMA_S_POINTER 0x00005004
2643
+
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
2644
+
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
2645
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
2646
+
{
2647
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
2648
+
}
2649
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
2650
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
2651
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
2652
+
{
2653
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
2654
+
}
2655
+
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
2656
+
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
2657
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
2658
+
{
2659
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
2660
+
}
2661
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
2662
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
2663
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
2664
+
{
2665
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
2666
+
}
2667
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
2668
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
2669
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
2670
+
{
2671
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
2672
+
}
2673
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
2674
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
2675
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
2676
+
{
2677
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
2678
+
}
2679
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
2680
+
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
2681
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
2682
+
{
2683
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
2684
+
}
2685
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
2686
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
2687
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
2688
+
{
2689
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
2690
+
}
2691
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
2692
+
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
2693
+
static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
2694
+
{
2695
+
return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
2696
+
}
2697
+
2698
+
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE 0x00005008
2699
+
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
2700
+
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
2701
+
static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
2702
+
{
2703
+
return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
2704
+
}
2705
+
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
2706
+
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
2707
+
static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
2708
+
{
2709
+
return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
2710
+
}
2711
+
2712
+
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH 0x0000500c
2713
+
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
2714
+
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
2715
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
2716
+
{
2717
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK;
2718
+
}
2719
+
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
2720
+
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
2721
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
2722
+
{
2723
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK;
2724
+
}
2725
+
2726
+
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT 0x00005010
2727
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xe0000000
2728
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 29
2729
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
2730
+
{
2731
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
2732
+
}
2733
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK 0x1fff0000
2734
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT 16
2735
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR(uint32_t val)
2736
+
{
2737
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK;
2738
+
}
2739
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x0000e000
2740
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
2741
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
2742
+
{
2743
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
2744
+
}
2745
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
2746
+
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
2747
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
2748
+
{
2749
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK;
2750
+
}
2751
+
2752
+
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL 0x00005014
2753
+
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xffffe000
2754
+
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 13
2755
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
2756
+
{
2757
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
2758
+
}
2759
+
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
2760
+
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
2761
+
static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
2762
+
{
2763
+
return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK;
2764
+
}
2765
+
2766
+
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR 0x00005018
2767
+
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
2768
+
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
2769
+
static inline uint32_t DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
2770
+
{
2771
+
return ((val) << DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
2772
+
}
2773
+
2774
+
#define REG_DPU_RDMA_RDMA_BRDMA_CFG 0x0000501c
2775
+
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK 0xffffffe0
2776
+
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT 5
2777
+
static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0(uint32_t val)
2778
+
{
2779
+
return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK;
2780
+
}
2781
+
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK 0x0000001e
2782
+
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT 1
2783
+
static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE(uint32_t val)
2784
+
{
2785
+
return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK;
2786
+
}
2787
+
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK 0x00000001
2788
+
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT 0
2789
+
static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1(uint32_t val)
2790
+
{
2791
+
return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK;
2792
+
}
2793
+
2794
+
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR 0x00005020
2795
+
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK 0xffffffff
2796
+
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT 0
2797
+
static inline uint32_t DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR(uint32_t val)
2798
+
{
2799
+
return ((val) << DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK;
2800
+
}
2801
+
2802
+
#define REG_DPU_RDMA_RDMA_NRDMA_CFG 0x00005028
2803
+
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK 0xffffffe0
2804
+
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT 5
2805
+
static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0(uint32_t val)
2806
+
{
2807
+
return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK;
2808
+
}
2809
+
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK 0x0000001e
2810
+
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT 1
2811
+
static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE(uint32_t val)
2812
+
{
2813
+
return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK;
2814
+
}
2815
+
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK 0x00000001
2816
+
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT 0
2817
+
static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1(uint32_t val)
2818
+
{
2819
+
return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK;
2820
+
}
2821
+
2822
+
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR 0x0000502c
2823
+
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK 0xffffffff
2824
+
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT 0
2825
+
static inline uint32_t DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR(uint32_t val)
2826
+
{
2827
+
return ((val) << DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK;
2828
+
}
2829
+
2830
+
#define REG_DPU_RDMA_RDMA_ERDMA_CFG 0x00005034
2831
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK 0xc0000000
2832
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT 30
2833
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE(uint32_t val)
2834
+
{
2835
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK;
2836
+
}
2837
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK 0x20000000
2838
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT 29
2839
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE(uint32_t val)
2840
+
{
2841
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK;
2842
+
}
2843
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK 0x10000000
2844
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT 28
2845
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN(uint32_t val)
2846
+
{
2847
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK;
2848
+
}
2849
+
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK 0x0ffffff0
2850
+
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT 4
2851
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0(uint32_t val)
2852
+
{
2853
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK;
2854
+
}
2855
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK 0x0000000c
2856
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT 2
2857
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE(uint32_t val)
2858
+
{
2859
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK;
2860
+
}
2861
+
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK 0x00000002
2862
+
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT 1
2863
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS(uint32_t val)
2864
+
{
2865
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK;
2866
+
}
2867
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK 0x00000001
2868
+
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT 0
2869
+
static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE(uint32_t val)
2870
+
{
2871
+
return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK;
2872
+
}
2873
+
2874
+
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR 0x00005038
2875
+
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK 0xffffffff
2876
+
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT 0
2877
+
static inline uint32_t DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR(uint32_t val)
2878
+
{
2879
+
return ((val) << DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK;
2880
+
}
2881
+
2882
+
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE 0x00005040
2883
+
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK 0xfffffff0
2884
+
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT 4
2885
+
static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE(uint32_t val)
2886
+
{
2887
+
return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK;
2888
+
}
2889
+
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
2890
+
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT 0
2891
+
static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0(uint32_t val)
2892
+
{
2893
+
return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK;
2894
+
}
2895
+
2896
+
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG 0x00005044
2897
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK 0xfffc0000
2898
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT 18
2899
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0(uint32_t val)
2900
+
{
2901
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK;
2902
+
}
2903
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK 0x00038000
2904
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT 15
2905
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION(uint32_t val)
2906
+
{
2907
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK;
2908
+
}
2909
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK 0x00007800
2910
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT 11
2911
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
2912
+
{
2913
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK;
2914
+
}
2915
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK 0x00000700
2916
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT 8
2917
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
2918
+
{
2919
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK;
2920
+
}
2921
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK 0x000000e0
2922
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT 5
2923
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION(uint32_t val)
2924
+
{
2925
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK;
2926
+
}
2927
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK 0x00000010
2928
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT 4
2929
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE(uint32_t val)
2930
+
{
2931
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK;
2932
+
}
2933
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK 0x00000008
2934
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT 3
2935
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN(uint32_t val)
2936
+
{
2937
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK;
2938
+
}
2939
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000006
2940
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT 1
2941
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
2942
+
{
2943
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK;
2944
+
}
2945
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
2946
+
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
2947
+
static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
2948
+
{
2949
+
return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK;
2950
+
}
2951
+
2952
+
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG 0x00005048
2953
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK 0xfff80000
2954
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT 19
2955
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR(uint32_t val)
2956
+
{
2957
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK;
2958
+
}
2959
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK 0x0007c000
2960
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT 14
2961
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0(uint32_t val)
2962
+
{
2963
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK;
2964
+
}
2965
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK 0x00002000
2966
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT 13
2967
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD(uint32_t val)
2968
+
{
2969
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK;
2970
+
}
2971
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK 0x00001000
2972
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT 12
2973
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN(uint32_t val)
2974
+
{
2975
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK;
2976
+
}
2977
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00000e00
2978
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 9
2979
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
2980
+
{
2981
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK;
2982
+
}
2983
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000001c0
2984
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT 6
2985
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
2986
+
{
2987
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK;
2988
+
}
2989
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK 0x00000038
2990
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT 3
2991
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT(uint32_t val)
2992
+
{
2993
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK;
2994
+
}
2995
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK 0x00000007
2996
+
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT 0
2997
+
static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH(uint32_t val)
2998
+
{
2999
+
return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK;
3000
+
}
3001
+
3002
+
#define REG_DPU_RDMA_RDMA_SURF_NOTCH 0x0000504c
3003
+
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK 0xfffffff0
3004
+
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT 4
3005
+
static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR(uint32_t val)
3006
+
{
3007
+
return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK;
3008
+
}
3009
+
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
3010
+
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT 0
3011
+
static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0(uint32_t val)
3012
+
{
3013
+
return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK;
3014
+
}
3015
+
3016
+
#define REG_DPU_RDMA_RDMA_PAD_CFG 0x00005064
3017
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK 0xffff0000
3018
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT 16
3019
+
static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE(uint32_t val)
3020
+
{
3021
+
return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK;
3022
+
}
3023
+
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK 0x0000ff80
3024
+
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT 7
3025
+
static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_0(uint32_t val)
3026
+
{
3027
+
return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK;
3028
+
}
3029
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK 0x00000070
3030
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT 4
3031
+
static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_TOP(uint32_t val)
3032
+
{
3033
+
return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK;
3034
+
}
3035
+
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK 0x00000008
3036
+
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT 3
3037
+
static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_1(uint32_t val)
3038
+
{
3039
+
return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK;
3040
+
}
3041
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK 0x00000007
3042
+
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT 0
3043
+
static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT(uint32_t val)
3044
+
{
3045
+
return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK;
3046
+
}
3047
+
3048
+
#define REG_DPU_RDMA_RDMA_WEIGHT 0x00005068
3049
+
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK 0xff000000
3050
+
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT 24
3051
+
static inline uint32_t DPU_RDMA_RDMA_WEIGHT_E_WEIGHT(uint32_t val)
3052
+
{
3053
+
return ((val) << DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK;
3054
+
}
3055
+
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK 0x00ff0000
3056
+
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT 16
3057
+
static inline uint32_t DPU_RDMA_RDMA_WEIGHT_N_WEIGHT(uint32_t val)
3058
+
{
3059
+
return ((val) << DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK;
3060
+
}
3061
+
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK 0x0000ff00
3062
+
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT 8
3063
+
static inline uint32_t DPU_RDMA_RDMA_WEIGHT_B_WEIGHT(uint32_t val)
3064
+
{
3065
+
return ((val) << DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK;
3066
+
}
3067
+
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK 0x000000ff
3068
+
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT 0
3069
+
static inline uint32_t DPU_RDMA_RDMA_WEIGHT_M_WEIGHT(uint32_t val)
3070
+
{
3071
+
return ((val) << DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK;
3072
+
}
3073
+
3074
+
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH 0x0000506c
3075
+
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK 0xfffffff0
3076
+
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT 4
3077
+
static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH(uint32_t val)
3078
+
{
3079
+
return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK;
3080
+
}
3081
+
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
3082
+
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT 0
3083
+
static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0(uint32_t val)
3084
+
{
3085
+
return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK;
3086
+
}
3087
+
3088
+
#define REG_PPU_S_STATUS 0x00006000
3089
+
#define PPU_S_STATUS_RESERVED_0__MASK 0xfffc0000
3090
+
#define PPU_S_STATUS_RESERVED_0__SHIFT 18
3091
+
static inline uint32_t PPU_S_STATUS_RESERVED_0(uint32_t val)
3092
+
{
3093
+
return ((val) << PPU_S_STATUS_RESERVED_0__SHIFT) & PPU_S_STATUS_RESERVED_0__MASK;
3094
+
}
3095
+
#define PPU_S_STATUS_STATUS_1__MASK 0x00030000
3096
+
#define PPU_S_STATUS_STATUS_1__SHIFT 16
3097
+
static inline uint32_t PPU_S_STATUS_STATUS_1(uint32_t val)
3098
+
{
3099
+
return ((val) << PPU_S_STATUS_STATUS_1__SHIFT) & PPU_S_STATUS_STATUS_1__MASK;
3100
+
}
3101
+
#define PPU_S_STATUS_RESERVED_1__MASK 0x0000fffc
3102
+
#define PPU_S_STATUS_RESERVED_1__SHIFT 2
3103
+
static inline uint32_t PPU_S_STATUS_RESERVED_1(uint32_t val)
3104
+
{
3105
+
return ((val) << PPU_S_STATUS_RESERVED_1__SHIFT) & PPU_S_STATUS_RESERVED_1__MASK;
3106
+
}
3107
+
#define PPU_S_STATUS_STATUS_0__MASK 0x00000003
3108
+
#define PPU_S_STATUS_STATUS_0__SHIFT 0
3109
+
static inline uint32_t PPU_S_STATUS_STATUS_0(uint32_t val)
3110
+
{
3111
+
return ((val) << PPU_S_STATUS_STATUS_0__SHIFT) & PPU_S_STATUS_STATUS_0__MASK;
3112
+
}
3113
+
3114
+
#define REG_PPU_S_POINTER 0x00006004
3115
+
#define PPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
3116
+
#define PPU_S_POINTER_RESERVED_0__SHIFT 17
3117
+
static inline uint32_t PPU_S_POINTER_RESERVED_0(uint32_t val)
3118
+
{
3119
+
return ((val) << PPU_S_POINTER_RESERVED_0__SHIFT) & PPU_S_POINTER_RESERVED_0__MASK;
3120
+
}
3121
+
#define PPU_S_POINTER_EXECUTER__MASK 0x00010000
3122
+
#define PPU_S_POINTER_EXECUTER__SHIFT 16
3123
+
static inline uint32_t PPU_S_POINTER_EXECUTER(uint32_t val)
3124
+
{
3125
+
return ((val) << PPU_S_POINTER_EXECUTER__SHIFT) & PPU_S_POINTER_EXECUTER__MASK;
3126
+
}
3127
+
#define PPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
3128
+
#define PPU_S_POINTER_RESERVED_1__SHIFT 6
3129
+
static inline uint32_t PPU_S_POINTER_RESERVED_1(uint32_t val)
3130
+
{
3131
+
return ((val) << PPU_S_POINTER_RESERVED_1__SHIFT) & PPU_S_POINTER_RESERVED_1__MASK;
3132
+
}
3133
+
#define PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
3134
+
#define PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
3135
+
static inline uint32_t PPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
3136
+
{
3137
+
return ((val) << PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
3138
+
}
3139
+
#define PPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
3140
+
#define PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
3141
+
static inline uint32_t PPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
3142
+
{
3143
+
return ((val) << PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_POINTER_PP_CLEAR__MASK;
3144
+
}
3145
+
#define PPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
3146
+
#define PPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
3147
+
static inline uint32_t PPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
3148
+
{
3149
+
return ((val) << PPU_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_S_POINTER_POINTER_PP_MODE__MASK;
3150
+
}
3151
+
#define PPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
3152
+
#define PPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
3153
+
static inline uint32_t PPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
3154
+
{
3155
+
return ((val) << PPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_S_POINTER_EXECUTER_PP_EN__MASK;
3156
+
}
3157
+
#define PPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
3158
+
#define PPU_S_POINTER_POINTER_PP_EN__SHIFT 1
3159
+
static inline uint32_t PPU_S_POINTER_POINTER_PP_EN(uint32_t val)
3160
+
{
3161
+
return ((val) << PPU_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_S_POINTER_POINTER_PP_EN__MASK;
3162
+
}
3163
+
#define PPU_S_POINTER_POINTER__MASK 0x00000001
3164
+
#define PPU_S_POINTER_POINTER__SHIFT 0
3165
+
static inline uint32_t PPU_S_POINTER_POINTER(uint32_t val)
3166
+
{
3167
+
return ((val) << PPU_S_POINTER_POINTER__SHIFT) & PPU_S_POINTER_POINTER__MASK;
3168
+
}
3169
+
3170
+
#define REG_PPU_OPERATION_ENABLE 0x00006008
3171
+
#define PPU_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
3172
+
#define PPU_OPERATION_ENABLE_RESERVED_0__SHIFT 1
3173
+
static inline uint32_t PPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
3174
+
{
3175
+
return ((val) << PPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_OPERATION_ENABLE_RESERVED_0__MASK;
3176
+
}
3177
+
#define PPU_OPERATION_ENABLE_OP_EN__MASK 0x00000001
3178
+
#define PPU_OPERATION_ENABLE_OP_EN__SHIFT 0
3179
+
static inline uint32_t PPU_OPERATION_ENABLE_OP_EN(uint32_t val)
3180
+
{
3181
+
return ((val) << PPU_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_OPERATION_ENABLE_OP_EN__MASK;
3182
+
}
3183
+
3184
+
#define REG_PPU_DATA_CUBE_IN_WIDTH 0x0000600c
3185
+
#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK 0xffffe000
3186
+
#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT 13
3187
+
static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
3188
+
{
3189
+
return ((val) << PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK;
3190
+
}
3191
+
#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK 0x00001fff
3192
+
#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT 0
3193
+
static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
3194
+
{
3195
+
return ((val) << PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
3196
+
}
3197
+
3198
+
#define REG_PPU_DATA_CUBE_IN_HEIGHT 0x00006010
3199
+
#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK 0xffffe000
3200
+
#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT 13
3201
+
static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
3202
+
{
3203
+
return ((val) << PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
3204
+
}
3205
+
#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK 0x00001fff
3206
+
#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT 0
3207
+
static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
3208
+
{
3209
+
return ((val) << PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
3210
+
}
3211
+
3212
+
#define REG_PPU_DATA_CUBE_IN_CHANNEL 0x00006014
3213
+
#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK 0xffffe000
3214
+
#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT 13
3215
+
static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
3216
+
{
3217
+
return ((val) << PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
3218
+
}
3219
+
#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK 0x00001fff
3220
+
#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT 0
3221
+
static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
3222
+
{
3223
+
return ((val) << PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
3224
+
}
3225
+
3226
+
#define REG_PPU_DATA_CUBE_OUT_WIDTH 0x00006018
3227
+
#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK 0xffffe000
3228
+
#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT 13
3229
+
static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0(uint32_t val)
3230
+
{
3231
+
return ((val) << PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK;
3232
+
}
3233
+
#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK 0x00001fff
3234
+
#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT 0
3235
+
static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH(uint32_t val)
3236
+
{
3237
+
return ((val) << PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK;
3238
+
}
3239
+
3240
+
#define REG_PPU_DATA_CUBE_OUT_HEIGHT 0x0000601c
3241
+
#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK 0xffffe000
3242
+
#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT 13
3243
+
static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0(uint32_t val)
3244
+
{
3245
+
return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK;
3246
+
}
3247
+
#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK 0x00001fff
3248
+
#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT 0
3249
+
static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT(uint32_t val)
3250
+
{
3251
+
return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK;
3252
+
}
3253
+
3254
+
#define REG_PPU_DATA_CUBE_OUT_CHANNEL 0x00006020
3255
+
#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK 0xffffe000
3256
+
#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT 13
3257
+
static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0(uint32_t val)
3258
+
{
3259
+
return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK;
3260
+
}
3261
+
#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK 0x00001fff
3262
+
#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT 0
3263
+
static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL(uint32_t val)
3264
+
{
3265
+
return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK;
3266
+
}
3267
+
3268
+
#define REG_PPU_OPERATION_MODE_CFG 0x00006024
3269
+
#define PPU_OPERATION_MODE_CFG_RESERVED_0__MASK 0x80000000
3270
+
#define PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT 31
3271
+
static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_0(uint32_t val)
3272
+
{
3273
+
return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_0__MASK;
3274
+
}
3275
+
#define PPU_OPERATION_MODE_CFG_INDEX_EN__MASK 0x40000000
3276
+
#define PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT 30
3277
+
static inline uint32_t PPU_OPERATION_MODE_CFG_INDEX_EN(uint32_t val)
3278
+
{
3279
+
return ((val) << PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT) & PPU_OPERATION_MODE_CFG_INDEX_EN__MASK;
3280
+
}
3281
+
#define PPU_OPERATION_MODE_CFG_RESERVED_1__MASK 0x20000000
3282
+
#define PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT 29
3283
+
static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_1(uint32_t val)
3284
+
{
3285
+
return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_1__MASK;
3286
+
}
3287
+
#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK 0x1fff0000
3288
+
#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT 16
3289
+
static inline uint32_t PPU_OPERATION_MODE_CFG_NOTCH_ADDR(uint32_t val)
3290
+
{
3291
+
return ((val) << PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT) & PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK;
3292
+
}
3293
+
#define PPU_OPERATION_MODE_CFG_RESERVED_2__MASK 0x0000ff00
3294
+
#define PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT 8
3295
+
static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_2(uint32_t val)
3296
+
{
3297
+
return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_2__MASK;
3298
+
}
3299
+
#define PPU_OPERATION_MODE_CFG_USE_CNT__MASK 0x000000e0
3300
+
#define PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT 5
3301
+
static inline uint32_t PPU_OPERATION_MODE_CFG_USE_CNT(uint32_t val)
3302
+
{
3303
+
return ((val) << PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT) & PPU_OPERATION_MODE_CFG_USE_CNT__MASK;
3304
+
}
3305
+
#define PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK 0x00000010
3306
+
#define PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT 4
3307
+
static inline uint32_t PPU_OPERATION_MODE_CFG_FLYING_MODE(uint32_t val)
3308
+
{
3309
+
return ((val) << PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT) & PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK;
3310
+
}
3311
+
#define PPU_OPERATION_MODE_CFG_RESERVED_3__MASK 0x0000000c
3312
+
#define PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT 2
3313
+
static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_3(uint32_t val)
3314
+
{
3315
+
return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_3__MASK;
3316
+
}
3317
+
#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK 0x00000003
3318
+
#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT 0
3319
+
static inline uint32_t PPU_OPERATION_MODE_CFG_POOLING_METHOD(uint32_t val)
3320
+
{
3321
+
return ((val) << PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT) & PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK;
3322
+
}
3323
+
3324
+
#define REG_PPU_POOLING_KERNEL_CFG 0x00006034
3325
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK 0xff000000
3326
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT 24
3327
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_0(uint32_t val)
3328
+
{
3329
+
return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK;
3330
+
}
3331
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00f00000
3332
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 20
3333
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
3334
+
{
3335
+
return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK;
3336
+
}
3337
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000f0000
3338
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT 16
3339
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
3340
+
{
3341
+
return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK;
3342
+
}
3343
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK 0x0000f000
3344
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT 12
3345
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_1(uint32_t val)
3346
+
{
3347
+
return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK;
3348
+
}
3349
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK 0x00000f00
3350
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT 8
3351
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT(uint32_t val)
3352
+
{
3353
+
return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK;
3354
+
}
3355
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK 0x000000f0
3356
+
#define PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT 4
3357
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_2(uint32_t val)
3358
+
{
3359
+
return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK;
3360
+
}
3361
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK 0x0000000f
3362
+
#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT 0
3363
+
static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH(uint32_t val)
3364
+
{
3365
+
return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK;
3366
+
}
3367
+
3368
+
#define REG_PPU_RECIP_KERNEL_WIDTH 0x00006038
3369
+
#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK 0xfffe0000
3370
+
#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT 17
3371
+
static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RESERVED_0(uint32_t val)
3372
+
{
3373
+
return ((val) << PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK;
3374
+
}
3375
+
#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK 0x0001ffff
3376
+
#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT 0
3377
+
static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH(uint32_t val)
3378
+
{
3379
+
return ((val) << PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK;
3380
+
}
3381
+
3382
+
#define REG_PPU_RECIP_KERNEL_HEIGHT 0x0000603c
3383
+
#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK 0xfffe0000
3384
+
#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT 17
3385
+
static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RESERVED_0(uint32_t val)
3386
+
{
3387
+
return ((val) << PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK;
3388
+
}
3389
+
#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK 0x0001ffff
3390
+
#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT 0
3391
+
static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT(uint32_t val)
3392
+
{
3393
+
return ((val) << PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK;
3394
+
}
3395
+
3396
+
#define REG_PPU_POOLING_PADDING_CFG 0x00006040
3397
+
#define PPU_POOLING_PADDING_CFG_RESERVED_0__MASK 0xffff8000
3398
+
#define PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT 15
3399
+
static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_0(uint32_t val)
3400
+
{
3401
+
return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_0__MASK;
3402
+
}
3403
+
#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK 0x00007000
3404
+
#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT 12
3405
+
static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_BOTTOM(uint32_t val)
3406
+
{
3407
+
return ((val) << PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK;
3408
+
}
3409
+
#define PPU_POOLING_PADDING_CFG_RESERVED_1__MASK 0x00000800
3410
+
#define PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT 11
3411
+
static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_1(uint32_t val)
3412
+
{
3413
+
return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_1__MASK;
3414
+
}
3415
+
#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK 0x00000700
3416
+
#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT 8
3417
+
static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_RIGHT(uint32_t val)
3418
+
{
3419
+
return ((val) << PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK;
3420
+
}
3421
+
#define PPU_POOLING_PADDING_CFG_RESERVED_2__MASK 0x00000080
3422
+
#define PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT 7
3423
+
static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_2(uint32_t val)
3424
+
{
3425
+
return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_2__MASK;
3426
+
}
3427
+
#define PPU_POOLING_PADDING_CFG_PAD_TOP__MASK 0x00000070
3428
+
#define PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT 4
3429
+
static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_TOP(uint32_t val)
3430
+
{
3431
+
return ((val) << PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_TOP__MASK;
3432
+
}
3433
+
#define PPU_POOLING_PADDING_CFG_RESERVED_3__MASK 0x00000008
3434
+
#define PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT 3
3435
+
static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_3(uint32_t val)
3436
+
{
3437
+
return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_3__MASK;
3438
+
}
3439
+
#define PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK 0x00000007
3440
+
#define PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT 0
3441
+
static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_LEFT(uint32_t val)
3442
+
{
3443
+
return ((val) << PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK;
3444
+
}
3445
+
3446
+
#define REG_PPU_PADDING_VALUE_1_CFG 0x00006044
3447
+
#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK 0xffffffff
3448
+
#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT 0
3449
+
static inline uint32_t PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0(uint32_t val)
3450
+
{
3451
+
return ((val) << PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT) & PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK;
3452
+
}
3453
+
3454
+
#define REG_PPU_PADDING_VALUE_2_CFG 0x00006048
3455
+
#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK 0xfffffff8
3456
+
#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT 3
3457
+
static inline uint32_t PPU_PADDING_VALUE_2_CFG_RESERVED_0(uint32_t val)
3458
+
{
3459
+
return ((val) << PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT) & PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK;
3460
+
}
3461
+
#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK 0x00000007
3462
+
#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT 0
3463
+
static inline uint32_t PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1(uint32_t val)
3464
+
{
3465
+
return ((val) << PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT) & PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK;
3466
+
}
3467
+
3468
+
#define REG_PPU_DST_BASE_ADDR 0x00006070
3469
+
#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK 0xfffffff0
3470
+
#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT 4
3471
+
static inline uint32_t PPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
3472
+
{
3473
+
return ((val) << PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
3474
+
}
3475
+
#define PPU_DST_BASE_ADDR_RESERVED_0__MASK 0x0000000f
3476
+
#define PPU_DST_BASE_ADDR_RESERVED_0__SHIFT 0
3477
+
static inline uint32_t PPU_DST_BASE_ADDR_RESERVED_0(uint32_t val)
3478
+
{
3479
+
return ((val) << PPU_DST_BASE_ADDR_RESERVED_0__SHIFT) & PPU_DST_BASE_ADDR_RESERVED_0__MASK;
3480
+
}
3481
+
3482
+
#define REG_PPU_DST_SURF_STRIDE 0x0000607c
3483
+
#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK 0xfffffff0
3484
+
#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT 4
3485
+
static inline uint32_t PPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
3486
+
{
3487
+
return ((val) << PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
3488
+
}
3489
+
#define PPU_DST_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
3490
+
#define PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT 0
3491
+
static inline uint32_t PPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
3492
+
{
3493
+
return ((val) << PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_DST_SURF_STRIDE_RESERVED_0__MASK;
3494
+
}
3495
+
3496
+
#define REG_PPU_DATA_FORMAT 0x00006084
3497
+
#define PPU_DATA_FORMAT_INDEX_ADD__MASK 0xfffffff0
3498
+
#define PPU_DATA_FORMAT_INDEX_ADD__SHIFT 4
3499
+
static inline uint32_t PPU_DATA_FORMAT_INDEX_ADD(uint32_t val)
3500
+
{
3501
+
return ((val) << PPU_DATA_FORMAT_INDEX_ADD__SHIFT) & PPU_DATA_FORMAT_INDEX_ADD__MASK;
3502
+
}
3503
+
#define PPU_DATA_FORMAT_DPU_FLYIN__MASK 0x00000008
3504
+
#define PPU_DATA_FORMAT_DPU_FLYIN__SHIFT 3
3505
+
static inline uint32_t PPU_DATA_FORMAT_DPU_FLYIN(uint32_t val)
3506
+
{
3507
+
return ((val) << PPU_DATA_FORMAT_DPU_FLYIN__SHIFT) & PPU_DATA_FORMAT_DPU_FLYIN__MASK;
3508
+
}
3509
+
#define PPU_DATA_FORMAT_PROC_PRECISION__MASK 0x00000007
3510
+
#define PPU_DATA_FORMAT_PROC_PRECISION__SHIFT 0
3511
+
static inline uint32_t PPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
3512
+
{
3513
+
return ((val) << PPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & PPU_DATA_FORMAT_PROC_PRECISION__MASK;
3514
+
}
3515
+
3516
+
#define REG_PPU_MISC_CTRL 0x000060dc
3517
+
#define PPU_MISC_CTRL_SURF_LEN__MASK 0xffff0000
3518
+
#define PPU_MISC_CTRL_SURF_LEN__SHIFT 16
3519
+
static inline uint32_t PPU_MISC_CTRL_SURF_LEN(uint32_t val)
3520
+
{
3521
+
return ((val) << PPU_MISC_CTRL_SURF_LEN__SHIFT) & PPU_MISC_CTRL_SURF_LEN__MASK;
3522
+
}
3523
+
#define PPU_MISC_CTRL_RESERVED_0__MASK 0x0000fe00
3524
+
#define PPU_MISC_CTRL_RESERVED_0__SHIFT 9
3525
+
static inline uint32_t PPU_MISC_CTRL_RESERVED_0(uint32_t val)
3526
+
{
3527
+
return ((val) << PPU_MISC_CTRL_RESERVED_0__SHIFT) & PPU_MISC_CTRL_RESERVED_0__MASK;
3528
+
}
3529
+
#define PPU_MISC_CTRL_MC_SURF_OUT__MASK 0x00000100
3530
+
#define PPU_MISC_CTRL_MC_SURF_OUT__SHIFT 8
3531
+
static inline uint32_t PPU_MISC_CTRL_MC_SURF_OUT(uint32_t val)
3532
+
{
3533
+
return ((val) << PPU_MISC_CTRL_MC_SURF_OUT__SHIFT) & PPU_MISC_CTRL_MC_SURF_OUT__MASK;
3534
+
}
3535
+
#define PPU_MISC_CTRL_NONALIGN__MASK 0x00000080
3536
+
#define PPU_MISC_CTRL_NONALIGN__SHIFT 7
3537
+
static inline uint32_t PPU_MISC_CTRL_NONALIGN(uint32_t val)
3538
+
{
3539
+
return ((val) << PPU_MISC_CTRL_NONALIGN__SHIFT) & PPU_MISC_CTRL_NONALIGN__MASK;
3540
+
}
3541
+
#define PPU_MISC_CTRL_RESERVED_1__MASK 0x00000070
3542
+
#define PPU_MISC_CTRL_RESERVED_1__SHIFT 4
3543
+
static inline uint32_t PPU_MISC_CTRL_RESERVED_1(uint32_t val)
3544
+
{
3545
+
return ((val) << PPU_MISC_CTRL_RESERVED_1__SHIFT) & PPU_MISC_CTRL_RESERVED_1__MASK;
3546
+
}
3547
+
#define PPU_MISC_CTRL_BURST_LEN__MASK 0x0000000f
3548
+
#define PPU_MISC_CTRL_BURST_LEN__SHIFT 0
3549
+
static inline uint32_t PPU_MISC_CTRL_BURST_LEN(uint32_t val)
3550
+
{
3551
+
return ((val) << PPU_MISC_CTRL_BURST_LEN__SHIFT) & PPU_MISC_CTRL_BURST_LEN__MASK;
3552
+
}
3553
+
3554
+
#define REG_PPU_RDMA_RDMA_S_STATUS 0x00007000
3555
+
#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
3556
+
#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
3557
+
static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
3558
+
{
3559
+
return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
3560
+
}
3561
+
#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
3562
+
#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
3563
+
static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
3564
+
{
3565
+
return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
3566
+
}
3567
+
#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
3568
+
#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
3569
+
static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
3570
+
{
3571
+
return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
3572
+
}
3573
+
#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
3574
+
#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
3575
+
static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
3576
+
{
3577
+
return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
3578
+
}
3579
+
3580
+
#define REG_PPU_RDMA_RDMA_S_POINTER 0x00007004
3581
+
#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
3582
+
#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
3583
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
3584
+
{
3585
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
3586
+
}
3587
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
3588
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
3589
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
3590
+
{
3591
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
3592
+
}
3593
+
#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
3594
+
#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
3595
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
3596
+
{
3597
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
3598
+
}
3599
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
3600
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
3601
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
3602
+
{
3603
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
3604
+
}
3605
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
3606
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
3607
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
3608
+
{
3609
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
3610
+
}
3611
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
3612
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
3613
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
3614
+
{
3615
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
3616
+
}
3617
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
3618
+
#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
3619
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
3620
+
{
3621
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
3622
+
}
3623
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
3624
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
3625
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
3626
+
{
3627
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
3628
+
}
3629
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
3630
+
#define PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
3631
+
static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
3632
+
{
3633
+
return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
3634
+
}
3635
+
3636
+
#define REG_PPU_RDMA_RDMA_OPERATION_ENABLE 0x00007008
3637
+
#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
3638
+
#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
3639
+
static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
3640
+
{
3641
+
return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
3642
+
}
3643
+
#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
3644
+
#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
3645
+
static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
3646
+
{
3647
+
return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
3648
+
}
3649
+
3650
+
#define REG_PPU_RDMA_RDMA_CUBE_IN_WIDTH 0x0000700c
3651
+
#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK 0xffffe000
3652
+
#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT 13
3653
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
3654
+
{
3655
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK;
3656
+
}
3657
+
#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK 0x00001fff
3658
+
#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT 0
3659
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
3660
+
{
3661
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
3662
+
}
3663
+
3664
+
#define REG_PPU_RDMA_RDMA_CUBE_IN_HEIGHT 0x00007010
3665
+
#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK 0xffffe000
3666
+
#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT 13
3667
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
3668
+
{
3669
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
3670
+
}
3671
+
#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK 0x00001fff
3672
+
#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT 0
3673
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
3674
+
{
3675
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
3676
+
}
3677
+
3678
+
#define REG_PPU_RDMA_RDMA_CUBE_IN_CHANNEL 0x00007014
3679
+
#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK 0xffffe000
3680
+
#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT 13
3681
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
3682
+
{
3683
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
3684
+
}
3685
+
#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK 0x00001fff
3686
+
#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT 0
3687
+
static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
3688
+
{
3689
+
return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
3690
+
}
3691
+
3692
+
#define REG_PPU_RDMA_RDMA_SRC_BASE_ADDR 0x0000701c
3693
+
#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
3694
+
#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
3695
+
static inline uint32_t PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
3696
+
{
3697
+
return ((val) << PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
3698
+
}
3699
+
3700
+
#define REG_PPU_RDMA_RDMA_SRC_LINE_STRIDE 0x00007024
3701
+
#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK 0xfffffff0
3702
+
#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT 4
3703
+
static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE(uint32_t val)
3704
+
{
3705
+
return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK;
3706
+
}
3707
+
#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK 0x0000000f
3708
+
#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT 0
3709
+
static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0(uint32_t val)
3710
+
{
3711
+
return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK;
3712
+
}
3713
+
3714
+
#define REG_PPU_RDMA_RDMA_SRC_SURF_STRIDE 0x00007028
3715
+
#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK 0xfffffff0
3716
+
#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT 4
3717
+
static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE(uint32_t val)
3718
+
{
3719
+
return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK;
3720
+
}
3721
+
#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
3722
+
#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT 0
3723
+
static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0(uint32_t val)
3724
+
{
3725
+
return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK;
3726
+
}
3727
+
3728
+
#define REG_PPU_RDMA_RDMA_DATA_FORMAT 0x00007030
3729
+
#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK 0xfffffffc
3730
+
#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT 2
3731
+
static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0(uint32_t val)
3732
+
{
3733
+
return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK;
3734
+
}
3735
+
#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK 0x00000003
3736
+
#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT 0
3737
+
static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION(uint32_t val)
3738
+
{
3739
+
return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK;
3740
+
}
3741
+
3742
+
#define REG_DDMA_CFG_OUTSTANDING 0x00008000
3743
+
#define DDMA_CFG_OUTSTANDING_RESERVED_0__MASK 0xffff0000
3744
+
#define DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT 16
3745
+
static inline uint32_t DDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
3746
+
{
3747
+
return ((val) << DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & DDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
3748
+
}
3749
+
#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK 0x0000ff00
3750
+
#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT 8
3751
+
static inline uint32_t DDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
3752
+
{
3753
+
return ((val) << DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
3754
+
}
3755
+
#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK 0x000000ff
3756
+
#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT 0
3757
+
static inline uint32_t DDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
3758
+
{
3759
+
return ((val) << DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
3760
+
}
3761
+
3762
+
#define REG_DDMA_RD_WEIGHT_0 0x00008004
3763
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK 0xff000000
3764
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT 24
3765
+
static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
3766
+
{
3767
+
return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
3768
+
}
3769
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK 0x00ff0000
3770
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT 16
3771
+
static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
3772
+
{
3773
+
return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
3774
+
}
3775
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK 0x0000ff00
3776
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT 8
3777
+
static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
3778
+
{
3779
+
return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
3780
+
}
3781
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK 0x000000ff
3782
+
#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT 0
3783
+
static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
3784
+
{
3785
+
return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
3786
+
}
3787
+
3788
+
#define REG_DDMA_WR_WEIGHT_0 0x00008008
3789
+
#define DDMA_WR_WEIGHT_0_RESERVED_0__MASK 0xffff0000
3790
+
#define DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT 16
3791
+
static inline uint32_t DDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
3792
+
{
3793
+
return ((val) << DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & DDMA_WR_WEIGHT_0_RESERVED_0__MASK;
3794
+
}
3795
+
#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK 0x0000ff00
3796
+
#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT 8
3797
+
static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
3798
+
{
3799
+
return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
3800
+
}
3801
+
#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK 0x000000ff
3802
+
#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT 0
3803
+
static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
3804
+
{
3805
+
return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
3806
+
}
3807
+
3808
+
#define REG_DDMA_CFG_ID_ERROR 0x0000800c
3809
+
#define DDMA_CFG_ID_ERROR_RESERVED_0__MASK 0xfffffc00
3810
+
#define DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT 10
3811
+
static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
3812
+
{
3813
+
return ((val) << DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_0__MASK;
3814
+
}
3815
+
#define DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK 0x000003c0
3816
+
#define DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT 6
3817
+
static inline uint32_t DDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
3818
+
{
3819
+
return ((val) << DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
3820
+
}
3821
+
#define DDMA_CFG_ID_ERROR_RESERVED_1__MASK 0x00000020
3822
+
#define DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT 5
3823
+
static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
3824
+
{
3825
+
return ((val) << DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_1__MASK;
3826
+
}
3827
+
#define DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK 0x0000001f
3828
+
#define DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT 0
3829
+
static inline uint32_t DDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
3830
+
{
3831
+
return ((val) << DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
3832
+
}
3833
+
3834
+
#define REG_DDMA_RD_WEIGHT_1 0x00008010
3835
+
#define DDMA_RD_WEIGHT_1_RESERVED_0__MASK 0xffffff00
3836
+
#define DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT 8
3837
+
static inline uint32_t DDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
3838
+
{
3839
+
return ((val) << DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & DDMA_RD_WEIGHT_1_RESERVED_0__MASK;
3840
+
}
3841
+
#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK 0x000000ff
3842
+
#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT 0
3843
+
static inline uint32_t DDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
3844
+
{
3845
+
return ((val) << DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
3846
+
}
3847
+
3848
+
#define REG_DDMA_CFG_DMA_FIFO_CLR 0x00008014
3849
+
#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK 0xfffffffe
3850
+
#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT 1
3851
+
static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
3852
+
{
3853
+
return ((val) << DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
3854
+
}
3855
+
#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK 0x00000001
3856
+
#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT 0
3857
+
static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
3858
+
{
3859
+
return ((val) << DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
3860
+
}
3861
+
3862
+
#define REG_DDMA_CFG_DMA_ARB 0x00008018
3863
+
#define DDMA_CFG_DMA_ARB_RESERVED_0__MASK 0xfffffc00
3864
+
#define DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT 10
3865
+
static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
3866
+
{
3867
+
return ((val) << DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_0__MASK;
3868
+
}
3869
+
#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK 0x00000200
3870
+
#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT 9
3871
+
static inline uint32_t DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
3872
+
{
3873
+
return ((val) << DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
3874
+
}
3875
+
#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK 0x00000100
3876
+
#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT 8
3877
+
static inline uint32_t DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
3878
+
{
3879
+
return ((val) << DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
3880
+
}
3881
+
#define DDMA_CFG_DMA_ARB_RESERVED_1__MASK 0x00000080
3882
+
#define DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT 7
3883
+
static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
3884
+
{
3885
+
return ((val) << DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_1__MASK;
3886
+
}
3887
+
#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK 0x00000070
3888
+
#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT 4
3889
+
static inline uint32_t DDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
3890
+
{
3891
+
return ((val) << DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
3892
+
}
3893
+
#define DDMA_CFG_DMA_ARB_RESERVED_2__MASK 0x00000008
3894
+
#define DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT 3
3895
+
static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
3896
+
{
3897
+
return ((val) << DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_2__MASK;
3898
+
}
3899
+
#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK 0x00000007
3900
+
#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT 0
3901
+
static inline uint32_t DDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
3902
+
{
3903
+
return ((val) << DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
3904
+
}
3905
+
3906
+
#define REG_DDMA_CFG_DMA_RD_QOS 0x00008020
3907
+
#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK 0xfffffc00
3908
+
#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT 10
3909
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
3910
+
{
3911
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
3912
+
}
3913
+
#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK 0x00000300
3914
+
#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT 8
3915
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
3916
+
{
3917
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
3918
+
}
3919
+
#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK 0x000000c0
3920
+
#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT 6
3921
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
3922
+
{
3923
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
3924
+
}
3925
+
#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK 0x00000030
3926
+
#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT 4
3927
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
3928
+
{
3929
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
3930
+
}
3931
+
#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK 0x0000000c
3932
+
#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT 2
3933
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
3934
+
{
3935
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
3936
+
}
3937
+
#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK 0x00000003
3938
+
#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT 0
3939
+
static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
3940
+
{
3941
+
return ((val) << DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
3942
+
}
3943
+
3944
+
#define REG_DDMA_CFG_DMA_RD_CFG 0x00008024
3945
+
#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK 0xffffe000
3946
+
#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT 13
3947
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
3948
+
{
3949
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
3950
+
}
3951
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK 0x00001000
3952
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT 12
3953
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
3954
+
{
3955
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
3956
+
}
3957
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK 0x00000f00
3958
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT 8
3959
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
3960
+
{
3961
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
3962
+
}
3963
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK 0x000000e0
3964
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT 5
3965
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
3966
+
{
3967
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
3968
+
}
3969
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK 0x00000018
3970
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT 3
3971
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
3972
+
{
3973
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
3974
+
}
3975
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK 0x00000007
3976
+
#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT 0
3977
+
static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
3978
+
{
3979
+
return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
3980
+
}
3981
+
3982
+
#define REG_DDMA_CFG_DMA_WR_CFG 0x00008028
3983
+
#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK 0xffffe000
3984
+
#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT 13
3985
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
3986
+
{
3987
+
return ((val) << DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
3988
+
}
3989
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK 0x00001000
3990
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT 12
3991
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
3992
+
{
3993
+
return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
3994
+
}
3995
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK 0x00000f00
3996
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT 8
3997
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
3998
+
{
3999
+
return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
4000
+
}
4001
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK 0x000000e0
4002
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT 5
4003
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
4004
+
{
4005
+
return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
4006
+
}
4007
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK 0x00000018
4008
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT 3
4009
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
4010
+
{
4011
+
return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
4012
+
}
4013
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK 0x00000007
4014
+
#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT 0
4015
+
static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
4016
+
{
4017
+
return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
4018
+
}
4019
+
4020
+
#define REG_DDMA_CFG_DMA_WSTRB 0x0000802c
4021
+
#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK 0xffffffff
4022
+
#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT 0
4023
+
static inline uint32_t DDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
4024
+
{
4025
+
return ((val) << DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
4026
+
}
4027
+
4028
+
#define REG_DDMA_CFG_STATUS 0x00008030
4029
+
#define DDMA_CFG_STATUS_RESERVED_0__MASK 0xfffffe00
4030
+
#define DDMA_CFG_STATUS_RESERVED_0__SHIFT 9
4031
+
static inline uint32_t DDMA_CFG_STATUS_RESERVED_0(uint32_t val)
4032
+
{
4033
+
return ((val) << DDMA_CFG_STATUS_RESERVED_0__SHIFT) & DDMA_CFG_STATUS_RESERVED_0__MASK;
4034
+
}
4035
+
#define DDMA_CFG_STATUS_IDEL__MASK 0x00000100
4036
+
#define DDMA_CFG_STATUS_IDEL__SHIFT 8
4037
+
static inline uint32_t DDMA_CFG_STATUS_IDEL(uint32_t val)
4038
+
{
4039
+
return ((val) << DDMA_CFG_STATUS_IDEL__SHIFT) & DDMA_CFG_STATUS_IDEL__MASK;
4040
+
}
4041
+
#define DDMA_CFG_STATUS_RESERVED_1__MASK 0x000000ff
4042
+
#define DDMA_CFG_STATUS_RESERVED_1__SHIFT 0
4043
+
static inline uint32_t DDMA_CFG_STATUS_RESERVED_1(uint32_t val)
4044
+
{
4045
+
return ((val) << DDMA_CFG_STATUS_RESERVED_1__SHIFT) & DDMA_CFG_STATUS_RESERVED_1__MASK;
4046
+
}
4047
+
4048
+
#define REG_SDMA_CFG_OUTSTANDING 0x00009000
4049
+
#define SDMA_CFG_OUTSTANDING_RESERVED_0__MASK 0xffff0000
4050
+
#define SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT 16
4051
+
static inline uint32_t SDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
4052
+
{
4053
+
return ((val) << SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & SDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
4054
+
}
4055
+
#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK 0x0000ff00
4056
+
#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT 8
4057
+
static inline uint32_t SDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
4058
+
{
4059
+
return ((val) << SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
4060
+
}
4061
+
#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK 0x000000ff
4062
+
#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT 0
4063
+
static inline uint32_t SDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
4064
+
{
4065
+
return ((val) << SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
4066
+
}
4067
+
4068
+
#define REG_SDMA_RD_WEIGHT_0 0x00009004
4069
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK 0xff000000
4070
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT 24
4071
+
static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
4072
+
{
4073
+
return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
4074
+
}
4075
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK 0x00ff0000
4076
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT 16
4077
+
static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
4078
+
{
4079
+
return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
4080
+
}
4081
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK 0x0000ff00
4082
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT 8
4083
+
static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
4084
+
{
4085
+
return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
4086
+
}
4087
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK 0x000000ff
4088
+
#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT 0
4089
+
static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
4090
+
{
4091
+
return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
4092
+
}
4093
+
4094
+
#define REG_SDMA_WR_WEIGHT_0 0x00009008
4095
+
#define SDMA_WR_WEIGHT_0_RESERVED_0__MASK 0xffff0000
4096
+
#define SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT 16
4097
+
static inline uint32_t SDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
4098
+
{
4099
+
return ((val) << SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & SDMA_WR_WEIGHT_0_RESERVED_0__MASK;
4100
+
}
4101
+
#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK 0x0000ff00
4102
+
#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT 8
4103
+
static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
4104
+
{
4105
+
return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
4106
+
}
4107
+
#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK 0x000000ff
4108
+
#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT 0
4109
+
static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
4110
+
{
4111
+
return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
4112
+
}
4113
+
4114
+
#define REG_SDMA_CFG_ID_ERROR 0x0000900c
4115
+
#define SDMA_CFG_ID_ERROR_RESERVED_0__MASK 0xfffffc00
4116
+
#define SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT 10
4117
+
static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
4118
+
{
4119
+
return ((val) << SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_0__MASK;
4120
+
}
4121
+
#define SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK 0x000003c0
4122
+
#define SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT 6
4123
+
static inline uint32_t SDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
4124
+
{
4125
+
return ((val) << SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
4126
+
}
4127
+
#define SDMA_CFG_ID_ERROR_RESERVED_1__MASK 0x00000020
4128
+
#define SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT 5
4129
+
static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
4130
+
{
4131
+
return ((val) << SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_1__MASK;
4132
+
}
4133
+
#define SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK 0x0000001f
4134
+
#define SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT 0
4135
+
static inline uint32_t SDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
4136
+
{
4137
+
return ((val) << SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
4138
+
}
4139
+
4140
+
#define REG_SDMA_RD_WEIGHT_1 0x00009010
4141
+
#define SDMA_RD_WEIGHT_1_RESERVED_0__MASK 0xffffff00
4142
+
#define SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT 8
4143
+
static inline uint32_t SDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
4144
+
{
4145
+
return ((val) << SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & SDMA_RD_WEIGHT_1_RESERVED_0__MASK;
4146
+
}
4147
+
#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK 0x000000ff
4148
+
#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT 0
4149
+
static inline uint32_t SDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
4150
+
{
4151
+
return ((val) << SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
4152
+
}
4153
+
4154
+
#define REG_SDMA_CFG_DMA_FIFO_CLR 0x00009014
4155
+
#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK 0xfffffffe
4156
+
#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT 1
4157
+
static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
4158
+
{
4159
+
return ((val) << SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
4160
+
}
4161
+
#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK 0x00000001
4162
+
#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT 0
4163
+
static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
4164
+
{
4165
+
return ((val) << SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
4166
+
}
4167
+
4168
+
#define REG_SDMA_CFG_DMA_ARB 0x00009018
4169
+
#define SDMA_CFG_DMA_ARB_RESERVED_0__MASK 0xfffffc00
4170
+
#define SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT 10
4171
+
static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
4172
+
{
4173
+
return ((val) << SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_0__MASK;
4174
+
}
4175
+
#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK 0x00000200
4176
+
#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT 9
4177
+
static inline uint32_t SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
4178
+
{
4179
+
return ((val) << SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
4180
+
}
4181
+
#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK 0x00000100
4182
+
#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT 8
4183
+
static inline uint32_t SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
4184
+
{
4185
+
return ((val) << SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
4186
+
}
4187
+
#define SDMA_CFG_DMA_ARB_RESERVED_1__MASK 0x00000080
4188
+
#define SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT 7
4189
+
static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
4190
+
{
4191
+
return ((val) << SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_1__MASK;
4192
+
}
4193
+
#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK 0x00000070
4194
+
#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT 4
4195
+
static inline uint32_t SDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
4196
+
{
4197
+
return ((val) << SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
4198
+
}
4199
+
#define SDMA_CFG_DMA_ARB_RESERVED_2__MASK 0x00000008
4200
+
#define SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT 3
4201
+
static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
4202
+
{
4203
+
return ((val) << SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_2__MASK;
4204
+
}
4205
+
#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK 0x00000007
4206
+
#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT 0
4207
+
static inline uint32_t SDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
4208
+
{
4209
+
return ((val) << SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
4210
+
}
4211
+
4212
+
#define REG_SDMA_CFG_DMA_RD_QOS 0x00009020
4213
+
#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK 0xfffffc00
4214
+
#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT 10
4215
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
4216
+
{
4217
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
4218
+
}
4219
+
#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK 0x00000300
4220
+
#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT 8
4221
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
4222
+
{
4223
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
4224
+
}
4225
+
#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK 0x000000c0
4226
+
#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT 6
4227
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
4228
+
{
4229
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
4230
+
}
4231
+
#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK 0x00000030
4232
+
#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT 4
4233
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
4234
+
{
4235
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
4236
+
}
4237
+
#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK 0x0000000c
4238
+
#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT 2
4239
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
4240
+
{
4241
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
4242
+
}
4243
+
#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK 0x00000003
4244
+
#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT 0
4245
+
static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
4246
+
{
4247
+
return ((val) << SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
4248
+
}
4249
+
4250
+
#define REG_SDMA_CFG_DMA_RD_CFG 0x00009024
4251
+
#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK 0xffffe000
4252
+
#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT 13
4253
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
4254
+
{
4255
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
4256
+
}
4257
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK 0x00001000
4258
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT 12
4259
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
4260
+
{
4261
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
4262
+
}
4263
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK 0x00000f00
4264
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT 8
4265
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
4266
+
{
4267
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
4268
+
}
4269
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK 0x000000e0
4270
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT 5
4271
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
4272
+
{
4273
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
4274
+
}
4275
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK 0x00000018
4276
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT 3
4277
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
4278
+
{
4279
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
4280
+
}
4281
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK 0x00000007
4282
+
#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT 0
4283
+
static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
4284
+
{
4285
+
return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
4286
+
}
4287
+
4288
+
#define REG_SDMA_CFG_DMA_WR_CFG 0x00009028
4289
+
#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK 0xffffe000
4290
+
#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT 13
4291
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
4292
+
{
4293
+
return ((val) << SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
4294
+
}
4295
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK 0x00001000
4296
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT 12
4297
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
4298
+
{
4299
+
return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
4300
+
}
4301
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK 0x00000f00
4302
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT 8
4303
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
4304
+
{
4305
+
return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
4306
+
}
4307
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK 0x000000e0
4308
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT 5
4309
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
4310
+
{
4311
+
return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
4312
+
}
4313
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK 0x00000018
4314
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT 3
4315
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
4316
+
{
4317
+
return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
4318
+
}
4319
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK 0x00000007
4320
+
#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT 0
4321
+
static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
4322
+
{
4323
+
return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
4324
+
}
4325
+
4326
+
#define REG_SDMA_CFG_DMA_WSTRB 0x0000902c
4327
+
#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK 0xffffffff
4328
+
#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT 0
4329
+
static inline uint32_t SDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
4330
+
{
4331
+
return ((val) << SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
4332
+
}
4333
+
4334
+
#define REG_SDMA_CFG_STATUS 0x00009030
4335
+
#define SDMA_CFG_STATUS_RESERVED_0__MASK 0xfffffe00
4336
+
#define SDMA_CFG_STATUS_RESERVED_0__SHIFT 9
4337
+
static inline uint32_t SDMA_CFG_STATUS_RESERVED_0(uint32_t val)
4338
+
{
4339
+
return ((val) << SDMA_CFG_STATUS_RESERVED_0__SHIFT) & SDMA_CFG_STATUS_RESERVED_0__MASK;
4340
+
}
4341
+
#define SDMA_CFG_STATUS_IDEL__MASK 0x00000100
4342
+
#define SDMA_CFG_STATUS_IDEL__SHIFT 8
4343
+
static inline uint32_t SDMA_CFG_STATUS_IDEL(uint32_t val)
4344
+
{
4345
+
return ((val) << SDMA_CFG_STATUS_IDEL__SHIFT) & SDMA_CFG_STATUS_IDEL__MASK;
4346
+
}
4347
+
#define SDMA_CFG_STATUS_RESERVED_1__MASK 0x000000ff
4348
+
#define SDMA_CFG_STATUS_RESERVED_1__SHIFT 0
4349
+
static inline uint32_t SDMA_CFG_STATUS_RESERVED_1(uint32_t val)
4350
+
{
4351
+
return ((val) << SDMA_CFG_STATUS_RESERVED_1__SHIFT) & SDMA_CFG_STATUS_RESERVED_1__MASK;
4352
+
}
4353
+
4354
+
#define REG_GLOBAL_OPERATION_ENABLE 0x0000f008
4355
+
#define GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK 0xffffff80
4356
+
#define GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT 7
4357
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_0(uint32_t val)
4358
+
{
4359
+
return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK;
4360
+
}
4361
+
#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK 0x00000040
4362
+
#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT 6
4363
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN(uint32_t val)
4364
+
{
4365
+
return ((val) << GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK;
4366
+
}
4367
+
#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK 0x00000020
4368
+
#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT 5
4369
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_OP_EN(uint32_t val)
4370
+
{
4371
+
return ((val) << GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK;
4372
+
}
4373
+
#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK 0x00000010
4374
+
#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT 4
4375
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN(uint32_t val)
4376
+
{
4377
+
return ((val) << GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK;
4378
+
}
4379
+
#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK 0x00000008
4380
+
#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT 3
4381
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_OP_EN(uint32_t val)
4382
+
{
4383
+
return ((val) << GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK;
4384
+
}
4385
+
#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK 0x00000004
4386
+
#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT 2
4387
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_CORE_OP_EN(uint32_t val)
4388
+
{
4389
+
return ((val) << GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK;
4390
+
}
4391
+
#define GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK 0x00000002
4392
+
#define GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT 1
4393
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_1(uint32_t val)
4394
+
{
4395
+
return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK;
4396
+
}
4397
+
#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK 0x00000001
4398
+
#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT 0
4399
+
static inline uint32_t GLOBAL_OPERATION_ENABLE_CNA_OP_EN(uint32_t val)
4400
+
{
4401
+
return ((val) << GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK;
4402
+
}
4403
+
4404
+
#endif /* __ROCKET_REGISTERS_XML__ */
+26
drivers/gpu/drm/bridge/Kconfig
+26
drivers/gpu/drm/bridge/Kconfig
···
122
122
select EXTCON
123
123
select CRYPTO
124
124
select CRYPTO_HASH
125
+
select REGMAP_I2C
125
126
help
126
127
ITE IT6505 DisplayPort bridge chip driver.
127
128
···
317
316
Support for non-programmable DRM bridges, such as ADI ADV7123, TI
318
317
THS8134 and THS8135 or passive resistor ladder DACs.
319
318
319
+
config DRM_SOLOMON_SSD2825
320
+
tristate "SSD2825 RGB/DSI bridge"
321
+
depends on SPI_MASTER && OF
322
+
select DRM_MIPI_DSI
323
+
select DRM_KMS_HELPER
324
+
select DRM_PANEL
325
+
help
326
+
Say Y here if you want support for the Solomon SSD2825 RGB/DSI
327
+
SPI bridge driver.
328
+
329
+
Say M here if you want to support this hardware as a module.
330
+
The module will be named "ssd2825".
331
+
320
332
config DRM_THINE_THC63LVD1024
321
333
tristate "Thine THC63LVD1024 LVDS decoder bridge"
322
334
depends on OF
···
451
437
help
452
438
Texas Instruments TPD12S015 HDMI level shifter and ESD protection
453
439
driver.
440
+
441
+
config DRM_WAVESHARE_BRIDGE
442
+
tristate "Waveshare DSI bridge"
443
+
depends on OF
444
+
depends on BACKLIGHT_CLASS_DEVICE
445
+
select DRM_PANEL_BRIDGE
446
+
select DRM_KMS_HELPER
447
+
select DRM_MIPI_DSI
448
+
select REGMAP_I2C
449
+
help
450
+
Driver for waveshare DSI to DPI bridge board.
451
+
Please say Y if you have such hardware
454
452
455
453
source "drivers/gpu/drm/bridge/analogix/Kconfig"
456
454
+2
drivers/gpu/drm/bridge/Makefile
+2
drivers/gpu/drm/bridge/Makefile
···
27
27
obj-$(CONFIG_DRM_SII902X) += sii902x.o
28
28
obj-$(CONFIG_DRM_SII9234) += sii9234.o
29
29
obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o
30
+
obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o
30
31
obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o
31
32
obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o
32
33
obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o
···
41
40
obj-$(CONFIG_DRM_TI_TDP158) += ti-tdp158.o
42
41
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
43
42
obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
43
+
obj-$(CONFIG_DRM_WAVESHARE_BRIDGE) += waveshare-dsi.o
44
44
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
45
45
obj-$(CONFIG_DRM_ITE_IT66121) += ite-it66121.o
46
46
+88
-123
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+88
-123
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
···
9
9
#include <drm/drm_drv.h>
10
10
#include <drm/drm_probe_helper.h>
11
11
#include <video/mipi_display.h>
12
+
#include <video/videomode.h>
12
13
13
14
#include <linux/clk.h>
14
15
#include <linux/interrupt.h>
···
418
417
#define DSI_OUTPUT_PORT 0
419
418
#define DSI_INPUT_PORT(inputid) (1 + (inputid))
420
419
421
-
#define DSI_HBP_FRAME_OVERHEAD 12
420
+
#define DSI_HBP_FRAME_PULSE_OVERHEAD 12
421
+
#define DSI_HBP_FRAME_EVENT_OVERHEAD 16
422
422
#define DSI_HSA_FRAME_OVERHEAD 14
423
423
#define DSI_HFP_FRAME_OVERHEAD 6
424
424
#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
···
454
452
return container_of(bridge, struct cdns_dsi_input, bridge);
455
453
}
456
454
457
-
static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,
458
-
bool mode_valid_check)
459
-
{
460
-
if (mode_valid_check)
461
-
return mode->hsync_start - mode->hdisplay;
462
-
463
-
return mode->crtc_hsync_start - mode->crtc_hdisplay;
464
-
}
465
-
466
455
static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,
467
456
unsigned int dpi_bpp,
468
457
unsigned int dsi_pkt_overhead)
···
469
476
}
470
477
471
478
static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
472
-
const struct drm_display_mode *mode,
473
-
struct cdns_dsi_cfg *dsi_cfg,
474
-
bool mode_valid_check)
479
+
const struct videomode *vm,
480
+
struct cdns_dsi_cfg *dsi_cfg)
475
481
{
476
482
struct cdns_dsi_output *output = &dsi->output;
477
-
unsigned int tmp;
478
-
bool sync_pulse = false;
483
+
u32 dpi_hsa, dpi_hbp, dpi_hfp, dpi_hact;
484
+
bool sync_pulse;
479
485
int bpp;
486
+
487
+
dpi_hsa = vm->hsync_len;
488
+
dpi_hbp = vm->hback_porch;
489
+
dpi_hfp = vm->hfront_porch;
490
+
dpi_hact = vm->hactive;
480
491
481
492
memset(dsi_cfg, 0, sizeof(*dsi_cfg));
482
493
483
-
if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
484
-
sync_pulse = true;
494
+
sync_pulse = output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
485
495
486
496
bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
487
497
488
-
if (mode_valid_check)
489
-
tmp = mode->htotal -
490
-
(sync_pulse ? mode->hsync_end : mode->hsync_start);
491
-
else
492
-
tmp = mode->crtc_htotal -
493
-
(sync_pulse ?
494
-
mode->crtc_hsync_end : mode->crtc_hsync_start);
495
-
496
-
dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD);
497
-
498
498
if (sync_pulse) {
499
-
if (mode_valid_check)
500
-
tmp = mode->hsync_end - mode->hsync_start;
501
-
else
502
-
tmp = mode->crtc_hsync_end - mode->crtc_hsync_start;
499
+
dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp, bpp,
500
+
DSI_HBP_FRAME_PULSE_OVERHEAD);
503
501
504
-
dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp,
502
+
dsi_cfg->hsa = dpi_to_dsi_timing(dpi_hsa, bpp,
505
503
DSI_HSA_FRAME_OVERHEAD);
504
+
} else {
505
+
dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp + dpi_hsa, bpp,
506
+
DSI_HBP_FRAME_EVENT_OVERHEAD);
507
+
508
+
dsi_cfg->hsa = 0;
506
509
}
507
510
508
-
dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ?
509
-
mode->hdisplay : mode->crtc_hdisplay,
510
-
bpp, 0);
511
-
dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),
512
-
bpp, DSI_HFP_FRAME_OVERHEAD);
511
+
dsi_cfg->hact = dpi_to_dsi_timing(dpi_hact, bpp, 0);
513
512
514
-
return 0;
515
-
}
513
+
dsi_cfg->hfp = dpi_to_dsi_timing(dpi_hfp, bpp, DSI_HFP_FRAME_OVERHEAD);
516
514
517
-
static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
518
-
struct cdns_dsi_cfg *dsi_cfg,
519
-
struct phy_configure_opts_mipi_dphy *phy_cfg,
520
-
const struct drm_display_mode *mode,
521
-
bool mode_valid_check)
522
-
{
523
-
struct cdns_dsi_output *output = &dsi->output;
524
-
unsigned long long dlane_bps;
525
-
unsigned long adj_dsi_htotal;
526
-
unsigned long dsi_htotal;
527
-
unsigned long dpi_htotal;
528
-
unsigned long dpi_hz;
529
-
unsigned int dsi_hfp_ext;
530
-
unsigned int lanes = output->dev->lanes;
515
+
dsi_cfg->htotal = dsi_cfg->hact + dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;
531
516
532
-
dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
533
-
if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
534
-
dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
535
-
536
-
dsi_htotal += dsi_cfg->hact;
537
-
dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;
538
-
539
-
/*
540
-
* Make sure DSI htotal is aligned on a lane boundary when calculating
541
-
* the expected data rate. This is done by extending HFP in case of
542
-
* misalignment.
543
-
*/
544
-
adj_dsi_htotal = dsi_htotal;
545
-
if (dsi_htotal % lanes)
546
-
adj_dsi_htotal += lanes - (dsi_htotal % lanes);
547
-
548
-
dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000;
549
-
dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;
550
-
551
-
/* data rate in bytes/sec is not an integer, refuse the mode. */
552
-
dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;
553
-
if (do_div(dlane_bps, lanes * dpi_htotal))
554
-
return -EINVAL;
555
-
556
-
/* data rate was in bytes/sec, convert to bits/sec. */
557
-
phy_cfg->hs_clk_rate = dlane_bps * 8;
558
-
559
-
dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
560
-
dsi_cfg->hfp += dsi_hfp_ext;
561
-
dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext;
517
+
if (sync_pulse) {
518
+
dsi_cfg->htotal += dsi_cfg->hbp + DSI_HBP_FRAME_PULSE_OVERHEAD;
519
+
dsi_cfg->htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
520
+
} else {
521
+
dsi_cfg->htotal += dsi_cfg->hbp + DSI_HBP_FRAME_EVENT_OVERHEAD;
522
+
}
562
523
563
524
return 0;
564
525
}
565
526
566
527
static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
567
-
const struct drm_display_mode *mode,
568
-
struct cdns_dsi_cfg *dsi_cfg,
569
-
bool mode_valid_check)
528
+
const struct videomode *vm,
529
+
struct cdns_dsi_cfg *dsi_cfg)
570
530
{
571
531
struct cdns_dsi_output *output = &dsi->output;
572
532
struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
573
-
unsigned long dsi_hss_hsa_hse_hbp;
574
533
unsigned int nlanes = output->dev->lanes;
575
-
int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);
576
534
int ret;
577
535
578
-
ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
536
+
ret = cdns_dsi_mode2cfg(dsi, vm, dsi_cfg);
579
537
if (ret)
580
538
return ret;
581
539
582
-
ret = phy_mipi_dphy_get_default_config(mode_clock * 1000,
540
+
ret = phy_mipi_dphy_get_default_config(vm->pixelclock,
583
541
mipi_dsi_pixel_format_to_bpp(output->dev->format),
584
542
nlanes, phy_cfg);
585
-
if (ret)
586
-
return ret;
587
-
588
-
ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);
589
543
if (ret)
590
544
return ret;
591
545
592
546
ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts);
593
547
if (ret)
594
548
return ret;
595
-
596
-
dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
597
-
if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
598
-
dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
599
-
600
-
/*
601
-
* Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO
602
-
* is empty before we start a receiving a new line on the DPI
603
-
* interface.
604
-
*/
605
-
if ((u64)phy_cfg->hs_clk_rate *
606
-
mode_to_dpi_hfp(mode, mode_valid_check) * nlanes <
607
-
(u64)dsi_hss_hsa_hse_hbp *
608
-
(mode_valid_check ? mode->clock : mode->crtc_clock) * 1000)
609
-
return -EINVAL;
610
549
611
550
return 0;
612
551
}
···
569
644
struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
570
645
struct cdns_dsi *dsi = input_to_dsi(input);
571
646
struct cdns_dsi_output *output = &dsi->output;
572
-
struct cdns_dsi_cfg dsi_cfg;
573
-
int bpp, ret;
647
+
int bpp;
574
648
575
649
/*
576
650
* VFP_DSI should be less than VFP_DPI and VFP_DSI should be at
···
586
662
bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
587
663
if ((mode->hdisplay * bpp) % 32)
588
664
return MODE_H_ILLEGAL;
589
-
590
-
ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, true);
591
-
if (ret)
592
-
return MODE_BAD;
593
665
594
666
return MODE_OK;
595
667
}
···
802
882
803
883
tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
804
884
phy_cfg->hs_clk_rate);
805
-
reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;
885
+
886
+
/*
887
+
* Estimated time [in clock cycles] to perform LP->HS on D-PHY.
888
+
* It is not clear how to calculate this, so for now,
889
+
* set it to 1/10 of the total number of clocks in a line.
890
+
*/
891
+
reg_wakeup = dsi_cfg.htotal / nlanes / 10;
806
892
writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
807
893
dsi->regs + VID_DPHY_TIME);
808
894
···
915
989
return input_fmts;
916
990
}
917
991
992
+
static long cdns_dsi_round_pclk(struct cdns_dsi *dsi, unsigned long pclk)
993
+
{
994
+
struct cdns_dsi_output *output = &dsi->output;
995
+
unsigned int nlanes = output->dev->lanes;
996
+
union phy_configure_opts phy_opts = { 0 };
997
+
u32 bitspp;
998
+
int ret;
999
+
1000
+
bitspp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
1001
+
1002
+
ret = phy_mipi_dphy_get_default_config(pclk, bitspp, nlanes,
1003
+
&phy_opts.mipi_dphy);
1004
+
if (ret)
1005
+
return ret;
1006
+
1007
+
ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &phy_opts);
1008
+
if (ret)
1009
+
return ret;
1010
+
1011
+
return div_u64((u64)phy_opts.mipi_dphy.hs_clk_rate * nlanes, bitspp);
1012
+
}
1013
+
918
1014
static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,
919
1015
struct drm_bridge_state *bridge_state,
920
1016
struct drm_crtc_state *crtc_state,
···
945
997
struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
946
998
struct cdns_dsi *dsi = input_to_dsi(input);
947
999
struct cdns_dsi_bridge_state *dsi_state = to_cdns_dsi_bridge_state(bridge_state);
948
-
const struct drm_display_mode *mode = &crtc_state->mode;
1000
+
struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
949
1001
struct cdns_dsi_cfg *dsi_cfg = &dsi_state->dsi_cfg;
1002
+
struct videomode vm;
1003
+
long pclk;
950
1004
951
-
return cdns_dsi_check_conf(dsi, mode, dsi_cfg, false);
1005
+
/* cdns-dsi requires negative syncs */
1006
+
adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1007
+
adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;
1008
+
1009
+
/*
1010
+
* The DPHY PLL has quite a coarsely grained clock rate options. See
1011
+
* what hsclk rate we can achieve based on the pixel clock, convert it
1012
+
* back to pixel clock, set that to the adjusted_mode->clock. This is
1013
+
* all in hopes that the CRTC will be able to provide us the requested
1014
+
* clock, as otherwise the DPI and DSI clocks will be out of sync.
1015
+
*/
1016
+
1017
+
pclk = cdns_dsi_round_pclk(dsi, adjusted_mode->clock * 1000);
1018
+
if (pclk < 0)
1019
+
return (int)pclk;
1020
+
1021
+
adjusted_mode->clock = pclk / 1000;
1022
+
1023
+
drm_display_mode_to_videomode(adjusted_mode, &vm);
1024
+
1025
+
return cdns_dsi_check_conf(dsi, &vm, dsi_cfg);
952
1026
}
953
1027
954
1028
static struct drm_bridge_state *
···
1051
1081
*/
1052
1082
if (output->dev)
1053
1083
return -EBUSY;
1054
-
1055
-
/* We do not support burst mode yet. */
1056
-
if (dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
1057
-
return -ENOTSUPP;
1058
1084
1059
1085
/*
1060
1086
* The host <-> device link might be described using an OF-graph
···
1408
1442
MODULE_DESCRIPTION("Cadence DSI driver");
1409
1443
MODULE_LICENSE("GPL");
1410
1444
MODULE_ALIAS("platform:cdns-dsi");
1411
-
+2
-2
drivers/gpu/drm/bridge/display-connector.c
+2
-2
drivers/gpu/drm/bridge/display-connector.c
···
108
108
struct drm_connector_state *conn_state,
109
109
unsigned int *num_output_fmts)
110
110
{
111
-
struct drm_bridge *prev_bridge = drm_bridge_get_prev_bridge(bridge);
111
+
struct drm_bridge *prev_bridge __free(drm_bridge_put) = drm_bridge_get_prev_bridge(bridge);
112
112
struct drm_bridge_state *prev_bridge_state;
113
113
114
114
if (!prev_bridge || !prev_bridge->funcs->atomic_get_output_bus_fmts) {
···
151
151
u32 output_fmt,
152
152
unsigned int *num_input_fmts)
153
153
{
154
-
struct drm_bridge *prev_bridge = drm_bridge_get_prev_bridge(bridge);
154
+
struct drm_bridge *prev_bridge __free(drm_bridge_put) = drm_bridge_get_prev_bridge(bridge);
155
155
struct drm_bridge_state *prev_bridge_state;
156
156
157
157
if (!prev_bridge || !prev_bridge->funcs->atomic_get_input_bus_fmts) {
+775
drivers/gpu/drm/bridge/ssd2825.c
+775
drivers/gpu/drm/bridge/ssd2825.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
#include <linux/clk.h>
4
+
#include <linux/delay.h>
5
+
#include <linux/device.h>
6
+
#include <linux/err.h>
7
+
#include <linux/kernel.h>
8
+
#include <linux/module.h>
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/mutex.h>
11
+
#include <linux/of.h>
12
+
#include <linux/regulator/consumer.h>
13
+
#include <linux/spi/spi.h>
14
+
#include <linux/units.h>
15
+
16
+
#include <drm/drm_atomic_helper.h>
17
+
#include <drm/drm_bridge.h>
18
+
#include <drm/drm_drv.h>
19
+
#include <drm/drm_mipi_dsi.h>
20
+
#include <drm/drm_of.h>
21
+
#include <drm/drm_panel.h>
22
+
#include <video/mipi_display.h>
23
+
24
+
#define SSD2825_DEVICE_ID_REG 0xb0
25
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_1 0xb1
26
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_2 0xb2
27
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_3 0xb3
28
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_4 0xb4
29
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_5 0xb5
30
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_6 0xb6
31
+
#define SSD2825_NON_BURST_EV BIT(2)
32
+
#define SSD2825_BURST BIT(3)
33
+
#define SSD2825_PCKL_HIGH BIT(13)
34
+
#define SSD2825_HSYNC_HIGH BIT(14)
35
+
#define SSD2825_VSYNC_HIGH BIT(15)
36
+
#define SSD2825_CONFIGURATION_REG 0xb7
37
+
#define SSD2825_CONF_REG_HS BIT(0)
38
+
#define SSD2825_CONF_REG_CKE BIT(1)
39
+
#define SSD2825_CONF_REG_SLP BIT(2)
40
+
#define SSD2825_CONF_REG_VEN BIT(3)
41
+
#define SSD2825_CONF_REG_HCLK BIT(4)
42
+
#define SSD2825_CONF_REG_CSS BIT(5)
43
+
#define SSD2825_CONF_REG_DCS BIT(6)
44
+
#define SSD2825_CONF_REG_REN BIT(7)
45
+
#define SSD2825_CONF_REG_ECD BIT(8)
46
+
#define SSD2825_CONF_REG_EOT BIT(9)
47
+
#define SSD2825_CONF_REG_LPE BIT(10)
48
+
#define SSD2825_VC_CTRL_REG 0xb8
49
+
#define SSD2825_PLL_CTRL_REG 0xb9
50
+
#define SSD2825_PLL_CONFIGURATION_REG 0xba
51
+
#define SSD2825_CLOCK_CTRL_REG 0xbb
52
+
#define SSD2825_PACKET_SIZE_CTRL_REG_1 0xbc
53
+
#define SSD2825_PACKET_SIZE_CTRL_REG_2 0xbd
54
+
#define SSD2825_PACKET_SIZE_CTRL_REG_3 0xbe
55
+
#define SSD2825_PACKET_DROP_REG 0xbf
56
+
#define SSD2825_OPERATION_CTRL_REG 0xc0
57
+
#define SSD2825_MAX_RETURN_SIZE_REG 0xc1
58
+
#define SSD2825_RETURN_DATA_COUNT_REG 0xc2
59
+
#define SSD2825_ACK_RESPONSE_REG 0xc3
60
+
#define SSD2825_LINE_CTRL_REG 0xc4
61
+
#define SSD2825_INTERRUPT_CTRL_REG 0xc5
62
+
#define SSD2825_INTERRUPT_STATUS_REG 0xc6
63
+
#define SSD2825_ERROR_STATUS_REG 0xc7
64
+
#define SSD2825_DATA_FORMAT_REG 0xc8
65
+
#define SSD2825_DELAY_ADJ_REG_1 0xc9
66
+
#define SSD2825_DELAY_ADJ_REG_2 0xca
67
+
#define SSD2825_DELAY_ADJ_REG_3 0xcb
68
+
#define SSD2825_DELAY_ADJ_REG_4 0xcc
69
+
#define SSD2825_DELAY_ADJ_REG_5 0xcd
70
+
#define SSD2825_DELAY_ADJ_REG_6 0xce
71
+
#define SSD2825_HS_TX_TIMER_REG_1 0xcf
72
+
#define SSD2825_HS_TX_TIMER_REG_2 0xd0
73
+
#define SSD2825_LP_RX_TIMER_REG_1 0xd1
74
+
#define SSD2825_LP_RX_TIMER_REG_2 0xd2
75
+
#define SSD2825_TE_STATUS_REG 0xd3
76
+
#define SSD2825_SPI_READ_REG 0xd4
77
+
#define SSD2825_SPI_READ_REG_RESET 0xfa
78
+
#define SSD2825_PLL_LOCK_REG 0xd5
79
+
#define SSD2825_TEST_REG 0xd6
80
+
#define SSD2825_TE_COUNT_REG 0xd7
81
+
#define SSD2825_ANALOG_CTRL_REG_1 0xd8
82
+
#define SSD2825_ANALOG_CTRL_REG_2 0xd9
83
+
#define SSD2825_ANALOG_CTRL_REG_3 0xda
84
+
#define SSD2825_ANALOG_CTRL_REG_4 0xdb
85
+
#define SSD2825_INTERRUPT_OUT_CTRL_REG 0xdc
86
+
#define SSD2825_RGB_INTERFACE_CTRL_REG_7 0xdd
87
+
#define SSD2825_LANE_CONFIGURATION_REG 0xde
88
+
#define SSD2825_DELAY_ADJ_REG_7 0xdf
89
+
#define SSD2825_INPUT_PIN_CTRL_REG_1 0xe0
90
+
#define SSD2825_INPUT_PIN_CTRL_REG_2 0xe1
91
+
#define SSD2825_BIDIR_PIN_CTRL_REG_1 0xe2
92
+
#define SSD2825_BIDIR_PIN_CTRL_REG_2 0xe3
93
+
#define SSD2825_BIDIR_PIN_CTRL_REG_3 0xe4
94
+
#define SSD2825_BIDIR_PIN_CTRL_REG_4 0xe5
95
+
#define SSD2825_BIDIR_PIN_CTRL_REG_5 0xe6
96
+
#define SSD2825_BIDIR_PIN_CTRL_REG_6 0xe7
97
+
#define SSD2825_BIDIR_PIN_CTRL_REG_7 0xe8
98
+
#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_1 0xe9
99
+
#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_2 0xea
100
+
#define SSD2825_CABC_BRIGHTNESS_STATUS_REG 0xeb
101
+
#define SSD2825_READ_REG 0xff
102
+
103
+
#define SSD2825_COM_BYTE 0x00
104
+
#define SSD2825_DAT_BYTE 0x01
105
+
106
+
#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3f)
107
+
#define SSD2825_LP_MIN_CLK 5000 /* KHz */
108
+
#define SSD2825_REF_MIN_CLK 2000 /* KHz */
109
+
110
+
static const struct regulator_bulk_data ssd2825_supplies[] = {
111
+
{ .supply = "dvdd" },
112
+
{ .supply = "avdd" },
113
+
{ .supply = "vddio" },
114
+
};
115
+
116
+
struct ssd2825_dsi_output {
117
+
struct mipi_dsi_device *dev;
118
+
struct drm_panel *panel;
119
+
struct drm_bridge *bridge;
120
+
};
121
+
122
+
struct ssd2825_priv {
123
+
struct spi_device *spi;
124
+
struct device *dev;
125
+
126
+
struct gpio_desc *reset_gpio;
127
+
struct regulator_bulk_data *supplies;
128
+
129
+
struct clk *tx_clk;
130
+
131
+
struct mipi_dsi_host dsi_host;
132
+
struct drm_bridge bridge;
133
+
struct ssd2825_dsi_output output;
134
+
135
+
struct mutex mlock; /* for host transfer operations */
136
+
137
+
u32 pd_lines; /* number of Parallel Port Input Data Lines */
138
+
u32 dsi_lanes; /* number of DSI Lanes */
139
+
140
+
/* Parameters for PLL programming */
141
+
u32 pll_freq_kbps; /* PLL in kbps */
142
+
u32 nibble_freq_khz; /* PLL div by 4 */
143
+
144
+
u32 hzd; /* HS Zero Delay in ns*/
145
+
u32 hpd; /* HS Prepare Delay is ns */
146
+
};
147
+
148
+
static inline struct ssd2825_priv *dsi_host_to_ssd2825(struct mipi_dsi_host *host)
149
+
{
150
+
return container_of(host, struct ssd2825_priv, dsi_host);
151
+
}
152
+
153
+
static inline struct ssd2825_priv *bridge_to_ssd2825(struct drm_bridge *bridge)
154
+
{
155
+
return container_of(bridge, struct ssd2825_priv, bridge);
156
+
}
157
+
158
+
static int ssd2825_write_raw(struct ssd2825_priv *priv, u8 high_byte, u8 low_byte)
159
+
{
160
+
struct spi_device *spi = priv->spi;
161
+
u8 tx_buf[2];
162
+
163
+
/*
164
+
* Low byte is the value, high byte defines type of
165
+
* write cycle, 0 for command and 1 for data.
166
+
*/
167
+
tx_buf[0] = low_byte;
168
+
tx_buf[1] = high_byte;
169
+
170
+
return spi_write(spi, tx_buf, 2);
171
+
}
172
+
173
+
static int ssd2825_write_reg(struct ssd2825_priv *priv, u8 reg, u16 command)
174
+
{
175
+
u8 datal = (command & 0x00FF);
176
+
u8 datah = (command & 0xFF00) >> 8;
177
+
int ret;
178
+
179
+
/* Command write cycle */
180
+
ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg);
181
+
if (ret)
182
+
return ret;
183
+
184
+
/* Data write cycle bits 7-0 */
185
+
ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datal);
186
+
if (ret)
187
+
return ret;
188
+
189
+
/* Data write cycle bits 15-8 */
190
+
ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datah);
191
+
if (ret)
192
+
return ret;
193
+
194
+
return 0;
195
+
}
196
+
197
+
static int ssd2825_write_dsi(struct ssd2825_priv *priv, const u8 *command, int len)
198
+
{
199
+
int ret, i;
200
+
201
+
ret = ssd2825_write_reg(priv, SSD2825_PACKET_SIZE_CTRL_REG_1, len);
202
+
if (ret)
203
+
return ret;
204
+
205
+
ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, SSD2825_PACKET_DROP_REG);
206
+
if (ret)
207
+
return ret;
208
+
209
+
for (i = 0; i < len; i++) {
210
+
ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, command[i]);
211
+
if (ret)
212
+
return ret;
213
+
}
214
+
215
+
return 0;
216
+
}
217
+
218
+
static int ssd2825_read_raw(struct ssd2825_priv *priv, u8 cmd, u16 *data)
219
+
{
220
+
struct spi_device *spi = priv->spi;
221
+
struct spi_message msg;
222
+
struct spi_transfer xfer[2];
223
+
u8 tx_buf[2];
224
+
u8 rx_buf[2];
225
+
int ret;
226
+
227
+
memset(&xfer, 0, sizeof(xfer));
228
+
229
+
tx_buf[1] = (cmd & 0xFF00) >> 8;
230
+
tx_buf[0] = (cmd & 0x00FF);
231
+
232
+
xfer[0].tx_buf = tx_buf;
233
+
xfer[0].bits_per_word = 9;
234
+
xfer[0].len = 2;
235
+
236
+
xfer[1].rx_buf = rx_buf;
237
+
xfer[1].bits_per_word = 16;
238
+
xfer[1].len = 2;
239
+
240
+
spi_message_init(&msg);
241
+
spi_message_add_tail(&xfer[0], &msg);
242
+
spi_message_add_tail(&xfer[1], &msg);
243
+
244
+
ret = spi_sync(spi, &msg);
245
+
if (ret) {
246
+
dev_err(&spi->dev, "ssd2825 read raw failed %d\n", ret);
247
+
return ret;
248
+
}
249
+
250
+
*data = rx_buf[1] | (rx_buf[0] << 8);
251
+
252
+
return 0;
253
+
}
254
+
255
+
static int ssd2825_read_reg(struct ssd2825_priv *priv, u8 reg, u16 *data)
256
+
{
257
+
int ret;
258
+
259
+
/* Reset the read register */
260
+
ret = ssd2825_write_reg(priv, SSD2825_SPI_READ_REG, SSD2825_SPI_READ_REG_RESET);
261
+
if (ret)
262
+
return ret;
263
+
264
+
/* Push the address to read */
265
+
ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg);
266
+
if (ret)
267
+
return ret;
268
+
269
+
/* Perform a reading cycle */
270
+
ret = ssd2825_read_raw(priv, SSD2825_SPI_READ_REG_RESET, data);
271
+
if (ret)
272
+
return ret;
273
+
274
+
return 0;
275
+
}
276
+
277
+
static int ssd2825_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev)
278
+
{
279
+
struct ssd2825_priv *priv = dsi_host_to_ssd2825(host);
280
+
struct drm_bridge *bridge;
281
+
struct drm_panel *panel;
282
+
struct device_node *ep;
283
+
int ret;
284
+
285
+
if (dev->lanes > 4) {
286
+
dev_err(priv->dev, "unsupported number of data lanes(%u)\n", dev->lanes);
287
+
return -EINVAL;
288
+
}
289
+
290
+
/*
291
+
* ssd2825 supports both Video and Pulse mode, but the driver only
292
+
* implements Video (event) mode currently
293
+
*/
294
+
if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
295
+
dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
296
+
return -EOPNOTSUPP;
297
+
}
298
+
299
+
ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, &bridge);
300
+
if (ret)
301
+
return ret;
302
+
303
+
if (panel) {
304
+
bridge = drm_panel_bridge_add_typed(panel, DRM_MODE_CONNECTOR_DSI);
305
+
if (IS_ERR(bridge))
306
+
return PTR_ERR(bridge);
307
+
}
308
+
309
+
priv->output.dev = dev;
310
+
priv->output.bridge = bridge;
311
+
priv->output.panel = panel;
312
+
313
+
priv->dsi_lanes = dev->lanes;
314
+
315
+
/* get input ep (port0/endpoint0) */
316
+
ret = -EINVAL;
317
+
ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
318
+
if (ep) {
319
+
ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines);
320
+
of_node_put(ep);
321
+
}
322
+
323
+
if (ret)
324
+
priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
325
+
326
+
drm_bridge_add(&priv->bridge);
327
+
328
+
return 0;
329
+
}
330
+
331
+
static int ssd2825_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev)
332
+
{
333
+
struct ssd2825_priv *priv = dsi_host_to_ssd2825(host);
334
+
335
+
drm_bridge_remove(&priv->bridge);
336
+
if (priv->output.panel)
337
+
drm_panel_bridge_remove(priv->output.bridge);
338
+
339
+
return 0;
340
+
}
341
+
342
+
static ssize_t ssd2825_dsi_host_transfer(struct mipi_dsi_host *host,
343
+
const struct mipi_dsi_msg *msg)
344
+
{
345
+
struct ssd2825_priv *priv = dsi_host_to_ssd2825(host);
346
+
u16 config;
347
+
int ret;
348
+
349
+
if (msg->rx_len) {
350
+
dev_warn(priv->dev, "MIPI rx is not supported\n");
351
+
return -EOPNOTSUPP;
352
+
}
353
+
354
+
guard(mutex)(&priv->mlock);
355
+
356
+
ret = ssd2825_read_reg(priv, SSD2825_CONFIGURATION_REG, &config);
357
+
if (ret)
358
+
return ret;
359
+
360
+
switch (msg->type) {
361
+
case MIPI_DSI_DCS_SHORT_WRITE:
362
+
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
363
+
case MIPI_DSI_DCS_LONG_WRITE:
364
+
config |= SSD2825_CONF_REG_DCS;
365
+
break;
366
+
case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
367
+
case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
368
+
case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
369
+
case MIPI_DSI_GENERIC_LONG_WRITE:
370
+
config &= ~SSD2825_CONF_REG_DCS;
371
+
break;
372
+
case MIPI_DSI_DCS_READ:
373
+
case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
374
+
case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
375
+
case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
376
+
default:
377
+
return 0;
378
+
}
379
+
380
+
ret = ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
381
+
if (ret)
382
+
return ret;
383
+
384
+
ret = ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000);
385
+
if (ret)
386
+
return ret;
387
+
388
+
ret = ssd2825_write_dsi(priv, msg->tx_buf, msg->tx_len);
389
+
if (ret)
390
+
return ret;
391
+
392
+
return 0;
393
+
}
394
+
395
+
static const struct mipi_dsi_host_ops ssd2825_dsi_host_ops = {
396
+
.attach = ssd2825_dsi_host_attach,
397
+
.detach = ssd2825_dsi_host_detach,
398
+
.transfer = ssd2825_dsi_host_transfer,
399
+
};
400
+
401
+
static void ssd2825_hw_reset(struct ssd2825_priv *priv)
402
+
{
403
+
gpiod_set_value_cansleep(priv->reset_gpio, 1);
404
+
usleep_range(5000, 6000);
405
+
gpiod_set_value_cansleep(priv->reset_gpio, 0);
406
+
usleep_range(5000, 6000);
407
+
}
408
+
409
+
/*
410
+
* PLL configuration register settings.
411
+
*
412
+
* See the "PLL Configuration Register Description" in the SSD2825 datasheet.
413
+
*/
414
+
static u16 construct_pll_config(struct ssd2825_priv *priv,
415
+
u32 desired_pll_freq_kbps, u32 reference_freq_khz)
416
+
{
417
+
u32 div_factor = 1, mul_factor, fr = 0;
418
+
419
+
while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK)
420
+
div_factor++;
421
+
if (div_factor > 31)
422
+
div_factor = 31;
423
+
424
+
mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
425
+
reference_freq_khz);
426
+
427
+
priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor;
428
+
priv->nibble_freq_khz = priv->pll_freq_kbps / 4;
429
+
430
+
if (priv->pll_freq_kbps >= 501000)
431
+
fr = 3;
432
+
else if (priv->pll_freq_kbps >= 251000)
433
+
fr = 2;
434
+
else if (priv->pll_freq_kbps >= 126000)
435
+
fr = 1;
436
+
437
+
return (fr << 14) | (div_factor << 8) | mul_factor;
438
+
}
439
+
440
+
static int ssd2825_setup_pll(struct ssd2825_priv *priv,
441
+
const struct drm_display_mode *mode)
442
+
{
443
+
u16 pll_config, lp_div;
444
+
u32 nibble_delay, pclk_mult, tx_freq_khz;
445
+
u8 hzd, hpd;
446
+
447
+
tx_freq_khz = clk_get_rate(priv->tx_clk) / KILO;
448
+
if (!tx_freq_khz)
449
+
tx_freq_khz = SSD2825_REF_MIN_CLK;
450
+
451
+
pclk_mult = priv->pd_lines / priv->dsi_lanes + 1;
452
+
pll_config = construct_pll_config(priv, pclk_mult * mode->clock,
453
+
tx_freq_khz);
454
+
455
+
lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8);
456
+
457
+
/* nibble_delay in nanoseconds */
458
+
nibble_delay = MICRO / priv->nibble_freq_khz;
459
+
460
+
hzd = priv->hzd / nibble_delay;
461
+
hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay;
462
+
463
+
/* Disable PLL */
464
+
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0000);
465
+
ssd2825_write_reg(priv, SSD2825_LINE_CTRL_REG, 0x0001);
466
+
467
+
/* Set delays */
468
+
ssd2825_write_reg(priv, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd);
469
+
470
+
/* Set PLL coefficients */
471
+
ssd2825_write_reg(priv, SSD2825_PLL_CONFIGURATION_REG, pll_config);
472
+
473
+
/* Clock Control Register */
474
+
ssd2825_write_reg(priv, SSD2825_CLOCK_CTRL_REG,
475
+
SSD2828_LP_CLOCK_DIVIDER(lp_div));
476
+
477
+
/* Enable PLL */
478
+
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001);
479
+
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);
480
+
481
+
return 0;
482
+
}
483
+
484
+
static void ssd2825_bridge_atomic_pre_enable(struct drm_bridge *bridge,
485
+
struct drm_atomic_state *state)
486
+
{
487
+
struct ssd2825_priv *priv = bridge_to_ssd2825(bridge);
488
+
struct mipi_dsi_device *dsi_dev = priv->output.dev;
489
+
const struct drm_crtc_state *crtc_state;
490
+
const struct drm_display_mode *mode;
491
+
struct drm_connector *connector;
492
+
struct drm_crtc *crtc;
493
+
u32 input_bus_flags = bridge->timings->input_bus_flags;
494
+
u16 flags = 0, config;
495
+
u8 pixel_format;
496
+
int ret;
497
+
498
+
/* Power Sequence */
499
+
ret = clk_prepare_enable(priv->tx_clk);
500
+
if (ret)
501
+
dev_err(priv->dev, "error enabling tx_clk (%d)\n", ret);
502
+
503
+
ret = regulator_bulk_enable(ARRAY_SIZE(ssd2825_supplies), priv->supplies);
504
+
if (ret)
505
+
dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
506
+
507
+
usleep_range(1000, 2000);
508
+
509
+
ssd2825_hw_reset(priv);
510
+
511
+
/* Perform SW reset */
512
+
ssd2825_write_reg(priv, SSD2825_OPERATION_CTRL_REG, 0x0100);
513
+
514
+
/* Set pixel format */
515
+
switch (dsi_dev->format) {
516
+
case MIPI_DSI_FMT_RGB565:
517
+
pixel_format = 0x00;
518
+
break;
519
+
case MIPI_DSI_FMT_RGB666_PACKED:
520
+
pixel_format = 0x01;
521
+
break;
522
+
case MIPI_DSI_FMT_RGB666:
523
+
pixel_format = 0x02;
524
+
break;
525
+
case MIPI_DSI_FMT_RGB888:
526
+
default:
527
+
pixel_format = 0x03;
528
+
break;
529
+
}
530
+
531
+
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
532
+
crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
533
+
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
534
+
mode = &crtc_state->adjusted_mode;
535
+
536
+
/* Set panel timings */
537
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_1,
538
+
((mode->vtotal - mode->vsync_end) << 8) |
539
+
(mode->htotal - mode->hsync_end));
540
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_2,
541
+
((mode->vtotal - mode->vsync_start) << 8) |
542
+
(mode->htotal - mode->hsync_start));
543
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_3,
544
+
((mode->vsync_start - mode->vdisplay) << 8) |
545
+
(mode->hsync_start - mode->hdisplay));
546
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_4, mode->hdisplay);
547
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_5, mode->vdisplay);
548
+
549
+
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
550
+
flags |= SSD2825_HSYNC_HIGH;
551
+
552
+
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
553
+
flags |= SSD2825_VSYNC_HIGH;
554
+
555
+
if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO)
556
+
flags |= SSD2825_NON_BURST_EV;
557
+
558
+
if (input_bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE)
559
+
flags |= SSD2825_PCKL_HIGH;
560
+
561
+
ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_6, flags | pixel_format);
562
+
ssd2825_write_reg(priv, SSD2825_LANE_CONFIGURATION_REG, dsi_dev->lanes - 1);
563
+
ssd2825_write_reg(priv, SSD2825_TEST_REG, 0x0004);
564
+
565
+
/* Call PLL configuration */
566
+
ssd2825_setup_pll(priv, mode);
567
+
568
+
usleep_range(10000, 11000);
569
+
570
+
config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_CKE | SSD2825_CONF_REG_DCS |
571
+
SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT;
572
+
573
+
if (dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)
574
+
config &= ~SSD2825_CONF_REG_HS;
575
+
576
+
if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
577
+
config &= ~SSD2825_CONF_REG_EOT;
578
+
579
+
/* Initial DSI configuration register set */
580
+
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
581
+
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);
582
+
583
+
if (priv->output.panel)
584
+
drm_panel_enable(priv->output.panel);
585
+
}
586
+
587
+
static void ssd2825_bridge_atomic_enable(struct drm_bridge *bridge,
588
+
struct drm_atomic_state *state)
589
+
{
590
+
struct ssd2825_priv *priv = bridge_to_ssd2825(bridge);
591
+
struct mipi_dsi_device *dsi_dev = priv->output.dev;
592
+
u16 config;
593
+
594
+
config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_DCS |
595
+
SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT;
596
+
597
+
if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO)
598
+
config |= SSD2825_CONF_REG_VEN;
599
+
600
+
if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
601
+
config &= ~SSD2825_CONF_REG_EOT;
602
+
603
+
/* Complete configuration after DSI commands were sent */
604
+
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config);
605
+
ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001);
606
+
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000);
607
+
}
608
+
609
+
static void ssd2825_bridge_atomic_disable(struct drm_bridge *bridge,
610
+
struct drm_atomic_state *state)
611
+
{
612
+
struct ssd2825_priv *priv = bridge_to_ssd2825(bridge);
613
+
int ret;
614
+
615
+
msleep(100);
616
+
617
+
/* Exit DSI configuration register set */
618
+
ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG,
619
+
SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT);
620
+
ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0);
621
+
622
+
/* HW disable */
623
+
gpiod_set_value_cansleep(priv->reset_gpio, 1);
624
+
usleep_range(5000, 6000);
625
+
626
+
ret = regulator_bulk_disable(ARRAY_SIZE(ssd2825_supplies),
627
+
priv->supplies);
628
+
if (ret < 0)
629
+
dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
630
+
631
+
clk_disable_unprepare(priv->tx_clk);
632
+
}
633
+
634
+
static int ssd2825_bridge_attach(struct drm_bridge *bridge, struct drm_encoder *encoder,
635
+
enum drm_bridge_attach_flags flags)
636
+
{
637
+
struct ssd2825_priv *priv = bridge_to_ssd2825(bridge);
638
+
639
+
return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
640
+
flags);
641
+
}
642
+
643
+
static enum drm_mode_status
644
+
ssd2825_bridge_mode_valid(struct drm_bridge *bridge,
645
+
const struct drm_display_info *info,
646
+
const struct drm_display_mode *mode)
647
+
{
648
+
if (mode->hdisplay > 1366)
649
+
return MODE_H_ILLEGAL;
650
+
651
+
if (mode->vdisplay > 1366)
652
+
return MODE_V_ILLEGAL;
653
+
654
+
return MODE_OK;
655
+
}
656
+
657
+
static bool ssd2825_mode_fixup(struct drm_bridge *bridge,
658
+
const struct drm_display_mode *mode,
659
+
struct drm_display_mode *adjusted_mode)
660
+
{
661
+
/* Default to positive sync */
662
+
663
+
if (!(adjusted_mode->flags &
664
+
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
665
+
adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
666
+
667
+
if (!(adjusted_mode->flags &
668
+
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
669
+
adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;
670
+
671
+
return true;
672
+
}
673
+
674
+
static const struct drm_bridge_funcs ssd2825_bridge_funcs = {
675
+
.attach = ssd2825_bridge_attach,
676
+
.mode_valid = ssd2825_bridge_mode_valid,
677
+
.mode_fixup = ssd2825_mode_fixup,
678
+
679
+
.atomic_pre_enable = ssd2825_bridge_atomic_pre_enable,
680
+
.atomic_enable = ssd2825_bridge_atomic_enable,
681
+
.atomic_disable = ssd2825_bridge_atomic_disable,
682
+
683
+
.atomic_reset = drm_atomic_helper_bridge_reset,
684
+
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
685
+
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
686
+
};
687
+
688
+
static const struct drm_bridge_timings default_ssd2825_timings = {
689
+
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
690
+
| DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
691
+
| DRM_BUS_FLAG_DE_HIGH,
692
+
};
693
+
694
+
static int ssd2825_probe(struct spi_device *spi)
695
+
{
696
+
struct ssd2825_priv *priv;
697
+
struct device *dev = &spi->dev;
698
+
struct device_node *np = dev->of_node;
699
+
int ret;
700
+
701
+
/* Driver supports only 8 bit 3 Wire mode */
702
+
spi->bits_per_word = 9;
703
+
704
+
ret = spi_setup(spi);
705
+
if (ret)
706
+
return ret;
707
+
708
+
priv = devm_drm_bridge_alloc(dev, struct ssd2825_priv, bridge, &ssd2825_bridge_funcs);
709
+
if (IS_ERR(priv))
710
+
return PTR_ERR(priv);
711
+
712
+
spi_set_drvdata(spi, priv);
713
+
714
+
priv->spi = spi;
715
+
priv->dev = dev;
716
+
717
+
mutex_init(&priv->mlock);
718
+
719
+
priv->tx_clk = devm_clk_get_optional(dev, NULL);
720
+
if (IS_ERR(priv->tx_clk))
721
+
return dev_err_probe(dev, PTR_ERR(priv->tx_clk),
722
+
"can't retrieve bridge tx_clk\n");
723
+
724
+
priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
725
+
GPIOD_OUT_HIGH);
726
+
if (IS_ERR(priv->reset_gpio))
727
+
return dev_err_probe(dev, PTR_ERR(priv->reset_gpio),
728
+
"failed to get reset GPIO\n");
729
+
730
+
ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(ssd2825_supplies),
731
+
ssd2825_supplies, &priv->supplies);
732
+
if (ret)
733
+
return dev_err_probe(dev, ret, "failed to get regulators\n");
734
+
735
+
priv->hzd = 133; /* ns */
736
+
device_property_read_u32(dev, "solomon,hs-zero-delay-ns", &priv->hzd);
737
+
738
+
priv->hpd = 40; /* ns */
739
+
device_property_read_u32(dev, "solomon,hs-prep-delay-ns", &priv->hpd);
740
+
741
+
priv->dsi_host.dev = dev;
742
+
priv->dsi_host.ops = &ssd2825_dsi_host_ops;
743
+
744
+
priv->bridge.timings = &default_ssd2825_timings;
745
+
priv->bridge.of_node = np;
746
+
747
+
return mipi_dsi_host_register(&priv->dsi_host);
748
+
}
749
+
750
+
static void ssd2825_remove(struct spi_device *spi)
751
+
{
752
+
struct ssd2825_priv *priv = spi_get_drvdata(spi);
753
+
754
+
mipi_dsi_host_unregister(&priv->dsi_host);
755
+
}
756
+
757
+
static const struct of_device_id ssd2825_of_match[] = {
758
+
{ .compatible = "solomon,ssd2825" },
759
+
{ /* sentinel */ }
760
+
};
761
+
MODULE_DEVICE_TABLE(of, ssd2825_of_match);
762
+
763
+
static struct spi_driver ssd2825_driver = {
764
+
.driver = {
765
+
.name = "ssd2825",
766
+
.of_match_table = ssd2825_of_match,
767
+
},
768
+
.probe = ssd2825_probe,
769
+
.remove = ssd2825_remove,
770
+
};
771
+
module_spi_driver(ssd2825_driver);
772
+
773
+
MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
774
+
MODULE_DESCRIPTION("Solomon SSD2825 RGB to MIPI-DSI bridge driver SPI");
775
+
MODULE_LICENSE("GPL");
+4
drivers/gpu/drm/display/drm_bridge_connector.c
+4
drivers/gpu/drm/display/drm_bridge_connector.c
···
816
816
817
817
if (bridge_connector->bridge_hdmi_cec &&
818
818
bridge_connector->bridge_hdmi_cec->ops & DRM_BRIDGE_OP_HDMI_CEC_NOTIFIER) {
819
+
bridge = bridge_connector->bridge_hdmi_cec;
820
+
819
821
ret = drmm_connector_hdmi_cec_notifier_register(connector,
820
822
NULL,
821
823
bridge->hdmi_cec_dev);
···
827
825
828
826
if (bridge_connector->bridge_hdmi_cec &&
829
827
bridge_connector->bridge_hdmi_cec->ops & DRM_BRIDGE_OP_HDMI_CEC_ADAPTER) {
828
+
bridge = bridge_connector->bridge_hdmi_cec;
829
+
830
830
ret = drmm_connector_hdmi_cec_register(connector,
831
831
&drm_bridge_connector_hdmi_cec_funcs,
832
832
bridge->hdmi_cec_adapter_name,
+7
drivers/gpu/drm/drm_atomic_helper.c
+7
drivers/gpu/drm/drm_atomic_helper.c
···
456
456
ret = drm_atomic_bridge_chain_check(bridge,
457
457
new_crtc_state,
458
458
new_conn_state);
459
+
drm_bridge_put(bridge);
459
460
if (ret) {
460
461
drm_dbg_atomic(encoder->dev, "Bridge atomic check failed\n");
461
462
return ret;
···
528
527
bridge = drm_bridge_chain_get_first_bridge(encoder);
529
528
ret = drm_bridge_chain_mode_valid(bridge, &connector->display_info,
530
529
mode);
530
+
drm_bridge_put(bridge);
531
531
if (ret != MODE_OK) {
532
532
drm_dbg_atomic(encoder->dev, "[BRIDGE] mode_valid() failed\n");
533
533
return ret;
···
1214
1212
*/
1215
1213
bridge = drm_bridge_chain_get_first_bridge(encoder);
1216
1214
drm_atomic_bridge_chain_disable(bridge, state);
1215
+
drm_bridge_put(bridge);
1217
1216
1218
1217
/* Right function depends upon target state. */
1219
1218
if (funcs) {
···
1332
1329
*/
1333
1330
bridge = drm_bridge_chain_get_first_bridge(encoder);
1334
1331
drm_atomic_bridge_chain_post_disable(bridge, state);
1332
+
drm_bridge_put(bridge);
1335
1333
}
1336
1334
}
1337
1335
···
1505
1501
1506
1502
bridge = drm_bridge_chain_get_first_bridge(encoder);
1507
1503
drm_bridge_chain_mode_set(bridge, mode, adjusted_mode);
1504
+
drm_bridge_put(bridge);
1508
1505
}
1509
1506
}
1510
1507
···
1585
1580
*/
1586
1581
bridge = drm_bridge_chain_get_first_bridge(encoder);
1587
1582
drm_atomic_bridge_chain_pre_enable(bridge, state);
1583
+
drm_bridge_put(bridge);
1588
1584
}
1589
1585
}
1590
1586
···
1661
1655
}
1662
1656
1663
1657
drm_atomic_bridge_chain_enable(bridge, state);
1658
+
drm_bridge_put(bridge);
1664
1659
}
1665
1660
}
1666
1661
+2
-2
drivers/gpu/drm/drm_bridge.c
+2
-2
drivers/gpu/drm/drm_bridge.c
···
941
941
{
942
942
unsigned int i, num_in_bus_fmts = 0;
943
943
struct drm_bridge_state *cur_state;
944
-
struct drm_bridge *prev_bridge;
944
+
struct drm_bridge *prev_bridge __free(drm_bridge_put) =
945
+
drm_bridge_get_prev_bridge(cur_bridge);
945
946
u32 *in_bus_fmts;
946
947
int ret;
947
948
948
-
prev_bridge = drm_bridge_get_prev_bridge(cur_bridge);
949
949
cur_state = drm_atomic_get_new_bridge_state(crtc_state->state,
950
950
cur_bridge);
951
951
+56
-30
drivers/gpu/drm/drm_gem.c
+56
-30
drivers/gpu/drm/drm_gem.c
···
332
332
if (obj->funcs->close)
333
333
obj->funcs->close(obj, file_priv);
334
334
335
+
mutex_lock(&file_priv->prime.lock);
336
+
335
337
drm_prime_remove_buf_handle(&file_priv->prime, id);
338
+
339
+
mutex_unlock(&file_priv->prime.lock);
340
+
336
341
drm_vma_node_revoke(&obj->vma_node, file_priv);
337
342
338
343
drm_gem_object_handle_put_unlocked(obj);
···
875
870
}
876
871
EXPORT_SYMBOL(drm_gem_dma_resv_wait);
877
872
878
-
/**
879
-
* drm_gem_close_ioctl - implementation of the GEM_CLOSE ioctl
880
-
* @dev: drm_device
881
-
* @data: ioctl data
882
-
* @file_priv: drm file-private structure
883
-
*
884
-
* Releases the handle to an mm object.
885
-
*/
886
873
int
887
874
drm_gem_close_ioctl(struct drm_device *dev, void *data,
888
875
struct drm_file *file_priv)
···
890
893
return ret;
891
894
}
892
895
893
-
/**
894
-
* drm_gem_flink_ioctl - implementation of the GEM_FLINK ioctl
895
-
* @dev: drm_device
896
-
* @data: ioctl data
897
-
* @file_priv: drm file-private structure
898
-
*
899
-
* Create a global name for an object, returning the name.
900
-
*
901
-
* Note that the name does not hold a reference; when the object
902
-
* is freed, the name goes away.
903
-
*/
904
896
int
905
897
drm_gem_flink_ioctl(struct drm_device *dev, void *data,
906
898
struct drm_file *file_priv)
···
929
943
return ret;
930
944
}
931
945
932
-
/**
933
-
* drm_gem_open_ioctl - implementation of the GEM_OPEN ioctl
934
-
* @dev: drm_device
935
-
* @data: ioctl data
936
-
* @file_priv: drm file-private structure
937
-
*
938
-
* Open an object using the global name, returning a handle and the size.
939
-
*
940
-
* This handle (of course) holds a reference to the object, so the object
941
-
* will not go away until the handle is deleted.
942
-
*/
943
946
int
944
947
drm_gem_open_ioctl(struct drm_device *dev, void *data,
945
948
struct drm_file *file_priv)
···
960
985
961
986
err:
962
987
drm_gem_object_put(obj);
988
+
return ret;
989
+
}
990
+
991
+
int drm_gem_change_handle_ioctl(struct drm_device *dev, void *data,
992
+
struct drm_file *file_priv)
993
+
{
994
+
struct drm_gem_change_handle *args = data;
995
+
struct drm_gem_object *obj;
996
+
int ret;
997
+
998
+
if (!drm_core_check_feature(dev, DRIVER_GEM))
999
+
return -EOPNOTSUPP;
1000
+
1001
+
obj = drm_gem_object_lookup(file_priv, args->handle);
1002
+
if (!obj)
1003
+
return -ENOENT;
1004
+
1005
+
if (args->handle == args->new_handle)
1006
+
return 0;
1007
+
1008
+
mutex_lock(&file_priv->prime.lock);
1009
+
1010
+
spin_lock(&file_priv->table_lock);
1011
+
ret = idr_alloc(&file_priv->object_idr, obj,
1012
+
args->new_handle, args->new_handle + 1, GFP_NOWAIT);
1013
+
spin_unlock(&file_priv->table_lock);
1014
+
1015
+
if (ret < 0)
1016
+
goto out_unlock;
1017
+
1018
+
if (obj->dma_buf) {
1019
+
ret = drm_prime_add_buf_handle(&file_priv->prime, obj->dma_buf, args->new_handle);
1020
+
if (ret < 0) {
1021
+
spin_lock(&file_priv->table_lock);
1022
+
idr_remove(&file_priv->object_idr, args->new_handle);
1023
+
spin_unlock(&file_priv->table_lock);
1024
+
goto out_unlock;
1025
+
}
1026
+
1027
+
drm_prime_remove_buf_handle(&file_priv->prime, args->handle);
1028
+
}
1029
+
1030
+
ret = 0;
1031
+
1032
+
spin_lock(&file_priv->table_lock);
1033
+
idr_remove(&file_priv->object_idr, args->handle);
1034
+
spin_unlock(&file_priv->table_lock);
1035
+
1036
+
out_unlock:
1037
+
mutex_unlock(&file_priv->prime.lock);
1038
+
963
1039
return ret;
964
1040
}
965
1041
+4
drivers/gpu/drm/drm_internal.h
+4
drivers/gpu/drm/drm_internal.h
···
85
85
86
86
void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv);
87
87
void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv);
88
+
int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
89
+
struct dma_buf *dma_buf, uint32_t handle);
88
90
void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv,
89
91
uint32_t handle);
90
92
···
172
170
struct drm_file *file_priv);
173
171
int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
174
172
struct drm_file *file_priv);
173
+
int drm_gem_change_handle_ioctl(struct drm_device *dev, void *data,
174
+
struct drm_file *file_priv);
175
175
int drm_gem_open_ioctl(struct drm_device *dev, void *data,
176
176
struct drm_file *file_priv);
177
177
void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
+1
drivers/gpu/drm/drm_ioctl.c
+1
drivers/gpu/drm/drm_ioctl.c
···
653
653
DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_RENDER_ALLOW),
654
654
DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH),
655
655
DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH),
656
+
DRM_IOCTL_DEF(DRM_IOCTL_GEM_CHANGE_HANDLE, drm_gem_change_handle_ioctl, DRM_RENDER_ALLOW),
656
657
657
658
DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, 0),
658
659
+51
-31
drivers/gpu/drm/drm_mipi_dsi.c
+51
-31
drivers/gpu/drm/drm_mipi_dsi.c
···
773
773
EXPORT_SYMBOL(mipi_dsi_generic_write);
774
774
775
775
/**
776
-
* mipi_dsi_generic_write_chatty() - mipi_dsi_generic_write() w/ an error log
777
-
* @dsi: DSI peripheral device
778
-
* @payload: buffer containing the payload
779
-
* @size: size of payload buffer
780
-
*
781
-
* Like mipi_dsi_generic_write() but includes a dev_err()
782
-
* call for you and returns 0 upon success, not the number of bytes sent.
783
-
*
784
-
* Return: 0 on success or a negative error code on failure.
785
-
*/
786
-
int mipi_dsi_generic_write_chatty(struct mipi_dsi_device *dsi,
787
-
const void *payload, size_t size)
788
-
{
789
-
struct device *dev = &dsi->dev;
790
-
ssize_t ret;
791
-
792
-
ret = mipi_dsi_generic_write(dsi, payload, size);
793
-
if (ret < 0) {
794
-
dev_err(dev, "sending generic data %*ph failed: %zd\n",
795
-
(int)size, payload, ret);
796
-
return ret;
797
-
}
798
-
799
-
return 0;
800
-
}
801
-
EXPORT_SYMBOL(mipi_dsi_generic_write_chatty);
802
-
803
-
/**
804
-
* mipi_dsi_generic_write_multi() - mipi_dsi_generic_write_chatty() w/ accum_err
776
+
* mipi_dsi_generic_write_multi() - mipi_dsi_generic_write() w/ accum_err
805
777
* @ctx: Context for multiple DSI transactions
806
778
* @payload: buffer containing the payload
807
779
* @size: size of payload buffer
808
780
*
809
-
* Like mipi_dsi_generic_write_chatty() but deals with errors in a way that
810
-
* makes it convenient to make several calls in a row.
781
+
* A wrapper around mipi_dsi_generic_write() that deals with errors in a way
782
+
* that makes it convenient to make several calls in a row.
811
783
*/
812
784
void mipi_dsi_generic_write_multi(struct mipi_dsi_multi_context *ctx,
813
785
const void *payload, size_t size)
···
799
827
}
800
828
}
801
829
EXPORT_SYMBOL(mipi_dsi_generic_write_multi);
830
+
831
+
/**
832
+
* mipi_dsi_dual_generic_write_multi() - mipi_dsi_generic_write_multi() for
833
+
* two dsi channels, one after the other
834
+
* @ctx: Context for multiple DSI transactions
835
+
* @dsi1: First dsi channel to write buffer to
836
+
* @dsi2: Second dsi channel to write buffer to
837
+
* @payload: Buffer containing the payload
838
+
* @size: Size of payload buffer
839
+
*
840
+
* A wrapper around mipi_dsi_generic_write_multi() that allows the user to
841
+
* conveniently write to two dsi channels, one after the other.
842
+
*/
843
+
void mipi_dsi_dual_generic_write_multi(struct mipi_dsi_multi_context *ctx,
844
+
struct mipi_dsi_device *dsi1,
845
+
struct mipi_dsi_device *dsi2,
846
+
const void *payload, size_t size)
847
+
{
848
+
ctx->dsi = dsi1;
849
+
mipi_dsi_generic_write_multi(ctx, payload, size);
850
+
ctx->dsi = dsi2;
851
+
mipi_dsi_generic_write_multi(ctx, payload, size);
852
+
}
853
+
EXPORT_SYMBOL(mipi_dsi_dual_generic_write_multi);
802
854
803
855
/**
804
856
* mipi_dsi_generic_read() - receive data using a generic read packet
···
1002
1006
}
1003
1007
}
1004
1008
EXPORT_SYMBOL(mipi_dsi_dcs_write_buffer_multi);
1009
+
1010
+
/**
1011
+
* mipi_dsi_dual_dcs_write_buffer_multi - mipi_dsi_dcs_write_buffer_multi() for
1012
+
* two dsi channels, one after the other
1013
+
* @ctx: Context for multiple DSI transactions
1014
+
* @dsi1: First dsi channel to write buffer to
1015
+
* @dsi2: Second dsi channel to write buffer to
1016
+
* @data: Buffer containing data to be transmitted
1017
+
* @len: Size of transmission buffer
1018
+
*
1019
+
* A wrapper around mipi_dsi_dcs_write_buffer_multi() that allows the user to
1020
+
* conveniently write to two dsi channels, one after the other.
1021
+
*/
1022
+
void mipi_dsi_dual_dcs_write_buffer_multi(struct mipi_dsi_multi_context *ctx,
1023
+
struct mipi_dsi_device *dsi1,
1024
+
struct mipi_dsi_device *dsi2,
1025
+
const void *data, size_t len)
1026
+
{
1027
+
ctx->dsi = dsi1;
1028
+
mipi_dsi_dcs_write_buffer_multi(ctx, data, len);
1029
+
ctx->dsi = dsi2;
1030
+
mipi_dsi_dcs_write_buffer_multi(ctx, data, len);
1031
+
}
1032
+
EXPORT_SYMBOL(mipi_dsi_dual_dcs_write_buffer_multi);
1005
1033
1006
1034
/**
1007
1035
* mipi_dsi_dcs_write() - send DCS write command
+1
-5
drivers/gpu/drm/drm_prime.c
+1
-5
drivers/gpu/drm/drm_prime.c
···
93
93
struct rb_node handle_rb;
94
94
};
95
95
96
-
static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
96
+
int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
97
97
struct dma_buf *dma_buf, uint32_t handle)
98
98
{
99
99
struct drm_prime_member *member;
···
190
190
{
191
191
struct rb_node *rb;
192
192
193
-
mutex_lock(&prime_fpriv->lock);
194
-
195
193
rb = prime_fpriv->handles.rb_node;
196
194
while (rb) {
197
195
struct drm_prime_member *member;
···
208
210
rb = rb->rb_left;
209
211
}
210
212
}
211
-
212
-
mutex_unlock(&prime_fpriv->lock);
213
213
}
214
214
215
215
void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv)
+1
drivers/gpu/drm/drm_probe_helper.c
+1
drivers/gpu/drm/drm_probe_helper.c
-2
drivers/gpu/drm/gud/gud_drv.c
-2
drivers/gpu/drm/gud/gud_drv.c
+2
-2
drivers/gpu/drm/mxsfb/lcdif_kms.c
+2
-2
drivers/gpu/drm/mxsfb/lcdif_kms.c
···
433
433
struct drm_connector *connector;
434
434
struct drm_encoder *encoder;
435
435
struct drm_bridge_state *bridge_state;
436
-
struct drm_bridge *bridge;
437
436
u32 bus_format, bus_flags;
438
437
bool format_set = false, flags_set = false;
439
438
int ret, i;
···
452
453
453
454
encoder = connector_state->best_encoder;
454
455
455
-
bridge = drm_bridge_chain_get_first_bridge(encoder);
456
+
struct drm_bridge *bridge __free(drm_bridge_put) =
457
+
drm_bridge_chain_get_first_bridge(encoder);
456
458
if (!bridge)
457
459
continue;
458
460
-8
drivers/gpu/drm/nouveau/Kconfig
-8
drivers/gpu/drm/nouveau/Kconfig
···
102
102
Say Y here if you want to enable experimental support for
103
103
Shared Virtual Memory (SVM).
104
104
105
-
config DRM_NOUVEAU_GSP_DEFAULT
106
-
bool "Use GSP firmware for Turing/Ampere (needs firmware installed)"
107
-
depends on DRM_NOUVEAU
108
-
default n
109
-
help
110
-
Say Y here if you want to use the GSP codepaths by default on
111
-
Turing and Ampere GPUs.
112
-
113
105
config DRM_NOUVEAU_CH7006
114
106
tristate "Chrontel ch7006 TV encoder"
115
107
depends on DRM_NOUVEAU
-2
drivers/gpu/drm/nouveau/nouveau_chan.h
-2
drivers/gpu/drm/nouveau/nouveau_chan.h
-1
drivers/gpu/drm/nouveau/nouveau_dma.h
-1
drivers/gpu/drm/nouveau/nouveau_dma.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/core/enum.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/core/enum.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ad102.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ad102.c
···
41
41
42
42
static struct nvkm_gsp_fwif
43
43
ad102_gsps[] = {
44
-
{ 1, tu102_gsp_load, &ad102_gsp, &r570_rm_ga102, "570.144", true },
45
-
{ 0, tu102_gsp_load, &ad102_gsp, &r535_rm_ga102, "535.113.01", true },
44
+
{ 1, tu102_gsp_load, &ad102_gsp, &r570_rm_ga102, "570.144" },
45
+
{ 0, tu102_gsp_load, &ad102_gsp, &r535_rm_ga102, "535.113.01" },
46
46
{}
47
47
};
48
48
+3
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
+3
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
···
138
138
nvkm_subdev_ctor(&nvkm_gsp, device, type, inst, &gsp->subdev);
139
139
140
140
fwif = nvkm_firmware_load(&gsp->subdev, fwif, "Gsp", gsp);
141
-
if (IS_ERR(fwif))
141
+
if (IS_ERR(fwif)) {
142
+
nvkm_error(&gsp->subdev, "Failed to load required firmware for device.");
142
143
return PTR_ERR(fwif);
144
+
}
143
145
144
146
gsp->func = fwif->func;
145
147
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb202.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb202.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h
+3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
+3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
···
582
582
* RMSecBusResetEnable - enables PCI secondary bus reset
583
583
* RMForcePcieConfigSave - forces GSP-RM to preserve PCI configuration
584
584
* registers on any PCI reset.
585
+
* RMDevidCheckIgnore - allows GSP-RM to boot even if the PCI dev ID
586
+
* is not found in the internal product name database.
585
587
*/
586
588
static const struct nv_gsp_registry_entries r535_registry_entries[] = {
587
589
{ "RMSecBusResetEnable", 1 },
588
590
{ "RMForcePcieConfigSave", 1 },
591
+
{ "RMDevidCheckIgnore", 1 },
589
592
};
590
593
#define NV_GSP_REG_NUM_ENTRIES ARRAY_SIZE(r535_registry_entries)
591
594
+1
-5
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
+1
-5
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
···
383
383
tu102_gsp_load_rm(struct nvkm_gsp *gsp, const struct nvkm_gsp_fwif *fwif)
384
384
{
385
385
struct nvkm_subdev *subdev = &gsp->subdev;
386
-
bool enable_gsp = fwif->enable;
387
386
int ret;
388
387
389
-
#if IS_ENABLED(CONFIG_DRM_NOUVEAU_GSP_DEFAULT)
390
-
enable_gsp = true;
391
-
#endif
392
-
if (!nvkm_boolopt(subdev->device->cfgopt, "NvGspRm", enable_gsp))
388
+
if (!nvkm_boolopt(subdev->device->cfgopt, "NvGspRm", true))
393
389
return -EINVAL;
394
390
395
391
ret = nvkm_gsp_load_fw(gsp, "gsp", fwif->ver, &gsp->fws.rm);
+9
-14
drivers/gpu/drm/nova/file.rs
+9
-14
drivers/gpu/drm/nova/file.rs
···
2
2
3
3
use crate::driver::{NovaDevice, NovaDriver};
4
4
use crate::gem::NovaObject;
5
-
use crate::uapi::{GemCreate, GemInfo, Getparam};
6
5
use kernel::{
7
6
alloc::flags::*,
8
7
drm::{self, gem::BaseObject},
9
8
pci,
10
9
prelude::*,
11
-
types::Opaque,
12
10
uapi,
13
11
};
14
12
···
24
26
/// IOCTL: get_param: Query GPU / driver metadata.
25
27
pub(crate) fn get_param(
26
28
dev: &NovaDevice,
27
-
getparam: &Opaque<uapi::drm_nova_getparam>,
29
+
getparam: &mut uapi::drm_nova_getparam,
28
30
_file: &drm::File<File>,
29
31
) -> Result<u32> {
30
32
let adev = &dev.adev;
31
33
let parent = adev.parent().ok_or(ENOENT)?;
32
34
let pdev: &pci::Device = parent.try_into()?;
33
-
let getparam: &Getparam = getparam.into();
34
35
35
-
let value = match getparam.param() as u32 {
36
+
let value = match getparam.param as u32 {
36
37
uapi::NOVA_GETPARAM_VRAM_BAR_SIZE => pdev.resource_len(1)?,
37
38
_ => return Err(EINVAL),
38
39
};
39
40
40
-
getparam.set_value(value);
41
+
getparam.value = value;
41
42
42
43
Ok(0)
43
44
}
···
44
47
/// IOCTL: gem_create: Create a new DRM GEM object.
45
48
pub(crate) fn gem_create(
46
49
dev: &NovaDevice,
47
-
req: &Opaque<uapi::drm_nova_gem_create>,
50
+
req: &mut uapi::drm_nova_gem_create,
48
51
file: &drm::File<File>,
49
52
) -> Result<u32> {
50
-
let req: &GemCreate = req.into();
51
-
let obj = NovaObject::new(dev, req.size().try_into()?)?;
53
+
let obj = NovaObject::new(dev, req.size.try_into()?)?;
52
54
53
-
req.set_handle(obj.create_handle(file)?);
55
+
req.handle = obj.create_handle(file)?;
54
56
55
57
Ok(0)
56
58
}
···
57
61
/// IOCTL: gem_info: Query GEM metadata.
58
62
pub(crate) fn gem_info(
59
63
_dev: &NovaDevice,
60
-
req: &Opaque<uapi::drm_nova_gem_info>,
64
+
req: &mut uapi::drm_nova_gem_info,
61
65
file: &drm::File<File>,
62
66
) -> Result<u32> {
63
-
let req: &GemInfo = req.into();
64
-
let bo = NovaObject::lookup_handle(file, req.handle())?;
67
+
let bo = NovaObject::lookup_handle(file, req.handle)?;
65
68
66
-
req.set_size(bo.size().try_into()?);
69
+
req.size = bo.size().try_into()?;
67
70
68
71
Ok(0)
69
72
}
-1
drivers/gpu/drm/nova/nova.rs
-1
drivers/gpu/drm/nova/nova.rs
-61
drivers/gpu/drm/nova/uapi.rs
-61
drivers/gpu/drm/nova/uapi.rs
···
1
-
// SPDX-License-Identifier: GPL-2.0
2
-
3
-
use kernel::uapi;
4
-
5
-
// TODO Work out some common infrastructure to avoid boilerplate code for uAPI abstractions.
6
-
7
-
macro_rules! define_uapi_abstraction {
8
-
($name:ident <= $inner:ty) => {
9
-
#[repr(transparent)]
10
-
pub struct $name(::kernel::types::Opaque<$inner>);
11
-
12
-
impl ::core::convert::From<&::kernel::types::Opaque<$inner>> for &$name {
13
-
fn from(value: &::kernel::types::Opaque<$inner>) -> Self {
14
-
// SAFETY: `Self` is a transparent wrapper of `$inner`.
15
-
unsafe { ::core::mem::transmute(value) }
16
-
}
17
-
}
18
-
};
19
-
}
20
-
21
-
define_uapi_abstraction!(Getparam <= uapi::drm_nova_getparam);
22
-
23
-
impl Getparam {
24
-
pub fn param(&self) -> u64 {
25
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_getparam`.
26
-
unsafe { (*self.0.get()).param }
27
-
}
28
-
29
-
pub fn set_value(&self, v: u64) {
30
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_getparam`.
31
-
unsafe { (*self.0.get()).value = v };
32
-
}
33
-
}
34
-
35
-
define_uapi_abstraction!(GemCreate <= uapi::drm_nova_gem_create);
36
-
37
-
impl GemCreate {
38
-
pub fn size(&self) -> u64 {
39
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_gem_create`.
40
-
unsafe { (*self.0.get()).size }
41
-
}
42
-
43
-
pub fn set_handle(&self, handle: u32) {
44
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_gem_create`.
45
-
unsafe { (*self.0.get()).handle = handle };
46
-
}
47
-
}
48
-
49
-
define_uapi_abstraction!(GemInfo <= uapi::drm_nova_gem_info);
50
-
51
-
impl GemInfo {
52
-
pub fn handle(&self) -> u32 {
53
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_gem_info`.
54
-
unsafe { (*self.0.get()).handle }
55
-
}
56
-
57
-
pub fn set_size(&self, size: u64) {
58
-
// SAFETY: `self.get()` is a valid pointer to a `struct drm_nova_gem_info`.
59
-
unsafe { (*self.0.get()).size = size };
60
-
}
61
-
}
+25
-1
drivers/gpu/drm/panel/Kconfig
+25
-1
drivers/gpu/drm/panel/Kconfig
···
215
215
216
216
If M is selected the module will be called panel-himax-hx8394.
217
217
218
+
config DRM_PANEL_HYDIS_HV101HD1
219
+
tristate "Hydis HV101HD1 panel"
220
+
depends on OF
221
+
depends on DRM_MIPI_DSI
222
+
depends on BACKLIGHT_CLASS_DEVICE
223
+
help
224
+
Say Y here if you want to enable support for the Hydis HV101HD1
225
+
2-lane 1366x768 MIPI DSI panel found in ASUS VivoTab RT TF600T.
226
+
HV101HD1 is a color active matrix TFT LCD module using amorphous
227
+
silicon TFT's (Thin Film Transistors) as an active switching devices.
228
+
229
+
If M is selected the module will be called panel-hydis-hv101hd1
230
+
218
231
config DRM_PANEL_ILITEK_IL9322
219
232
tristate "Ilitek ILI9322 320x240 QVGA panels"
220
233
depends on OF && SPI
···
856
843
select DRM_MIPI_DSI
857
844
select VIDEOMODE_HELPERS
858
845
846
+
config DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01
847
+
tristate "Samsung AMS561RA01 panel with S6E8AA5X01 controller"
848
+
depends on GPIOLIB && OF && REGULATOR
849
+
depends on DRM_MIPI_DSI
850
+
depends on BACKLIGHT_CLASS_DEVICE
851
+
help
852
+
Say Y here if you want to enable support for Samsung AMS561RA01
853
+
panel, which uses Samsung's S6E8AA5X01 controller. The panel has a
854
+
~5.6 inch AMOLED display, and the controller is driven by the MIPI
855
+
DSI protocol with 4 lanes.
856
+
859
857
config DRM_PANEL_SAMSUNG_SOFEF00
860
858
tristate "Samsung sofef00/s6e3fc2x01 OnePlus 6/6T DSI cmd mode panels"
861
859
depends on OF
···
995
971
depends on BACKLIGHT_CLASS_DEVICE
996
972
help
997
973
Say Y here if you want to enable support for STARTEK KD070FHFID015 DSI panel
998
-
based on RENESAS-R69429 controller. The pannel is a 7-inch TFT LCD display
974
+
based on RENESAS-R69429 controller. The panel is a 7-inch TFT LCD display
999
975
with a resolution of 1024 x 600 pixels. It provides a MIPI DSI interface to
1000
976
the host, a built-in LED backlight and touch controller.
1001
977
+2
drivers/gpu/drm/panel/Makefile
+2
drivers/gpu/drm/panel/Makefile
···
22
22
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o
23
23
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112B) += panel-himax-hx83112b.o
24
24
obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o
25
+
obj-$(CONFIG_DRM_PANEL_HYDIS_HV101HD1) += panel-hydis-hv101hd1.o
25
26
obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
26
27
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o
27
28
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9805) += panel-ilitek-ili9805.o
···
88
87
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24) += panel-samsung-s6e88a0-ams427ap24.o
89
88
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01) += panel-samsung-s6e88a0-ams452ef01.o
90
89
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
90
+
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01) += panel-samsung-s6e8aa5x01-ams561ra01.o
91
91
obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF00) += panel-samsung-sofef00.o
92
92
obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
93
93
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
+38
-6
drivers/gpu/drm/panel/panel-edp.c
+38
-6
drivers/gpu/drm/panel/panel-edp.c
···
1736
1736
.enable = 50,
1737
1737
};
1738
1738
1739
-
static const struct panel_delay delay_200_500_e50_p2e200 = {
1739
+
static const struct panel_delay delay_200_500_e50_d50_p2e200 = {
1740
1740
.hpd_absent = 200,
1741
1741
.unprepare = 500,
1742
1742
.enable = 50,
1743
+
.disable = 50,
1743
1744
.prepare_to_enable = 200,
1744
1745
};
1745
1746
···
1796
1795
.disable = 10,
1797
1796
};
1798
1797
1798
+
static const struct panel_delay delay_200_500_e200_d50 = {
1799
+
.hpd_absent = 200,
1800
+
.unprepare = 500,
1801
+
.enable = 200,
1802
+
.disable = 50,
1803
+
};
1804
+
1799
1805
static const struct panel_delay delay_200_150_e200 = {
1800
1806
.hpd_absent = 200,
1801
1807
.unprepare = 150,
···
1836
1828
.powered_on_to_enable = 335,
1837
1829
};
1838
1830
1831
+
static const struct panel_delay delay_200_500_e50_d100 = {
1832
+
.hpd_absent = 200,
1833
+
.unprepare = 500,
1834
+
.enable = 50,
1835
+
.disable = 100,
1836
+
};
1837
+
1839
1838
#define EDP_PANEL_ENTRY(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _delay, _name) \
1840
1839
{ \
1841
1840
.ident = { \
···
1872
1857
* Sort first by vendor, then by product ID.
1873
1858
*/
1874
1859
static const struct edp_panel_entry edp_panels[] = {
1860
+
EDP_PANEL_ENTRY('A', 'U', 'O', 0x04a4, &delay_200_500_e50, "B122UAN01.0"),
1875
1861
EDP_PANEL_ENTRY('A', 'U', 'O', 0x105c, &delay_200_500_e50, "B116XTN01.0"),
1876
1862
EDP_PANEL_ENTRY('A', 'U', 'O', 0x1062, &delay_200_500_e50, "B120XAN01.0"),
1877
1863
EDP_PANEL_ENTRY('A', 'U', 'O', 0x125c, &delay_200_500_e50, "Unknown"),
···
1891
1875
EDP_PANEL_ENTRY2('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01.0",
1892
1876
&auo_b116xa3_mode),
1893
1877
EDP_PANEL_ENTRY('A', 'U', 'O', 0x435c, &delay_200_500_e50, "Unknown"),
1878
+
EDP_PANEL_ENTRY('A', 'U', 'O', 0x52b0, &delay_200_500_e50, "B116XAK02.0"),
1894
1879
EDP_PANEL_ENTRY('A', 'U', 'O', 0x582d, &delay_200_500_e50, "B133UAN01.0"),
1895
1880
EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"),
1896
1881
EDP_PANEL_ENTRY('A', 'U', 'O', 0x635c, &delay_200_500_e50, "B116XAN06.3"),
···
1899
1882
EDP_PANEL_ENTRY('A', 'U', 'O', 0x723c, &delay_200_500_e50, "B140XTN07.2"),
1900
1883
EDP_PANEL_ENTRY('A', 'U', 'O', 0x73aa, &delay_200_500_e50, "B116XTN02.3"),
1901
1884
EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"),
1885
+
EDP_PANEL_ENTRY('A', 'U', 'O', 0x8bba, &delay_200_500_e50, "B140UAN08.5"),
1902
1886
EDP_PANEL_ENTRY('A', 'U', 'O', 0xa199, &delay_200_500_e50, "B116XAN06.1"),
1903
1887
EDP_PANEL_ENTRY('A', 'U', 'O', 0xa7b3, &delay_200_500_e50, "B140UAN04.4"),
1904
1888
EDP_PANEL_ENTRY('A', 'U', 'O', 0xc4b4, &delay_200_500_e50, "B116XAT04.1"),
1905
1889
EDP_PANEL_ENTRY('A', 'U', 'O', 0xc9a8, &delay_200_500_e50, "B140QAN08.H"),
1890
+
EDP_PANEL_ENTRY('A', 'U', 'O', 0xcdba, &delay_200_500_e50, "B140UAX01.2"),
1906
1891
EDP_PANEL_ENTRY('A', 'U', 'O', 0xd497, &delay_200_500_e50, "B120XAN01.0"),
1907
1892
EDP_PANEL_ENTRY('A', 'U', 'O', 0xf390, &delay_200_500_e50, "B140XTN07.7"),
1908
1893
···
1953
1934
EDP_PANEL_ENTRY('B', 'O', 'E', 0x09dd, &delay_200_500_e50, "NT116WHM-N21"),
1954
1935
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a1b, &delay_200_500_e50, "NV133WUM-N63"),
1955
1936
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a36, &delay_200_500_e200, "Unknown"),
1956
-
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a3e, &delay_200_500_e80, "NV116WHM-N49"),
1937
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a3e, &delay_200_500_e80_d50, "NV116WHM-N49"),
1957
1938
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a5d, &delay_200_500_e50, "NV116WHM-N45"),
1958
1939
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ac5, &delay_200_500_e50, "NV116WHM-N4C"),
1959
1940
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ae8, &delay_200_500_e50_p2e80, "NV140WUM-N41"),
1960
1941
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b09, &delay_200_500_e50_po2e200, "NV140FHM-NZ"),
1961
1942
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b1e, &delay_200_500_e80, "NE140QDM-N6A"),
1962
-
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b34, &delay_200_500_e80, "NV122WUM-N41"),
1943
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b34, &delay_200_500_e80_d50, "NV122WUM-N41"),
1963
1944
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b43, &delay_200_500_e200, "NV140FHM-T09"),
1964
1945
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b56, &delay_200_500_e80, "NT140FHM-N47"),
1965
1946
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b66, &delay_200_500_e80, "NE140WUM-N6G"),
1966
1947
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c20, &delay_200_500_e80, "NT140FHM-N47"),
1967
1948
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c93, &delay_200_500_e200, "Unknown"),
1968
1949
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cb6, &delay_200_500_e200, "NT116WHM-N44"),
1950
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf6, &delay_200_500_e200, "NV140WUM-N64"),
1969
1951
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cfa, &delay_200_500_e50, "NV116WHM-A4D"),
1952
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0d45, &delay_200_500_e80, "NV116WHM-N4B"),
1970
1953
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0d73, &delay_200_500_e80, "NE140WUM-N6S"),
1954
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ddf, &delay_200_500_e80, "NV116WHM-T01"),
1971
1955
1972
1956
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1130, &delay_200_500_e50, "N116BGE-EB2"),
1973
1957
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1132, &delay_200_500_e80_d50, "N116BGE-EA2"),
···
1988
1966
EDP_PANEL_ENTRY('C', 'M', 'N', 0x115b, &delay_200_500_e80_d50, "N116BCN-EB1"),
1989
1967
EDP_PANEL_ENTRY('C', 'M', 'N', 0x115d, &delay_200_500_e80_d50, "N116BCA-EA2"),
1990
1968
EDP_PANEL_ENTRY('C', 'M', 'N', 0x115e, &delay_200_500_e80_d50, "N116BCA-EA1"),
1969
+
EDP_PANEL_ENTRY('C', 'M', 'N', 0x115f, &delay_200_500_e80_d50, "N116BCL-EAK"),
1991
1970
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1160, &delay_200_500_e80_d50, "N116BCJ-EAK"),
1992
1971
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1161, &delay_200_500_e80, "N116BCP-EA2"),
1993
1972
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1163, &delay_200_500_e80_d50, "N116BCJ-EAK"),
1994
1973
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1247, &delay_200_500_e80_d50, "N120ACA-EA1"),
1974
+
EDP_PANEL_ENTRY('C', 'M', 'N', 0x124c, &delay_200_500_e80_d50, "N122JCA-ENK"),
1995
1975
EDP_PANEL_ENTRY('C', 'M', 'N', 0x142b, &delay_200_500_e80_d50, "N140HCA-EAC"),
1996
1976
EDP_PANEL_ENTRY('C', 'M', 'N', 0x142e, &delay_200_500_e80_d50, "N140BGA-EA4"),
1997
1977
EDP_PANEL_ENTRY('C', 'M', 'N', 0x144f, &delay_200_500_e80_d50, "N140HGA-EA1"),
1998
1978
EDP_PANEL_ENTRY('C', 'M', 'N', 0x1468, &delay_200_500_e80, "N140HGA-EA1"),
1979
+
EDP_PANEL_ENTRY('C', 'M', 'N', 0x14a8, &delay_200_500_e80, "N140JCA-ELP"),
1999
1980
EDP_PANEL_ENTRY('C', 'M', 'N', 0x14d4, &delay_200_500_e80_d50, "N140HCA-EAC"),
2000
1981
EDP_PANEL_ENTRY('C', 'M', 'N', 0x14d6, &delay_200_500_e80_d50, "N140BGA-EA4"),
2001
1982
EDP_PANEL_ENTRY('C', 'M', 'N', 0x14e5, &delay_200_500_e80_d50, "N140HGA-EA1"),
2002
1983
EDP_PANEL_ENTRY('C', 'M', 'N', 0x162b, &delay_200_500_e80_d50, "N160JCE-ELL"),
1984
+
EDP_PANEL_ENTRY('C', 'M', 'N', 0x7402, &delay_200_500_e200_d50, "N116BCA-EAK"),
2003
1985
2004
-
EDP_PANEL_ENTRY('C', 'S', 'O', 0x1200, &delay_200_500_e50_p2e200, "MNC207QS1-1"),
2005
-
EDP_PANEL_ENTRY('C', 'S', 'O', 0x1413, &delay_200_500_e50_p2e200, "MNE007JA1-2"),
1986
+
EDP_PANEL_ENTRY('C', 'S', 'O', 0x1200, &delay_200_500_e50_d50_p2e200, "MNC207QS1-1"),
1987
+
EDP_PANEL_ENTRY('C', 'S', 'O', 0x1413, &delay_200_500_e50_d50_p2e200, "MNE007JA1-2"),
2006
1988
2007
1989
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1100, &delay_200_500_e80_d50, "MNB601LS1-1"),
2008
1990
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1103, &delay_200_500_e80_d50, "MNB601LS1-3"),
2009
-
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1104, &delay_200_500_e50, "MNB601LS1-4"),
1991
+
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1104, &delay_200_500_e50_d100, "MNB601LS1-4"),
2010
1992
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1448, &delay_200_500_e50, "MNE007QS3-7"),
2011
1993
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1457, &delay_80_500_e80_p2e200, "MNE007QS3-8"),
1994
+
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1462, &delay_200_500_e50, "MNE007QS5-2"),
1995
+
EDP_PANEL_ENTRY('C', 'S', 'W', 0x1468, &delay_200_500_e50, "MNE007QB2-2"),
2012
1996
2013
1997
EDP_PANEL_ENTRY('E', 'T', 'C', 0x0000, &delay_50_500_e200_d200_po2e335, "LP079QX1-SP0V"),
2014
1998
···
2055
2027
EDP_PANEL_ENTRY('S', 'H', 'P', 0x1523, &delay_80_500_e50, "LQ140M1JW46"),
2056
2028
EDP_PANEL_ENTRY('S', 'H', 'P', 0x153a, &delay_200_500_e50, "LQ140T1JH01"),
2057
2029
EDP_PANEL_ENTRY('S', 'H', 'P', 0x154c, &delay_200_500_p2e100, "LQ116M1JW10"),
2030
+
EDP_PANEL_ENTRY('S', 'H', 'P', 0x158f, &delay_200_500_p2e100, "LQ134Z1"),
2058
2031
EDP_PANEL_ENTRY('S', 'H', 'P', 0x1593, &delay_200_500_p2e100, "LQ134N1"),
2059
2032
2060
2033
EDP_PANEL_ENTRY('S', 'T', 'A', 0x0004, &delay_200_500_e200, "116KHD024006"),
2061
2034
EDP_PANEL_ENTRY('S', 'T', 'A', 0x0009, &delay_200_500_e250, "116QHD024002"),
2062
2035
EDP_PANEL_ENTRY('S', 'T', 'A', 0x0100, &delay_100_500_e200, "2081116HHD028001-51D"),
2036
+
2037
+
EDP_PANEL_ENTRY('T', 'M', 'A', 0x0811, &delay_200_500_e80_d50, "TM140VDXP01-04"),
2038
+
EDP_PANEL_ENTRY('T', 'M', 'A', 0x2094, &delay_200_500_e50_d100, "TL140VDMS03-01"),
2063
2039
2064
2040
{ /* sentinal */ }
2065
2041
};
+1
-1
drivers/gpu/drm/panel/panel-himax-hx8279.c
+1
-1
drivers/gpu/drm/panel/panel-himax-hx8279.c
+188
drivers/gpu/drm/panel/panel-hydis-hv101hd1.c
+188
drivers/gpu/drm/panel/panel-hydis-hv101hd1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
#include <linux/array_size.h>
4
+
#include <linux/delay.h>
5
+
#include <linux/err.h>
6
+
#include <linux/gpio/consumer.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/property.h>
10
+
#include <linux/regulator/consumer.h>
11
+
12
+
#include <video/mipi_display.h>
13
+
14
+
#include <drm/drm_mipi_dsi.h>
15
+
#include <drm/drm_modes.h>
16
+
#include <drm/drm_panel.h>
17
+
18
+
struct hv101hd1 {
19
+
struct drm_panel panel;
20
+
struct mipi_dsi_device *dsi;
21
+
struct regulator_bulk_data *supplies;
22
+
};
23
+
24
+
static const struct regulator_bulk_data hv101hd1_supplies[] = {
25
+
{ .supply = "vdd" },
26
+
{ .supply = "vio" },
27
+
};
28
+
29
+
static inline struct hv101hd1 *to_hv101hd1(struct drm_panel *panel)
30
+
{
31
+
return container_of(panel, struct hv101hd1, panel);
32
+
}
33
+
34
+
static int hv101hd1_prepare(struct drm_panel *panel)
35
+
{
36
+
struct hv101hd1 *hv = to_hv101hd1(panel);
37
+
struct mipi_dsi_multi_context ctx = { .dsi = hv->dsi };
38
+
struct device *dev = &hv->dsi->dev;
39
+
int ret;
40
+
41
+
ret = regulator_bulk_enable(ARRAY_SIZE(hv101hd1_supplies), hv->supplies);
42
+
if (ret) {
43
+
dev_err(dev, "error enabling regulators (%d)\n", ret);
44
+
return ret;
45
+
}
46
+
47
+
mipi_dsi_dcs_exit_sleep_mode_multi(&ctx);
48
+
mipi_dsi_msleep(&ctx, 20);
49
+
50
+
mipi_dsi_dcs_set_display_on_multi(&ctx);
51
+
mipi_dsi_msleep(&ctx, 20);
52
+
53
+
return 0;
54
+
}
55
+
56
+
static int hv101hd1_disable(struct drm_panel *panel)
57
+
{
58
+
struct hv101hd1 *hv = to_hv101hd1(panel);
59
+
struct mipi_dsi_multi_context ctx = { .dsi = hv->dsi };
60
+
61
+
mipi_dsi_dcs_set_display_off_multi(&ctx);
62
+
mipi_dsi_msleep(&ctx, 120);
63
+
mipi_dsi_dcs_enter_sleep_mode_multi(&ctx);
64
+
mipi_dsi_msleep(&ctx, 20);
65
+
66
+
return 0;
67
+
}
68
+
69
+
static int hv101hd1_unprepare(struct drm_panel *panel)
70
+
{
71
+
struct hv101hd1 *hv = to_hv101hd1(panel);
72
+
73
+
return regulator_bulk_disable(ARRAY_SIZE(hv101hd1_supplies),
74
+
hv->supplies);
75
+
}
76
+
77
+
static const struct drm_display_mode hv101hd1_mode = {
78
+
.clock = (1366 + 74 + 36 + 24) * (768 + 21 + 7 + 4) * 60 / 1000,
79
+
.hdisplay = 1366,
80
+
.hsync_start = 1366 + 74,
81
+
.hsync_end = 1366 + 74 + 36,
82
+
.htotal = 1366 + 74 + 36 + 24,
83
+
.vdisplay = 768,
84
+
.vsync_start = 768 + 21,
85
+
.vsync_end = 768 + 21 + 7,
86
+
.vtotal = 768 + 21 + 7 + 4,
87
+
.width_mm = 140,
88
+
.height_mm = 220,
89
+
};
90
+
91
+
static int hv101hd1_get_modes(struct drm_panel *panel, struct drm_connector *connector)
92
+
{
93
+
struct drm_display_mode *mode;
94
+
95
+
mode = drm_mode_duplicate(connector->dev, &hv101hd1_mode);
96
+
if (!mode)
97
+
return -ENOMEM;
98
+
99
+
drm_mode_set_name(mode);
100
+
101
+
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
102
+
103
+
connector->display_info.width_mm = mode->width_mm;
104
+
connector->display_info.height_mm = mode->height_mm;
105
+
106
+
drm_mode_probed_add(connector, mode);
107
+
108
+
return 1;
109
+
}
110
+
111
+
static const struct drm_panel_funcs hv101hd1_panel_funcs = {
112
+
.prepare = hv101hd1_prepare,
113
+
.disable = hv101hd1_disable,
114
+
.unprepare = hv101hd1_unprepare,
115
+
.get_modes = hv101hd1_get_modes,
116
+
};
117
+
118
+
static int hv101hd1_probe(struct mipi_dsi_device *dsi)
119
+
{
120
+
struct device *dev = &dsi->dev;
121
+
struct hv101hd1 *hv;
122
+
int ret;
123
+
124
+
hv = devm_drm_panel_alloc(dev, struct hv101hd1, panel,
125
+
&hv101hd1_panel_funcs,
126
+
DRM_MODE_CONNECTOR_DSI);
127
+
if (IS_ERR(hv))
128
+
return PTR_ERR(hv);
129
+
130
+
ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(hv101hd1_supplies),
131
+
hv101hd1_supplies, &hv->supplies);
132
+
if (ret)
133
+
return dev_err_probe(dev, ret, "failed to get regulators\n");
134
+
135
+
hv->dsi = dsi;
136
+
mipi_dsi_set_drvdata(dsi, hv);
137
+
138
+
dsi->lanes = 2;
139
+
dsi->format = MIPI_DSI_FMT_RGB888;
140
+
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
141
+
142
+
ret = drm_panel_of_backlight(&hv->panel);
143
+
if (ret)
144
+
return dev_err_probe(dev, ret, "Failed to get backlight\n");
145
+
146
+
drm_panel_add(&hv->panel);
147
+
148
+
ret = mipi_dsi_attach(dsi);
149
+
if (ret) {
150
+
drm_panel_remove(&hv->panel);
151
+
return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
152
+
}
153
+
154
+
return 0;
155
+
}
156
+
157
+
static void hv101hd1_remove(struct mipi_dsi_device *dsi)
158
+
{
159
+
struct hv101hd1 *hv = mipi_dsi_get_drvdata(dsi);
160
+
int ret;
161
+
162
+
ret = mipi_dsi_detach(dsi);
163
+
if (ret < 0)
164
+
dev_err(&dsi->dev,
165
+
"Failed to detach from DSI host: %d\n", ret);
166
+
167
+
drm_panel_remove(&hv->panel);
168
+
}
169
+
170
+
static const struct of_device_id hv101hd1_of_match[] = {
171
+
{ .compatible = "hydis,hv101hd1" },
172
+
{ /* sentinel */ }
173
+
};
174
+
MODULE_DEVICE_TABLE(of, hv101hd1_of_match);
175
+
176
+
static struct mipi_dsi_driver hv101hd1_driver = {
177
+
.driver = {
178
+
.name = "panel-hv101hd1",
179
+
.of_match_table = hv101hd1_of_match,
180
+
},
181
+
.probe = hv101hd1_probe,
182
+
.remove = hv101hd1_remove,
183
+
};
184
+
module_mipi_dsi_driver(hv101hd1_driver);
185
+
186
+
MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
187
+
MODULE_DESCRIPTION("DRM driver for Hydis HV101HD1 panel");
188
+
MODULE_LICENSE("GPL");
+59
-137
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
+59
-137
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
···
81
81
static int jdi_panel_unprepare(struct drm_panel *panel)
82
82
{
83
83
struct jdi_panel *jdi = to_panel_jdi(panel);
84
-
int ret;
85
84
86
-
ret = mipi_dsi_dcs_set_display_off(jdi->link1);
87
-
if (ret < 0)
88
-
dev_err(panel->dev, "failed to set display off: %d\n", ret);
85
+
/*
86
+
* One context per panel since we'll continue trying to shut down the
87
+
* other panel even if one isn't responding.
88
+
*/
89
+
struct mipi_dsi_multi_context dsi_ctx1 = { .dsi = jdi->link1 };
90
+
struct mipi_dsi_multi_context dsi_ctx2 = { .dsi = jdi->link2 };
89
91
90
-
ret = mipi_dsi_dcs_set_display_off(jdi->link2);
91
-
if (ret < 0)
92
-
dev_err(panel->dev, "failed to set display off: %d\n", ret);
92
+
mipi_dsi_dcs_set_display_off_multi(&dsi_ctx1);
93
+
mipi_dsi_dcs_set_display_off_multi(&dsi_ctx2);
93
94
94
95
/* Specified by JDI @ 50ms, subject to change */
95
96
msleep(50);
96
97
97
-
ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link1);
98
-
if (ret < 0)
99
-
dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
100
-
ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link2);
101
-
if (ret < 0)
102
-
dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
98
+
/* Doesn't hurt to try sleep mode even if display off fails */
99
+
dsi_ctx1.accum_err = 0;
100
+
dsi_ctx2.accum_err = 0;
101
+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx1);
102
+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx2);
103
103
104
104
/* Specified by JDI @ 150ms, subject to change */
105
105
msleep(150);
···
123
123
/* Specified by JDI @ 20ms, subject to change */
124
124
msleep(20);
125
125
126
-
return ret;
127
-
}
128
-
129
-
static int jdi_setup_symmetrical_split(struct mipi_dsi_device *left,
130
-
struct mipi_dsi_device *right,
131
-
const struct drm_display_mode *mode)
132
-
{
133
-
int err;
134
-
135
-
err = mipi_dsi_dcs_set_column_address(left, 0, mode->hdisplay / 2 - 1);
136
-
if (err < 0) {
137
-
dev_err(&left->dev, "failed to set column address: %d\n", err);
138
-
return err;
139
-
}
140
-
141
-
err = mipi_dsi_dcs_set_column_address(right, 0, mode->hdisplay / 2 - 1);
142
-
if (err < 0) {
143
-
dev_err(&right->dev, "failed to set column address: %d\n", err);
144
-
return err;
145
-
}
146
-
147
-
err = mipi_dsi_dcs_set_page_address(left, 0, mode->vdisplay - 1);
148
-
if (err < 0) {
149
-
dev_err(&left->dev, "failed to set page address: %d\n", err);
150
-
return err;
151
-
}
152
-
153
-
err = mipi_dsi_dcs_set_page_address(right, 0, mode->vdisplay - 1);
154
-
if (err < 0) {
155
-
dev_err(&right->dev, "failed to set page address: %d\n", err);
156
-
return err;
157
-
}
158
-
159
126
return 0;
160
127
}
161
128
162
-
static int jdi_write_dcdc_registers(struct jdi_panel *jdi)
129
+
static void jdi_setup_symmetrical_split(struct mipi_dsi_multi_context *dsi_ctx,
130
+
struct mipi_dsi_device *left,
131
+
struct mipi_dsi_device *right,
132
+
const struct drm_display_mode *mode)
133
+
{
134
+
mipi_dsi_dual(mipi_dsi_dcs_set_column_address_multi,
135
+
dsi_ctx, left, right,
136
+
0, mode->hdisplay / 2 - 1);
137
+
mipi_dsi_dual(mipi_dsi_dcs_set_page_address_multi,
138
+
dsi_ctx, left, right,
139
+
0, mode->vdisplay - 1);
140
+
}
141
+
142
+
static void jdi_write_dcdc_registers(struct mipi_dsi_multi_context *dsi_ctx,
143
+
struct jdi_panel *jdi)
163
144
{
164
145
/* Clear the manufacturer command access protection */
165
-
mipi_dsi_generic_write_seq(jdi->link1, MCS_CMD_ACS_PROT,
166
-
MCS_CMD_ACS_PROT_OFF);
167
-
mipi_dsi_generic_write_seq(jdi->link2, MCS_CMD_ACS_PROT,
168
-
MCS_CMD_ACS_PROT_OFF);
146
+
mipi_dsi_dual_generic_write_seq_multi(dsi_ctx, jdi->link1, jdi->link2,
147
+
MCS_CMD_ACS_PROT,
148
+
MCS_CMD_ACS_PROT_OFF);
169
149
/*
170
-
* Change the VGH/VGL divide rations to move the noise generated by the
150
+
* Change the VGH/VGL divide ratios to move the noise generated by the
171
151
* TCONN. This should hopefully avoid interaction with the backlight
172
152
* controller.
173
153
*/
174
-
mipi_dsi_generic_write_seq(jdi->link1, MCS_PWR_CTRL_FUNC,
175
-
MCS_PWR_CTRL_PARAM1_VGH_330_DIV |
176
-
MCS_PWR_CTRL_PARAM1_DEFAULT,
177
-
MCS_PWR_CTRL_PARAM2_VGL_410_DIV |
178
-
MCS_PWR_CTRL_PARAM2_DEFAULT);
179
-
180
-
mipi_dsi_generic_write_seq(jdi->link2, MCS_PWR_CTRL_FUNC,
181
-
MCS_PWR_CTRL_PARAM1_VGH_330_DIV |
182
-
MCS_PWR_CTRL_PARAM1_DEFAULT,
183
-
MCS_PWR_CTRL_PARAM2_VGL_410_DIV |
184
-
MCS_PWR_CTRL_PARAM2_DEFAULT);
185
-
186
-
return 0;
154
+
mipi_dsi_dual_generic_write_seq_multi(dsi_ctx, jdi->link1, jdi->link2,
155
+
MCS_PWR_CTRL_FUNC,
156
+
MCS_PWR_CTRL_PARAM1_VGH_330_DIV |
157
+
MCS_PWR_CTRL_PARAM1_DEFAULT,
158
+
MCS_PWR_CTRL_PARAM2_VGL_410_DIV |
159
+
MCS_PWR_CTRL_PARAM2_DEFAULT);
187
160
}
188
161
189
162
static int jdi_panel_prepare(struct drm_panel *panel)
190
163
{
191
164
struct jdi_panel *jdi = to_panel_jdi(panel);
165
+
struct mipi_dsi_multi_context dsi_ctx = {};
192
166
int err;
193
167
194
168
/* Disable backlight to avoid showing random pixels
···
205
231
* put in place to communicate the configuration back to the DSI host
206
232
* controller.
207
233
*/
208
-
err = jdi_setup_symmetrical_split(jdi->link1, jdi->link2,
209
-
jdi->mode);
210
-
if (err < 0) {
211
-
dev_err(panel->dev, "failed to set up symmetrical split: %d\n",
212
-
err);
213
-
goto poweroff;
214
-
}
234
+
jdi_setup_symmetrical_split(&dsi_ctx, jdi->link1, jdi->link2,
235
+
jdi->mode);
215
236
216
-
err = mipi_dsi_dcs_set_tear_scanline(jdi->link1,
217
-
jdi->mode->vdisplay - 16);
218
-
if (err < 0) {
219
-
dev_err(panel->dev, "failed to set tear scanline: %d\n", err);
220
-
goto poweroff;
221
-
}
237
+
mipi_dsi_dual(mipi_dsi_dcs_set_tear_scanline_multi,
238
+
&dsi_ctx, jdi->link1, jdi->link2,
239
+
jdi->mode->vdisplay - 16);
222
240
223
-
err = mipi_dsi_dcs_set_tear_scanline(jdi->link2,
224
-
jdi->mode->vdisplay - 16);
225
-
if (err < 0) {
226
-
dev_err(panel->dev, "failed to set tear scanline: %d\n", err);
227
-
goto poweroff;
228
-
}
241
+
mipi_dsi_dual(mipi_dsi_dcs_set_tear_on_multi,
242
+
&dsi_ctx, jdi->link1, jdi->link2,
243
+
MIPI_DSI_DCS_TEAR_MODE_VBLANK);
229
244
230
-
err = mipi_dsi_dcs_set_tear_on(jdi->link1,
231
-
MIPI_DSI_DCS_TEAR_MODE_VBLANK);
232
-
if (err < 0) {
233
-
dev_err(panel->dev, "failed to set tear on: %d\n", err);
234
-
goto poweroff;
235
-
}
245
+
mipi_dsi_dual(mipi_dsi_dcs_set_pixel_format_multi,
246
+
&dsi_ctx, jdi->link1, jdi->link2,
247
+
MIPI_DCS_PIXEL_FMT_24BIT);
236
248
237
-
err = mipi_dsi_dcs_set_tear_on(jdi->link2,
238
-
MIPI_DSI_DCS_TEAR_MODE_VBLANK);
239
-
if (err < 0) {
240
-
dev_err(panel->dev, "failed to set tear on: %d\n", err);
241
-
goto poweroff;
242
-
}
249
+
mipi_dsi_dual(mipi_dsi_dcs_exit_sleep_mode_multi,
250
+
&dsi_ctx, jdi->link1, jdi->link2);
243
251
244
-
err = mipi_dsi_dcs_set_pixel_format(jdi->link1, MIPI_DCS_PIXEL_FMT_24BIT);
245
-
if (err < 0) {
246
-
dev_err(panel->dev, "failed to set pixel format: %d\n", err);
247
-
goto poweroff;
248
-
}
249
-
250
-
err = mipi_dsi_dcs_set_pixel_format(jdi->link2, MIPI_DCS_PIXEL_FMT_24BIT);
251
-
if (err < 0) {
252
-
dev_err(panel->dev, "failed to set pixel format: %d\n", err);
253
-
goto poweroff;
254
-
}
255
-
256
-
err = mipi_dsi_dcs_exit_sleep_mode(jdi->link1);
257
-
if (err < 0) {
258
-
dev_err(panel->dev, "failed to exit sleep mode: %d\n", err);
259
-
goto poweroff;
260
-
}
261
-
262
-
err = mipi_dsi_dcs_exit_sleep_mode(jdi->link2);
263
-
if (err < 0) {
264
-
dev_err(panel->dev, "failed to exit sleep mode: %d\n", err);
265
-
goto poweroff;
266
-
}
267
-
268
-
err = jdi_write_dcdc_registers(jdi);
269
-
if (err < 0) {
270
-
dev_err(panel->dev, "failed to write dcdc registers: %d\n", err);
271
-
goto poweroff;
272
-
}
252
+
jdi_write_dcdc_registers(&dsi_ctx, jdi);
273
253
/*
274
-
* We need to wait 150ms between mipi_dsi_dcs_exit_sleep_mode() and
275
-
* mipi_dsi_dcs_set_display_on().
254
+
* We need to wait 150ms between mipi_dsi_dcs_exit_sleep_mode_multi()
255
+
* and mipi_dsi_dcs_set_display_on_multi().
276
256
*/
277
-
msleep(150);
257
+
mipi_dsi_msleep(&dsi_ctx, 150);
278
258
279
-
err = mipi_dsi_dcs_set_display_on(jdi->link1);
280
-
if (err < 0) {
281
-
dev_err(panel->dev, "failed to set display on: %d\n", err);
282
-
goto poweroff;
283
-
}
259
+
mipi_dsi_dual(mipi_dsi_dcs_set_display_on_multi,
260
+
&dsi_ctx, jdi->link1, jdi->link2);
284
261
285
-
err = mipi_dsi_dcs_set_display_on(jdi->link2);
286
-
if (err < 0) {
287
-
dev_err(panel->dev, "failed to set display on: %d\n", err);
262
+
if (dsi_ctx.accum_err < 0)
288
263
goto poweroff;
289
-
}
290
264
291
265
jdi->link1->mode_flags &= ~MIPI_DSI_MODE_LPM;
292
266
jdi->link2->mode_flags &= ~MIPI_DSI_MODE_LPM;
+1
-1
drivers/gpu/drm/panel/panel-novatek-nt35560.c
+1
-1
drivers/gpu/drm/panel/panel-novatek-nt35560.c
+398
-406
drivers/gpu/drm/panel/panel-novatek-nt36523.c
+398
-406
drivers/gpu/drm/panel/panel-novatek-nt36523.c
···
23
23
24
24
#define DSI_NUM_MIN 1
25
25
26
-
#define mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, cmd, seq...) \
27
-
do { \
28
-
dsi_ctx.dsi = dsi0; \
29
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, cmd, seq); \
30
-
dsi_ctx.dsi = dsi1; \
31
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, cmd, seq); \
32
-
} while (0)
33
-
34
26
struct panel_info {
35
27
struct drm_panel panel;
36
28
struct mipi_dsi_device *dsi[2];
···
63
71
struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
64
72
struct mipi_dsi_multi_context dsi_ctx = { .dsi = NULL };
65
73
/* No datasheet, so write magic init sequence directly */
66
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
67
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
68
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x05);
69
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x20);
70
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
71
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x18, 0x40);
72
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
73
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
74
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x02);
75
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x23);
76
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
77
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x00, 0x80);
78
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x01, 0x84);
79
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x05, 0x2d);
80
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x06, 0x00);
81
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x07, 0x00);
82
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x08, 0x01);
83
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x09, 0x45);
84
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x11, 0x02);
85
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x12, 0x80);
86
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x15, 0x83);
87
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x16, 0x0c);
88
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x29, 0x0a);
89
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x30, 0xff);
90
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x31, 0xfe);
91
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x32, 0xfd);
92
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x33, 0xfb);
93
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x34, 0xf8);
94
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x35, 0xf5);
95
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x36, 0xf3);
96
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x37, 0xf2);
97
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x38, 0xf2);
98
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x39, 0xf2);
99
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3a, 0xef);
100
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3b, 0xec);
101
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3d, 0xe9);
102
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3f, 0xe5);
103
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x40, 0xe5);
104
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x41, 0xe5);
105
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2a, 0x13);
106
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x45, 0xff);
107
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x46, 0xf4);
108
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x47, 0xe7);
109
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x48, 0xda);
110
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x49, 0xcd);
111
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4a, 0xc0);
112
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4b, 0xb3);
113
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4c, 0xb2);
114
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4d, 0xb2);
115
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4e, 0xb2);
116
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4f, 0x99);
117
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x50, 0x80);
118
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x68);
119
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x52, 0x66);
120
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x53, 0x66);
121
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x54, 0x66);
122
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2b, 0x0e);
123
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x58, 0xff);
124
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x59, 0xfb);
125
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5a, 0xf7);
126
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5b, 0xf3);
127
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5c, 0xef);
128
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5d, 0xe3);
129
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5e, 0xda);
130
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5f, 0xd8);
131
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x60, 0xd8);
132
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x61, 0xd8);
133
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x62, 0xcb);
134
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x63, 0xbf);
135
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x64, 0xb3);
136
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x65, 0xb2);
137
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x66, 0xb2);
138
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x67, 0xb2);
139
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
140
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
141
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x25, 0x47);
142
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x30, 0x47);
143
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x39, 0x47);
144
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x26);
145
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
146
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x19, 0x10);
147
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1a, 0xe0);
148
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1b, 0x10);
149
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1c, 0x00);
150
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2a, 0x10);
151
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2b, 0xe0);
152
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
153
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
154
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
155
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
156
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x84, 0x08);
157
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x85, 0x0c);
158
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x20);
159
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
160
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x00);
161
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
162
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
163
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x91, 0x1f);
164
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x92, 0x0f);
165
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x93, 0x01);
166
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x94, 0x18);
167
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x95, 0x03);
168
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x96, 0x01);
169
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
170
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb0, 0x01);
171
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
172
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
173
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x19, 0x1f);
174
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1b, 0x1b);
175
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x24);
176
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
177
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb8, 0x28);
178
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x27);
179
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
180
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd0, 0x31);
181
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd1, 0x20);
182
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd2, 0x30);
183
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd4, 0x08);
184
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xde, 0x80);
185
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xdf, 0x02);
186
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x26);
187
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
188
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x00, 0x81);
189
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
190
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x22);
191
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
192
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9f, 0x50);
193
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x6f, 0x01);
194
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x70, 0x11);
195
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x73, 0x01);
196
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x74, 0x49);
197
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x76, 0x01);
198
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x77, 0x49);
199
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xa0, 0x3f);
200
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xa9, 0x50);
201
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xaa, 0x28);
202
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xab, 0x28);
203
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xad, 0x10);
204
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb8, 0x00);
205
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x49);
206
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xba, 0x49);
207
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbb, 0x49);
208
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbe, 0x04);
209
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbf, 0x49);
210
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc0, 0x04);
211
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc1, 0x59);
212
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc2, 0x00);
213
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc5, 0x00);
214
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc6, 0x01);
215
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc7, 0x48);
216
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xca, 0x43);
217
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xcb, 0x3c);
218
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xce, 0x00);
219
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xcf, 0x43);
220
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd0, 0x3c);
221
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd3, 0x43);
222
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd4, 0x3c);
223
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd7, 0x00);
224
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xdc, 0x43);
225
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xdd, 0x3c);
226
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xe1, 0x43);
227
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xe2, 0x3c);
228
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xf2, 0x00);
229
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xf3, 0x01);
230
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xf4, 0x48);
231
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
232
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
233
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x13, 0x01);
234
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x14, 0x23);
235
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbc, 0x01);
236
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbd, 0x23);
237
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
238
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
239
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x97, 0x3c);
240
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x98, 0x02);
241
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x99, 0x95);
242
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9a, 0x03);
243
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9b, 0x00);
244
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9c, 0x0b);
245
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9d, 0x0a);
246
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9e, 0x90);
247
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x22);
248
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
249
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9f, 0x50);
250
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x23);
251
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
252
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xa3, 0x50);
253
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xe0);
254
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
255
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x14, 0x60);
256
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x16, 0xc0);
257
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4f, 0x02);
258
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
259
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
260
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3a, 0x08);
261
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xd0);
262
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
263
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x02, 0xaf);
264
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x09, 0xee);
265
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1c, 0x99);
266
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1d, 0x09);
267
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
268
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
269
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x0f, 0xff);
270
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x53, 0x2c);
271
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x35, 0x00);
272
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbb, 0x13);
273
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
274
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x11);
74
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
75
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
76
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x05);
77
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20);
78
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
79
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x18, 0x40);
80
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
81
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
82
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x02);
83
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x23);
84
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
85
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x00, 0x80);
86
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x01, 0x84);
87
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x05, 0x2d);
88
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x06, 0x00);
89
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x07, 0x00);
90
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x08, 0x01);
91
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x09, 0x45);
92
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x11, 0x02);
93
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x12, 0x80);
94
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x15, 0x83);
95
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x16, 0x0c);
96
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x29, 0x0a);
97
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x30, 0xff);
98
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x31, 0xfe);
99
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x32, 0xfd);
100
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x33, 0xfb);
101
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x34, 0xf8);
102
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x35, 0xf5);
103
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x36, 0xf3);
104
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x37, 0xf2);
105
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x38, 0xf2);
106
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x39, 0xf2);
107
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3a, 0xef);
108
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3b, 0xec);
109
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3d, 0xe9);
110
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3f, 0xe5);
111
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x40, 0xe5);
112
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x41, 0xe5);
113
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2a, 0x13);
114
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x45, 0xff);
115
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x46, 0xf4);
116
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x47, 0xe7);
117
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x48, 0xda);
118
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x49, 0xcd);
119
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4a, 0xc0);
120
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4b, 0xb3);
121
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4c, 0xb2);
122
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4d, 0xb2);
123
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4e, 0xb2);
124
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4f, 0x99);
125
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x50, 0x80);
126
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x68);
127
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x52, 0x66);
128
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x53, 0x66);
129
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x54, 0x66);
130
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2b, 0x0e);
131
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x58, 0xff);
132
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x59, 0xfb);
133
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5a, 0xf7);
134
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5b, 0xf3);
135
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5c, 0xef);
136
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5d, 0xe3);
137
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5e, 0xda);
138
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5f, 0xd8);
139
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x60, 0xd8);
140
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x61, 0xd8);
141
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x62, 0xcb);
142
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x63, 0xbf);
143
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x64, 0xb3);
144
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x65, 0xb2);
145
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x66, 0xb2);
146
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x67, 0xb2);
147
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
148
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
149
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x25, 0x47);
150
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x30, 0x47);
151
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x39, 0x47);
152
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x26);
153
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
154
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x19, 0x10);
155
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1a, 0xe0);
156
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1b, 0x10);
157
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1c, 0x00);
158
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2a, 0x10);
159
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2b, 0xe0);
160
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
161
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
162
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
163
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
164
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x84, 0x08);
165
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x85, 0x0c);
166
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20);
167
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
168
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x00);
169
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
170
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
171
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x91, 0x1f);
172
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x92, 0x0f);
173
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x93, 0x01);
174
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x94, 0x18);
175
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x95, 0x03);
176
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x96, 0x01);
177
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
178
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb0, 0x01);
179
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
180
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
181
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x19, 0x1f);
182
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1b, 0x1b);
183
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x24);
184
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
185
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb8, 0x28);
186
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x27);
187
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
188
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd0, 0x31);
189
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd1, 0x20);
190
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd2, 0x30);
191
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd4, 0x08);
192
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xde, 0x80);
193
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xdf, 0x02);
194
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x26);
195
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
196
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x00, 0x81);
197
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
198
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x22);
199
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
200
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9f, 0x50);
201
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x6f, 0x01);
202
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x70, 0x11);
203
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x73, 0x01);
204
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x74, 0x49);
205
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x76, 0x01);
206
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x77, 0x49);
207
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xa0, 0x3f);
208
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xa9, 0x50);
209
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xaa, 0x28);
210
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xab, 0x28);
211
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xad, 0x10);
212
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb8, 0x00);
213
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x49);
214
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xba, 0x49);
215
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbb, 0x49);
216
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbe, 0x04);
217
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbf, 0x49);
218
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc0, 0x04);
219
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc1, 0x59);
220
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc2, 0x00);
221
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc5, 0x00);
222
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc6, 0x01);
223
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc7, 0x48);
224
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xca, 0x43);
225
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xcb, 0x3c);
226
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xce, 0x00);
227
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xcf, 0x43);
228
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd0, 0x3c);
229
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd3, 0x43);
230
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd4, 0x3c);
231
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd7, 0x00);
232
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xdc, 0x43);
233
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xdd, 0x3c);
234
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xe1, 0x43);
235
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xe2, 0x3c);
236
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xf2, 0x00);
237
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xf3, 0x01);
238
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xf4, 0x48);
239
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
240
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
241
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x13, 0x01);
242
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x14, 0x23);
243
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbc, 0x01);
244
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbd, 0x23);
245
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
246
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
247
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x97, 0x3c);
248
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x98, 0x02);
249
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x99, 0x95);
250
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9a, 0x03);
251
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9b, 0x00);
252
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9c, 0x0b);
253
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9d, 0x0a);
254
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9e, 0x90);
255
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x22);
256
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
257
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9f, 0x50);
258
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x23);
259
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
260
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xa3, 0x50);
261
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xe0);
262
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
263
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x14, 0x60);
264
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x16, 0xc0);
265
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4f, 0x02);
266
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
267
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
268
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3a, 0x08);
269
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xd0);
270
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
271
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x02, 0xaf);
272
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x09, 0xee);
273
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1c, 0x99);
274
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1d, 0x09);
275
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
276
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
277
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x0f, 0xff);
278
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x53, 0x2c);
279
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x35, 0x00);
280
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbb, 0x13);
281
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
282
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x11);
275
283
mipi_dsi_msleep(&dsi_ctx, 70);
276
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x29);
284
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x29);
277
285
278
286
return dsi_ctx.accum_err;
279
287
}
···
284
292
struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
285
293
struct mipi_dsi_multi_context dsi_ctx = { .dsi = NULL };
286
294
/* No datasheet, so write magic init sequence directly */
287
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
288
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
289
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x05);
290
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x20);
291
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
292
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x18, 0x40);
293
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
294
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
295
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x02);
296
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xd0);
297
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
298
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x02, 0xaf);
299
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x00, 0x30);
300
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x09, 0xee);
301
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1c, 0x99);
302
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1d, 0x09);
303
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
304
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
305
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3a, 0x08);
306
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xe0);
307
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
308
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4f, 0x02);
309
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x20);
310
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
311
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x58, 0x40);
312
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
313
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
314
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x35, 0x00);
315
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x23);
316
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
317
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x00, 0x80);
318
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x01, 0x84);
319
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x05, 0x2d);
320
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x06, 0x00);
321
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x07, 0x00);
322
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x08, 0x01);
323
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x09, 0x45);
324
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x11, 0x02);
325
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x12, 0x80);
326
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x15, 0x83);
327
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x16, 0x0c);
328
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x29, 0x0a);
329
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x30, 0xff);
330
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x31, 0xfe);
331
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x32, 0xfd);
332
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x33, 0xfb);
333
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x34, 0xf8);
334
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x35, 0xf5);
335
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x36, 0xf3);
336
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x37, 0xf2);
337
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x38, 0xf2);
338
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x39, 0xf2);
339
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3a, 0xef);
340
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3b, 0xec);
341
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3d, 0xe9);
342
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3f, 0xe5);
343
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x40, 0xe5);
344
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x41, 0xe5);
345
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2a, 0x13);
346
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x45, 0xff);
347
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x46, 0xf4);
348
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x47, 0xe7);
349
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x48, 0xda);
350
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x49, 0xcd);
351
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4a, 0xc0);
352
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4b, 0xb3);
353
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4c, 0xb2);
354
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4d, 0xb2);
355
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4e, 0xb2);
356
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x4f, 0x99);
357
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x50, 0x80);
358
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x68);
359
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x52, 0x66);
360
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x53, 0x66);
361
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x54, 0x66);
362
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2b, 0x0e);
363
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x58, 0xff);
364
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x59, 0xfb);
365
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5a, 0xf7);
366
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5b, 0xf3);
367
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5c, 0xef);
368
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5d, 0xe3);
369
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5e, 0xda);
370
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x5f, 0xd8);
371
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x60, 0xd8);
372
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x61, 0xd8);
373
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x62, 0xcb);
374
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x63, 0xbf);
375
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x64, 0xb3);
376
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x65, 0xb2);
377
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x66, 0xb2);
378
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x67, 0xb2);
379
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
380
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
381
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x0f, 0xff);
382
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x53, 0x2c);
383
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x55, 0x00);
384
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbb, 0x13);
385
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
386
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
387
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
388
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x25, 0x46);
389
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x30, 0x46);
390
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x39, 0x46);
391
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x26);
392
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
393
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
394
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x19, 0x10);
395
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1a, 0xe0);
396
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1b, 0x10);
397
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1c, 0x00);
398
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2a, 0x10);
399
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x2b, 0xe0);
400
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
401
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
402
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x84, 0x08);
403
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x85, 0x0c);
404
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x20);
405
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
406
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x51, 0x00);
407
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
408
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
409
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x91, 0x1f);
410
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x92, 0x0f);
411
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x93, 0x01);
412
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x94, 0x18);
413
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x95, 0x03);
414
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x96, 0x01);
415
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
416
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb0, 0x01);
417
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
418
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
419
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x19, 0x1f);
420
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x1b, 0x1b);
421
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x24);
422
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
423
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb8, 0x28);
424
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x27);
425
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
426
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd0, 0x31);
427
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd1, 0x20);
428
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd4, 0x08);
429
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xde, 0x80);
430
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xdf, 0x02);
431
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x26);
432
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
433
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x00, 0x81);
434
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
435
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x22);
436
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
437
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x6f, 0x01);
438
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x70, 0x11);
439
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x73, 0x01);
440
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x74, 0x4d);
441
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xa0, 0x3f);
442
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xa9, 0x50);
443
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xaa, 0x28);
444
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xab, 0x28);
445
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xad, 0x10);
446
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb8, 0x00);
447
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xb9, 0x4b);
448
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xba, 0x96);
449
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbb, 0x4b);
450
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbe, 0x07);
451
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbf, 0x4b);
452
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc0, 0x07);
453
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc1, 0x5c);
454
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc2, 0x00);
455
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc5, 0x00);
456
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc6, 0x3f);
457
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xc7, 0x00);
458
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xca, 0x08);
459
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xcb, 0x40);
460
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xce, 0x00);
461
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xcf, 0x08);
462
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd0, 0x40);
463
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd3, 0x08);
464
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xd4, 0x40);
465
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x25);
466
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
467
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbc, 0x01);
468
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xbd, 0x1c);
469
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
470
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
471
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x9a, 0x03);
472
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0xff, 0x10);
473
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x11);
295
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
296
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
297
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x05);
298
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20);
299
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
300
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x18, 0x40);
301
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
302
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
303
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x02);
304
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xd0);
305
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
306
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x02, 0xaf);
307
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x00, 0x30);
308
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x09, 0xee);
309
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1c, 0x99);
310
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1d, 0x09);
311
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
312
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
313
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3a, 0x08);
314
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xe0);
315
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
316
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4f, 0x02);
317
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20);
318
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
319
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x58, 0x40);
320
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
321
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
322
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x35, 0x00);
323
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x23);
324
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
325
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x00, 0x80);
326
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x01, 0x84);
327
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x05, 0x2d);
328
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x06, 0x00);
329
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x07, 0x00);
330
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x08, 0x01);
331
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x09, 0x45);
332
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x11, 0x02);
333
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x12, 0x80);
334
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x15, 0x83);
335
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x16, 0x0c);
336
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x29, 0x0a);
337
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x30, 0xff);
338
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x31, 0xfe);
339
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x32, 0xfd);
340
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x33, 0xfb);
341
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x34, 0xf8);
342
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x35, 0xf5);
343
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x36, 0xf3);
344
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x37, 0xf2);
345
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x38, 0xf2);
346
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x39, 0xf2);
347
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3a, 0xef);
348
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3b, 0xec);
349
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3d, 0xe9);
350
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3f, 0xe5);
351
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x40, 0xe5);
352
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x41, 0xe5);
353
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2a, 0x13);
354
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x45, 0xff);
355
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x46, 0xf4);
356
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x47, 0xe7);
357
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x48, 0xda);
358
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x49, 0xcd);
359
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4a, 0xc0);
360
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4b, 0xb3);
361
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4c, 0xb2);
362
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4d, 0xb2);
363
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4e, 0xb2);
364
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x4f, 0x99);
365
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x50, 0x80);
366
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x68);
367
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x52, 0x66);
368
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x53, 0x66);
369
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x54, 0x66);
370
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2b, 0x0e);
371
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x58, 0xff);
372
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x59, 0xfb);
373
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5a, 0xf7);
374
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5b, 0xf3);
375
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5c, 0xef);
376
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5d, 0xe3);
377
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5e, 0xda);
378
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x5f, 0xd8);
379
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x60, 0xd8);
380
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x61, 0xd8);
381
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x62, 0xcb);
382
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x63, 0xbf);
383
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x64, 0xb3);
384
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x65, 0xb2);
385
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x66, 0xb2);
386
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x67, 0xb2);
387
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
388
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
389
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x0f, 0xff);
390
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x53, 0x2c);
391
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x55, 0x00);
392
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbb, 0x13);
393
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
394
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
395
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
396
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x25, 0x46);
397
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x30, 0x46);
398
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x39, 0x46);
399
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x26);
400
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
401
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
402
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x19, 0x10);
403
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1a, 0xe0);
404
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1b, 0x10);
405
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1c, 0x00);
406
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2a, 0x10);
407
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x2b, 0xe0);
408
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0xf0);
409
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
410
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x84, 0x08);
411
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x85, 0x0c);
412
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20);
413
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
414
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x51, 0x00);
415
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
416
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
417
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x91, 0x1f);
418
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x92, 0x0f);
419
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x93, 0x01);
420
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x94, 0x18);
421
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x95, 0x03);
422
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x96, 0x01);
423
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
424
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb0, 0x01);
425
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
426
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
427
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x19, 0x1f);
428
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x1b, 0x1b);
429
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x24);
430
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
431
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb8, 0x28);
432
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x27);
433
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
434
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd0, 0x31);
435
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd1, 0x20);
436
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd4, 0x08);
437
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xde, 0x80);
438
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xdf, 0x02);
439
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x26);
440
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
441
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x00, 0x81);
442
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x01, 0xb0);
443
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x22);
444
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
445
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x6f, 0x01);
446
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x70, 0x11);
447
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x73, 0x01);
448
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x74, 0x4d);
449
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xa0, 0x3f);
450
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xa9, 0x50);
451
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xaa, 0x28);
452
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xab, 0x28);
453
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xad, 0x10);
454
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb8, 0x00);
455
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x4b);
456
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xba, 0x96);
457
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbb, 0x4b);
458
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbe, 0x07);
459
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbf, 0x4b);
460
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc0, 0x07);
461
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc1, 0x5c);
462
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc2, 0x00);
463
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc5, 0x00);
464
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc6, 0x3f);
465
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xc7, 0x00);
466
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xca, 0x08);
467
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xcb, 0x40);
468
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xce, 0x00);
469
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xcf, 0x08);
470
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd0, 0x40);
471
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd3, 0x08);
472
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xd4, 0x40);
473
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x25);
474
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
475
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbc, 0x01);
476
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xbd, 0x1c);
477
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x2a);
478
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01);
479
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x9a, 0x03);
480
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10);
481
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x11);
474
482
mipi_dsi_msleep(&dsi_ctx, 70);
475
-
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, 0x29);
483
+
mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x29);
476
484
477
485
return dsi_ctx.accum_err;
478
486
}
+2
-5
drivers/gpu/drm/panel/panel-orisetech-ota5601a.c
+2
-5
drivers/gpu/drm/panel/panel-orisetech-ota5601a.c
···
276
276
}
277
277
278
278
err = drm_panel_of_backlight(&panel->drm_panel);
279
-
if (err) {
280
-
if (err != -EPROBE_DEFER)
281
-
dev_err(dev, "Failed to get backlight handle\n");
282
-
return err;
283
-
}
279
+
if (err)
280
+
return dev_err_probe(dev, err, "Failed to get backlight handle\n");
284
281
285
282
drm_panel_add(&panel->drm_panel);
286
283
+981
drivers/gpu/drm/panel/panel-samsung-s6e8aa5x01-ams561ra01.c
+981
drivers/gpu/drm/panel/panel-samsung-s6e8aa5x01-ams561ra01.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Samsung AMS561RA01 panel with S6E8AA5X01 controller.
4
+
*
5
+
* Copyright (C) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
6
+
*/
7
+
8
+
#include <linux/backlight.h>
9
+
#include <linux/gpio/consumer.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/regulator/consumer.h>
13
+
14
+
#include <drm/drm_mipi_dsi.h>
15
+
#include <drm/drm_modes.h>
16
+
#include <drm/drm_panel.h>
17
+
#include <drm/drm_probe_helper.h>
18
+
19
+
/* Manufacturer Command Set */
20
+
#define MCS_AIDCTL 0xb2
21
+
#define MCS_ADAPTIVECTL 0xb5
22
+
#define MCS_ELVSS 0xb6
23
+
#define MCS_TEMPERCTL 0xb8
24
+
#define MCS_PENTILE 0xc0
25
+
#define MCS_GAMMACTL 0xca
26
+
#define MCS_LTPSCTL 0xcb
27
+
#define MCS_PCD 0xcc
28
+
#define MCS_ERRFLAG 0xe7
29
+
#define MCS_ACCESSPROT 0xf0
30
+
#define MCS_DISPCTL 0xf2
31
+
#define MCS_GAMMAUPD 0xf7
32
+
33
+
#define GAMMA_CMD_LEN 34
34
+
#define AID_CMD_LEN 3
35
+
36
+
static const struct {
37
+
u8 gamma[GAMMA_CMD_LEN];
38
+
u8 aid[AID_CMD_LEN];
39
+
} s6e8aa5x01_ams561ra01_cmds[] = {
40
+
{
41
+
/* 5 nits */
42
+
{ MCS_GAMMACTL,
43
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x94,
44
+
0x88, 0x89, 0x8a, 0x87, 0x87, 0x89,
45
+
0x8d, 0x8c, 0x8d, 0x89, 0x8c, 0x8e,
46
+
0x8e, 0x8f, 0x90, 0xa3, 0xa2, 0x9a,
47
+
0xcf, 0xca, 0x9f, 0xe6, 0xff, 0xb4,
48
+
0x00, 0x00, 0x00, },
49
+
{ MCS_AIDCTL, 0x05, 0xa5 },
50
+
}, {
51
+
/* 6 nits */
52
+
{ MCS_GAMMACTL,
53
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x95,
54
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
55
+
0x8c, 0x8a, 0x8c, 0x85, 0x88, 0x8c,
56
+
0x8b, 0x8c, 0x8e, 0xa2, 0xa2, 0x9a,
57
+
0xd0, 0xcc, 0xa2, 0xed, 0xff, 0xb7,
58
+
0x00, 0x00, 0x00, },
59
+
{ MCS_AIDCTL, 0x05, 0x95 },
60
+
}, {
61
+
/* 7 nits */
62
+
{ MCS_GAMMACTL,
63
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x95,
64
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
65
+
0x8c, 0x8a, 0x8c, 0x85, 0x88, 0x8c,
66
+
0x8b, 0x8c, 0x8e, 0xa2, 0xa2, 0x99,
67
+
0xc8, 0xc4, 0x9d, 0xed, 0xff, 0xb7,
68
+
0x00, 0x00, 0x00, },
69
+
{ MCS_AIDCTL, 0x05, 0x89 },
70
+
}, {
71
+
/* 8 nits */
72
+
{ MCS_GAMMACTL,
73
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
74
+
0x88, 0x89, 0x8a, 0x87, 0x87, 0x89,
75
+
0x8a, 0x88, 0x8b, 0x83, 0x86, 0x8b,
76
+
0x8c, 0x8b, 0x8d, 0x9d, 0x9f, 0x97,
77
+
0xc7, 0xc3, 0x9c, 0xf5, 0xff, 0xbb,
78
+
0x00, 0x00, 0x00, },
79
+
{ MCS_AIDCTL, 0x05, 0x7e },
80
+
}, {
81
+
/* 9 nits */
82
+
{ MCS_GAMMACTL,
83
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
84
+
0x88, 0x89, 0x8a, 0x87, 0x87, 0x89,
85
+
0x89, 0x86, 0x8a, 0x82, 0x84, 0x88,
86
+
0x90, 0x8f, 0x91, 0x95, 0x97, 0x94,
87
+
0xc6, 0xc2, 0x9d, 0xf5, 0xff, 0xbb,
88
+
0x00, 0x00, 0x00, },
89
+
{ MCS_AIDCTL, 0x05, 0x73 },
90
+
}, {
91
+
/* 10 nits */
92
+
{ MCS_GAMMACTL,
93
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
94
+
0x88, 0x89, 0x8a, 0x87, 0x87, 0x89,
95
+
0x89, 0x86, 0x8a, 0x82, 0x84, 0x88,
96
+
0x90, 0x8f, 0x91, 0x94, 0x97, 0x93,
97
+
0xc6, 0xc2, 0x9e, 0xec, 0xff, 0xb7,
98
+
0x00, 0x00, 0x00, },
99
+
{ MCS_AIDCTL, 0x05, 0x67 },
100
+
}, {
101
+
/* 11 nits */
102
+
{ MCS_GAMMACTL,
103
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
104
+
0x88, 0x89, 0x8a, 0x87, 0x87, 0x89,
105
+
0x89, 0x86, 0x8a, 0x82, 0x84, 0x88,
106
+
0x8b, 0x8b, 0x8d, 0x90, 0x93, 0x92,
107
+
0xc5, 0xc1, 0x9c, 0xf5, 0xff, 0xbb,
108
+
0x00, 0x00, 0x00, },
109
+
{ MCS_AIDCTL, 0x05, 0x56 },
110
+
}, {
111
+
/* 12 nits */
112
+
{ MCS_GAMMACTL,
113
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
114
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
115
+
0x89, 0x86, 0x89, 0x82, 0x84, 0x88,
116
+
0x87, 0x86, 0x8a, 0x8c, 0x90, 0x8f,
117
+
0xcd, 0xc9, 0xa1, 0xec, 0xff, 0xb7,
118
+
0x00, 0x00, 0x00, },
119
+
{ MCS_AIDCTL, 0x05, 0x4a },
120
+
}, {
121
+
/* 13 nits */
122
+
{ MCS_GAMMACTL,
123
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
124
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
125
+
0x89, 0x86, 0x89, 0x82, 0x84, 0x88,
126
+
0x87, 0x86, 0x8a, 0x8c, 0x90, 0x8e,
127
+
0xc4, 0xbf, 0x9c, 0xf5, 0xff, 0xbb,
128
+
0x00, 0x00, 0x00, },
129
+
{ MCS_AIDCTL, 0x05, 0x3b },
130
+
}, {
131
+
/* 14 nits */
132
+
{ MCS_GAMMACTL,
133
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
134
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
135
+
0x89, 0x86, 0x89, 0x82, 0x84, 0x88,
136
+
0x87, 0x86, 0x89, 0x8c, 0x90, 0x8f,
137
+
0xc2, 0xbf, 0x9c, 0xec, 0xff, 0xb7,
138
+
0x00, 0x00, 0x00, },
139
+
{ MCS_AIDCTL, 0x05, 0x35 },
140
+
}, {
141
+
/* 15 nits */
142
+
{ MCS_GAMMACTL,
143
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
144
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
145
+
0x89, 0x86, 0x89, 0x82, 0x84, 0x88,
146
+
0x87, 0x86, 0x89, 0x8c, 0x90, 0x8f,
147
+
0xb7, 0xb6, 0x96, 0xec, 0xff, 0xb7,
148
+
0x00, 0x00, 0x00, },
149
+
{ MCS_AIDCTL, 0x05, 0x25 },
150
+
}, {
151
+
/* 16 nits */
152
+
{ MCS_GAMMACTL,
153
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
154
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
155
+
0x89, 0x86, 0x89, 0x82, 0x84, 0x88,
156
+
0x88, 0x86, 0x89, 0x8c, 0x90, 0x8f,
157
+
0xb7, 0xb6, 0x96, 0xec, 0xff, 0xb7,
158
+
0x00, 0x00, 0x00, },
159
+
{ MCS_AIDCTL, 0x05, 0x20 },
160
+
}, {
161
+
/* 17 nits */
162
+
{ MCS_GAMMACTL,
163
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
164
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
165
+
0x89, 0x86, 0x89, 0x7f, 0x80, 0x86,
166
+
0x86, 0x85, 0x89, 0x88, 0x8c, 0x8e,
167
+
0xbf, 0xbe, 0x9c, 0xec, 0xff, 0xb7,
168
+
0x00, 0x00, 0x00, },
169
+
{ MCS_AIDCTL, 0x05, 0x11 },
170
+
}, {
171
+
/* 19 nits */
172
+
{ MCS_GAMMACTL,
173
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
174
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
175
+
0x89, 0x86, 0x89, 0x7f, 0x80, 0x86,
176
+
0x87, 0x85, 0x89, 0x88, 0x8c, 0x8e,
177
+
0xb3, 0xb4, 0x97, 0xeb, 0xff, 0xb7,
178
+
0x00, 0x00, 0x00, },
179
+
{ MCS_AIDCTL, 0x04, 0xf2 },
180
+
}, {
181
+
/* 20 nits */
182
+
{ MCS_GAMMACTL,
183
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x95,
184
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
185
+
0x89, 0x86, 0x89, 0x7f, 0x80, 0x86,
186
+
0x87, 0x85, 0x89, 0x89, 0x8c, 0x8e,
187
+
0xb3, 0xb4, 0x97, 0xeb, 0xff, 0xb7,
188
+
0x00, 0x00, 0x00, },
189
+
{ MCS_AIDCTL, 0x04, 0xe4 },
190
+
}, {
191
+
/* 21 nits */
192
+
{ MCS_GAMMACTL,
193
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x96,
194
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
195
+
0x8a, 0x88, 0x8b, 0x7d, 0x7e, 0x84,
196
+
0x8c, 0x8a, 0x8c, 0x8e, 0x90, 0x8f,
197
+
0xb6, 0xb6, 0x97, 0xe3, 0xff, 0xb3,
198
+
0x00, 0x00, 0x00, },
199
+
{ MCS_AIDCTL, 0x04, 0xd5 },
200
+
}, {
201
+
/* 22 nits */
202
+
{ MCS_GAMMACTL,
203
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x97,
204
+
0x88, 0x89, 0x8b, 0x87, 0x87, 0x89,
205
+
0x8a, 0x88, 0x8b, 0x81, 0x82, 0x86,
206
+
0x87, 0x86, 0x88, 0x8e, 0x90, 0x8f,
207
+
0xb6, 0xb6, 0x95, 0xe3, 0xff, 0xb3,
208
+
0x00, 0x00, 0x00, },
209
+
{ MCS_AIDCTL, 0x04, 0xc5 },
210
+
}, {
211
+
/* 24 nits */
212
+
{ MCS_GAMMACTL,
213
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x97,
214
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
215
+
0x8a, 0x87, 0x8a, 0x81, 0x82, 0x86,
216
+
0x87, 0x86, 0x88, 0x8e, 0x90, 0x8f,
217
+
0xb6, 0xb6, 0x94, 0xe3, 0xff, 0xb3,
218
+
0x00, 0x00, 0x00, },
219
+
{ MCS_AIDCTL, 0x04, 0xa7 },
220
+
}, {
221
+
/* 25 nits */
222
+
{ MCS_GAMMACTL,
223
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x98,
224
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
225
+
0x8a, 0x87, 0x8a, 0x81, 0x82, 0x86,
226
+
0x87, 0x86, 0x87, 0x8e, 0x90, 0x8f,
227
+
0xbf, 0xbf, 0x9a, 0xda, 0xfa, 0xaf,
228
+
0x00, 0x00, 0x00, },
229
+
{ MCS_AIDCTL, 0x04, 0x95 },
230
+
}, {
231
+
/* 27 nits */
232
+
{ MCS_GAMMACTL,
233
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x99,
234
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
235
+
0x8a, 0x87, 0x8a, 0x83, 0x86, 0x8a,
236
+
0x88, 0x87, 0x87, 0x88, 0x8b, 0x8c,
237
+
0xbf, 0xbf, 0x9a, 0xda, 0xfa, 0xaf,
238
+
0x00, 0x00, 0x00, },
239
+
{ MCS_AIDCTL, 0x04, 0x76 },
240
+
}, {
241
+
/* 29 nits */
242
+
{ MCS_GAMMACTL,
243
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x99,
244
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
245
+
0x8a, 0x87, 0x8b, 0x83, 0x86, 0x89,
246
+
0x88, 0x87, 0x88, 0x88, 0x8b, 0x8b,
247
+
0xbf, 0xbf, 0x9a, 0xda, 0xfa, 0xaf,
248
+
0x00, 0x00, 0x00, },
249
+
{ MCS_AIDCTL, 0x04, 0x54 },
250
+
}, {
251
+
/* 30 nits */
252
+
{ MCS_GAMMACTL,
253
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9a,
254
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
255
+
0x8a, 0x87, 0x8a, 0x84, 0x86, 0x8a,
256
+
0x87, 0x87, 0x87, 0x88, 0x8b, 0x8b,
257
+
0xbf, 0xbf, 0x99, 0xda, 0xfa, 0xaf,
258
+
0x00, 0x00, 0x00, },
259
+
{ MCS_AIDCTL, 0x04, 0x44 },
260
+
}, {
261
+
/* 32 nits */
262
+
{ MCS_GAMMACTL,
263
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9a,
264
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
265
+
0x89, 0x87, 0x8a, 0x84, 0x86, 0x8a,
266
+
0x87, 0x87, 0x87, 0x89, 0x8b, 0x8b,
267
+
0xbf, 0xbf, 0x98, 0xd2, 0xf2, 0xac,
268
+
0x00, 0x00, 0x00, },
269
+
{ MCS_AIDCTL, 0x04, 0x1f },
270
+
}, {
271
+
/* 34 nits */
272
+
{ MCS_GAMMACTL,
273
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
274
+
0x88, 0x89, 0x8b, 0x88, 0x88, 0x8a,
275
+
0x8b, 0x87, 0x8b, 0x83, 0x86, 0x89,
276
+
0x87, 0x87, 0x88, 0x88, 0x8b, 0x8a,
277
+
0xbf, 0xbf, 0x98, 0xd2, 0xf2, 0xac,
278
+
0x00, 0x00, 0x00, },
279
+
{ MCS_AIDCTL, 0x03, 0xff },
280
+
}, {
281
+
/* 37 nits */
282
+
{ MCS_GAMMACTL,
283
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
284
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
285
+
0x8a, 0x87, 0x8a, 0x81, 0x82, 0x86,
286
+
0x86, 0x86, 0x86, 0x8d, 0x90, 0x8d,
287
+
0xc0, 0xbf, 0x9a, 0xd2, 0xf2, 0xac,
288
+
0x00, 0x00, 0x00, },
289
+
{ MCS_AIDCTL, 0x03, 0xd3 },
290
+
}, {
291
+
/* 39 nits */
292
+
{ MCS_GAMMACTL,
293
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
294
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
295
+
0x8a, 0x87, 0x8a, 0x81, 0x82, 0x86,
296
+
0x87, 0x86, 0x87, 0x8d, 0x90, 0x8d,
297
+
0xb6, 0xb6, 0x93, 0xda, 0xf9, 0xaf,
298
+
0x00, 0x00, 0x00, },
299
+
{ MCS_AIDCTL, 0x03, 0xb3 },
300
+
}, {
301
+
/* 41 nits */
302
+
{ MCS_GAMMACTL,
303
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
304
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
305
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x85,
306
+
0x87, 0x86, 0x87, 0x8d, 0x90, 0x8d,
307
+
0xb6, 0xb6, 0x94, 0xda, 0xf9, 0xaf,
308
+
0x00, 0x00, 0x00, },
309
+
{ MCS_AIDCTL, 0x03, 0x93 },
310
+
}, {
311
+
/* 44 nits */
312
+
{ MCS_GAMMACTL,
313
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
314
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
315
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x86,
316
+
0x87, 0x86, 0x86, 0x85, 0x87, 0x8a,
317
+
0xbe, 0xbe, 0x99, 0xda, 0xf9, 0xaf,
318
+
0x00, 0x00, 0x00, },
319
+
{ MCS_AIDCTL, 0x03, 0x66 },
320
+
}, {
321
+
/* 47 nits */
322
+
{ MCS_GAMMACTL,
323
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9b,
324
+
0x89, 0x89, 0x8c, 0x88, 0x88, 0x8a,
325
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x86,
326
+
0x88, 0x86, 0x87, 0x84, 0x87, 0x89,
327
+
0xb4, 0xb4, 0x94, 0xe2, 0xff, 0xb3,
328
+
0x00, 0x00, 0x00, },
329
+
{ MCS_AIDCTL, 0x03, 0x40 },
330
+
}, {
331
+
/* 50 nits */
332
+
{ MCS_GAMMACTL,
333
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9c,
334
+
0x89, 0x89, 0x8b, 0x88, 0x88, 0x8a,
335
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x86,
336
+
0x88, 0x86, 0x87, 0x84, 0x87, 0x89,
337
+
0xb4, 0xb4, 0x95, 0xe2, 0xff, 0xb3,
338
+
0x00, 0x00, 0x00, },
339
+
{ MCS_AIDCTL, 0x03, 0x0e },
340
+
}, {
341
+
/* 53 nits */
342
+
{ MCS_GAMMACTL,
343
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9c,
344
+
0x89, 0x89, 0x8b, 0x88, 0x88, 0x8a,
345
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x86,
346
+
0x88, 0x86, 0x87, 0x85, 0x87, 0x8a,
347
+
0xb4, 0xb4, 0x96, 0xe2, 0xff, 0xb3,
348
+
0x00, 0x00, 0x00, },
349
+
{ MCS_AIDCTL, 0x02, 0xe2 },
350
+
}, {
351
+
/* 56 nits */
352
+
{ MCS_GAMMACTL,
353
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9c,
354
+
0x89, 0x89, 0x8b, 0x88, 0x88, 0x8a,
355
+
0x8a, 0x87, 0x8b, 0x81, 0x82, 0x86,
356
+
0x88, 0x86, 0x87, 0x85, 0x87, 0x8a,
357
+
0xab, 0xab, 0x90, 0xdd, 0xf7, 0xaf,
358
+
0x00, 0x00, 0x00, },
359
+
{ MCS_AIDCTL, 0x02, 0xb5 },
360
+
}, {
361
+
/* 60 nits */
362
+
{ MCS_GAMMACTL,
363
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9c,
364
+
0x89, 0x89, 0x8b, 0x88, 0x88, 0x8a,
365
+
0x8a, 0x87, 0x8b, 0x82, 0x82, 0x87,
366
+
0x83, 0x81, 0x84, 0x81, 0x84, 0x88,
367
+
0xb3, 0xb3, 0x96, 0xcf, 0xe5, 0xa8,
368
+
0x00, 0x00, 0x00, },
369
+
{ MCS_AIDCTL, 0x02, 0x77 },
370
+
}, {
371
+
/* 64 nits */
372
+
{ MCS_GAMMACTL,
373
+
0x00, 0x98, 0x00, 0xa4, 0x00, 0x9c,
374
+
0x89, 0x89, 0x8b, 0x88, 0x88, 0x8a,
375
+
0x8a, 0x87, 0x8b, 0x82, 0x82, 0x87,
376
+
0x83, 0x81, 0x84, 0x82, 0x84, 0x88,
377
+
0xb2, 0xb3, 0x97, 0xcf, 0xe5, 0xa8,
378
+
0x00, 0x00, 0x00, },
379
+
{ MCS_AIDCTL, 0x02, 0x36 },
380
+
}, {
381
+
/* 68 nits */
382
+
{ MCS_GAMMACTL,
383
+
0x00, 0x9b, 0x00, 0xa6, 0x00, 0x9d,
384
+
0x88, 0x88, 0x89, 0x89, 0x89, 0x8b,
385
+
0x8a, 0x88, 0x8b, 0x7f, 0x80, 0x86,
386
+
0x88, 0x86, 0x87, 0x7d, 0x7f, 0x85,
387
+
0xb2, 0xb3, 0x97, 0xcf, 0xe5, 0xa8,
388
+
0x00, 0x00, 0x00, },
389
+
{ MCS_AIDCTL, 0x02, 0x15 },
390
+
}, {
391
+
/* 72 nits */
392
+
{ MCS_GAMMACTL,
393
+
0x00, 0x9c, 0x00, 0xa9, 0x00, 0xa0,
394
+
0x88, 0x88, 0x89, 0x88, 0x88, 0x8a,
395
+
0x8c, 0x8a, 0x8d, 0x7f, 0x81, 0x85,
396
+
0x84, 0x82, 0x84, 0x85, 0x87, 0x8a,
397
+
0xaa, 0xab, 0x93, 0xcf, 0xe5, 0xa8,
398
+
0x00, 0x00, 0x00, },
399
+
{ MCS_AIDCTL, 0x02, 0x15 },
400
+
}, {
401
+
/* 77 nits */
402
+
{ MCS_GAMMACTL,
403
+
0x00, 0xa1, 0x00, 0xad, 0x00, 0xa5,
404
+
0x89, 0x89, 0x8a, 0x88, 0x87, 0x89,
405
+
0x8c, 0x89, 0x8d, 0x7f, 0x81, 0x85,
406
+
0x84, 0x83, 0x84, 0x81, 0x83, 0x86,
407
+
0xaa, 0xab, 0x93, 0xc0, 0xd3, 0xa1,
408
+
0x00, 0x00, 0x00, },
409
+
{ MCS_AIDCTL, 0x02, 0x15 },
410
+
}, {
411
+
/* 82 nits */
412
+
{ MCS_GAMMACTL,
413
+
0x00, 0xa5, 0x00, 0xb0, 0x00, 0xa9,
414
+
0x88, 0x89, 0x89, 0x85, 0x86, 0x89,
415
+
0x8a, 0x88, 0x8b, 0x82, 0x82, 0x87,
416
+
0x81, 0x80, 0x82, 0x89, 0x8b, 0x8b,
417
+
0xa2, 0xa3, 0x8e, 0xc0, 0xd3, 0xa1,
418
+
0x00, 0x00, 0x00, },
419
+
{ MCS_AIDCTL, 0x02, 0x15 },
420
+
}, {
421
+
/* 87 nits */
422
+
{ MCS_GAMMACTL,
423
+
0x00, 0xab, 0x00, 0xb4, 0x00, 0xad,
424
+
0x88, 0x89, 0x8a, 0x84, 0x86, 0x88,
425
+
0x8a, 0x88, 0x8b, 0x7f, 0x7f, 0x84,
426
+
0x86, 0x84, 0x85, 0x85, 0x86, 0x88,
427
+
0xa2, 0xa3, 0x8f, 0xc0, 0xd3, 0xa1,
428
+
0x00, 0x00, 0x00, },
429
+
{ MCS_AIDCTL, 0x02, 0x15 },
430
+
}, {
431
+
/* 93 nits */
432
+
{ MCS_GAMMACTL,
433
+
0x00, 0xaf, 0x00, 0xb9, 0x00, 0xb1,
434
+
0x88, 0x89, 0x8a, 0x84, 0x85, 0x87,
435
+
0x8a, 0x89, 0x8b, 0x7e, 0x7e, 0x83,
436
+
0x87, 0x86, 0x86, 0x88, 0x8a, 0x89,
437
+
0x9c, 0x9c, 0x8b, 0xc0, 0xd3, 0xa1,
438
+
0x00, 0x00, 0x00, },
439
+
{ MCS_AIDCTL, 0x02, 0x15 },
440
+
}, {
441
+
/* 98 nits */
442
+
{ MCS_GAMMACTL,
443
+
0x00, 0xb3, 0x00, 0xbc, 0x00, 0xb5,
444
+
0x88, 0x88, 0x88, 0x84, 0x84, 0x86,
445
+
0x8a, 0x88, 0x8a, 0x7f, 0x7f, 0x84,
446
+
0x84, 0x83, 0x84, 0x88, 0x8a, 0x89,
447
+
0x9c, 0x9c, 0x8b, 0xc0, 0xd3, 0xa1,
448
+
0x00, 0x00, 0x00, },
449
+
{ MCS_AIDCTL, 0x02, 0x15 },
450
+
}, {
451
+
/* 105 nits */
452
+
{ MCS_GAMMACTL,
453
+
0x00, 0xb7, 0x00, 0xc0, 0x00, 0xba,
454
+
0x87, 0x87, 0x88, 0x85, 0x85, 0x87,
455
+
0x89, 0x88, 0x89, 0x7f, 0x7f, 0x83,
456
+
0x81, 0x80, 0x82, 0x88, 0x8a, 0x89,
457
+
0x9c, 0x9c, 0x8c, 0xb2, 0xc2, 0x9a,
458
+
0x00, 0x00, 0x00, },
459
+
{ MCS_AIDCTL, 0x02, 0x15 },
460
+
}, {
461
+
/* 111 nits */
462
+
{ MCS_GAMMACTL,
463
+
0x00, 0xbb, 0x00, 0xc3, 0x00, 0xbe,
464
+
0x87, 0x87, 0x88, 0x85, 0x85, 0x88,
465
+
0x88, 0x87, 0x89, 0x80, 0x80, 0x84,
466
+
0x81, 0x81, 0x82, 0x85, 0x86, 0x87,
467
+
0x9c, 0x9c, 0x8b, 0xb2, 0xc2, 0x9a,
468
+
0x00, 0x00, 0x00, },
469
+
{ MCS_AIDCTL, 0x02, 0x15 },
470
+
}, {
471
+
/* 119 nits */
472
+
{ MCS_GAMMACTL,
473
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc4,
474
+
0x87, 0x87, 0x88, 0x82, 0x84, 0x86,
475
+
0x87, 0x85, 0x87, 0x82, 0x81, 0x84,
476
+
0x83, 0x82, 0x83, 0x80, 0x81, 0x84,
477
+
0x9c, 0x9c, 0x8c, 0xb2, 0xc2, 0x9a,
478
+
0x00, 0x00, 0x00, },
479
+
{ MCS_AIDCTL, 0x02, 0x14 },
480
+
}, {
481
+
/* 126 nits */
482
+
{ MCS_GAMMACTL,
483
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc4,
484
+
0x87, 0x87, 0x88, 0x82, 0x84, 0x86,
485
+
0x87, 0x85, 0x87, 0x82, 0x81, 0x84,
486
+
0x83, 0x82, 0x83, 0x80, 0x81, 0x84,
487
+
0x9c, 0x9c, 0x8d, 0xb2, 0xc2, 0x9a,
488
+
0x00, 0x00, 0x00, },
489
+
{ MCS_AIDCTL, 0x01, 0xde },
490
+
}, {
491
+
/* 134 nits */
492
+
{ MCS_GAMMACTL,
493
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc4,
494
+
0x87, 0x87, 0x88, 0x82, 0x84, 0x86,
495
+
0x87, 0x85, 0x87, 0x82, 0x81, 0x84,
496
+
0x83, 0x82, 0x83, 0x80, 0x81, 0x84,
497
+
0x9c, 0x9c, 0x8d, 0xa4, 0xb0, 0x92,
498
+
0x00, 0x00, 0x00, },
499
+
{ MCS_AIDCTL, 0x01, 0x94 },
500
+
}, {
501
+
/* 143 nits */
502
+
{ MCS_GAMMACTL,
503
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc3,
504
+
0x87, 0x87, 0x88, 0x82, 0x84, 0x86,
505
+
0x87, 0x85, 0x87, 0x82, 0x81, 0x85,
506
+
0x83, 0x82, 0x83, 0x80, 0x81, 0x84,
507
+
0x92, 0x92, 0x89, 0xab, 0xb6, 0x96,
508
+
0x00, 0x00, 0x00, },
509
+
{ MCS_AIDCTL, 0x01, 0x46 },
510
+
}, {
511
+
/* 152 nits */
512
+
{ MCS_GAMMACTL,
513
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc3,
514
+
0x87, 0x87, 0x88, 0x83, 0x84, 0x86,
515
+
0x87, 0x85, 0x87, 0x81, 0x81, 0x85,
516
+
0x84, 0x82, 0x83, 0x80, 0x81, 0x83,
517
+
0x92, 0x92, 0x8b, 0xab, 0xb6, 0x96,
518
+
0x00, 0x00, 0x00, },
519
+
{ MCS_AIDCTL, 0x00, 0xfa },
520
+
}, {
521
+
/* 162 nits */
522
+
{ MCS_GAMMACTL,
523
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc3,
524
+
0x87, 0x87, 0x88, 0x83, 0x84, 0x86,
525
+
0x87, 0x85, 0x87, 0x81, 0x81, 0x84,
526
+
0x84, 0x82, 0x84, 0x80, 0x81, 0x83,
527
+
0x92, 0x92, 0x8b, 0x9d, 0xa4, 0x8e,
528
+
0x00, 0x00, 0x00, },
529
+
{ MCS_AIDCTL, 0x00, 0xac },
530
+
}, {
531
+
/* 172 nits */
532
+
{ MCS_GAMMACTL,
533
+
0x00, 0xc0, 0x00, 0xc8, 0x00, 0xc3,
534
+
0x87, 0x87, 0x88, 0x83, 0x84, 0x86,
535
+
0x87, 0x85, 0x87, 0x81, 0x81, 0x84,
536
+
0x84, 0x82, 0x83, 0x80, 0x81, 0x84,
537
+
0x93, 0x92, 0x8c, 0x9d, 0xa4, 0x8e,
538
+
0x00, 0x00, 0x00, },
539
+
{ MCS_AIDCTL, 0x00, 0x57 },
540
+
}, {
541
+
/* 183 nits */
542
+
{ MCS_GAMMACTL,
543
+
0x00, 0xc2, 0x00, 0xca, 0x00, 0xc5,
544
+
0x86, 0x86, 0x87, 0x85, 0x84, 0x87,
545
+
0x87, 0x86, 0x88, 0x7e, 0x80, 0x83,
546
+
0x84, 0x82, 0x83, 0x80, 0x81, 0x83,
547
+
0x93, 0x92, 0x8c, 0x9d, 0xa4, 0x8e,
548
+
0x00, 0x00, 0x00, },
549
+
{ MCS_AIDCTL, 0x00, 0x10 },
550
+
}, {
551
+
/* 195 nits */
552
+
{ MCS_GAMMACTL,
553
+
0x00, 0xc7, 0x00, 0xce, 0x00, 0xc9,
554
+
0x86, 0x87, 0x86, 0x83, 0x83, 0x85,
555
+
0x85, 0x84, 0x86, 0x82, 0x82, 0x85,
556
+
0x80, 0x80, 0x81, 0x81, 0x81, 0x84,
557
+
0x93, 0x92, 0x8c, 0x9d, 0xa4, 0x8e,
558
+
0x00, 0x00, 0x00, },
559
+
{ MCS_AIDCTL, 0x00, 0x10 },
560
+
}, {
561
+
/* 207 nits */
562
+
{ MCS_GAMMACTL,
563
+
0x00, 0xcc, 0x00, 0xd2, 0x00, 0xce,
564
+
0x86, 0x86, 0x87, 0x81, 0x83, 0x84,
565
+
0x84, 0x82, 0x84, 0x83, 0x83, 0x85,
566
+
0x81, 0x81, 0x82, 0x7c, 0x7d, 0x81,
567
+
0x93, 0x92, 0x8c, 0x9d, 0xa4, 0x8e,
568
+
0x00, 0x00, 0x00, },
569
+
{ MCS_AIDCTL, 0x00, 0x10 },
570
+
}, {
571
+
/* 220 nits */
572
+
{ MCS_GAMMACTL,
573
+
0x00, 0xd1, 0x00, 0xd6, 0x00, 0xd3,
574
+
0x86, 0x86, 0x86, 0x81, 0x83, 0x84,
575
+
0x84, 0x82, 0x84, 0x80, 0x80, 0x83,
576
+
0x81, 0x81, 0x82, 0x7c, 0x7d, 0x81,
577
+
0x93, 0x92, 0x8c, 0x9d, 0xa4, 0x8e,
578
+
0x00, 0x00, 0x00, },
579
+
{ MCS_AIDCTL, 0x00, 0x10 },
580
+
}, {
581
+
/* 234 nits */
582
+
{ MCS_GAMMACTL,
583
+
0x00, 0xd6, 0x00, 0xdb, 0x00, 0xd8,
584
+
0x85, 0x85, 0x85, 0x81, 0x83, 0x84,
585
+
0x83, 0x82, 0x83, 0x80, 0x80, 0x82,
586
+
0x84, 0x82, 0x83, 0x79, 0x79, 0x7e,
587
+
0x93, 0x92, 0x8d, 0x9d, 0xa4, 0x8e,
588
+
0x00, 0x00, 0x00, },
589
+
{ MCS_AIDCTL, 0x00, 0x10 },
590
+
}, {
591
+
/* 249 nits */
592
+
{ MCS_GAMMACTL,
593
+
0x00, 0xdc, 0x00, 0xe0, 0x00, 0xdd,
594
+
0x84, 0x84, 0x84, 0x81, 0x82, 0x83,
595
+
0x84, 0x82, 0x84, 0x7f, 0x7f, 0x82,
596
+
0x81, 0x80, 0x81, 0x80, 0x81, 0x82,
597
+
0x8c, 0x8c, 0x86, 0x9d, 0xa4, 0x8e,
598
+
0x00, 0x00, 0x00, },
599
+
{ MCS_AIDCTL, 0x00, 0x10 },
600
+
}, {
601
+
/* 265 nits */
602
+
{ MCS_GAMMACTL,
603
+
0x00, 0xe2, 0x00, 0xe5, 0x00, 0xe3,
604
+
0x83, 0x83, 0x83, 0x81, 0x82, 0x83,
605
+
0x82, 0x82, 0x83, 0x82, 0x81, 0x83,
606
+
0x7f, 0x7e, 0x80, 0x7c, 0x7d, 0x80,
607
+
0x8c, 0x8c, 0x86, 0x8e, 0x92, 0x87,
608
+
0x00, 0x00, 0x00, },
609
+
{ MCS_AIDCTL, 0x00, 0x10 },
610
+
}, {
611
+
/* 282 nits */
612
+
{ MCS_GAMMACTL,
613
+
0x00, 0xe8, 0x00, 0xea, 0x00, 0xe9,
614
+
0x83, 0x83, 0x83, 0x80, 0x82, 0x82,
615
+
0x81, 0x82, 0x82, 0x82, 0x81, 0x82,
616
+
0x81, 0x80, 0x81, 0x80, 0x80, 0x81,
617
+
0x85, 0x85, 0x83, 0x8e, 0x92, 0x87,
618
+
0x00, 0x00, 0x00, },
619
+
{ MCS_AIDCTL, 0x00, 0x10 },
620
+
}, {
621
+
/* 300 nits */
622
+
{ MCS_GAMMACTL,
623
+
0x00, 0xed, 0x00, 0xef, 0x00, 0xed,
624
+
0x81, 0x82, 0x81, 0x81, 0x81, 0x82,
625
+
0x82, 0x82, 0x83, 0x80, 0x80, 0x81,
626
+
0x81, 0x81, 0x82, 0x83, 0x83, 0x83,
627
+
0x80, 0x80, 0x7f, 0x8e, 0x92, 0x87,
628
+
0x00, 0x00, 0x00, },
629
+
{ MCS_AIDCTL, 0x00, 0x10 },
630
+
}, {
631
+
/* 316 nits */
632
+
{ MCS_GAMMACTL,
633
+
0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf3,
634
+
0x80, 0x81, 0x80, 0x81, 0x81, 0x81,
635
+
0x82, 0x82, 0x82, 0x81, 0x80, 0x81,
636
+
0x82, 0x82, 0x83, 0x80, 0x80, 0x80,
637
+
0x80, 0x80, 0x7f, 0x80, 0x80, 0x80,
638
+
0x00, 0x00, 0x00, },
639
+
{ MCS_AIDCTL, 0x00, 0x10 },
640
+
}, {
641
+
/* 333 nits */
642
+
{ MCS_GAMMACTL,
643
+
0x00, 0xf8, 0x00, 0xf8, 0x00, 0xf8,
644
+
0x80, 0x81, 0x80, 0x81, 0x80, 0x81,
645
+
0x81, 0x82, 0x82, 0x81, 0x80, 0x81,
646
+
0x83, 0x83, 0x83, 0x7e, 0x7d, 0x7e,
647
+
0x80, 0x80, 0x7f, 0x80, 0x80, 0x80,
648
+
0x00, 0x00, 0x00, },
649
+
{ MCS_AIDCTL, 0x00, 0x10 },
650
+
}, {
651
+
/* 360 nits */
652
+
{ MCS_GAMMACTL,
653
+
0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
654
+
0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
655
+
0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
656
+
0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
657
+
0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
658
+
0x00, 0x00, 0x00, },
659
+
{ MCS_AIDCTL, 0x00, 0x10 },
660
+
}, {
661
+
/* 378 nits */
662
+
{ MCS_GAMMACTL,
663
+
0x01, 0x04, 0x01, 0x03, 0x01, 0x04,
664
+
0x7f, 0x7f, 0x80, 0x7f, 0x7f, 0x7f,
665
+
0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
666
+
0x80, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
667
+
0x80, 0x80, 0x7f, 0x7f, 0x7f, 0x7f,
668
+
0x00, 0x00, 0x00, },
669
+
{ MCS_AIDCTL, 0x00, 0x10 },
670
+
}, {
671
+
/* 395 nits */
672
+
{ MCS_GAMMACTL,
673
+
0x01, 0x09, 0x01, 0x07, 0x01, 0x08,
674
+
0x7e, 0x7f, 0x80, 0x7f, 0x7f, 0x7f,
675
+
0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
676
+
0x80, 0x7f, 0x7f, 0x7e, 0x7e, 0x7e,
677
+
0x80, 0x80, 0x7f, 0x7e, 0x7e, 0x7f,
678
+
0x00, 0x00, 0x00, },
679
+
{ MCS_AIDCTL, 0x00, 0x10 },
680
+
}, {
681
+
/* 413 nits */
682
+
{ MCS_GAMMACTL,
683
+
0x01, 0x0e, 0x01, 0x0b, 0x01, 0x0c,
684
+
0x7e, 0x7f, 0x80, 0x7e, 0x7e, 0x7e,
685
+
0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f,
686
+
0x80, 0x7f, 0x7f, 0x7d, 0x7d, 0x7d,
687
+
0x80, 0x80, 0x7f, 0x7d, 0x7e, 0x7e,
688
+
0x00, 0x00, 0x00, },
689
+
{ MCS_AIDCTL, 0x00, 0x10 },
690
+
}, {
691
+
/* 430 nits */
692
+
{ MCS_GAMMACTL,
693
+
0x01, 0x13, 0x01, 0x0f, 0x01, 0x10,
694
+
0x7d, 0x7f, 0x80, 0x7e, 0x7e, 0x7e,
695
+
0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f,
696
+
0x80, 0x7f, 0x7f, 0x7d, 0x7d, 0x7d,
697
+
0x80, 0x80, 0x7f, 0x7c, 0x7d, 0x7e,
698
+
0x00, 0x00, 0x00, },
699
+
{ MCS_AIDCTL, 0x00, 0x10 },
700
+
}, {
701
+
/* 448 nits */
702
+
{ MCS_GAMMACTL,
703
+
0x01, 0x18, 0x01, 0x13, 0x01, 0x14,
704
+
0x7c, 0x7e, 0x80, 0x7e, 0x7e, 0x7e,
705
+
0x7e, 0x7e, 0x7d, 0x7e, 0x7f, 0x7e,
706
+
0x80, 0x7f, 0x7f, 0x7c, 0x7c, 0x7c,
707
+
0x80, 0x80, 0x7e, 0x7b, 0x7c, 0x7d,
708
+
0x00, 0x00, 0x00, },
709
+
{ MCS_AIDCTL, 0x00, 0x10 },
710
+
}, {
711
+
/* 465 nits */
712
+
{ MCS_GAMMACTL,
713
+
0x01, 0x1d, 0x01, 0x17, 0x01, 0x18,
714
+
0x7c, 0x7e, 0x80, 0x7d, 0x7d, 0x7d,
715
+
0x7d, 0x7d, 0x7d, 0x7e, 0x7f, 0x7e,
716
+
0x80, 0x7f, 0x7f, 0x7b, 0x7b, 0x7b,
717
+
0x80, 0x80, 0x7e, 0x7a, 0x7c, 0x7d,
718
+
0x00, 0x00, 0x00, },
719
+
{ MCS_AIDCTL, 0x00, 0x10 },
720
+
}, {
721
+
/* 483 nits */
722
+
{ MCS_GAMMACTL,
723
+
0x01, 0x22, 0x01, 0x1b, 0x01, 0x1c,
724
+
0x7b, 0x7e, 0x80, 0x7d, 0x7d, 0x7d,
725
+
0x7d, 0x7d, 0x7c, 0x7e, 0x7f, 0x7e,
726
+
0x80, 0x7f, 0x7f, 0x7a, 0x7a, 0x7a,
727
+
0x80, 0x80, 0x7e, 0x79, 0x7b, 0x7c,
728
+
0x00, 0x00, 0x00, },
729
+
{ MCS_AIDCTL, 0x00, 0x10 },
730
+
}, {
731
+
/* 500 nits */
732
+
{ MCS_GAMMACTL,
733
+
0x01, 0x27, 0x01, 0x1f, 0x01, 0x20,
734
+
0x7b, 0x7e, 0x80, 0x7d, 0x7d, 0x7d,
735
+
0x7d, 0x7d, 0x7c, 0x7e, 0x7f, 0x7e,
736
+
0x80, 0x7f, 0x7f, 0x7a, 0x7a, 0x7a,
737
+
0x81, 0x80, 0x7e, 0x79, 0x7b, 0x7c,
738
+
0x00, 0x00, 0x00, },
739
+
{ MCS_AIDCTL, 0x00, 0x10 },
740
+
},
741
+
};
742
+
743
+
struct s6e8aa5x01_ams561ra01_ctx {
744
+
struct drm_panel panel;
745
+
struct mipi_dsi_device *dsi;
746
+
struct backlight_device *bl;
747
+
struct gpio_desc *reset_gpio;
748
+
struct regulator_bulk_data *supplies;
749
+
u32 nr_supplies;
750
+
};
751
+
752
+
static const struct regulator_bulk_data s6e8aa5x01_ams561ra01_supplies[] = {
753
+
{ .supply = "vdd" },
754
+
{ .supply = "vci" },
755
+
};
756
+
757
+
static inline struct s6e8aa5x01_ams561ra01_ctx *to_ctx(struct drm_panel *panel)
758
+
{
759
+
return container_of(panel, struct s6e8aa5x01_ams561ra01_ctx, panel);
760
+
}
761
+
762
+
static int s6e8aa5x01_ams561ra01_update_status(struct backlight_device *bl)
763
+
{
764
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = bl_get_data(bl);
765
+
struct mipi_dsi_multi_context dsi = { .dsi = ctx->dsi };
766
+
u16 lvl = backlight_get_brightness(bl);
767
+
768
+
if (!ctx->panel.enabled)
769
+
return 0;
770
+
771
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_ACCESSPROT, 0x5a, 0x5a);
772
+
773
+
mipi_dsi_dcs_write_buffer_multi(&dsi,
774
+
s6e8aa5x01_ams561ra01_cmds[lvl].gamma,
775
+
GAMMA_CMD_LEN);
776
+
mipi_dsi_dcs_write_buffer_multi(&dsi,
777
+
s6e8aa5x01_ams561ra01_cmds[lvl].aid,
778
+
AID_CMD_LEN);
779
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_GAMMAUPD, 0x03);
780
+
781
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_ACCESSPROT, 0xa5, 0xa5);
782
+
783
+
return dsi.accum_err;
784
+
}
785
+
786
+
static int s6e8aa5x01_ams561ra01_prepare(struct drm_panel *panel)
787
+
{
788
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = to_ctx(panel);
789
+
struct device *dev = &ctx->dsi->dev;
790
+
int ret;
791
+
792
+
ret = regulator_bulk_enable(ctx->nr_supplies, ctx->supplies);
793
+
if (ret < 0) {
794
+
dev_err(dev, "failed to enable regulators: %d\n", ret);
795
+
return ret;
796
+
}
797
+
798
+
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
799
+
usleep_range(5000, 6000);
800
+
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
801
+
usleep_range(5000, 6000);
802
+
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
803
+
usleep_range(10000, 11000);
804
+
805
+
return 0;
806
+
}
807
+
808
+
static int s6e8aa5x01_ams561ra01_unprepare(struct drm_panel *panel)
809
+
{
810
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = to_ctx(panel);
811
+
812
+
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
813
+
usleep_range(5000, 6000);
814
+
815
+
regulator_bulk_disable(ctx->nr_supplies, ctx->supplies);
816
+
817
+
return 0;
818
+
}
819
+
820
+
static int s6e8aa5x01_ams561ra01_enable(struct drm_panel *panel)
821
+
{
822
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = to_ctx(panel);
823
+
struct mipi_dsi_multi_context dsi = { .dsi = ctx->dsi };
824
+
825
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi);
826
+
mipi_dsi_msleep(&dsi, 100);
827
+
828
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_ACCESSPROT, 0x5a, 0x5a);
829
+
830
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_PENTILE, 0xd8, 0xd8, 0x00);
831
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_PCD, 0x5c);
832
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_ERRFLAG, 0xed, 0xc7, 0x23, 0x67);
833
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_DISPCTL, 0x0c, 0x0c, 0xb9, 0x01);
834
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_LTPSCTL,
835
+
0x00, 0x45, 0x10, 0x10, 0x08, 0x32, 0x54, 0x00,
836
+
0x00, 0x00, 0x00, 0x07, 0x06, 0x00, 0x00, 0x00,
837
+
0x00, 0x00, 0x48, 0x5e, 0x00, 0x00, 0x00, 0x00,
838
+
0x00, 0x03, 0x00, 0x00, 0x00, 0xad, 0x00, 0x00,
839
+
0x08, 0x05, 0x2a, 0x54, 0x03, 0xcc, 0x00, 0xff,
840
+
0xfb, 0x03, 0x0d, 0x00, 0x11, 0x0f, 0x02, 0x03,
841
+
0x0b, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
842
+
0x13, 0x13, 0x13, 0x13, 0x00, 0x02, 0x03, 0x0b,
843
+
0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
844
+
0x13, 0x13);
845
+
846
+
mipi_dsi_dcs_write_seq_multi(&dsi, MCS_ACCESSPROT, 0xa5, 0xa5);
847
+
848
+
mipi_dsi_dcs_set_display_on_multi(&dsi);
849
+
850
+
return dsi.accum_err;
851
+
}
852
+
853
+
static int s6e8aa5x01_ams561ra01_disable(struct drm_panel *panel)
854
+
{
855
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = to_ctx(panel);
856
+
struct mipi_dsi_multi_context dsi = { .dsi = ctx->dsi };
857
+
858
+
mipi_dsi_dcs_set_display_off_multi(&dsi);
859
+
mipi_dsi_msleep(&dsi, 100);
860
+
861
+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi);
862
+
mipi_dsi_msleep(&dsi, 150);
863
+
864
+
return dsi.accum_err;
865
+
}
866
+
867
+
static const struct drm_display_mode s6e8aa5x01_ams561ra01_mode = {
868
+
.clock = (720 + 62 + 2 + 26) * (1480 + 12 + 2 + 10) * 60 / 1000,
869
+
.hdisplay = 720,
870
+
.hsync_start = 720 + 62,
871
+
.hsync_end = 720 + 62 + 2,
872
+
.htotal = 720 + 62 + 2 + 26,
873
+
.vdisplay = 1480,
874
+
.vsync_start = 1480 + 12,
875
+
.vsync_end = 1480 + 12 + 2,
876
+
.vtotal = 1480 + 12 + 2 + 10,
877
+
.width_mm = 62,
878
+
.height_mm = 128,
879
+
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
880
+
};
881
+
882
+
static int s6e8aa5x01_ams561ra01_get_modes(struct drm_panel *panel,
883
+
struct drm_connector *connector)
884
+
{
885
+
return drm_connector_helper_get_modes_fixed(connector,
886
+
&s6e8aa5x01_ams561ra01_mode);
887
+
}
888
+
889
+
static const struct backlight_ops s6e8aa5x01_ams561ra01_bl_ops = {
890
+
.update_status = s6e8aa5x01_ams561ra01_update_status,
891
+
};
892
+
893
+
static const struct drm_panel_funcs s6e8aa5x01_ams561ra01_panel_funcs = {
894
+
.prepare = s6e8aa5x01_ams561ra01_prepare,
895
+
.unprepare = s6e8aa5x01_ams561ra01_unprepare,
896
+
.enable = s6e8aa5x01_ams561ra01_enable,
897
+
.disable = s6e8aa5x01_ams561ra01_disable,
898
+
.get_modes = s6e8aa5x01_ams561ra01_get_modes,
899
+
};
900
+
901
+
static int s6e8aa5x01_ams561ra01_probe(struct mipi_dsi_device *dsi)
902
+
{
903
+
struct device *dev = &dsi->dev;
904
+
struct s6e8aa5x01_ams561ra01_ctx *ctx;
905
+
int ret;
906
+
907
+
ctx = devm_drm_panel_alloc(dev, struct s6e8aa5x01_ams561ra01_ctx, panel,
908
+
&s6e8aa5x01_ams561ra01_panel_funcs,
909
+
DRM_MODE_CONNECTOR_DSI);
910
+
if (IS_ERR(ctx))
911
+
return PTR_ERR(ctx);
912
+
913
+
ctx->dsi = dsi;
914
+
mipi_dsi_set_drvdata(dsi, ctx);
915
+
916
+
ctx->nr_supplies = ARRAY_SIZE(s6e8aa5x01_ams561ra01_supplies);
917
+
ret = devm_regulator_bulk_get_const(dev, ctx->nr_supplies,
918
+
s6e8aa5x01_ams561ra01_supplies,
919
+
&ctx->supplies);
920
+
if (ret < 0)
921
+
return dev_err_probe(dev, ret, "failed to get regulators\n");
922
+
923
+
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
924
+
if (IS_ERR(ctx->reset_gpio))
925
+
return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
926
+
"failed to get reset-gpios\n");
927
+
928
+
ctx->bl = devm_backlight_device_register(dev, dev_name(dev), dev, ctx,
929
+
&s6e8aa5x01_ams561ra01_bl_ops,
930
+
NULL);
931
+
if (IS_ERR(ctx->bl))
932
+
return dev_err_probe(dev, PTR_ERR(ctx->bl),
933
+
"failed to register backlight device\n");
934
+
935
+
ctx->bl->props.type = BACKLIGHT_PLATFORM;
936
+
ctx->bl->props.brightness = ARRAY_SIZE(s6e8aa5x01_ams561ra01_cmds) - 1;
937
+
ctx->bl->props.max_brightness = ctx->bl->props.brightness;
938
+
939
+
dsi->lanes = 4;
940
+
dsi->format = MIPI_DSI_FMT_RGB888;
941
+
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
942
+
MIPI_DSI_MODE_VIDEO_NO_HFP;
943
+
944
+
ctx->panel.prepare_prev_first = true;
945
+
drm_panel_add(&ctx->panel);
946
+
947
+
ret = devm_mipi_dsi_attach(dev, dsi);
948
+
if (ret < 0) {
949
+
drm_panel_remove(&ctx->panel);
950
+
return dev_err_probe(dev, ret, "failed to attach to DSI host\n");
951
+
}
952
+
953
+
return 0;
954
+
}
955
+
956
+
static void s6e8aa5x01_ams561ra01_remove(struct mipi_dsi_device *dsi)
957
+
{
958
+
struct s6e8aa5x01_ams561ra01_ctx *ctx = mipi_dsi_get_drvdata(dsi);
959
+
960
+
drm_panel_remove(&ctx->panel);
961
+
}
962
+
963
+
static const struct of_device_id s6e8aa5x01_ams561ra01_of_device_id[] = {
964
+
{ .compatible = "samsung,s6e8aa5x01-ams561ra01" },
965
+
{ }
966
+
};
967
+
MODULE_DEVICE_TABLE(of, s6e8aa5x01_ams561ra01_of_device_id);
968
+
969
+
static struct mipi_dsi_driver s6e8aa5x01_ams561ra01_dsi_driver = {
970
+
.probe = s6e8aa5x01_ams561ra01_probe,
971
+
.remove = s6e8aa5x01_ams561ra01_remove,
972
+
.driver = {
973
+
.name = "panel-samsung-s6e8aa5x01-ams561ra01",
974
+
.of_match_table = s6e8aa5x01_ams561ra01_of_device_id,
975
+
},
976
+
};
977
+
module_mipi_dsi_driver(s6e8aa5x01_ams561ra01_dsi_driver);
978
+
979
+
MODULE_AUTHOR("Kaustabh Chakraborty <kauschluss@disroot.org>");
980
+
MODULE_DESCRIPTION("Samsung AMS561RA01 Panel with S6E8AA5X01 Controller");
981
+
MODULE_LICENSE("GPL");
+26
drivers/gpu/drm/panel/panel-simple.c
+26
drivers/gpu/drm/panel/panel-simple.c
···
3716
3716
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3717
3717
};
3718
3718
3719
+
static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = {
3720
+
.clock = 33300,
3721
+
.hdisplay = 800,
3722
+
.hsync_start = 800 + 210,
3723
+
.hsync_end = 800 + 210 + 20,
3724
+
.htotal = 800 + 210 + 20 + 26,
3725
+
.vdisplay = 480,
3726
+
.vsync_start = 480 + 22,
3727
+
.vsync_end = 480 + 22 + 10,
3728
+
.vtotal = 480 + 22 + 10 + 13,
3729
+
};
3730
+
3731
+
static const struct panel_desc olimex_lcd_olinuxino_5cts = {
3732
+
.modes = &olimex_lcd_olinuxino_5cts_mode,
3733
+
.num_modes = 1,
3734
+
.size = {
3735
+
.width = 154,
3736
+
.height = 86,
3737
+
},
3738
+
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3739
+
};
3740
+
3741
+
3719
3742
static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3720
3743
.pixelclock = { 30000000, 30000000, 50000000 },
3721
3744
.hactive = { 800, 800, 800 },
···
5301
5278
}, {
5302
5279
.compatible = "olimex,lcd-olinuxino-43-ts",
5303
5280
.data = &olimex_lcd_olinuxino_43ts,
5281
+
}, {
5282
+
.compatible = "olimex,lcd-olinuxino-5-cts",
5283
+
.data = &olimex_lcd_olinuxino_5cts,
5304
5284
}, {
5305
5285
.compatible = "ontat,kd50g21-40nt-a1",
5306
5286
.data = &ontat_kd50g21_40nt_a1,
+1
-1
drivers/gpu/drm/panel/panel-sitronix-st7703.c
+1
-1
drivers/gpu/drm/panel/panel-sitronix-st7703.c
+2
drivers/gpu/drm/panel/panel-summit.c
+2
drivers/gpu/drm/panel/panel-summit.c
+9
-16
drivers/gpu/drm/panthor/panthor_drv.c
+9
-16
drivers/gpu/drm/panthor/panthor_drv.c
···
1103
1103
1104
1104
ret = group_priority_permit(file, args->priority);
1105
1105
if (ret)
1106
-
return ret;
1106
+
goto out;
1107
1107
1108
1108
ret = panthor_group_create(pfile, args, queue_args);
1109
-
if (ret >= 0) {
1110
-
args->group_handle = ret;
1111
-
ret = 0;
1112
-
}
1109
+
if (ret < 0)
1110
+
goto out;
1111
+
args->group_handle = ret;
1112
+
ret = 0;
1113
1113
1114
+
out:
1114
1115
kvfree(queue_args);
1115
1116
return ret;
1116
1117
}
···
1401
1400
struct panthor_file *pfile;
1402
1401
int ret;
1403
1402
1404
-
if (!try_module_get(THIS_MODULE))
1405
-
return -EINVAL;
1406
-
1407
1403
pfile = kzalloc(sizeof(*pfile), GFP_KERNEL);
1408
-
if (!pfile) {
1409
-
ret = -ENOMEM;
1410
-
goto err_put_mod;
1411
-
}
1404
+
if (!pfile)
1405
+
return -ENOMEM;
1412
1406
1413
1407
pfile->ptdev = ptdev;
1414
1408
pfile->user_mmio.offset = DRM_PANTHOR_USER_MMIO_OFFSET;
···
1435
1439
1436
1440
err_free_file:
1437
1441
kfree(pfile);
1438
-
1439
-
err_put_mod:
1440
-
module_put(THIS_MODULE);
1441
1442
return ret;
1442
1443
}
1443
1444
···
1447
1454
panthor_vm_pool_destroy(pfile);
1448
1455
1449
1456
kfree(pfile);
1450
-
module_put(THIS_MODULE);
1451
1457
}
1452
1458
1453
1459
static const struct drm_ioctl_desc panthor_drm_driver_ioctls[] = {
···
1547
1555
}
1548
1556
1549
1557
static const struct file_operations panthor_drm_driver_fops = {
1558
+
.owner = THIS_MODULE,
1550
1559
.open = drm_open,
1551
1560
.release = drm_release,
1552
1561
.unlocked_ioctl = drm_ioctl,
+38
-5
drivers/gpu/drm/panthor/panthor_sched.c
+38
-5
drivers/gpu/drm/panthor/panthor_sched.c
···
641
641
size_t kbo_sizes;
642
642
} fdinfo;
643
643
644
+
/** @task_info: Info of current->group_leader that created the group. */
645
+
struct {
646
+
/** @task_info.pid: pid of current->group_leader */
647
+
pid_t pid;
648
+
649
+
/** @task_info.comm: comm of current->group_leader */
650
+
char comm[TASK_COMM_LEN];
651
+
} task_info;
652
+
644
653
/** @state: Group state. */
645
654
enum panthor_group_state state;
646
655
···
1364
1355
fatal = cs_iface->output->fatal;
1365
1356
info = cs_iface->output->fatal_info;
1366
1357
1367
-
if (group)
1358
+
if (group) {
1359
+
drm_warn(&ptdev->base, "CS_FATAL: pid=%d, comm=%s\n",
1360
+
group->task_info.pid, group->task_info.comm);
1361
+
1368
1362
group->fatal_queues |= BIT(cs_id);
1363
+
}
1369
1364
1370
1365
if (CS_EXCEPTION_TYPE(fatal) == DRM_PANTHOR_EXCEPTION_CS_UNRECOVERABLE) {
1371
1366
/* If this exception is unrecoverable, queue a reset, and make
···
1427
1414
dma_fence_set_error(job->done_fence, -EINVAL);
1428
1415
}
1429
1416
spin_unlock(&queue->fence_ctx.lock);
1417
+
}
1418
+
1419
+
if (group) {
1420
+
drm_warn(&ptdev->base, "CS_FAULT: pid=%d, comm=%s\n",
1421
+
group->task_info.pid, group->task_info.comm);
1430
1422
}
1431
1423
1432
1424
drm_warn(&ptdev->base,
···
1650
1632
1651
1633
lockdep_assert_held(&sched->lock);
1652
1634
1653
-
drm_warn(&ptdev->base, "CSG slot %d progress timeout\n", csg_id);
1654
-
1655
1635
group = csg_slot->group;
1656
-
if (!drm_WARN_ON(&ptdev->base, !group))
1636
+
if (!drm_WARN_ON(&ptdev->base, !group)) {
1637
+
drm_warn(&ptdev->base, "CSG_PROGRESS_TIMER_EVENT: pid=%d, comm=%s\n",
1638
+
group->task_info.pid, group->task_info.comm);
1639
+
1657
1640
group->timedout = true;
1641
+
}
1642
+
1643
+
drm_warn(&ptdev->base, "CSG slot %d progress timeout\n", csg_id);
1658
1644
1659
1645
sched_queue_delayed_work(sched, tick, 0);
1660
1646
}
···
3240
3218
struct panthor_scheduler *sched = ptdev->scheduler;
3241
3219
struct panthor_queue *queue = group->queues[job->queue_idx];
3242
3220
3243
-
drm_warn(&ptdev->base, "job timeout\n");
3221
+
drm_warn(&ptdev->base, "job timeout: pid=%d, comm=%s, seqno=%llu\n",
3222
+
group->task_info.pid, group->task_info.comm, job->done_fence->seqno);
3244
3223
3245
3224
drm_WARN_ON(&ptdev->base, atomic_read(&sched->reset.in_progress));
3246
3225
···
3412
3389
return ERR_PTR(ret);
3413
3390
}
3414
3391
3392
+
static void group_init_task_info(struct panthor_group *group)
3393
+
{
3394
+
struct task_struct *task = current->group_leader;
3395
+
3396
+
group->task_info.pid = task->pid;
3397
+
get_task_comm(group->task_info.comm, task);
3398
+
}
3399
+
3415
3400
static void add_group_kbo_sizes(struct panthor_device *ptdev,
3416
3401
struct panthor_group *group)
3417
3402
{
···
3570
3539
3571
3540
add_group_kbo_sizes(group->ptdev, group);
3572
3541
spin_lock_init(&group->fdinfo.lock);
3542
+
3543
+
group_init_task_info(group);
3573
3544
3574
3545
return gid;
3575
3546
+4
-4
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+4
-4
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
···
913
913
* Power Management
914
914
*/
915
915
916
-
static int __maybe_unused rzg2l_mipi_pm_runtime_suspend(struct device *dev)
916
+
static int rzg2l_mipi_pm_runtime_suspend(struct device *dev)
917
917
{
918
918
struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
919
919
···
923
923
return 0;
924
924
}
925
925
926
-
static int __maybe_unused rzg2l_mipi_pm_runtime_resume(struct device *dev)
926
+
static int rzg2l_mipi_pm_runtime_resume(struct device *dev)
927
927
{
928
928
struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
929
929
int ret;
···
940
940
}
941
941
942
942
static const struct dev_pm_ops rzg2l_mipi_pm_ops = {
943
-
SET_RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
943
+
RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
944
944
};
945
945
946
946
/* -----------------------------------------------------------------------------
···
1072
1072
.remove = rzg2l_mipi_dsi_remove,
1073
1073
.driver = {
1074
1074
.name = "rzg2l-mipi-dsi",
1075
-
.pm = &rzg2l_mipi_pm_ops,
1075
+
.pm = pm_ptr(&rzg2l_mipi_pm_ops),
1076
1076
.of_match_table = rzg2l_mipi_dsi_of_table,
1077
1077
},
1078
1078
};
+21
-32
drivers/gpu/drm/scheduler/sched_main.c
+21
-32
drivers/gpu/drm/scheduler/sched_main.c
···
349
349
}
350
350
351
351
/**
352
-
* __drm_sched_run_free_queue - enqueue free-job work
353
-
* @sched: scheduler instance
354
-
*/
355
-
static void __drm_sched_run_free_queue(struct drm_gpu_scheduler *sched)
356
-
{
357
-
if (!READ_ONCE(sched->pause_submit))
358
-
queue_work(sched->submit_wq, &sched->work_free_job);
359
-
}
360
-
361
-
/**
362
-
* drm_sched_run_free_queue - enqueue free-job work if ready
352
+
* drm_sched_run_free_queue - enqueue free-job work
363
353
* @sched: scheduler instance
364
354
*/
365
355
static void drm_sched_run_free_queue(struct drm_gpu_scheduler *sched)
366
356
{
367
-
struct drm_sched_job *job;
368
-
369
-
job = list_first_entry_or_null(&sched->pending_list,
370
-
struct drm_sched_job, list);
371
-
if (job && dma_fence_is_signaled(&job->s_fence->finished))
372
-
__drm_sched_run_free_queue(sched);
373
-
}
374
-
375
-
static void drm_sched_run_free_queue_unlocked(struct drm_gpu_scheduler *sched)
376
-
{
377
-
spin_lock(&sched->job_list_lock);
378
-
drm_sched_run_free_queue(sched);
379
-
spin_unlock(&sched->job_list_lock);
357
+
if (!READ_ONCE(sched->pause_submit))
358
+
queue_work(sched->submit_wq, &sched->work_free_job);
380
359
}
381
360
382
361
/**
···
377
398
dma_fence_get(&s_fence->finished);
378
399
drm_sched_fence_finished(s_fence, result);
379
400
dma_fence_put(&s_fence->finished);
380
-
__drm_sched_run_free_queue(sched);
401
+
drm_sched_run_free_queue(sched);
381
402
}
382
403
383
404
/**
···
1113
1134
* drm_sched_get_finished_job - fetch the next finished job to be destroyed
1114
1135
*
1115
1136
* @sched: scheduler instance
1137
+
* @have_more: are there more finished jobs on the list
1138
+
*
1139
+
* Informs the caller through @have_more whether there are more finished jobs
1140
+
* besides the returned one.
1116
1141
*
1117
1142
* Returns the next finished job from the pending list (if there is one)
1118
1143
* ready for it to be destroyed.
1119
1144
*/
1120
1145
static struct drm_sched_job *
1121
-
drm_sched_get_finished_job(struct drm_gpu_scheduler *sched)
1146
+
drm_sched_get_finished_job(struct drm_gpu_scheduler *sched, bool *have_more)
1122
1147
{
1123
1148
struct drm_sched_job *job, *next;
1124
1149
···
1130
1147
1131
1148
job = list_first_entry_or_null(&sched->pending_list,
1132
1149
struct drm_sched_job, list);
1133
-
1134
1150
if (job && dma_fence_is_signaled(&job->s_fence->finished)) {
1135
1151
/* remove job from pending_list */
1136
1152
list_del_init(&job->list);
1137
1153
1138
1154
/* cancel this job's TO timer */
1139
1155
cancel_delayed_work(&sched->work_tdr);
1140
-
/* make the scheduled timestamp more accurate */
1156
+
1157
+
*have_more = false;
1141
1158
next = list_first_entry_or_null(&sched->pending_list,
1142
1159
typeof(*next), list);
1143
-
1144
1160
if (next) {
1161
+
/* make the scheduled timestamp more accurate */
1145
1162
if (test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT,
1146
1163
&next->s_fence->scheduled.flags))
1147
1164
next->s_fence->scheduled.timestamp =
1148
1165
dma_fence_timestamp(&job->s_fence->finished);
1166
+
1167
+
*have_more = dma_fence_is_signaled(&next->s_fence->finished);
1168
+
1149
1169
/* start TO timer for next job */
1150
1170
drm_sched_start_timeout(sched);
1151
1171
}
···
1207
1221
struct drm_gpu_scheduler *sched =
1208
1222
container_of(w, struct drm_gpu_scheduler, work_free_job);
1209
1223
struct drm_sched_job *job;
1224
+
bool have_more;
1210
1225
1211
-
job = drm_sched_get_finished_job(sched);
1212
-
if (job)
1226
+
job = drm_sched_get_finished_job(sched, &have_more);
1227
+
if (job) {
1213
1228
sched->ops->free_job(job);
1229
+
if (have_more)
1230
+
drm_sched_run_free_queue(sched);
1231
+
}
1214
1232
1215
-
drm_sched_run_free_queue_unlocked(sched);
1216
1233
drm_sched_run_job_queue(sched);
1217
1234
}
1218
1235
+1
-1
drivers/gpu/drm/scheduler/tests/mock_scheduler.c
+1
-1
drivers/gpu/drm/scheduler/tests/mock_scheduler.c
+4
-3
drivers/gpu/drm/scheduler/tests/sched_tests.h
+4
-3
drivers/gpu/drm/scheduler/tests/sched_tests.h
···
95
95
96
96
struct completion done;
97
97
98
-
#define DRM_MOCK_SCHED_JOB_DONE 0x1
99
-
#define DRM_MOCK_SCHED_JOB_TIMEDOUT 0x2
100
-
#define DRM_MOCK_SCHED_JOB_DONT_RESET 0x4
98
+
#define DRM_MOCK_SCHED_JOB_DONE 0x1
99
+
#define DRM_MOCK_SCHED_JOB_TIMEDOUT 0x2
100
+
#define DRM_MOCK_SCHED_JOB_DONT_RESET 0x4
101
+
#define DRM_MOCK_SCHED_JOB_RESET_SKIPPED 0x8
101
102
unsigned long flags;
102
103
103
104
struct list_head link;
+2
-2
drivers/gpu/drm/scheduler/tests/tests_basic.c
+2
-2
drivers/gpu/drm/scheduler/tests/tests_basic.c
···
317
317
KUNIT_ASSERT_FALSE(test, done);
318
318
319
319
KUNIT_ASSERT_EQ(test,
320
-
job->flags & DRM_MOCK_SCHED_JOB_DONT_RESET,
321
-
0);
320
+
job->flags & DRM_MOCK_SCHED_JOB_RESET_SKIPPED,
321
+
DRM_MOCK_SCHED_JOB_RESET_SKIPPED);
322
322
323
323
i = drm_mock_sched_advance(sched, 1);
324
324
KUNIT_ASSERT_EQ(test, i, 1);
+5
-10
drivers/gpu/drm/sysfb/simpledrm.c
+5
-10
drivers/gpu/drm/sysfb/simpledrm.c
···
4
4
#include <linux/clk.h>
5
5
#include <linux/of_clk.h>
6
6
#include <linux/minmax.h>
7
-
#include <linux/of_address.h>
7
+
#include <linux/of_reserved_mem.h>
8
8
#include <linux/platform_data/simplefb.h>
9
9
#include <linux/platform_device.h>
10
10
#include <linux/pm_domain.h>
···
179
179
static struct resource *
180
180
simplefb_get_memory_of(struct drm_device *dev, struct device_node *of_node)
181
181
{
182
-
struct device_node *np;
183
-
struct resource *res;
182
+
struct resource r, *res;
184
183
int err;
185
184
186
-
np = of_parse_phandle(of_node, "memory-region", 0);
187
-
if (!np)
185
+
err = of_reserved_mem_region_to_resource(of_node, 0, &r);
186
+
if (err)
188
187
return NULL;
189
188
190
-
res = devm_kzalloc(dev->dev, sizeof(*res), GFP_KERNEL);
189
+
res = devm_kmemdup(dev->dev, &r, sizeof(r), GFP_KERNEL);
191
190
if (!res)
192
191
return ERR_PTR(-ENOMEM);
193
-
194
-
err = of_address_to_resource(np, 0, res);
195
-
if (err)
196
-
return ERR_PTR(err);
197
192
198
193
if (of_property_present(of_node, "reg"))
199
194
drm_warn(dev, "preferring \"memory-region\" over \"reg\" property\n");
+5
-2
drivers/gpu/drm/tidss/tidss_crtc.c
+5
-2
drivers/gpu/drm/tidss/tidss_crtc.c
···
91
91
struct dispc_device *dispc = tidss->dispc;
92
92
struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
93
93
u32 hw_videoport = tcrtc->hw_videoport;
94
-
const struct drm_display_mode *mode;
94
+
struct drm_display_mode *mode;
95
95
enum drm_mode_status ok;
96
96
97
97
dev_dbg(ddev->dev, "%s\n", __func__);
···
107
107
__func__, mode->hdisplay, mode->vdisplay, mode->clock);
108
108
return -EINVAL;
109
109
}
110
+
111
+
if (drm_atomic_crtc_needs_modeset(crtc_state))
112
+
drm_mode_set_crtcinfo(mode, 0);
110
113
111
114
return dispc_vp_bus_check(dispc, hw_videoport, crtc_state);
112
115
}
···
228
225
tidss_runtime_get(tidss);
229
226
230
227
r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport,
231
-
mode->clock * 1000);
228
+
mode->crtc_clock * 1000);
232
229
if (r != 0)
233
230
return;
234
231
+8
-8
drivers/gpu/drm/tidss/tidss_dispc.c
+8
-8
drivers/gpu/drm/tidss/tidss_dispc.c
···
1215
1215
1216
1216
dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
1217
1217
1218
-
hfp = mode->hsync_start - mode->hdisplay;
1219
-
hsw = mode->hsync_end - mode->hsync_start;
1220
-
hbp = mode->htotal - mode->hsync_end;
1218
+
hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;
1219
+
hsw = mode->crtc_hsync_end - mode->crtc_hsync_start;
1220
+
hbp = mode->crtc_htotal - mode->crtc_hsync_end;
1221
1221
1222
-
vfp = mode->vsync_start - mode->vdisplay;
1223
-
vsw = mode->vsync_end - mode->vsync_start;
1224
-
vbp = mode->vtotal - mode->vsync_end;
1222
+
vfp = mode->crtc_vsync_start - mode->crtc_vdisplay;
1223
+
vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
1224
+
vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
1225
1225
1226
1226
dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
1227
1227
FLD_VAL(hsw - 1, 7, 0) |
···
1263
1263
FLD_VAL(ivs, 12, 12));
1264
1264
1265
1265
dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1266
-
FLD_VAL(mode->hdisplay - 1, 11, 0) |
1267
-
FLD_VAL(mode->vdisplay - 1, 27, 16));
1266
+
FLD_VAL(mode->crtc_hdisplay - 1, 11, 0) |
1267
+
FLD_VAL(mode->crtc_vdisplay - 1, 27, 16));
1268
1268
1269
1269
VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1270
1270
}
+3
drivers/gpu/drm/tidss/tidss_dispc.h
+3
drivers/gpu/drm/tidss/tidss_dispc.h
···
7
7
#ifndef __TIDSS_DISPC_H__
8
8
#define __TIDSS_DISPC_H__
9
9
10
+
#include <drm/drm_color_mgmt.h>
11
+
10
12
#include "tidss_drv.h"
11
13
12
14
struct dispc_device;
13
15
14
16
struct drm_crtc_state;
17
+
struct drm_plane_state;
15
18
16
19
enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
17
20
+9
drivers/gpu/drm/tidss/tidss_drv.c
+9
drivers/gpu/drm/tidss/tidss_drv.c
···
8
8
#include <linux/of.h>
9
9
#include <linux/module.h>
10
10
#include <linux/pm_runtime.h>
11
+
#include <linux/aperture.h>
11
12
12
13
#include <drm/clients/drm_client_setup.h>
13
14
#include <drm/drm_atomic.h>
···
193
192
goto err_irq_uninstall;
194
193
}
195
194
195
+
/* Remove possible early fb before setting up the fbdev */
196
+
ret = aperture_remove_all_conflicting_devices(tidss_driver.name);
197
+
if (ret)
198
+
goto err_drm_dev_unreg;
199
+
196
200
drm_client_setup(ddev, NULL);
197
201
198
202
dev_dbg(dev, "%s done\n", __func__);
199
203
200
204
return 0;
205
+
206
+
err_drm_dev_unreg:
207
+
drm_dev_unregister(ddev);
201
208
202
209
err_irq_uninstall:
203
210
tidss_irq_uninstall(ddev);
+2
drivers/gpu/drm/tidss/tidss_drv.h
+2
drivers/gpu/drm/tidss/tidss_drv.h
-1
drivers/gpu/drm/tidss/tidss_oldi.c
-1
drivers/gpu/drm/tidss/tidss_oldi.c
+2
drivers/gpu/drm/tidss/tidss_plane.h
+2
drivers/gpu/drm/tidss/tidss_plane.h
+2
drivers/gpu/drm/tidss/tidss_scale_coefs.h
+2
drivers/gpu/drm/tidss/tidss_scale_coefs.h
+7
-9
drivers/gpu/drm/tiny/repaper.c
+7
-9
drivers/gpu/drm/tiny/repaper.c
···
510
510
epd->factored_stage_time = epd->stage_time * factor10x / 10;
511
511
}
512
512
513
-
static int repaper_fb_dirty(struct drm_framebuffer *fb,
513
+
static int repaper_fb_dirty(struct drm_framebuffer *fb, const struct iosys_map *vmap,
514
514
struct drm_format_conv_state *fmtcnv_state)
515
515
{
516
-
struct drm_gem_dma_object *dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
517
516
struct repaper_epd *epd = drm_to_epd(fb->dev);
518
517
unsigned int dst_pitch = 0;
519
-
struct iosys_map dst, vmap;
518
+
struct iosys_map dst;
520
519
struct drm_rect clip;
521
520
int idx, ret = 0;
522
521
u8 *buf = NULL;
···
545
546
goto out_free;
546
547
547
548
iosys_map_set_vaddr(&dst, buf);
548
-
iosys_map_set_vaddr(&vmap, dma_obj->vaddr);
549
-
drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, &vmap, fb, &clip, fmtcnv_state);
549
+
drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, &clip, fmtcnv_state);
550
550
551
551
drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
552
552
···
830
832
struct drm_plane_state *old_state)
831
833
{
832
834
struct drm_plane_state *state = pipe->plane.state;
833
-
struct drm_format_conv_state fmtcnv_state = DRM_FORMAT_CONV_STATE_INIT;
835
+
struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
834
836
struct drm_rect rect;
835
837
836
838
if (!pipe->crtc.state->active)
837
839
return;
838
840
839
841
if (drm_atomic_helper_damage_merged(old_state, state, &rect))
840
-
repaper_fb_dirty(state->fb, &fmtcnv_state);
841
-
842
-
drm_format_conv_state_release(&fmtcnv_state);
842
+
repaper_fb_dirty(state->fb, shadow_plane_state->data,
843
+
&shadow_plane_state->fmtcnv_state);
843
844
}
844
845
845
846
static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = {
···
846
849
.enable = repaper_pipe_enable,
847
850
.disable = repaper_pipe_disable,
848
851
.update = repaper_pipe_update,
852
+
DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS,
849
853
};
850
854
851
855
static int repaper_connector_get_modes(struct drm_connector *connector)
+13
-14
drivers/gpu/drm/tiny/sharp-memory.c
+13
-14
drivers/gpu/drm/tiny/sharp-memory.c
···
126
126
127
127
static void sharp_memory_set_tx_buffer_data(u8 *buffer,
128
128
struct drm_framebuffer *fb,
129
+
const struct iosys_map *vmap,
129
130
struct drm_rect clip,
130
131
u32 pitch,
131
132
struct drm_format_conv_state *fmtcnv_state)
132
133
{
133
134
int ret;
134
-
struct iosys_map dst, vmap;
135
-
struct drm_gem_dma_object *dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
135
+
struct iosys_map dst;
136
136
137
137
ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
138
138
if (ret)
139
139
return;
140
140
141
141
iosys_map_set_vaddr(&dst, buffer);
142
-
iosys_map_set_vaddr(&vmap, dma_obj->vaddr);
143
142
144
-
drm_fb_xrgb8888_to_mono(&dst, &pitch, &vmap, fb, &clip, fmtcnv_state);
143
+
drm_fb_xrgb8888_to_mono(&dst, &pitch, vmap, fb, &clip, fmtcnv_state);
145
144
146
145
drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
147
146
}
148
147
149
148
static int sharp_memory_update_display(struct sharp_memory_device *smd,
150
149
struct drm_framebuffer *fb,
150
+
const struct iosys_map *vmap,
151
151
struct drm_rect clip,
152
152
struct drm_format_conv_state *fmtcnv_state)
153
153
{
···
163
163
sharp_memory_set_tx_buffer_mode(&tx_buffer[0],
164
164
SHARP_MEMORY_DISPLAY_UPDATE_MODE, vcom);
165
165
sharp_memory_set_tx_buffer_addresses(&tx_buffer[1], clip, pitch);
166
-
sharp_memory_set_tx_buffer_data(&tx_buffer[2], fb, clip, pitch, fmtcnv_state);
166
+
sharp_memory_set_tx_buffer_data(&tx_buffer[2], fb, vmap, clip, pitch, fmtcnv_state);
167
167
168
168
ret = sharp_memory_spi_write(smd->spi, tx_buffer, tx_buffer_size);
169
169
···
206
206
return ret;
207
207
}
208
208
209
-
static void sharp_memory_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect,
209
+
static void sharp_memory_fb_dirty(struct drm_framebuffer *fb, const struct iosys_map *vmap,
210
+
struct drm_rect *rect,
210
211
struct drm_format_conv_state *fmtconv_state)
211
212
{
212
213
struct drm_rect clip;
···
219
218
clip.y1 = rect->y1;
220
219
clip.y2 = rect->y2;
221
220
222
-
sharp_memory_update_display(smd, fb, clip, fmtconv_state);
221
+
sharp_memory_update_display(smd, fb, vmap, clip, fmtconv_state);
223
222
}
224
223
225
224
static int sharp_memory_plane_atomic_check(struct drm_plane *plane,
···
243
242
{
244
243
struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
245
244
struct drm_plane_state *plane_state = plane->state;
246
-
struct drm_format_conv_state fmtcnv_state = DRM_FORMAT_CONV_STATE_INIT;
245
+
struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
247
246
struct sharp_memory_device *smd;
248
247
struct drm_rect rect;
249
248
···
252
251
return;
253
252
254
253
if (drm_atomic_helper_damage_merged(old_state, plane_state, &rect))
255
-
sharp_memory_fb_dirty(plane_state->fb, &rect, &fmtcnv_state);
256
-
257
-
drm_format_conv_state_release(&fmtcnv_state);
254
+
sharp_memory_fb_dirty(plane_state->fb, shadow_plane_state->data,
255
+
&rect, &shadow_plane_state->fmtcnv_state);
258
256
}
259
257
260
258
static const struct drm_plane_helper_funcs sharp_memory_plane_helper_funcs = {
261
259
.prepare_fb = drm_gem_plane_helper_prepare_fb,
262
260
.atomic_check = sharp_memory_plane_atomic_check,
263
261
.atomic_update = sharp_memory_plane_atomic_update,
262
+
DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
264
263
};
265
264
266
265
static bool sharp_memory_format_mod_supported(struct drm_plane *plane,
···
274
273
.update_plane = drm_atomic_helper_update_plane,
275
274
.disable_plane = drm_atomic_helper_disable_plane,
276
275
.destroy = drm_plane_cleanup,
277
-
.reset = drm_atomic_helper_plane_reset,
278
-
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
279
-
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
276
+
DRM_GEM_SHADOW_PLANE_FUNCS,
280
277
.format_mod_supported = sharp_memory_format_mod_supported,
281
278
};
282
279
+11
drivers/gpu/drm/v3d/v3d_drv.c
+11
drivers/gpu/drm/v3d/v3d_drv.c
···
46
46
static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
47
47
struct drm_file *file_priv)
48
48
{
49
+
struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
49
50
struct v3d_dev *v3d = to_v3d_dev(dev);
50
51
struct drm_v3d_get_param *args = data;
51
52
static const u32 reg_map[] = {
···
107
106
return 0;
108
107
case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES:
109
108
args->value = !!v3d->gemfs;
109
+
return 0;
110
+
case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER:
111
+
mutex_lock(&v3d->reset_lock);
112
+
args->value = v3d->reset_counter;
113
+
mutex_unlock(&v3d->reset_lock);
114
+
return 0;
115
+
case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER:
116
+
mutex_lock(&v3d->reset_lock);
117
+
args->value = v3d_priv->reset_counter;
118
+
mutex_unlock(&v3d->reset_lock);
110
119
return 0;
111
120
default:
112
121
DRM_DEBUG("Unknown parameter %d\n", args->param);
+11
drivers/gpu/drm/v3d/v3d_drv.h
+11
drivers/gpu/drm/v3d/v3d_drv.h
···
204
204
* all jobs.
205
205
*/
206
206
struct v3d_perfmon *global_perfmon;
207
+
208
+
/* Global reset counter. The counter must be incremented when
209
+
* a GPU reset happens. It must be protected by @reset_lock.
210
+
*/
211
+
unsigned int reset_counter;
207
212
};
208
213
209
214
static inline struct v3d_dev *
···
238
233
239
234
/* Stores the GPU stats for a specific queue for this fd. */
240
235
struct v3d_stats stats[V3D_MAX_QUEUES];
236
+
237
+
/* Per-fd reset counter, must be incremented when a job submitted
238
+
* by this fd causes a GPU reset. It must be protected by
239
+
* &struct v3d_dev->reset_lock.
240
+
*/
241
+
unsigned int reset_counter;
241
242
};
242
243
243
244
struct v3d_bo {
+5
drivers/gpu/drm/v3d/v3d_sched.c
+5
drivers/gpu/drm/v3d/v3d_sched.c
···
721
721
static enum drm_gpu_sched_stat
722
722
v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
723
723
{
724
+
struct v3d_job *job = to_v3d_job(sched_job);
725
+
struct v3d_file_priv *v3d_priv = job->file->driver_priv;
724
726
enum v3d_queue q;
725
727
726
728
mutex_lock(&v3d->reset_lock);
···
736
734
737
735
/* get the GPU back into the init state */
738
736
v3d_reset(v3d);
737
+
738
+
v3d->reset_counter++;
739
+
v3d_priv->reset_counter++;
739
740
740
741
for (q = 0; q < V3D_MAX_QUEUES; q++)
741
742
drm_sched_resubmit_jobs(&v3d->queue[q].sched);
+13
drivers/gpu/drm/vkms/vkms_output.c
+13
drivers/gpu/drm/vkms/vkms_output.c
···
77
77
return ret;
78
78
}
79
79
80
+
encoder_cfg->encoder->possible_clones |=
81
+
drm_encoder_mask(encoder_cfg->encoder);
82
+
80
83
vkms_config_encoder_for_each_possible_crtc(encoder_cfg, idx, possible_crtc) {
81
84
encoder_cfg->encoder->possible_crtcs |=
82
85
drm_crtc_mask(&possible_crtc->crtc->crtc);
86
+
87
+
if (vkms_config_crtc_get_writeback(possible_crtc)) {
88
+
struct drm_encoder *wb_encoder =
89
+
&possible_crtc->crtc->wb_encoder;
90
+
91
+
encoder_cfg->encoder->possible_clones |=
92
+
drm_encoder_mask(wb_encoder);
93
+
wb_encoder->possible_clones |=
94
+
drm_encoder_mask(encoder_cfg->encoder);
95
+
}
83
96
}
84
97
}
85
98
+2
drivers/gpu/drm/vkms/vkms_writeback.c
+2
drivers/gpu/drm/vkms/vkms_writeback.c
···
174
174
if (ret)
175
175
return ret;
176
176
vkms_output->wb_encoder.possible_crtcs |= drm_crtc_mask(&vkms_output->crtc);
177
+
vkms_output->wb_encoder.possible_clones |=
178
+
drm_encoder_mask(&vkms_output->wb_encoder);
177
179
178
180
drm_connector_helper_add(&wb->base, &vkms_wb_conn_helper_funcs);
179
181
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
···
538
538
if (likely(eaction->tv_sec != NULL)) {
539
539
struct timespec64 ts;
540
540
541
-
ktime_to_timespec64(f->timestamp);
541
+
ts = ktime_to_timespec64(f->timestamp);
542
542
/* monotonic time, so no y2038 overflow */
543
543
*eaction->tv_sec = ts.tv_sec;
544
544
*eaction->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
+17
-3
include/drm/drm_bridge.h
+17
-3
include/drm/drm_bridge.h
···
23
23
#ifndef __DRM_BRIDGE_H__
24
24
#define __DRM_BRIDGE_H__
25
25
26
+
#include <linux/cleanup.h>
26
27
#include <linux/ctype.h>
27
28
#include <linux/list.h>
28
29
#include <linux/mutex.h>
···
1277
1276
struct drm_bridge *drm_bridge_get(struct drm_bridge *bridge);
1278
1277
void drm_bridge_put(struct drm_bridge *bridge);
1279
1278
1279
+
/* Cleanup action for use with __free() */
1280
+
DEFINE_FREE(drm_bridge_put, struct drm_bridge *, if (_T) drm_bridge_put(_T))
1281
+
1280
1282
void *__devm_drm_bridge_alloc(struct device *dev, size_t size, size_t offset,
1281
1283
const struct drm_bridge_funcs *funcs);
1282
1284
···
1369
1365
* drm_bridge_get_prev_bridge() - Get the previous bridge in the chain
1370
1366
* @bridge: bridge object
1371
1367
*
1368
+
* The caller is responsible of having a reference to @bridge via
1369
+
* drm_bridge_get() or equivalent. This function leaves the refcount of
1370
+
* @bridge unmodified.
1371
+
*
1372
+
* The refcount of the returned bridge is incremented. Use drm_bridge_put()
1373
+
* when done with it.
1374
+
*
1372
1375
* RETURNS:
1373
1376
* the previous bridge in the chain, or NULL if @bridge is the first.
1374
1377
*/
···
1385
1374
if (list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain))
1386
1375
return NULL;
1387
1376
1388
-
return list_prev_entry(bridge, chain_node);
1377
+
return drm_bridge_get(list_prev_entry(bridge, chain_node));
1389
1378
}
1390
1379
1391
1380
/**
1392
1381
* drm_bridge_chain_get_first_bridge() - Get the first bridge in the chain
1393
1382
* @encoder: encoder object
1383
+
*
1384
+
* The refcount of the returned bridge is incremented. Use drm_bridge_put()
1385
+
* when done with it.
1394
1386
*
1395
1387
* RETURNS:
1396
1388
* the first bridge in the chain, or NULL if @encoder has no bridge attached
···
1402
1388
static inline struct drm_bridge *
1403
1389
drm_bridge_chain_get_first_bridge(struct drm_encoder *encoder)
1404
1390
{
1405
-
return list_first_entry_or_null(&encoder->bridge_chain,
1406
-
struct drm_bridge, chain_node);
1391
+
return drm_bridge_get(list_first_entry_or_null(&encoder->bridge_chain,
1392
+
struct drm_bridge, chain_node));
1407
1393
}
1408
1394
1409
1395
/**
+95
-23
include/drm/drm_mipi_dsi.h
+95
-23
include/drm/drm_mipi_dsi.h
···
288
288
289
289
ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
290
290
size_t size);
291
-
int mipi_dsi_generic_write_chatty(struct mipi_dsi_device *dsi,
292
-
const void *payload, size_t size);
293
291
void mipi_dsi_generic_write_multi(struct mipi_dsi_multi_context *ctx,
294
292
const void *payload, size_t size);
293
+
void mipi_dsi_dual_generic_write_multi(struct mipi_dsi_multi_context *ctx,
294
+
struct mipi_dsi_device *dsi1,
295
+
struct mipi_dsi_device *dsi2,
296
+
const void *payload, size_t size);
295
297
ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
296
298
size_t num_params, void *data, size_t size);
297
299
u32 drm_mipi_dsi_get_input_bus_fmt(enum mipi_dsi_pixel_format dsi_format);
···
334
332
const void *data, size_t len);
335
333
void mipi_dsi_dcs_write_buffer_multi(struct mipi_dsi_multi_context *ctx,
336
334
const void *data, size_t len);
335
+
void mipi_dsi_dual_dcs_write_buffer_multi(struct mipi_dsi_multi_context *ctx,
336
+
struct mipi_dsi_device *dsi1,
337
+
struct mipi_dsi_device *dsi2,
338
+
const void *data, size_t len);
337
339
ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
338
340
const void *data, size_t len);
339
341
ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
···
389
383
void mipi_dsi_dcs_set_tear_off_multi(struct mipi_dsi_multi_context *ctx);
390
384
391
385
/**
392
-
* mipi_dsi_generic_write_seq - transmit data using a generic write packet
393
-
*
394
-
* This macro will print errors for you and will RETURN FROM THE CALLING
395
-
* FUNCTION (yes this is non-intuitive) upon error.
396
-
*
397
-
* Because of the non-intuitive return behavior, THIS MACRO IS DEPRECATED.
398
-
* Please replace calls of it with mipi_dsi_generic_write_seq_multi().
399
-
*
400
-
* @dsi: DSI peripheral device
401
-
* @seq: buffer containing the payload
402
-
*/
403
-
#define mipi_dsi_generic_write_seq(dsi, seq...) \
404
-
do { \
405
-
static const u8 d[] = { seq }; \
406
-
int ret; \
407
-
ret = mipi_dsi_generic_write_chatty(dsi, d, ARRAY_SIZE(d)); \
408
-
if (ret < 0) \
409
-
return ret; \
410
-
} while (0)
411
-
412
-
/**
413
386
* mipi_dsi_generic_write_seq_multi - transmit data using a generic write packet
414
387
*
415
388
* This macro will print errors for you and error handling is optimized for
···
417
432
do { \
418
433
static const u8 d[] = { cmd, seq }; \
419
434
mipi_dsi_dcs_write_buffer_multi(ctx, d, ARRAY_SIZE(d)); \
435
+
} while (0)
436
+
437
+
/**
438
+
* mipi_dsi_dual - send the same MIPI DSI command to two interfaces
439
+
*
440
+
* This macro will send the specified MIPI DSI command twice, once per each of
441
+
* the two interfaces supplied. This is useful for reducing duplication of code
442
+
* in panel drivers which use two parallel serial interfaces.
443
+
*
444
+
* Note that the _func parameter cannot accept a macro such as
445
+
* mipi_dsi_generic_write_multi() or mipi_dsi_dcs_write_buffer_multi(). See
446
+
* mipi_dsi_dual_generic_write_multi() and
447
+
* mipi_dsi_dual_dcs_write_buffer_multi() instead.
448
+
*
449
+
* WARNING: This macro reuses the _func argument and the optional trailing
450
+
* arguments twice each, which may cause unintended side effects. For example,
451
+
* adding the postfix increment ++ operator to one of the arguments to be
452
+
* passed to _func will cause the variable to be incremented twice instead of
453
+
* once and the variable will be its original value + 1 when sent to _dsi2.
454
+
*
455
+
* @_func: MIPI DSI function to pass context and arguments into
456
+
* @_ctx: Context for multiple DSI transactions
457
+
* @_dsi1: First DSI interface to act as recipient of the MIPI DSI command
458
+
* @_dsi2: Second DSI interface to act as recipient of the MIPI DSI command
459
+
* @...: Arguments to pass to MIPI DSI function or macro
460
+
*/
461
+
462
+
#define mipi_dsi_dual(_func, _ctx, _dsi1, _dsi2, ...) \
463
+
do { \
464
+
struct mipi_dsi_multi_context *_ctxcpy = (_ctx); \
465
+
_ctxcpy->dsi = (_dsi1); \
466
+
(_func)(_ctxcpy, ##__VA_ARGS__); \
467
+
_ctxcpy->dsi = (_dsi2); \
468
+
(_func)(_ctxcpy, ##__VA_ARGS__); \
469
+
} while (0)
470
+
471
+
/**
472
+
* mipi_dsi_dual_generic_write_seq_multi - transmit data using a generic write
473
+
* packet to two dsi interfaces, one after the other
474
+
*
475
+
* This macro will send the specified generic packet twice, once per each of
476
+
* the two interfaces supplied. This is useful for reducing duplication of code
477
+
* in panel drivers which use two parallel serial interfaces.
478
+
*
479
+
* Note that if an error occurs while transmitting the packet to the first DSI
480
+
* interface, the packet will not be sent to the second DSI interface.
481
+
*
482
+
* This macro will print errors for you and error handling is optimized for
483
+
* callers that call this multiple times in a row.
484
+
*
485
+
* @_ctx: Context for multiple DSI transactions
486
+
* @_dsi1: First DSI interface to act as recipient of packet
487
+
* @_dsi2: Second DSI interface to act as recipient of packet
488
+
* @_seq: buffer containing the payload
489
+
*/
490
+
#define mipi_dsi_dual_generic_write_seq_multi(_ctx, _dsi1, _dsi2, _seq...) \
491
+
do { \
492
+
static const u8 d[] = { _seq }; \
493
+
mipi_dsi_dual_generic_write_multi(_ctx, _dsi1, _dsi2, d, \
494
+
ARRAY_SIZE(d)); \
495
+
} while (0)
496
+
497
+
/**
498
+
* mipi_dsi_dual_dcs_write_seq_multi - transmit a DCS command with payload to
499
+
* two dsi interfaces, one after the other
500
+
*
501
+
* This macro will send the specified DCS command with payload twice, once per
502
+
* each of the two interfaces supplied. This is useful for reducing duplication
503
+
* of code in panel drivers which use two parallel serial interfaces.
504
+
*
505
+
* Note that if an error occurs while transmitting the payload to the first DSI
506
+
* interface, the payload will not be sent to the second DSI interface.
507
+
*
508
+
* This macro will print errors for you and error handling is optimized for
509
+
* callers that call this multiple times in a row.
510
+
*
511
+
* @_ctx: Context for multiple DSI transactions
512
+
* @_dsi1: First DSI interface to act as recipient of packet
513
+
* @_dsi2: Second DSI interface to act as recipient of packet
514
+
* @_cmd: Command
515
+
* @_seq: buffer containing the payload
516
+
*/
517
+
#define mipi_dsi_dual_dcs_write_seq_multi(_ctx, _dsi1, _dsi2, _cmd, _seq...) \
518
+
do { \
519
+
static const u8 d[] = { _cmd, _seq }; \
520
+
mipi_dsi_dual_dcs_write_buffer_multi(_ctx, _dsi1, _dsi2, d, \
521
+
ARRAY_SIZE(d)); \
420
522
} while (0)
421
523
422
524
/**
+7
include/linux/fbcon.h
+7
include/linux/fbcon.h
···
1
1
#ifndef _LINUX_FBCON_H
2
2
#define _LINUX_FBCON_H
3
3
4
+
#include <linux/compiler_types.h>
5
+
6
+
struct fb_blit_caps;
7
+
struct fb_info;
8
+
struct fb_var_screeninfo;
9
+
struct fb_videomode;
10
+
4
11
#ifdef CONFIG_FRAMEBUFFER_CONSOLE
5
12
void __init fb_console_init(void);
6
13
void __exit fb_console_exit(void);
+25
include/uapi/drm/amdxdna_accel.h
+25
include/uapi/drm/amdxdna_accel.h
···
154
154
};
155
155
156
156
/**
157
+
* struct amdxdna_drm_va_entry
158
+
* @vaddr: Virtual address.
159
+
* @len: Size of entry.
160
+
*/
161
+
struct amdxdna_drm_va_entry {
162
+
__u64 vaddr;
163
+
__u64 len;
164
+
};
165
+
166
+
/**
167
+
* struct amdxdna_drm_va_tbl
168
+
* @dmabuf_fd: The fd of dmabuf.
169
+
* @num_entries: Number of va entries.
170
+
* @va_entries: Array of va entries.
171
+
*
172
+
* The input can be either a dmabuf fd or a virtual address entry table.
173
+
* When dmabuf_fd is used, num_entries must be zero.
174
+
*/
175
+
struct amdxdna_drm_va_tbl {
176
+
__s32 dmabuf_fd;
177
+
__u32 num_entries;
178
+
struct amdxdna_drm_va_entry va_entries[];
179
+
};
180
+
181
+
/**
157
182
* struct amdxdna_drm_create_bo - Create a buffer object.
158
183
* @flags: Buffer flags. MBZ.
159
184
* @vaddr: User VA of buffer if applied. MBZ.
+51
-12
include/uapi/drm/drm.h
+51
-12
include/uapi/drm/drm.h
···
597
597
int drm_dd_minor;
598
598
};
599
599
600
-
/* DRM_IOCTL_GEM_CLOSE ioctl argument type */
600
+
/**
601
+
* struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl.
602
+
* @handle: Handle of the object to be closed.
603
+
* @pad: Padding.
604
+
*
605
+
* Releases the handle to an mm object.
606
+
*/
601
607
struct drm_gem_close {
602
-
/** Handle of the object to be closed. */
603
608
__u32 handle;
604
609
__u32 pad;
605
610
};
606
611
607
-
/* DRM_IOCTL_GEM_FLINK ioctl argument type */
612
+
/**
613
+
* struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl.
614
+
* @handle: Handle for the object being named.
615
+
* @name: Returned global name.
616
+
*
617
+
* Create a global name for an object, returning the name.
618
+
*
619
+
* Note that the name does not hold a reference; when the object
620
+
* is freed, the name goes away.
621
+
*/
608
622
struct drm_gem_flink {
609
-
/** Handle for the object being named */
610
623
__u32 handle;
611
-
612
-
/** Returned global name */
613
624
__u32 name;
614
625
};
615
626
616
-
/* DRM_IOCTL_GEM_OPEN ioctl argument type */
627
+
/**
628
+
* struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl.
629
+
* @name: Name of object being opened.
630
+
* @handle: Returned handle for the object.
631
+
* @size: Returned size of the object
632
+
*
633
+
* Open an object using the global name, returning a handle and the size.
634
+
*
635
+
* This handle (of course) holds a reference to the object, so the object
636
+
* will not go away until the handle is deleted.
637
+
*/
617
638
struct drm_gem_open {
618
-
/** Name of object being opened */
619
639
__u32 name;
620
-
621
-
/** Returned handle for the object */
622
640
__u32 handle;
623
-
624
-
/** Returned size of the object */
625
641
__u64 size;
642
+
};
643
+
644
+
/**
645
+
* struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl.
646
+
* @handle: The handle of a gem object.
647
+
* @new_handle: An available gem handle.
648
+
*
649
+
* This ioctl changes the handle of a GEM object to the specified one.
650
+
* The new handle must be unused. On success the old handle is closed
651
+
* and all further IOCTL should refer to the new handle only.
652
+
* Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle.
653
+
*/
654
+
struct drm_gem_change_handle {
655
+
__u32 handle;
656
+
__u32 new_handle;
626
657
};
627
658
628
659
/**
···
1339
1308
* The call will fail if the name contains whitespaces or non-printable chars.
1340
1309
*/
1341
1310
#define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name)
1311
+
1312
+
/**
1313
+
* DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle
1314
+
*
1315
+
* Some applications (notably CRIU) need objects to have specific gem handles.
1316
+
* This ioctl changes the object at one gem handle to use a new gem handle.
1317
+
*/
1318
+
#define DRM_IOCTL_GEM_CHANGE_HANDLE DRM_IOWR(0xD2, struct drm_gem_change_handle)
1342
1319
1343
1320
/*
1344
1321
* Device specific ioctls should only be in their respective headers
+8
include/uapi/drm/drm_mode.h
+8
include/uapi/drm/drm_mode.h
···
962
962
* Request that the kernel sends back a vblank event (see
963
963
* struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the
964
964
* page-flip is done.
965
+
*
966
+
* When used with atomic uAPI, one event will be delivered per CRTC included in
967
+
* the atomic commit. A CRTC is included in an atomic commit if one of its
968
+
* properties is set, or if a property is set on a connector or plane linked
969
+
* via the CRTC_ID property to the CRTC. At least one CRTC must be included,
970
+
* and all pulled in CRTCs must be either previously or newly powered on (in
971
+
* other words, a powered off CRTC which stays off cannot be included in the
972
+
* atomic commit).
965
973
*/
966
974
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
967
975
/**
+142
include/uapi/drm/rocket_accel.h
+142
include/uapi/drm/rocket_accel.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2024 Tomeu Vizoso
4
+
*/
5
+
#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
6
+
#define __DRM_UAPI_ROCKET_ACCEL_H__
7
+
8
+
#include "drm.h"
9
+
10
+
#if defined(__cplusplus)
11
+
extern "C" {
12
+
#endif
13
+
14
+
#define DRM_ROCKET_CREATE_BO 0x00
15
+
#define DRM_ROCKET_SUBMIT 0x01
16
+
#define DRM_ROCKET_PREP_BO 0x02
17
+
#define DRM_ROCKET_FINI_BO 0x03
18
+
19
+
#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
20
+
#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
21
+
#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
22
+
#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
23
+
24
+
/**
25
+
* struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
26
+
*
27
+
*/
28
+
struct drm_rocket_create_bo {
29
+
/** Input: Size of the requested BO. */
30
+
__u32 size;
31
+
32
+
/** Output: GEM handle for the BO. */
33
+
__u32 handle;
34
+
35
+
/**
36
+
* Output: DMA address for the BO in the NPU address space. This address
37
+
* is private to the DRM fd and is valid for the lifetime of the GEM
38
+
* handle.
39
+
*/
40
+
__u64 dma_address;
41
+
42
+
/** Output: Offset into the drm node to use for subsequent mmap call. */
43
+
__u64 offset;
44
+
};
45
+
46
+
/**
47
+
* struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
48
+
*
49
+
* Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
50
+
* synchronization.
51
+
*/
52
+
struct drm_rocket_prep_bo {
53
+
/** Input: GEM handle of the buffer object. */
54
+
__u32 handle;
55
+
56
+
/** Reserved, must be zero. */
57
+
__u32 reserved;
58
+
59
+
/** Input: Amount of time to wait for NPU jobs. */
60
+
__s64 timeout_ns;
61
+
};
62
+
63
+
/**
64
+
* struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
65
+
*
66
+
* Synchronize caches for NPU access.
67
+
*/
68
+
struct drm_rocket_fini_bo {
69
+
/** Input: GEM handle of the buffer object. */
70
+
__u32 handle;
71
+
72
+
/** Reserved, must be zero. */
73
+
__u32 reserved;
74
+
};
75
+
76
+
/**
77
+
* struct drm_rocket_task - A task to be run on the NPU
78
+
*
79
+
* A task is the smallest unit of work that can be run on the NPU.
80
+
*/
81
+
struct drm_rocket_task {
82
+
/** Input: DMA address to NPU mapping of register command buffer */
83
+
__u32 regcmd;
84
+
85
+
/** Input: Number of commands in the register command buffer */
86
+
__u32 regcmd_count;
87
+
};
88
+
89
+
/**
90
+
* struct drm_rocket_job - A job to be run on the NPU
91
+
*
92
+
* The kernel will schedule the execution of this job taking into account its
93
+
* dependencies with other jobs. All tasks in the same job will be executed
94
+
* sequentially on the same core, to benefit from memory residency in SRAM.
95
+
*/
96
+
struct drm_rocket_job {
97
+
/** Input: Pointer to an array of struct drm_rocket_task. */
98
+
__u64 tasks;
99
+
100
+
/** Input: Pointer to a u32 array of the BOs that are read by the job. */
101
+
__u64 in_bo_handles;
102
+
103
+
/** Input: Pointer to a u32 array of the BOs that are written to by the job. */
104
+
__u64 out_bo_handles;
105
+
106
+
/** Input: Number of tasks passed in. */
107
+
__u32 task_count;
108
+
109
+
/** Input: Size in bytes of the structs in the @tasks field. */
110
+
__u32 task_struct_size;
111
+
112
+
/** Input: Number of input BO handles passed in (size is that times 4). */
113
+
__u32 in_bo_handle_count;
114
+
115
+
/** Input: Number of output BO handles passed in (size is that times 4). */
116
+
__u32 out_bo_handle_count;
117
+
};
118
+
119
+
/**
120
+
* struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
121
+
*
122
+
* The kernel will schedule the execution of these jobs in dependency order.
123
+
*/
124
+
struct drm_rocket_submit {
125
+
/** Input: Pointer to an array of struct drm_rocket_job. */
126
+
__u64 jobs;
127
+
128
+
/** Input: Number of jobs passed in. */
129
+
__u32 job_count;
130
+
131
+
/** Input: Size in bytes of the structs in the @jobs field. */
132
+
__u32 job_struct_size;
133
+
134
+
/** Reserved, must be zero. */
135
+
__u64 reserved;
136
+
};
137
+
138
+
#if defined(__cplusplus)
139
+
}
140
+
#endif
141
+
142
+
#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */
+2
include/uapi/drm/v3d_drm.h
+2
include/uapi/drm/v3d_drm.h
+7
-4
rust/kernel/drm/ioctl.rs
+7
-4
rust/kernel/drm/ioctl.rs
···
83
83
///
84
84
/// ```ignore
85
85
/// fn foo(device: &kernel::drm::Device<Self>,
86
-
/// data: &Opaque<uapi::argument_type>,
86
+
/// data: &mut uapi::argument_type,
87
87
/// file: &kernel::drm::File<Self::File>,
88
88
/// ) -> Result<u32>
89
89
/// ```
···
138
138
// SAFETY: The ioctl argument has size `_IOC_SIZE(cmd)`, which we
139
139
// asserted above matches the size of this type, and all bit patterns of
140
140
// UAPI structs must be valid.
141
-
let data = unsafe {
142
-
&*(raw_data as *const $crate::types::Opaque<$crate::uapi::$struct>)
143
-
};
141
+
// The `ioctl` argument is exclusively owned by the handler
142
+
// and guaranteed by the C implementation (`drm_ioctl()`) to remain
143
+
// valid for the entire lifetime of the reference taken here.
144
+
// There is no concurrent access or aliasing; no other references
145
+
// to this object exist during this call.
146
+
let data = unsafe { &mut *(raw_data.cast::<$crate::uapi::$struct>()) };
144
147
// SAFETY: This is just the DRM file structure
145
148
let file = unsafe { $crate::drm::File::from_raw(raw_file) };
146
149