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linux
pwm: meson: Support constant and polarity bits
Newer meson PWM IPs support constant and polarity bits. Support them to
correctly implement constant and inverted output levels.
Using constant bit allows to have truly stable low or high output level.
Since hi and low regs internally increment its values by 1 just writing
zero to any of them gives 1 clock count impulse. If constant bit is set
zero value in hi and low regs is not incremented.
Using polarity bit instead of swapping hi and low reg values allows to
correctly identify inversion in .get_state().
Signed-off-by: George Stark <gnstark@salutedevices.com>
Link: https://lore.kernel.org/r/20241119125318.3492261-3-gnstark@salutedevices.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
authored by
George Stark
and committed by
Uwe Kleine-König
dd4d280a
8c22e890
+54
-7
+54
-7
drivers/pwm/pwm-meson.c
+54
-7
drivers/pwm/pwm-meson.c
···
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6
* PWM output is achieved by calculating a clock that permits calculating
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* two periods (low and high). The counter then has to be set to switch after
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* N cycles for the first half period.
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-
* The hardware has no "polarity" setting. This driver reverses the period
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+
* Partly the hardware has no "polarity" setting. This driver reverses the period
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* cycles (the low length is inverted with the high length) for
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* PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
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* from the hardware.
···
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#define MISC_B_CLK_SEL_SHIFT 6
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#define MISC_A_CLK_SEL_SHIFT 4
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#define MISC_CLK_SEL_MASK 0x3
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+
#define MISC_B_CONSTANT_EN BIT(29)
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+
#define MISC_A_CONSTANT_EN BIT(28)
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+
#define MISC_B_INVERT_EN BIT(27)
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+
#define MISC_A_INVERT_EN BIT(26)
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#define MISC_B_EN BIT(1)
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#define MISC_A_EN BIT(0)
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···
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u8 clk_div_shift;
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u8 clk_en_shift;
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u32 pwm_en_mask;
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+
u32 const_en_mask;
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+
u32 inv_en_mask;
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} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
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{
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.reg_offset = REG_PWM_A,
···
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.clk_div_shift = MISC_A_CLK_DIV_SHIFT,
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.clk_en_shift = MISC_A_CLK_EN_SHIFT,
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.pwm_en_mask = MISC_A_EN,
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+
.const_en_mask = MISC_A_CONSTANT_EN,
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+
.inv_en_mask = MISC_A_INVERT_EN,
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},
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{
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.reg_offset = REG_PWM_B,
···
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.clk_div_shift = MISC_B_CLK_DIV_SHIFT,
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.clk_en_shift = MISC_B_CLK_EN_SHIFT,
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.pwm_en_mask = MISC_B_EN,
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.const_en_mask = MISC_B_CONSTANT_EN,
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.inv_en_mask = MISC_B_INVERT_EN,
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}
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};
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···
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unsigned long rate;
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unsigned int hi;
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unsigned int lo;
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bool constant;
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bool inverted;
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struct clk_mux mux;
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struct clk_divider div;
···
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struct meson_pwm_data {
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const char *const parent_names[MESON_NUM_MUX_PARENTS];
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int (*channels_init)(struct pwm_chip *chip);
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+
bool has_constant;
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bool has_polarity;
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};
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struct meson_pwm {
···
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* Fixing this needs some care however as some machines might rely on
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* this.
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*/
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-
if (state->polarity == PWM_POLARITY_INVERSED)
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+
if (state->polarity == PWM_POLARITY_INVERSED && !meson->data->has_polarity)
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duty = period - duty;
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freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
···
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if (duty == period) {
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channel->hi = cnt;
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channel->lo = 0;
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channel->constant = true;
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} else if (duty == 0) {
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channel->hi = 0;
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channel->lo = cnt;
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channel->constant = true;
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} else {
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duty_cnt = mul_u64_u64_div_u64(fin_freq, duty, NSEC_PER_SEC);
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···
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channel->hi = duty_cnt;
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channel->lo = cnt - duty_cnt;
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channel->constant = false;
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}
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channel->rate = fin_freq;
···
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value = readl(meson->base + REG_MISC_AB);
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value |= channel_data->pwm_en_mask;
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+
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+
if (meson->data->has_constant) {
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value &= ~channel_data->const_en_mask;
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+
if (channel->constant)
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+
value |= channel_data->const_en_mask;
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+
}
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+
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+
if (meson->data->has_polarity) {
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+
value &= ~channel_data->inv_en_mask;
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+
if (channel->inverted)
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+
value |= channel_data->inv_en_mask;
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+
}
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+
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writel(value, meson->base + REG_MISC_AB);
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spin_unlock_irqrestore(&meson->lock, flags);
···
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static void meson_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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+
struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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+
struct meson_pwm_channel_data *channel_data;
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unsigned long flags;
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u32 value;
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+
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+
channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
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spin_lock_irqsave(&meson->lock, flags);
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value = readl(meson->base + REG_MISC_AB);
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value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
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value &= ~channel_data->pwm_en_mask;
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+
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+
if (meson->data->has_polarity) {
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+
value &= ~channel_data->inv_en_mask;
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+
if (channel->inverted)
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value |= channel_data->inv_en_mask;
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+
}
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+
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writel(value, meson->base + REG_MISC_AB);
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spin_unlock_irqrestore(&meson->lock, flags);
···
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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int err = 0;
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+
channel->inverted = (state->polarity == PWM_POLARITY_INVERSED);
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+
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if (!state->enabled) {
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-
if (state->polarity == PWM_POLARITY_INVERSED) {
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+
if (channel->inverted && !meson->data->has_polarity) {
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/*
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* This IP block revision doesn't have an "always high"
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+
* Some of IP block revisions don't have an "always high"
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* setting which we can use for "inverted disabled".
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* Instead we achieve this by setting mux parent with
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* highest rate and minimum divider value, resulting
···
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channel->rate = ULONG_MAX;
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channel->hi = ~0;
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channel->lo = 0;
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channel->constant = true;
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meson_pwm_enable(chip, pwm);
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} else {
···
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value = readl(meson->base + REG_MISC_AB);
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state->enabled = value & channel_data->pwm_en_mask;
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+
if (meson->data->has_polarity && (value & channel_data->inv_en_mask))
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+
state->polarity = PWM_POLARITY_INVERSED;
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else
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state->polarity = PWM_POLARITY_NORMAL;
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+
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value = readl(meson->base + channel_data->reg_offset);
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lo = FIELD_GET(PWM_LOW_MASK, value);
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hi = FIELD_GET(PWM_HIGH_MASK, value);
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state->period = meson_pwm_cnt_to_ns(chip, pwm, lo + hi);
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state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, hi);
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-
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state->polarity = PWM_POLARITY_NORMAL;
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return 0;
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}