+4

Documentation/devicetree/bindings/serial/ingenic,uart.yaml

reviewed

··· 20 20 oneOf: 21 21 - enum: 22 22 - ingenic,jz4740-uart 23 23 + - ingenic,jz4750-uart 23 24 - ingenic,jz4760-uart 24 25 - ingenic,jz4780-uart 25 26 - ingenic,x1000-uart ··· 32 31 - items: 33 32 - const: ingenic,jz4725b-uart 34 33 - const: ingenic,jz4740-uart 34 34 + - items: 35 35 + - const: ingenic,jz4755-uart 36 36 + - const: ingenic,jz4750-uart 35 37 36 38 reg: 37 39 maxItems: 1

+1

Documentation/devicetree/bindings/serial/renesas,scif.yaml

reviewed

··· 67 67 - enum: 68 68 - renesas,scif-r8a779a0 # R-Car V3U 69 69 - renesas,scif-r8a779f0 # R-Car S4-8 70 70 + - renesas,scif-r8a779g0 # R-Car V4H 70 71 - const: renesas,rcar-gen4-scif # R-Car Gen4 71 72 - const: renesas,scif # generic SCIF compatible UART 72 73

+1 -2

Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml

reviewed

··· 67 67 - if: 68 68 properties: 69 69 xlnx,use-parity: 70 70 - contains: 71 71 - const: 1 70 70 + const: 1 72 71 then: 73 72 required: 74 73 - xlnx,odd-parity

+3

Documentation/driver-api/serial/driver.rst

reviewed

··· 78 78 uart_get_lsr_info uart_handle_dcd_change uart_handle_cts_change 79 79 uart_try_toggle_sysrq uart_get_console 80 80 81 81 + .. kernel-doc:: include/linux/serial_core.h 82 82 + :identifiers: uart_port_tx_limited uart_port_tx 83 83 + 81 84 Other notes 82 85 ----------- 83 86

+30 -26

Documentation/driver-api/serial/serial-rs485.rst

reviewed

··· 29 29 3. Data Structures Already Available in the Kernel 30 30 ================================================== 31 31 32 32 - The Linux kernel provides the serial_rs485 structure (see [1]) to handle 33 33 - RS485 communications. This data structure is used to set and configure RS485 32 32 + The Linux kernel provides the struct serial_rs485 to handle RS485 33 33 + communications. This data structure is used to set and configure RS485 34 34 parameters in the platform data and in ioctls. 35 35 36 36 - The device tree can also provide RS485 boot time parameters (see [2] 37 37 - for bindings). The driver is in charge of filling this data structure from 38 38 - the values given by the device tree. 36 36 + The device tree can also provide RS485 boot time parameters 37 37 + [#DT-bindings]_. The serial core fills the struct serial_rs485 from the 38 38 + values given by the device tree when the driver calls 39 39 + uart_get_rs485_mode(). 39 40 40 41 Any driver for devices capable of working both as RS232 and RS485 should 41 41 - implement the rs485_config callback and provide rs485_supported in the 42 42 - uart_port structure. The serial core calls rs485_config to do the device 43 43 - specific part in response to TIOCSRS485 ioctl (see below). The rs485_config 44 44 - callback receives a pointer to a sanitizated serial_rs485 structure. The 45 45 - serial_rs485 userspace provides is sanitized before calling rs485_config 46 46 - using rs485_supported that indicates what RS485 features the driver supports 47 47 - for the uart_port. TIOCGRS485 ioctl can be used to read back the 48 48 - serial_rs485 structure matching to the current configuration. 42 42 + implement the ``rs485_config`` callback and provide ``rs485_supported`` 43 43 + in the ``struct uart_port``. The serial core calls ``rs485_config`` to do 44 44 + the device specific part in response to TIOCSRS485 ioctl (see below). The 45 45 + ``rs485_config`` callback receives a pointer to a sanitizated struct 46 46 + serial_rs485. The struct serial_rs485 userspace provides is sanitized 47 47 + before calling ``rs485_config`` using ``rs485_supported`` that indicates 48 48 + what RS485 features the driver supports for the ``struct uart_port``. 49 49 + TIOCGRS485 ioctl can be used to read back the struct serial_rs485 50 50 + matching to the current configuration. 51 51 + 52 52 + .. kernel-doc:: include/uapi/linux/serial.h 53 53 + :identifiers: serial_rs485 uart_get_rs485_mode 49 54 50 55 4. Usage from user-level 51 56 ======================== ··· 108 103 ======================== 109 104 110 105 The Linux kernel provides addressing mode for multipoint RS-485 serial 111 111 - communications line. The addressing mode is enabled with SER_RS485_ADDRB 112 112 - flag in serial_rs485. Struct serial_rs485 has two additional flags and 113 113 - fields for enabling receive and destination addresses. 106 106 + communications line. The addressing mode is enabled with 107 107 + ``SER_RS485_ADDRB`` flag in struct serial_rs485. The struct serial_rs485 108 108 + has two additional flags and fields for enabling receive and destination 109 109 + addresses. 114 110 115 111 Address mode flags: 116 116 - - SER_RS485_ADDRB: Enabled addressing mode (sets also ADDRB in termios). 117 117 - - SER_RS485_ADDR_RECV: Receive (filter) address enabled. 118 118 - - SER_RS485_ADDR_DEST: Set destination address. 112 112 + - ``SER_RS485_ADDRB``: Enabled addressing mode (sets also ADDRB in termios). 113 113 + - ``SER_RS485_ADDR_RECV``: Receive (filter) address enabled. 114 114 + - ``SER_RS485_ADDR_DEST``: Set destination address. 119 115 120 120 - Address fields (enabled with corresponding SER_RS485_ADDR_* flag): 121 121 - - addr_recv: Receive address. 122 122 - - addr_dest: Destination address. 116 116 + Address fields (enabled with corresponding ``SER_RS485_ADDR_*`` flag): 117 117 + - ``addr_recv``: Receive address. 118 118 + - ``addr_dest``: Destination address. 123 119 124 120 Once a receive address is set, the communication can occur only with the 125 121 particular device and other peers are filtered out. It is left up to the 126 122 receiver side to enforce the filtering. Receive address will be cleared 127 127 - if SER_RS485_ADDR_RECV is not set. 123 123 + if ``SER_RS485_ADDR_RECV`` is not set. 128 124 129 125 Note: not all devices supporting RS485 support multipoint addressing. 130 126 131 127 6. References 132 128 ============= 133 129 134 134 - [1] include/uapi/linux/serial.h 135 135 - 136 136 - [2] Documentation/devicetree/bindings/serial/rs485.txt 130 130 + .. [#DT-bindings] Documentation/devicetree/bindings/serial/rs485.txt

+19

drivers/tty/Kconfig

reviewed

··· 149 149 When not in use, each legacy PTY occupies 12 bytes on 32-bit 150 150 architectures and 24 bytes on 64-bit architectures. 151 151 152 152 + config LEGACY_TIOCSTI 153 153 + bool "Allow legacy TIOCSTI usage" 154 154 + default y 155 155 + help 156 156 + Historically the kernel has allowed TIOCSTI, which will push 157 157 + characters into a controlling TTY. This continues to be used 158 158 + as a malicious privilege escalation mechanism, and provides no 159 159 + meaningful real-world utility any more. Its use is considered 160 160 + a dangerous legacy operation, and can be disabled on most 161 161 + systems. 162 162 + 163 163 + Say 'Y here only if you have confirmed that your system's 164 164 + userspace depends on this functionality to continue operating 165 165 + normally. 166 166 + 167 167 + This functionality can be changed at runtime with the 168 168 + dev.tty.legacy_tiocsti sysctl. This configuration option sets 169 169 + the default value of the sysctl. 170 170 + 152 171 config LDISC_AUTOLOAD 153 172 bool "Automatically load TTY Line Disciplines" 154 173 default y

+2 -2

drivers/tty/ehv_bytechan.c

reviewed

··· 118 118 return 0; 119 119 120 120 stdout_irq = irq_of_parse_and_map(np, 0); 121 121 - if (stdout_irq == NO_IRQ) { 121 121 + if (!stdout_irq) { 122 122 pr_err("ehv-bc: no 'interrupts' property in %pOF node\n", np); 123 123 return 0; 124 124 } ··· 696 696 697 697 bc->rx_irq = irq_of_parse_and_map(np, 0); 698 698 bc->tx_irq = irq_of_parse_and_map(np, 1); 699 699 - if ((bc->rx_irq == NO_IRQ) || (bc->tx_irq == NO_IRQ)) { 699 699 + if (!bc->rx_irq || !bc->tx_irq) { 700 700 dev_err(&pdev->dev, "no 'interrupts' property in %pOFn node\n", 701 701 np); 702 702 ret = -ENODEV;

+1 -1

drivers/tty/hvc/hvc_rtas.c

reviewed

··· 26 26 #include "hvc_console.h" 27 27 28 28 #define hvc_rtas_cookie 0x67781e15 29 29 - struct hvc_struct *hvc_rtas_dev; 29 29 + static struct hvc_struct *hvc_rtas_dev; 30 30 31 31 static int rtascons_put_char_token = RTAS_UNKNOWN_SERVICE; 32 32 static int rtascons_get_char_token = RTAS_UNKNOWN_SERVICE;

+378 -24

drivers/tty/n_gsm.c

reviewed

··· 38 38 #include <linux/sched/signal.h> 39 39 #include <linux/interrupt.h> 40 40 #include <linux/tty.h> 41 41 + #include <linux/bitfield.h> 41 42 #include <linux/ctype.h> 42 43 #include <linux/mm.h> 44 44 + #include <linux/math.h> 43 45 #include <linux/string.h> 44 46 #include <linux/slab.h> 45 47 #include <linux/poll.h> ··· 77 75 78 76 #define T1 10 /* 100mS */ 79 77 #define T2 34 /* 333mS */ 78 78 + #define T3 10 /* 10s */ 80 79 #define N2 3 /* Retry 3 times */ 80 80 + #define K 2 /* outstanding I frames */ 81 81 + 82 82 + #define MAX_T3 255 /* In seconds. */ 83 83 + #define MAX_WINDOW_SIZE 7 /* Limit of K in error recovery mode. */ 81 84 82 85 /* Use long timers for testing at low speed with debug on */ 83 86 #ifdef DEBUG_TIMING ··· 96 89 */ 97 90 #define MAX_MRU 1500 98 91 #define MAX_MTU 1500 92 92 + #define MIN_MTU (PROT_OVERHEAD + 1) 99 93 /* SOF, ADDR, CTRL, LEN1, LEN2, ..., FCS, EOF */ 100 94 #define PROT_OVERHEAD 7 101 95 #define GSM_NET_TX_TIMEOUT (HZ*10) ··· 128 120 129 121 enum gsm_dlci_state { 130 122 DLCI_CLOSED, 123 123 + DLCI_CONFIGURE, /* Sending PN (for adaption > 1) */ 131 124 DLCI_OPENING, /* Sending SABM not seen UA */ 132 125 DLCI_OPEN, /* SABM/UA complete */ 133 126 DLCI_CLOSING, /* Sending DISC not seen UA/DM */ ··· 168 159 int prev_adaption; 169 160 u32 modem_rx; /* Our incoming virtual modem lines */ 170 161 u32 modem_tx; /* Our outgoing modem lines */ 162 162 + unsigned int mtu; 171 163 bool dead; /* Refuse re-open */ 164 164 + /* Configuration */ 165 165 + u8 prio; /* Priority */ 166 166 + u8 ftype; /* Frame type */ 167 167 + u8 k; /* Window size */ 172 168 /* Flow control */ 173 169 bool throttled; /* Private copy of throttle state */ 174 170 bool constipated; /* Throttle status for outgoing */ ··· 185 171 void (*prev_data)(struct gsm_dlci *dlci, const u8 *data, int len); 186 172 struct net_device *net; /* network interface, if created */ 187 173 }; 174 174 + 175 175 + /* 176 176 + * Parameter bits used for parameter negotiation according to 3GPP 27.010 177 177 + * chapter 5.4.6.3.1. 178 178 + */ 179 179 + 180 180 + struct gsm_dlci_param_bits { 181 181 + u8 d_bits; 182 182 + u8 i_cl_bits; 183 183 + u8 p_bits; 184 184 + u8 t_bits; 185 185 + __le16 n_bits; 186 186 + u8 na_bits; 187 187 + u8 k_bits; 188 188 + }; 189 189 + 190 190 + static_assert(sizeof(struct gsm_dlci_param_bits) == 8); 191 191 + 192 192 + #define PN_D_FIELD_DLCI GENMASK(5, 0) 193 193 + #define PN_I_CL_FIELD_FTYPE GENMASK(3, 0) 194 194 + #define PN_I_CL_FIELD_ADAPTION GENMASK(7, 4) 195 195 + #define PN_P_FIELD_PRIO GENMASK(5, 0) 196 196 + #define PN_T_FIELD_T1 GENMASK(7, 0) 197 197 + #define PN_N_FIELD_N1 GENMASK(15, 0) 198 198 + #define PN_NA_FIELD_N2 GENMASK(7, 0) 199 199 + #define PN_K_FIELD_K GENMASK(2, 0) 188 200 189 201 /* Total number of supported devices */ 190 202 #define GSM_TTY_MINORS 256 ··· 322 282 int adaption; /* 1 or 2 supported */ 323 283 u8 ftype; /* UI or UIH */ 324 284 int t1, t2; /* Timers in 1/100th of a sec */ 285 285 + unsigned int t3; /* Power wake-up timer in seconds. */ 325 286 int n2; /* Retry count */ 287 287 + u8 k; /* Window size */ 326 288 327 289 /* Statistics (not currently exposed) */ 328 290 unsigned long bad_fcs; ··· 439 397 #define INIT_FCS 0xFF 440 398 #define GOOD_FCS 0xCF 441 399 400 400 + static void gsm_dlci_close(struct gsm_dlci *dlci); 442 401 static int gsmld_output(struct gsm_mux *gsm, u8 *data, int len); 443 402 static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk); 444 403 static struct gsm_msg *gsm_data_alloc(struct gsm_mux *gsm, u8 addr, int len, ··· 560 517 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 16, 1, data, len, 561 518 true); 562 519 kfree(prefix); 520 520 + } 521 521 + 522 522 + /** 523 523 + * gsm_encode_params - encode DLCI parameters 524 524 + * @dlci: DLCI to encode from 525 525 + * @params: buffer to fill with the encoded parameters 526 526 + * 527 527 + * Encodes the parameters according to GSM 07.10 section 5.4.6.3.1 528 528 + * table 3. 529 529 + */ 530 530 + static int gsm_encode_params(const struct gsm_dlci *dlci, 531 531 + struct gsm_dlci_param_bits *params) 532 532 + { 533 533 + const struct gsm_mux *gsm = dlci->gsm; 534 534 + unsigned int i, cl; 535 535 + 536 536 + switch (dlci->ftype) { 537 537 + case UIH: 538 538 + i = 0; /* UIH */ 539 539 + break; 540 540 + case UI: 541 541 + i = 1; /* UI */ 542 542 + break; 543 543 + default: 544 544 + pr_debug("unsupported frame type %d\n", dlci->ftype); 545 545 + return -EINVAL; 546 546 + } 547 547 + 548 548 + switch (dlci->adaption) { 549 549 + case 1: /* Unstructured */ 550 550 + cl = 0; /* convergence layer type 1 */ 551 551 + break; 552 552 + case 2: /* Unstructured with modem bits. */ 553 553 + cl = 1; /* convergence layer type 2 */ 554 554 + break; 555 555 + default: 556 556 + pr_debug("unsupported adaption %d\n", dlci->adaption); 557 557 + return -EINVAL; 558 558 + } 559 559 + 560 560 + params->d_bits = FIELD_PREP(PN_D_FIELD_DLCI, dlci->addr); 561 561 + /* UIH, convergence layer type 1 */ 562 562 + params->i_cl_bits = FIELD_PREP(PN_I_CL_FIELD_FTYPE, i) | 563 563 + FIELD_PREP(PN_I_CL_FIELD_ADAPTION, cl); 564 564 + params->p_bits = FIELD_PREP(PN_P_FIELD_PRIO, dlci->prio); 565 565 + params->t_bits = FIELD_PREP(PN_T_FIELD_T1, gsm->t1); 566 566 + params->n_bits = cpu_to_le16(FIELD_PREP(PN_N_FIELD_N1, dlci->mtu)); 567 567 + params->na_bits = FIELD_PREP(PN_NA_FIELD_N2, gsm->n2); 568 568 + params->k_bits = FIELD_PREP(PN_K_FIELD_K, dlci->k); 569 569 + 570 570 + return 0; 563 571 } 564 572 565 573 /** ··· 1170 1076 return 0; 1171 1077 1172 1078 /* MTU/MRU count only the data bits but watch adaption mode */ 1173 1173 - if ((len + h) > gsm->mtu) 1174 1174 - len = gsm->mtu - h; 1079 1079 + if ((len + h) > dlci->mtu) 1080 1080 + len = dlci->mtu - h; 1175 1081 1176 1082 size = len + h; 1177 1083 1178 1178 - msg = gsm_data_alloc(gsm, dlci->addr, size, gsm->ftype); 1084 1084 + msg = gsm_data_alloc(gsm, dlci->addr, size, dlci->ftype); 1179 1085 if (!msg) 1180 1086 return -ENOMEM; 1181 1087 dp = msg->data; ··· 1239 1145 len = dlci->skb->len + overhead; 1240 1146 1241 1147 /* MTU/MRU count only the data bits */ 1242 1242 - if (len > gsm->mtu) { 1148 1148 + if (len > dlci->mtu) { 1243 1149 if (dlci->adaption == 3) { 1244 1150 /* Over long frame, bin it */ 1245 1151 dev_kfree_skb_any(dlci->skb); 1246 1152 dlci->skb = NULL; 1247 1153 return 0; 1248 1154 } 1249 1249 - len = gsm->mtu; 1155 1155 + len = dlci->mtu; 1250 1156 } else 1251 1157 last = 1; 1252 1158 1253 1159 size = len + overhead; 1254 1254 - msg = gsm_data_alloc(gsm, dlci->addr, size, gsm->ftype); 1160 1160 + msg = gsm_data_alloc(gsm, dlci->addr, size, dlci->ftype); 1255 1161 if (msg == NULL) { 1256 1162 skb_queue_tail(&dlci->skb_list, dlci->skb); 1257 1163 dlci->skb = NULL; ··· 1308 1214 return -EINVAL; 1309 1215 } 1310 1216 1311 1311 - msg = gsm_data_alloc(gsm, dlci->addr, size, gsm->ftype); 1217 1217 + msg = gsm_data_alloc(gsm, dlci->addr, size, dlci->ftype); 1312 1218 if (!msg) { 1313 1219 pr_err("%s: gsm_data_alloc error", __func__); 1314 1220 return -ENOMEM; ··· 1381 1287 } 1382 1288 if (!sent) 1383 1289 break; 1384 1384 - }; 1290 1290 + } 1385 1291 1386 1292 return ret; 1387 1293 } ··· 1434 1340 static int gsm_control_command(struct gsm_mux *gsm, int cmd, const u8 *data, 1435 1341 int dlen) 1436 1342 { 1437 1437 - struct gsm_msg *msg = gsm_data_alloc(gsm, 0, dlen + 2, gsm->ftype); 1343 1343 + struct gsm_msg *msg; 1438 1344 1345 1345 + msg = gsm_data_alloc(gsm, 0, dlen + 2, gsm->dlci[0]->ftype); 1439 1346 if (msg == NULL) 1440 1347 return -ENOMEM; 1441 1348 ··· 1462 1367 int dlen) 1463 1368 { 1464 1369 struct gsm_msg *msg; 1465 1465 - msg = gsm_data_alloc(gsm, 0, dlen + 2, gsm->ftype); 1370 1370 + 1371 1371 + msg = gsm_data_alloc(gsm, 0, dlen + 2, gsm->dlci[0]->ftype); 1466 1372 if (msg == NULL) 1467 1373 return; 1468 1374 msg->data[0] = (cmd & 0xFE) << 1 | EA; /* Clear C/R */ ··· 1534 1438 } 1535 1439 1536 1440 /** 1441 1441 + * gsm_process_negotiation - process received parameters 1442 1442 + * @gsm: GSM channel 1443 1443 + * @addr: DLCI address 1444 1444 + * @cr: command/response 1445 1445 + * @params: encoded parameters from the parameter negotiation message 1446 1446 + * 1447 1447 + * Used when the response for our parameter negotiation command was 1448 1448 + * received. 1449 1449 + */ 1450 1450 + static int gsm_process_negotiation(struct gsm_mux *gsm, unsigned int addr, 1451 1451 + unsigned int cr, 1452 1452 + const struct gsm_dlci_param_bits *params) 1453 1453 + { 1454 1454 + struct gsm_dlci *dlci = gsm->dlci[addr]; 1455 1455 + unsigned int ftype, i, adaption, prio, n1, k; 1456 1456 + 1457 1457 + i = FIELD_GET(PN_I_CL_FIELD_FTYPE, params->i_cl_bits); 1458 1458 + adaption = FIELD_GET(PN_I_CL_FIELD_ADAPTION, params->i_cl_bits) + 1; 1459 1459 + prio = FIELD_GET(PN_P_FIELD_PRIO, params->p_bits); 1460 1460 + n1 = FIELD_GET(PN_N_FIELD_N1, get_unaligned_le16(&params->n_bits)); 1461 1461 + k = FIELD_GET(PN_K_FIELD_K, params->k_bits); 1462 1462 + 1463 1463 + if (n1 < MIN_MTU) { 1464 1464 + if (debug & DBG_ERRORS) 1465 1465 + pr_info("%s N1 out of range in PN\n", __func__); 1466 1466 + return -EINVAL; 1467 1467 + } 1468 1468 + 1469 1469 + switch (i) { 1470 1470 + case 0x00: 1471 1471 + ftype = UIH; 1472 1472 + break; 1473 1473 + case 0x01: 1474 1474 + ftype = UI; 1475 1475 + break; 1476 1476 + case 0x02: /* I frames are not supported */ 1477 1477 + if (debug & DBG_ERRORS) 1478 1478 + pr_info("%s unsupported I frame request in PN\n", 1479 1479 + __func__); 1480 1480 + return -EINVAL; 1481 1481 + default: 1482 1482 + if (debug & DBG_ERRORS) 1483 1483 + pr_info("%s i out of range in PN\n", __func__); 1484 1484 + return -EINVAL; 1485 1485 + } 1486 1486 + 1487 1487 + if (!cr && gsm->initiator) { 1488 1488 + if (adaption != dlci->adaption) { 1489 1489 + if (debug & DBG_ERRORS) 1490 1490 + pr_info("%s invalid adaption %d in PN\n", 1491 1491 + __func__, adaption); 1492 1492 + return -EINVAL; 1493 1493 + } 1494 1494 + if (prio != dlci->prio) { 1495 1495 + if (debug & DBG_ERRORS) 1496 1496 + pr_info("%s invalid priority %d in PN", 1497 1497 + __func__, prio); 1498 1498 + return -EINVAL; 1499 1499 + } 1500 1500 + if (n1 > gsm->mru || n1 > dlci->mtu) { 1501 1501 + /* We requested a frame size but the other party wants 1502 1502 + * to send larger frames. The standard allows only a 1503 1503 + * smaller response value than requested (5.4.6.3.1). 1504 1504 + */ 1505 1505 + if (debug & DBG_ERRORS) 1506 1506 + pr_info("%s invalid N1 %d in PN\n", __func__, 1507 1507 + n1); 1508 1508 + return -EINVAL; 1509 1509 + } 1510 1510 + dlci->mtu = n1; 1511 1511 + if (ftype != dlci->ftype) { 1512 1512 + if (debug & DBG_ERRORS) 1513 1513 + pr_info("%s invalid i %d in PN\n", __func__, i); 1514 1514 + return -EINVAL; 1515 1515 + } 1516 1516 + if (ftype != UI && ftype != UIH && k > dlci->k) { 1517 1517 + if (debug & DBG_ERRORS) 1518 1518 + pr_info("%s invalid k %d in PN\n", __func__, k); 1519 1519 + return -EINVAL; 1520 1520 + } 1521 1521 + dlci->k = k; 1522 1522 + } else if (cr && !gsm->initiator) { 1523 1523 + /* Only convergence layer type 1 and 2 are supported. */ 1524 1524 + if (adaption != 1 && adaption != 2) { 1525 1525 + if (debug & DBG_ERRORS) 1526 1526 + pr_info("%s invalid adaption %d in PN\n", 1527 1527 + __func__, adaption); 1528 1528 + return -EINVAL; 1529 1529 + } 1530 1530 + dlci->adaption = adaption; 1531 1531 + if (n1 > gsm->mru) { 1532 1532 + /* Propose a smaller value */ 1533 1533 + dlci->mtu = gsm->mru; 1534 1534 + } else if (n1 > MAX_MTU) { 1535 1535 + /* Propose a smaller value */ 1536 1536 + dlci->mtu = MAX_MTU; 1537 1537 + } else { 1538 1538 + dlci->mtu = n1; 1539 1539 + } 1540 1540 + dlci->prio = prio; 1541 1541 + dlci->ftype = ftype; 1542 1542 + dlci->k = k; 1543 1543 + } else { 1544 1544 + return -EINVAL; 1545 1545 + } 1546 1546 + 1547 1547 + return 0; 1548 1548 + } 1549 1549 + 1550 1550 + /** 1537 1551 * gsm_control_modem - modem status received 1538 1552 * @gsm: GSM channel 1539 1553 * @data: data following command ··· 1694 1488 tty_kref_put(tty); 1695 1489 } 1696 1490 gsm_control_reply(gsm, CMD_MSC, data, clen); 1491 1491 + } 1492 1492 + 1493 1493 + /** 1494 1494 + * gsm_control_negotiation - parameter negotiation received 1495 1495 + * @gsm: GSM channel 1496 1496 + * @cr: command/response flag 1497 1497 + * @data: data following command 1498 1498 + * @dlen: data length 1499 1499 + * 1500 1500 + * We have received a parameter negotiation message. This is used by 1501 1501 + * the GSM mux protocol to configure protocol parameters for a new DLCI. 1502 1502 + */ 1503 1503 + static void gsm_control_negotiation(struct gsm_mux *gsm, unsigned int cr, 1504 1504 + const u8 *data, unsigned int dlen) 1505 1505 + { 1506 1506 + unsigned int addr; 1507 1507 + struct gsm_dlci_param_bits pn_reply; 1508 1508 + struct gsm_dlci *dlci; 1509 1509 + struct gsm_dlci_param_bits *params; 1510 1510 + 1511 1511 + if (dlen < sizeof(struct gsm_dlci_param_bits)) 1512 1512 + return; 1513 1513 + 1514 1514 + /* Invalid DLCI? */ 1515 1515 + params = (struct gsm_dlci_param_bits *)data; 1516 1516 + addr = FIELD_GET(PN_D_FIELD_DLCI, params->d_bits); 1517 1517 + if (addr == 0 || addr >= NUM_DLCI || !gsm->dlci[addr]) 1518 1518 + return; 1519 1519 + dlci = gsm->dlci[addr]; 1520 1520 + 1521 1521 + /* Too late for parameter negotiation? */ 1522 1522 + if ((!cr && dlci->state == DLCI_OPENING) || dlci->state == DLCI_OPEN) 1523 1523 + return; 1524 1524 + 1525 1525 + /* Process the received parameters */ 1526 1526 + if (gsm_process_negotiation(gsm, addr, cr, params) != 0) { 1527 1527 + /* Negotiation failed. Close the link. */ 1528 1528 + if (debug & DBG_ERRORS) 1529 1529 + pr_info("%s PN failed\n", __func__); 1530 1530 + gsm_dlci_close(dlci); 1531 1531 + return; 1532 1532 + } 1533 1533 + 1534 1534 + if (cr) { 1535 1535 + /* Reply command with accepted parameters. */ 1536 1536 + if (gsm_encode_params(dlci, &pn_reply) == 0) 1537 1537 + gsm_control_reply(gsm, CMD_PN, (const u8 *)&pn_reply, 1538 1538 + sizeof(pn_reply)); 1539 1539 + else if (debug & DBG_ERRORS) 1540 1540 + pr_info("%s PN invalid\n", __func__); 1541 1541 + } else if (dlci->state == DLCI_CONFIGURE) { 1542 1542 + /* Proceed with link setup by sending SABM before UA */ 1543 1543 + dlci->state = DLCI_OPENING; 1544 1544 + gsm_command(gsm, dlci->addr, SABM|PF); 1545 1545 + mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 1546 1546 + } else { 1547 1547 + if (debug & DBG_ERRORS) 1548 1548 + pr_info("%s PN in invalid state\n", __func__); 1549 1549 + } 1697 1550 } 1698 1551 1699 1552 /** ··· 1864 1599 /* Modem wishes to enter power saving state */ 1865 1600 gsm_control_reply(gsm, CMD_PSC, NULL, 0); 1866 1601 break; 1602 1602 + /* Optional commands */ 1603 1603 + case CMD_PN: 1604 1604 + /* Modem sends a parameter negotiation command */ 1605 1605 + gsm_control_negotiation(gsm, 1, data, clen); 1606 1606 + break; 1867 1607 /* Optional unsupported commands */ 1868 1868 - case CMD_PN: /* Parameter negotiation */ 1869 1608 case CMD_RPN: /* Remote port negotiation */ 1870 1609 case CMD_SNC: /* Service negotiation command */ 1871 1610 default: ··· 1902 1633 spin_lock_irqsave(&gsm->control_lock, flags); 1903 1634 1904 1635 ctrl = gsm->pending_cmd; 1905 1905 - /* Does the reply match our command */ 1906 1636 command |= 1; 1637 1637 + /* Does the reply match our command */ 1907 1638 if (ctrl != NULL && (command == ctrl->cmd || command == CMD_NSC)) { 1908 1639 /* Our command was replied to, kill the retry timer */ 1909 1640 del_timer(&gsm->t2_timer); ··· 1913 1644 ctrl->error = -EOPNOTSUPP; 1914 1645 ctrl->done = 1; 1915 1646 wake_up(&gsm->event); 1647 1647 + /* Or did we receive the PN response to our PN command */ 1648 1648 + } else if (command == CMD_PN) { 1649 1649 + gsm_control_negotiation(gsm, 0, data, clen); 1916 1650 } 1917 1651 spin_unlock_irqrestore(&gsm->control_lock, flags); 1918 1652 } ··· 2094 1822 } 2095 1823 2096 1824 /** 1825 1825 + * gsm_dlci_negotiate - start parameter negotiation 1826 1826 + * @dlci: DLCI to open 1827 1827 + * 1828 1828 + * Starts the parameter negotiation for the new DLCI. This needs to be done 1829 1829 + * before the DLCI initialized the channel via SABM. 1830 1830 + */ 1831 1831 + static int gsm_dlci_negotiate(struct gsm_dlci *dlci) 1832 1832 + { 1833 1833 + struct gsm_mux *gsm = dlci->gsm; 1834 1834 + struct gsm_dlci_param_bits params; 1835 1835 + int ret; 1836 1836 + 1837 1837 + ret = gsm_encode_params(dlci, &params); 1838 1838 + if (ret != 0) 1839 1839 + return ret; 1840 1840 + 1841 1841 + /* We cannot asynchronous wait for the command response with 1842 1842 + * gsm_command() and gsm_control_wait() at this point. 1843 1843 + */ 1844 1844 + ret = gsm_control_command(gsm, CMD_PN, (const u8 *)&params, 1845 1845 + sizeof(params)); 1846 1846 + 1847 1847 + return ret; 1848 1848 + } 1849 1849 + 1850 1850 + /** 2097 1851 * gsm_dlci_t1 - T1 timer expiry 2098 1852 * @t: timer contained in the DLCI that opened 2099 1853 * ··· 2140 1842 struct gsm_mux *gsm = dlci->gsm; 2141 1843 2142 1844 switch (dlci->state) { 1845 1845 + case DLCI_CONFIGURE: 1846 1846 + if (dlci->retries && gsm_dlci_negotiate(dlci) == 0) { 1847 1847 + dlci->retries--; 1848 1848 + mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 1849 1849 + } else { 1850 1850 + gsm_dlci_begin_close(dlci); /* prevent half open link */ 1851 1851 + } 1852 1852 + break; 2143 1853 case DLCI_OPENING: 2144 1854 if (dlci->retries) { 2145 1855 dlci->retries--; ··· 2186 1880 * to the modem which should then reply with a UA or ADM, at which point 2187 1881 * we will move into open state. Opening is done asynchronously with retry 2188 1882 * running off timers and the responses. 1883 1883 + * Parameter negotiation is performed before SABM if required. 2189 1884 */ 2190 1885 2191 1886 static void gsm_dlci_begin_open(struct gsm_dlci *dlci) 2192 1887 { 2193 2193 - struct gsm_mux *gsm = dlci->gsm; 2194 2194 - if (dlci->state == DLCI_OPEN || dlci->state == DLCI_OPENING) 1888 1888 + struct gsm_mux *gsm = dlci ? dlci->gsm : NULL; 1889 1889 + bool need_pn = false; 1890 1890 + 1891 1891 + if (!gsm) 2195 1892 return; 2196 2196 - dlci->retries = gsm->n2; 2197 2197 - dlci->state = DLCI_OPENING; 2198 2198 - gsm_command(dlci->gsm, dlci->addr, SABM|PF); 2199 2199 - mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 1893 1893 + 1894 1894 + if (dlci->addr != 0) { 1895 1895 + if (gsm->adaption != 1 || gsm->adaption != dlci->adaption) 1896 1896 + need_pn = true; 1897 1897 + if (dlci->prio != (roundup(dlci->addr + 1, 8) - 1)) 1898 1898 + need_pn = true; 1899 1899 + if (gsm->ftype != dlci->ftype) 1900 1900 + need_pn = true; 1901 1901 + } 1902 1902 + 1903 1903 + switch (dlci->state) { 1904 1904 + case DLCI_CLOSED: 1905 1905 + case DLCI_CLOSING: 1906 1906 + dlci->retries = gsm->n2; 1907 1907 + if (!need_pn) { 1908 1908 + dlci->state = DLCI_OPENING; 1909 1909 + gsm_command(gsm, dlci->addr, SABM|PF); 1910 1910 + } else { 1911 1911 + /* Configure DLCI before setup */ 1912 1912 + dlci->state = DLCI_CONFIGURE; 1913 1913 + if (gsm_dlci_negotiate(dlci) != 0) { 1914 1914 + gsm_dlci_close(dlci); 1915 1915 + return; 1916 1916 + } 1917 1917 + } 1918 1918 + mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 1919 1919 + break; 1920 1920 + default: 1921 1921 + break; 1922 1922 + } 2200 1923 } 2201 1924 2202 1925 /** ··· 2413 2078 dlci->gsm = gsm; 2414 2079 dlci->addr = addr; 2415 2080 dlci->adaption = gsm->adaption; 2081 2081 + dlci->mtu = gsm->mtu; 2082 2082 + if (addr == 0) 2083 2083 + dlci->prio = 0; 2084 2084 + else 2085 2085 + dlci->prio = roundup(addr + 1, 8) - 1; 2086 2086 + dlci->ftype = gsm->ftype; 2087 2087 + dlci->k = gsm->k; 2416 2088 dlci->state = DLCI_CLOSED; 2417 2089 if (addr) { 2418 2090 dlci->data = gsm_dlci_data; ··· 2994 2652 2995 2653 gsm->t1 = T1; 2996 2654 gsm->t2 = T2; 2655 2655 + gsm->t3 = T3; 2997 2656 gsm->n2 = N2; 2657 2657 + gsm->k = K; 2998 2658 gsm->ftype = UIH; 2999 2659 gsm->adaption = 1; 3000 2660 gsm->encoding = GSM_ADV_OPT; ··· 3036 2692 c->initiator = gsm->initiator; 3037 2693 c->t1 = gsm->t1; 3038 2694 c->t2 = gsm->t2; 3039 3039 - c->t3 = 0; /* Not supported */ 2695 2695 + c->t3 = gsm->t3; 3040 2696 c->n2 = gsm->n2; 3041 2697 if (gsm->ftype == UIH) 3042 2698 c->i = 1; ··· 3045 2701 pr_debug("Ftype %d i %d\n", gsm->ftype, c->i); 3046 2702 c->mru = gsm->mru; 3047 2703 c->mtu = gsm->mtu; 3048 3048 - c->k = 0; 2704 2704 + c->k = gsm->k; 3049 2705 } 3050 2706 3051 2707 static int gsm_config(struct gsm_mux *gsm, struct gsm_config *c) ··· 3058 2714 if ((c->adaption != 1 && c->adaption != 2) || c->k) 3059 2715 return -EOPNOTSUPP; 3060 2716 /* Check the MRU/MTU range looks sane */ 3061 3061 - if (c->mru > MAX_MRU || c->mtu > MAX_MTU || c->mru < 8 || c->mtu < 8) 2717 2717 + if (c->mru < MIN_MTU || c->mtu < MIN_MTU) 2718 2718 + return -EINVAL; 2719 2719 + if (c->mru > MAX_MRU || c->mtu > MAX_MTU) 2720 2720 + return -EINVAL; 2721 2721 + if (c->t3 > MAX_T3) 3062 2722 return -EINVAL; 3063 2723 if (c->n2 > 255) 3064 2724 return -EINVAL; 3065 2725 if (c->encapsulation > 1) /* Basic, advanced, no I */ 3066 2726 return -EINVAL; 3067 2727 if (c->initiator > 1) 2728 2728 + return -EINVAL; 2729 2729 + if (c->k > MAX_WINDOW_SIZE) 3068 2730 return -EINVAL; 3069 2731 if (c->i == 0 || c->i > 2) /* UIH and UI only */ 3070 2732 return -EINVAL; ··· 3119 2769 gsm->t1 = c->t1; 3120 2770 if (c->t2) 3121 2771 gsm->t2 = c->t2; 2772 2772 + if (c->t3) 2773 2773 + gsm->t3 = c->t3; 2774 2774 + if (c->k) 2775 2775 + gsm->k = c->k; 3122 2776 3123 2777 /* 3124 2778 * FIXME: We need to separate activation/deactivation from adding ··· 3653 3299 pr_err("alloc_netdev failed\n"); 3654 3300 return -ENOMEM; 3655 3301 } 3656 3656 - net->mtu = dlci->gsm->mtu; 3657 3657 - net->min_mtu = 8; 3658 3658 - net->max_mtu = dlci->gsm->mtu; 3302 3302 + net->mtu = dlci->mtu; 3303 3303 + net->min_mtu = MIN_MTU; 3304 3304 + net->max_mtu = dlci->mtu; 3659 3305 mux_net = netdev_priv(net); 3660 3306 mux_net->dlci = dlci; 3661 3307 kref_init(&mux_net->ref);

+3 -3

drivers/tty/n_tty.c

reviewed

··· 2130 2130 ssize_t retval = 0; 2131 2131 long timeout; 2132 2132 bool packet; 2133 2133 - size_t tail; 2133 2133 + size_t old_tail; 2134 2134 2135 2135 /* 2136 2136 * Is this a continuation of a read started earler? ··· 2193 2193 } 2194 2194 2195 2195 packet = tty->ctrl.packet; 2196 2196 - tail = ldata->read_tail; 2196 2196 + old_tail = ldata->read_tail; 2197 2197 2198 2198 add_wait_queue(&tty->read_wait, &wait); 2199 2199 while (nr) { ··· 2282 2282 if (time) 2283 2283 timeout = time; 2284 2284 } 2285 2285 - if (tail != ldata->read_tail) 2285 2285 + if (old_tail != ldata->read_tail) 2286 2286 n_tty_kick_worker(tty); 2287 2287 up_read(&tty->termios_rwsem); 2288 2288

+5 -27

drivers/tty/serial/21285.c

reviewed

··· 154 154 static irqreturn_t serial21285_tx_chars(int irq, void *dev_id) 155 155 { 156 156 struct uart_port *port = dev_id; 157 157 - struct circ_buf *xmit = &port->state->xmit; 158 158 - int count = 256; 157 157 + u8 ch; 159 158 160 160 - if (port->x_char) { 161 161 - *CSR_UARTDR = port->x_char; 162 162 - port->icount.tx++; 163 163 - port->x_char = 0; 164 164 - goto out; 165 165 - } 166 166 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 167 167 - serial21285_stop_tx(port); 168 168 - goto out; 169 169 - } 159 159 + uart_port_tx_limited(port, ch, 256, 160 160 + !(*CSR_UARTFLG & 0x20), 161 161 + *CSR_UARTDR = ch, 162 162 + ({})); 170 163 171 171 - do { 172 172 - *CSR_UARTDR = xmit->buf[xmit->tail]; 173 173 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 174 174 - port->icount.tx++; 175 175 - if (uart_circ_empty(xmit)) 176 176 - break; 177 177 - } while (--count > 0 && !(*CSR_UARTFLG & 0x20)); 178 178 - 179 179 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 180 180 - uart_write_wakeup(port); 181 181 - 182 182 - if (uart_circ_empty(xmit)) 183 183 - serial21285_stop_tx(port); 184 184 - 185 185 - out: 186 164 return IRQ_HANDLED; 187 165 } 188 166

+10 -4

drivers/tty/serial/8250/8250_bcm7271.c

reviewed

··· 425 425 426 426 priv->dma.tx_err = 0; 427 427 memcpy(priv->tx_buf, &xmit->buf[xmit->tail], tx_size); 428 428 - xmit->tail += tx_size; 429 429 - xmit->tail &= UART_XMIT_SIZE - 1; 430 430 - p->port.icount.tx += tx_size; 428 428 + uart_xmit_advance(&p->port, tx_size); 431 429 432 430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 433 431 uart_write_wakeup(&p->port); ··· 1210 1212 1211 1213 static int __init brcmuart_init(void) 1212 1214 { 1215 1215 + int ret; 1216 1216 + 1213 1217 brcmuart_debugfs_root = debugfs_create_dir( 1214 1218 brcmuart_platform_driver.driver.name, NULL); 1215 1215 - return platform_driver_register(&brcmuart_platform_driver); 1219 1219 + ret = platform_driver_register(&brcmuart_platform_driver); 1220 1220 + if (ret) { 1221 1221 + debugfs_remove_recursive(brcmuart_debugfs_root); 1222 1222 + return ret; 1223 1223 + } 1224 1224 + 1225 1225 + return 0; 1216 1226 } 1217 1227 module_init(brcmuart_init); 1218 1228

+3 -2

drivers/tty/serial/8250/8250_core.c

reviewed

··· 32 32 #include <linux/nmi.h> 33 33 #include <linux/mutex.h> 34 34 #include <linux/slab.h> 35 35 + #include <linux/string_helpers.h> 35 36 #include <linux/uaccess.h> 36 37 #include <linux/io.h> 37 38 #ifdef CONFIG_SPARC ··· 1176 1175 1177 1176 serial8250_isa_init_ports(); 1178 1177 1179 1179 - pr_info("Serial: 8250/16550 driver, %d ports, IRQ sharing %sabled\n", 1180 1180 - nr_uarts, share_irqs ? "en" : "dis"); 1178 1178 + pr_info("Serial: 8250/16550 driver, %d ports, IRQ sharing %s\n", 1179 1179 + nr_uarts, str_enabled_disabled(share_irqs)); 1181 1180 1182 1181 #ifdef CONFIG_SPARC 1183 1182 ret = sunserial_register_minors(&serial8250_reg, UART_NR);

+16 -3

drivers/tty/serial/8250/8250_dma.c

reviewed

··· 38 38 spin_unlock_irqrestore(&p->port.lock, flags); 39 39 } 40 40 41 41 - static void __dma_rx_complete(void *param) 41 41 + static void __dma_rx_complete(struct uart_8250_port *p) 42 42 { 43 43 - struct uart_8250_port *p = param; 44 43 struct uart_8250_dma *dma = p->dma; 45 44 struct tty_port *tty_port = &p->port.state->port; 46 45 struct dma_tx_state state; ··· 54 55 p->port.icount.rx += count; 55 56 56 57 tty_flip_buffer_push(tty_port); 58 58 + } 59 59 + 60 60 + static void dma_rx_complete(void *param) 61 61 + { 62 62 + struct uart_8250_port *p = param; 63 63 + struct uart_8250_dma *dma = p->dma; 64 64 + unsigned long flags; 65 65 + 66 66 + __dma_rx_complete(p); 67 67 + 68 68 + spin_lock_irqsave(&p->port.lock, flags); 69 69 + if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR)) 70 70 + p->dma->rx_dma(p); 71 71 + spin_unlock_irqrestore(&p->port.lock, flags); 57 72 } 58 73 59 74 int serial8250_tx_dma(struct uart_8250_port *p) ··· 143 130 return -EBUSY; 144 131 145 132 dma->rx_running = 1; 146 146 - desc->callback = __dma_rx_complete; 133 133 + desc->callback = dma_rx_complete; 147 134 desc->callback_param = p; 148 135 149 136 dma->rx_cookie = dmaengine_submit(desc);

+29 -3

drivers/tty/serial/8250/8250_ingenic.c

reviewed

··· 87 87 dev->port.uartclk = be32_to_cpup(prop); 88 88 } 89 89 90 90 - static int __init ingenic_early_console_setup(struct earlycon_device *dev, 90 90 + static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev, 91 91 const char *opt) 92 92 { 93 93 struct uart_port *port = &dev->port; ··· 102 102 103 103 uart_parse_options(opt, &baud, &parity, &bits, &flow); 104 104 } 105 105 - 106 106 - ingenic_early_console_setup_clock(dev); 107 105 108 106 if (dev->baud) 109 107 baud = dev->baud; ··· 127 129 return 0; 128 130 } 129 131 132 132 + static int __init ingenic_early_console_setup(struct earlycon_device *dev, 133 133 + const char *opt) 134 134 + { 135 135 + ingenic_early_console_setup_clock(dev); 136 136 + 137 137 + return ingenic_earlycon_setup_tail(dev, opt); 138 138 + } 139 139 + 140 140 + static int __init jz4750_early_console_setup(struct earlycon_device *dev, 141 141 + const char *opt) 142 142 + { 143 143 + /* 144 144 + * JZ4750/55/60 have an optional /2 divider between the EXT 145 145 + * oscillator and some peripherals including UART, which will 146 146 + * be enabled if using a 24 MHz oscillator, and disabled when 147 147 + * using a 12 MHz oscillator. 148 148 + */ 149 149 + ingenic_early_console_setup_clock(dev); 150 150 + if (dev->port.uartclk >= 16000000) 151 151 + dev->port.uartclk /= 2; 152 152 + 153 153 + return ingenic_earlycon_setup_tail(dev, opt); 154 154 + } 155 155 + 130 156 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart", 131 157 ingenic_early_console_setup); 158 158 + 159 159 + OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart", 160 160 + jz4750_early_console_setup); 132 161 133 162 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart", 134 163 ingenic_early_console_setup); ··· 353 328 354 329 static const struct of_device_id of_match[] = { 355 330 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config }, 331 331 + { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config }, 356 332 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config }, 357 333 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config }, 358 334 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },

+82 -3

drivers/tty/serial/8250/8250_omap.c

reviewed

··· 44 44 #define UART_HAS_EFR2 BIT(4) 45 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 47 + #define UART_HAS_NATIVE_RS485 BIT(7) 47 48 48 49 #define OMAP_UART_FCR_RX_TRIG 6 49 50 #define OMAP_UART_FCR_TX_TRIG 4 ··· 102 101 #define UART_OMAP_IER2 0x1B 103 102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 103 104 104 + /* Mode Definition Register 3 */ 105 105 + #define UART_OMAP_MDR3 0x20 106 106 + #define UART_OMAP_MDR3_DIR_POL BIT(3) 107 107 + #define UART_OMAP_MDR3_DIR_EN BIT(4) 108 108 + 105 109 /* Enhanced features register 2 */ 106 110 #define UART_OMAP_EFR2 0x23 107 111 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) ··· 118 112 int line; 119 113 u8 habit; 120 114 u8 mdr1; 115 115 + u8 mdr3; 121 116 u8 efr; 122 117 u8 scr; 123 118 u8 wer; ··· 353 346 354 347 __omap8250_set_mctrl(&up->port, up->port.mctrl); 355 348 356 356 - if (up->port.rs485.flags & SER_RS485_ENABLED) 349 349 + serial_out(up, UART_OMAP_MDR3, priv->mdr3); 350 350 + 351 351 + if (up->port.rs485.flags & SER_RS485_ENABLED && 352 352 + up->port.rs485_config == serial8250_em485_config) 357 353 serial8250_em485_stop_tx(up); 358 354 } 359 355 ··· 802 792 803 793 pm_runtime_mark_last_busy(port->dev); 804 794 pm_runtime_put_autosuspend(port->dev); 795 795 + } 796 796 + 797 797 + static int omap8250_rs485_config(struct uart_port *port, 798 798 + struct ktermios *termios, 799 799 + struct serial_rs485 *rs485) 800 800 + { 801 801 + struct omap8250_priv *priv = port->private_data; 802 802 + struct uart_8250_port *up = up_to_u8250p(port); 803 803 + u32 fixed_delay_rts_before_send = 0; 804 804 + u32 fixed_delay_rts_after_send = 0; 805 805 + unsigned int baud; 806 806 + 807 807 + /* 808 808 + * There is a fixed delay of 3 bit clock cycles after the TX shift 809 809 + * register is going empty to allow time for the stop bit to transition 810 810 + * through the transceiver before direction is changed to receive. 811 811 + * 812 812 + * Additionally there appears to be a 1 bit clock delay between writing 813 813 + * to the THR register and transmission of the start bit, per page 8783 814 814 + * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 815 815 + */ 816 816 + if (priv->quot) { 817 817 + if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 818 818 + baud = port->uartclk / (16 * priv->quot); 819 819 + else 820 820 + baud = port->uartclk / (13 * priv->quot); 821 821 + 822 822 + fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 823 823 + fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 824 824 + } 825 825 + 826 826 + /* 827 827 + * Fall back to RS485 software emulation if the UART is missing 828 828 + * hardware support, if the device tree specifies an mctrl_gpio 829 829 + * (indicates that RTS is unavailable due to a pinmux conflict) 830 830 + * or if the requested delays exceed the fixed hardware delays. 831 831 + */ 832 832 + if (!(priv->habit & UART_HAS_NATIVE_RS485) || 833 833 + mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 834 834 + rs485->delay_rts_after_send > fixed_delay_rts_after_send || 835 835 + rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 836 836 + priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 837 837 + serial_out(up, UART_OMAP_MDR3, priv->mdr3); 838 838 + 839 839 + port->rs485_config = serial8250_em485_config; 840 840 + return serial8250_em485_config(port, termios, rs485); 841 841 + } 842 842 + 843 843 + rs485->delay_rts_after_send = fixed_delay_rts_after_send; 844 844 + rs485->delay_rts_before_send = fixed_delay_rts_before_send; 845 845 + 846 846 + if (rs485->flags & SER_RS485_ENABLED) 847 847 + priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 848 848 + else 849 849 + priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 850 850 + 851 851 + /* 852 852 + * Retain same polarity semantics as RS485 software emulation, 853 853 + * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 854 854 + */ 855 855 + if (rs485->flags & SER_RS485_RTS_ON_SEND) 856 856 + priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 857 857 + else 858 858 + priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 859 859 + 860 860 + serial_out(up, UART_OMAP_MDR3, priv->mdr3); 861 861 + 862 862 + return 0; 805 863 } 806 864 807 865 #ifdef CONFIG_SERIAL_8250_DMA ··· 1321 1243 static struct omap8250_platdata am654_platdata = { 1322 1244 .dma_params = &am654_dma, 1323 1245 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1324 1324 - UART_RX_TIMEOUT_QUIRK, 1246 1246 + UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1325 1247 }; 1326 1248 1327 1249 static struct omap8250_platdata am33xx_platdata = { ··· 1414 1336 up.port.shutdown = omap_8250_shutdown; 1415 1337 up.port.throttle = omap_8250_throttle; 1416 1338 up.port.unthrottle = omap_8250_unthrottle; 1417 1417 - up.port.rs485_config = serial8250_em485_config; 1339 1339 + up.port.rs485_config = omap8250_rs485_config; 1340 1340 + /* same rs485_supported for software emulation and native RS485 */ 1418 1341 up.port.rs485_supported = serial8250_em485_supported; 1419 1342 up.rs485_start_tx = serial8250_em485_start_tx; 1420 1343 up.rs485_stop_tx = serial8250_em485_stop_tx;

+1 -2

drivers/tty/serial/8250/8250_port.c

reviewed

··· 1842 1842 */ 1843 1843 serial_in(up, UART_SCR); 1844 1844 } 1845 1845 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1846 1846 - port->icount.tx++; 1845 1845 + uart_xmit_advance(port, 1); 1847 1846 if (uart_circ_empty(xmit)) 1848 1847 break; 1849 1848 if ((up->capabilities & UART_CAP_HFIFO) &&

+2

drivers/tty/serial/Kconfig

reviewed

··· 958 958 config SERIAL_SIFIVE 959 959 tristate "SiFive UART support" 960 960 depends on OF 961 961 + default SOC_SIFIVE || SOC_CANAAN 961 962 select SERIAL_CORE 962 963 help 963 964 Select this option if you are building a kernel for a device that ··· 968 967 config SERIAL_SIFIVE_CONSOLE 969 968 bool "Console on SiFive UART" 970 969 depends on SERIAL_SIFIVE=y 970 970 + default SOC_SIFIVE || SOC_CANAAN 971 971 select SERIAL_CORE_CONSOLE 972 972 select SERIAL_EARLYCON 973 973 help

+34 -78

drivers/tty/serial/altera_jtaguart.c

reviewed

··· 50 50 #define ALTERA_JTAGUART_CONTROL_AC_MSK 0x00000400 51 51 #define ALTERA_JTAGUART_CONTROL_WSPACE_MSK 0xFFFF0000 52 52 53 53 - /* 54 54 - * Local per-uart structure. 55 55 - */ 56 56 - struct altera_jtaguart { 57 57 - struct uart_port port; 58 58 - unsigned int sigs; /* Local copy of line sigs */ 59 59 - unsigned long imr; /* Local IMR mirror */ 60 60 - }; 61 61 - 62 53 static unsigned int altera_jtaguart_tx_space(struct uart_port *port, u32 *ctlp) 63 54 { 64 55 u32 ctl = readl(port->membase + ALTERA_JTAGUART_CONTROL_REG); ··· 76 85 77 86 static void altera_jtaguart_start_tx(struct uart_port *port) 78 87 { 79 79 - struct altera_jtaguart *pp = 80 80 - container_of(port, struct altera_jtaguart, port); 81 81 - 82 82 - pp->imr |= ALTERA_JTAGUART_CONTROL_WE_MSK; 83 83 - writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 88 88 + port->read_status_mask |= ALTERA_JTAGUART_CONTROL_WE_MSK; 89 89 + writel(port->read_status_mask, 90 90 + port->membase + ALTERA_JTAGUART_CONTROL_REG); 84 91 } 85 92 86 93 static void altera_jtaguart_stop_tx(struct uart_port *port) 87 94 { 88 88 - struct altera_jtaguart *pp = 89 89 - container_of(port, struct altera_jtaguart, port); 90 90 - 91 91 - pp->imr &= ~ALTERA_JTAGUART_CONTROL_WE_MSK; 92 92 - writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 95 95 + port->read_status_mask &= ~ALTERA_JTAGUART_CONTROL_WE_MSK; 96 96 + writel(port->read_status_mask, 97 97 + port->membase + ALTERA_JTAGUART_CONTROL_REG); 93 98 } 94 99 95 100 static void altera_jtaguart_stop_rx(struct uart_port *port) 96 101 { 97 97 - struct altera_jtaguart *pp = 98 98 - container_of(port, struct altera_jtaguart, port); 99 99 - 100 100 - pp->imr &= ~ALTERA_JTAGUART_CONTROL_RE_MSK; 101 101 - writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 102 102 + port->read_status_mask &= ~ALTERA_JTAGUART_CONTROL_RE_MSK; 103 103 + writel(port->read_status_mask, 104 104 + port->membase + ALTERA_JTAGUART_CONTROL_REG); 102 105 } 103 106 104 107 static void altera_jtaguart_break_ctl(struct uart_port *port, int break_state) ··· 108 123 tty_termios_copy_hw(termios, old); 109 124 } 110 125 111 111 - static void altera_jtaguart_rx_chars(struct altera_jtaguart *pp) 126 126 + static void altera_jtaguart_rx_chars(struct uart_port *port) 112 127 { 113 113 - struct uart_port *port = &pp->port; 114 114 - unsigned char ch, flag; 128 128 + unsigned char ch; 115 129 unsigned long status; 116 130 117 131 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & 118 132 ALTERA_JTAGUART_DATA_RVALID_MSK) { 119 133 ch = status & ALTERA_JTAGUART_DATA_DATA_MSK; 120 120 - flag = TTY_NORMAL; 121 134 port->icount.rx++; 122 135 123 136 if (uart_handle_sysrq_char(port, ch)) 124 137 continue; 125 125 - uart_insert_char(port, 0, 0, ch, flag); 138 138 + uart_insert_char(port, 0, 0, ch, TTY_NORMAL); 126 139 } 127 140 128 141 tty_flip_buffer_push(&port->state->port); 129 142 } 130 143 131 131 - static void altera_jtaguart_tx_chars(struct altera_jtaguart *pp) 144 144 + static void altera_jtaguart_tx_chars(struct uart_port *port) 132 145 { 133 133 - struct uart_port *port = &pp->port; 134 134 - struct circ_buf *xmit = &port->state->xmit; 135 135 - unsigned int pending, count; 146 146 + unsigned int count; 147 147 + u8 ch; 136 148 137 137 - if (port->x_char) { 138 138 - /* Send special char - probably flow control */ 139 139 - writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); 140 140 - port->x_char = 0; 141 141 - port->icount.tx++; 142 142 - return; 143 143 - } 149 149 + count = altera_jtaguart_tx_space(port, NULL); 144 150 145 145 - pending = uart_circ_chars_pending(xmit); 146 146 - if (pending > 0) { 147 147 - count = altera_jtaguart_tx_space(port, NULL); 148 148 - if (count > pending) 149 149 - count = pending; 150 150 - if (count > 0) { 151 151 - pending -= count; 152 152 - while (count--) { 153 153 - writel(xmit->buf[xmit->tail], 154 154 - port->membase + ALTERA_JTAGUART_DATA_REG); 155 155 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 156 156 - port->icount.tx++; 157 157 - } 158 158 - if (pending < WAKEUP_CHARS) 159 159 - uart_write_wakeup(port); 160 160 - } 161 161 - } 162 162 - 163 163 - if (pending == 0) 164 164 - altera_jtaguart_stop_tx(port); 151 151 + uart_port_tx_limited(port, ch, count, 152 152 + true, 153 153 + writel(ch, port->membase + ALTERA_JTAGUART_DATA_REG), 154 154 + ({})); 165 155 } 166 156 167 157 static irqreturn_t altera_jtaguart_interrupt(int irq, void *data) 168 158 { 169 159 struct uart_port *port = data; 170 170 - struct altera_jtaguart *pp = 171 171 - container_of(port, struct altera_jtaguart, port); 172 160 unsigned int isr; 173 161 174 162 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> 175 175 - ALTERA_JTAGUART_CONTROL_RI_OFF) & pp->imr; 163 163 + ALTERA_JTAGUART_CONTROL_RI_OFF) & port->read_status_mask; 176 164 177 165 spin_lock(&port->lock); 178 166 179 167 if (isr & ALTERA_JTAGUART_CONTROL_RE_MSK) 180 180 - altera_jtaguart_rx_chars(pp); 168 168 + altera_jtaguart_rx_chars(port); 181 169 if (isr & ALTERA_JTAGUART_CONTROL_WE_MSK) 182 182 - altera_jtaguart_tx_chars(pp); 170 170 + altera_jtaguart_tx_chars(port); 183 171 184 172 spin_unlock(&port->lock); 185 173 ··· 169 211 170 212 static int altera_jtaguart_startup(struct uart_port *port) 171 213 { 172 172 - struct altera_jtaguart *pp = 173 173 - container_of(port, struct altera_jtaguart, port); 174 214 unsigned long flags; 175 215 int ret; 176 216 ··· 183 227 spin_lock_irqsave(&port->lock, flags); 184 228 185 229 /* Enable RX interrupts now */ 186 186 - pp->imr = ALTERA_JTAGUART_CONTROL_RE_MSK; 187 187 - writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 230 230 + port->read_status_mask = ALTERA_JTAGUART_CONTROL_RE_MSK; 231 231 + writel(port->read_status_mask, 232 232 + port->membase + ALTERA_JTAGUART_CONTROL_REG); 188 233 189 234 spin_unlock_irqrestore(&port->lock, flags); 190 235 ··· 194 237 195 238 static void altera_jtaguart_shutdown(struct uart_port *port) 196 239 { 197 197 - struct altera_jtaguart *pp = 198 198 - container_of(port, struct altera_jtaguart, port); 199 240 unsigned long flags; 200 241 201 242 spin_lock_irqsave(&port->lock, flags); 202 243 203 244 /* Disable all interrupts now */ 204 204 - pp->imr = 0; 205 205 - writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 245 245 + port->read_status_mask = 0; 246 246 + writel(port->read_status_mask, 247 247 + port->membase + ALTERA_JTAGUART_CONTROL_REG); 206 248 207 249 spin_unlock_irqrestore(&port->lock, flags); 208 250 ··· 254 298 }; 255 299 256 300 #define ALTERA_JTAGUART_MAXPORTS 1 257 257 - static struct altera_jtaguart altera_jtaguart_ports[ALTERA_JTAGUART_MAXPORTS]; 301 301 + static struct uart_port altera_jtaguart_ports[ALTERA_JTAGUART_MAXPORTS]; 258 302 259 303 #if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE) 260 304 ··· 297 341 static void altera_jtaguart_console_write(struct console *co, const char *s, 298 342 unsigned int count) 299 343 { 300 300 - struct uart_port *port = &(altera_jtaguart_ports + co->index)->port; 344 344 + struct uart_port *port = &altera_jtaguart_ports[co->index]; 301 345 302 346 uart_console_write(port, s, count, altera_jtaguart_console_putc); 303 347 } ··· 309 353 310 354 if (co->index < 0 || co->index >= ALTERA_JTAGUART_MAXPORTS) 311 355 return -EINVAL; 312 312 - port = &altera_jtaguart_ports[co->index].port; 356 356 + port = &altera_jtaguart_ports[co->index]; 313 357 if (port->membase == NULL) 314 358 return -ENODEV; 315 359 return 0; ··· 389 433 if (i >= ALTERA_JTAGUART_MAXPORTS) 390 434 return -EINVAL; 391 435 392 392 - port = &altera_jtaguart_ports[i].port; 436 436 + port = &altera_jtaguart_ports[i]; 393 437 394 438 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 395 439 if (res_mem) ··· 433 477 if (i == -1) 434 478 i = 0; 435 479 436 436 - port = &altera_jtaguart_ports[i].port; 480 480 + port = &altera_jtaguart_ports[i]; 437 481 uart_remove_one_port(&altera_jtaguart_driver, port); 438 482 iounmap(port->membase); 439 483

+8 -26

drivers/tty/serial/altera_uart.c

reviewed

··· 247 247 248 248 static void altera_uart_tx_chars(struct uart_port *port) 249 249 { 250 250 - struct circ_buf *xmit = &port->state->xmit; 250 250 + u8 ch; 251 251 252 252 - if (port->x_char) { 253 253 - /* Send special char - probably flow control */ 254 254 - altera_uart_writel(port, port->x_char, ALTERA_UART_TXDATA_REG); 255 255 - port->x_char = 0; 256 256 - port->icount.tx++; 257 257 - return; 258 258 - } 259 259 - 260 260 - while (altera_uart_readl(port, ALTERA_UART_STATUS_REG) & 261 261 - ALTERA_UART_STATUS_TRDY_MSK) { 262 262 - if (xmit->head == xmit->tail) 263 263 - break; 264 264 - altera_uart_writel(port, xmit->buf[xmit->tail], 265 265 - ALTERA_UART_TXDATA_REG); 266 266 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 267 267 - port->icount.tx++; 268 268 - } 269 269 - 270 270 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 271 271 - uart_write_wakeup(port); 272 272 - 273 273 - if (uart_circ_empty(xmit)) 274 274 - altera_uart_stop_tx(port); 252 252 + uart_port_tx(port, ch, 253 253 + altera_uart_readl(port, ALTERA_UART_STATUS_REG) & 254 254 + ALTERA_UART_STATUS_TRDY_MSK, 255 255 + altera_uart_writel(port, ch, ALTERA_UART_TXDATA_REG)); 275 256 } 276 257 277 258 static irqreturn_t altera_uart_interrupt(int irq, void *data) 278 259 { 279 260 struct uart_port *port = data; 280 261 struct altera_uart *pp = container_of(port, struct altera_uart, port); 262 262 + unsigned long flags; 281 263 unsigned int isr; 282 264 283 265 isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr; 284 266 285 285 - spin_lock(&port->lock); 267 267 + spin_lock_irqsave(&port->lock, flags); 286 268 if (isr & ALTERA_UART_STATUS_RRDY_MSK) 287 269 altera_uart_rx_chars(port); 288 270 if (isr & ALTERA_UART_STATUS_TRDY_MSK) 289 271 altera_uart_tx_chars(port); 290 290 - spin_unlock(&port->lock); 272 272 + spin_unlock_irqrestore(&port->lock, flags); 291 273 292 274 return IRQ_RETVAL(isr); 293 275 }

+5 -27

drivers/tty/serial/amba-pl010.c

reviewed

··· 164 164 165 165 static void pl010_tx_chars(struct uart_port *port) 166 166 { 167 167 - struct circ_buf *xmit = &port->state->xmit; 168 168 - int count; 167 167 + u8 ch; 169 168 170 170 - if (port->x_char) { 171 171 - writel(port->x_char, port->membase + UART01x_DR); 172 172 - port->icount.tx++; 173 173 - port->x_char = 0; 174 174 - return; 175 175 - } 176 176 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 177 177 - pl010_stop_tx(port); 178 178 - return; 179 179 - } 180 180 - 181 181 - count = port->fifosize >> 1; 182 182 - do { 183 183 - writel(xmit->buf[xmit->tail], port->membase + UART01x_DR); 184 184 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 185 185 - port->icount.tx++; 186 186 - if (uart_circ_empty(xmit)) 187 187 - break; 188 188 - } while (--count > 0); 189 189 - 190 190 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 191 191 - uart_write_wakeup(port); 192 192 - 193 193 - if (uart_circ_empty(xmit)) 194 194 - pl010_stop_tx(port); 169 169 + uart_port_tx_limited(port, ch, port->fifosize >> 1, 170 170 + true, 171 171 + writel(ch, port->membase + UART01x_DR), 172 172 + ({})); 195 173 } 196 174 197 175 static void pl010_modem_status(struct uart_amba_port *uap)

+14 -3

drivers/tty/serial/amba-pl011.c

reviewed

··· 677 677 * Now we know that DMA will fire, so advance the ring buffer 678 678 * with the stuff we just dispatched. 679 679 */ 680 680 - xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 681 681 - uap->port.icount.tx += count; 680 680 + uart_xmit_advance(&uap->port, count); 682 681 683 682 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 684 683 uart_write_wakeup(&uap->port); ··· 1044 1045 */ 1045 1046 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1046 1047 { 1048 1048 + if (!uap->using_rx_dma) 1049 1049 + return; 1050 1050 + 1047 1051 /* FIXME. Just disable the DMA enable */ 1048 1052 uap->dmacr &= ~UART011_RXDMAE; 1049 1053 pl011_write(uap->dmacr, uap, REG_DMACR); ··· 1830 1828 static void pl011_unthrottle_rx(struct uart_port *port) 1831 1829 { 1832 1830 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1831 1831 + unsigned long flags; 1833 1832 1834 1834 - pl011_enable_interrupts(uap); 1833 1833 + spin_lock_irqsave(&uap->port.lock, flags); 1834 1834 + 1835 1835 + uap->im = UART011_RTIM; 1836 1836 + if (!pl011_dma_rx_running(uap)) 1837 1837 + uap->im |= UART011_RXIM; 1838 1838 + 1839 1839 + pl011_write(uap->im, uap, REG_IMSC); 1840 1840 + 1841 1841 + spin_unlock_irqrestore(&uap->port.lock, flags); 1835 1842 } 1836 1843 1837 1844 static int pl011_startup(struct uart_port *port)

+5 -29

drivers/tty/serial/apbuart.c

reviewed

··· 122 122 123 123 static void apbuart_tx_chars(struct uart_port *port) 124 124 { 125 125 - struct circ_buf *xmit = &port->state->xmit; 126 126 - int count; 125 125 + u8 ch; 127 126 128 128 - if (port->x_char) { 129 129 - UART_PUT_CHAR(port, port->x_char); 130 130 - port->icount.tx++; 131 131 - port->x_char = 0; 132 132 - return; 133 133 - } 134 134 - 135 135 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 136 136 - apbuart_stop_tx(port); 137 137 - return; 138 138 - } 139 139 - 140 140 - /* amba: fill FIFO */ 141 141 - count = port->fifosize >> 1; 142 142 - do { 143 143 - UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 144 144 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 145 145 - port->icount.tx++; 146 146 - if (uart_circ_empty(xmit)) 147 147 - break; 148 148 - } while (--count > 0); 149 149 - 150 150 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 151 151 - uart_write_wakeup(port); 152 152 - 153 153 - if (uart_circ_empty(xmit)) 154 154 - apbuart_stop_tx(port); 127 127 + uart_port_tx_limited(port, ch, port->fifosize >> 1, 128 128 + true, 129 129 + UART_PUT_CHAR(port, ch), 130 130 + ({})); 155 131 } 156 132 157 133 static irqreturn_t apbuart_int(int irq, void *dev_id)

+1 -2

drivers/tty/serial/ar933x_uart.c

reviewed

··· 425 425 426 426 ar933x_uart_putc(up, xmit->buf[xmit->tail]); 427 427 428 428 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 429 429 - up->port.icount.tx++; 428 428 + uart_xmit_advance(&up->port, 1); 430 429 } while (--count > 0); 431 430 432 431 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+1 -2

drivers/tty/serial/arc_uart.c

reviewed

··· 166 166 sent = 1; 167 167 } else if (!uart_circ_empty(xmit)) { 168 168 ch = xmit->buf[xmit->tail]; 169 169 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 170 170 - port->icount.tx++; 169 169 + uart_xmit_advance(port, 1); 171 170 while (!(UART_GET_STATUS(port) & TXEMPTY)) 172 171 cpu_relax(); 173 172 UART_SET_DATA(port, ch);

+32 -48

drivers/tty/serial/atmel_serial.c

reviewed

··· 552 552 static void atmel_stop_tx(struct uart_port *port) 553 553 { 554 554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 555 555 + bool is_pdc = atmel_use_pdc_tx(port); 556 556 + bool is_dma = is_pdc || atmel_use_dma_tx(port); 555 557 556 556 - if (atmel_use_pdc_tx(port)) { 558 558 + if (is_pdc) { 557 559 /* disable PDC transmit */ 558 560 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 559 561 } 560 562 561 561 - /* 562 562 - * Disable the transmitter. 563 563 - * This is mandatory when DMA is used, otherwise the DMA buffer 564 564 - * is fully transmitted. 565 565 - */ 566 566 - atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 567 567 - atmel_port->tx_stopped = true; 563 563 + if (is_dma) { 564 564 + /* 565 565 + * Disable the transmitter. 566 566 + * This is mandatory when DMA is used, otherwise the DMA buffer 567 567 + * is fully transmitted. 568 568 + */ 569 569 + atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 570 570 + atmel_port->tx_stopped = true; 571 571 + } 568 572 569 573 /* Disable interrupts */ 570 574 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); ··· 576 572 if (atmel_uart_is_half_duplex(port)) 577 573 if (!atomic_read(&atmel_port->tasklet_shutdown)) 578 574 atmel_start_rx(port); 579 579 - 580 575 } 581 576 582 577 /* ··· 584 581 static void atmel_start_tx(struct uart_port *port) 585 582 { 586 583 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 584 584 + bool is_pdc = atmel_use_pdc_tx(port); 585 585 + bool is_dma = is_pdc || atmel_use_dma_tx(port); 587 586 588 588 - if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 587 587 + if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 589 588 & ATMEL_PDC_TXTEN)) 590 589 /* The transmitter is already running. Yes, we 591 590 really need this.*/ 592 591 return; 593 592 594 594 - if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) 595 595 - if (atmel_uart_is_half_duplex(port)) 596 596 - atmel_stop_rx(port); 593 593 + if (is_dma && atmel_uart_is_half_duplex(port)) 594 594 + atmel_stop_rx(port); 597 595 598 598 - if (atmel_use_pdc_tx(port)) 596 596 + if (is_pdc) { 599 597 /* re-enable PDC transmit */ 600 598 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 599 599 + } 601 600 602 601 /* Enable interrupts */ 603 602 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 604 603 605 605 - /* re-enable the transmitter */ 606 606 - atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 607 607 - atmel_port->tx_stopped = false; 604 604 + if (is_dma) { 605 605 + /* re-enable the transmitter */ 606 606 + atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 607 607 + atmel_port->tx_stopped = false; 608 608 + } 608 609 } 609 610 610 611 /* ··· 831 824 */ 832 825 static void atmel_tx_chars(struct uart_port *port) 833 826 { 834 834 - struct circ_buf *xmit = &port->state->xmit; 835 827 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 828 828 + bool pending; 829 829 + u8 ch; 836 830 837 837 - if (port->x_char && 838 838 - (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) { 839 839 - atmel_uart_write_char(port, port->x_char); 840 840 - port->icount.tx++; 841 841 - port->x_char = 0; 842 842 - } 843 843 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 844 844 - return; 845 845 - 846 846 - while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) { 847 847 - atmel_uart_write_char(port, xmit->buf[xmit->tail]); 848 848 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 849 849 - port->icount.tx++; 850 850 - if (uart_circ_empty(xmit)) 851 851 - break; 852 852 - } 853 853 - 854 854 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 855 855 - uart_write_wakeup(port); 856 856 - 857 857 - if (!uart_circ_empty(xmit)) { 831 831 + pending = uart_port_tx(port, ch, 832 832 + atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY, 833 833 + atmel_uart_write_char(port, ch)); 834 834 + if (pending) { 858 835 /* we still have characters to transmit, so we should continue 859 836 * transmitting them when TX is ready, regardless of 860 837 * mode or duplexity ··· 866 875 867 876 if (chan) 868 877 dmaengine_terminate_all(chan); 869 869 - xmit->tail += atmel_port->tx_len; 870 870 - xmit->tail &= UART_XMIT_SIZE - 1; 871 871 - 872 872 - port->icount.tx += atmel_port->tx_len; 878 878 + uart_xmit_advance(port, atmel_port->tx_len); 873 879 874 880 spin_lock_irq(&atmel_port->lock_tx); 875 881 async_tx_ack(atmel_port->desc_tx); ··· 1459 1471 /* nothing left to transmit? */ 1460 1472 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1461 1473 return; 1462 1462 - 1463 1463 - xmit->tail += pdc->ofs; 1464 1464 - xmit->tail &= UART_XMIT_SIZE - 1; 1465 1465 - 1466 1466 - port->icount.tx += pdc->ofs; 1474 1474 + uart_xmit_advance(port, pdc->ofs); 1467 1475 pdc->ofs = 0; 1468 1476 1469 1477 /* more to transmit - setup next transfer */

+9 -38

drivers/tty/serial/bcm63xx_uart.c

reviewed

··· 303 303 */ 304 304 static void bcm_uart_do_tx(struct uart_port *port) 305 305 { 306 306 - struct circ_buf *xmit; 307 307 - unsigned int val, max_count; 308 308 - 309 309 - if (port->x_char) { 310 310 - bcm_uart_writel(port, port->x_char, UART_FIFO_REG); 311 311 - port->icount.tx++; 312 312 - port->x_char = 0; 313 313 - return; 314 314 - } 315 315 - 316 316 - if (uart_tx_stopped(port)) { 317 317 - bcm_uart_stop_tx(port); 318 318 - return; 319 319 - } 320 320 - 321 321 - xmit = &port->state->xmit; 322 322 - if (uart_circ_empty(xmit)) 323 323 - goto txq_empty; 306 306 + unsigned int val; 307 307 + bool pending; 308 308 + u8 ch; 324 309 325 310 val = bcm_uart_readl(port, UART_MCTL_REG); 326 311 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; 327 327 - max_count = port->fifosize - val; 328 312 329 329 - while (max_count--) { 330 330 - unsigned int c; 313 313 + pending = uart_port_tx_limited(port, ch, port->fifosize - val, 314 314 + true, 315 315 + bcm_uart_writel(port, ch, UART_FIFO_REG), 316 316 + ({})); 317 317 + if (pending) 318 318 + return; 331 319 332 332 - c = xmit->buf[xmit->tail]; 333 333 - bcm_uart_writel(port, c, UART_FIFO_REG); 334 334 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 335 335 - port->icount.tx++; 336 336 - if (uart_circ_empty(xmit)) 337 337 - break; 338 338 - } 339 339 - 340 340 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 341 341 - uart_write_wakeup(port); 342 342 - 343 343 - if (uart_circ_empty(xmit)) 344 344 - goto txq_empty; 345 345 - return; 346 346 - 347 347 - txq_empty: 348 320 /* nothing to send, disable transmit interrupt */ 349 321 val = bcm_uart_readl(port, UART_IR_REG); 350 322 val &= ~UART_TX_INT_MASK; 351 323 bcm_uart_writel(port, val, UART_IR_REG); 352 352 - return; 353 324 } 354 325 355 326 /*

+1 -2

drivers/tty/serial/clps711x.c

reviewed

··· 166 166 u32 sysflg = 0; 167 167 168 168 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); 169 169 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 170 170 - port->icount.tx++; 169 169 + uart_xmit_advance(port, 1); 171 170 172 171 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 173 172 if (sysflg & SYSFLG_UTXFF)

+1 -2

drivers/tty/serial/cpm_uart/cpm_uart_core.c

reviewed

··· 684 684 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 685 685 while (count < pinfo->tx_fifosize) { 686 686 *p++ = xmit->buf[xmit->tail]; 687 687 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 688 688 - port->icount.tx++; 687 687 + uart_xmit_advance(port, 1); 689 688 count++; 690 689 if (xmit->head == xmit->tail) 691 690 break;

+1 -2

drivers/tty/serial/digicolor-usart.c

reviewed

··· 202 202 203 203 while (!uart_circ_empty(xmit)) { 204 204 writeb(xmit->buf[xmit->tail], port->membase + UA_EMI_REC); 205 205 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 206 206 - port->icount.tx++; 205 205 + uart_xmit_advance(port, 1); 207 206 208 207 if (digicolor_uart_tx_full(port)) 209 208 break;

+1 -2

drivers/tty/serial/dz.c

reviewed

··· 279 279 * so we go one char at a time) :-< 280 280 */ 281 281 tmp = xmit->buf[xmit->tail]; 282 282 - xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1); 283 282 dz_out(dport, DZ_TDR, tmp); 284 284 - dport->port.icount.tx++; 283 283 + uart_xmit_advance(&dport->port, 1); 285 284 286 285 if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS) 287 286 uart_write_wakeup(&dport->port);

+1 -2

drivers/tty/serial/fsl_linflexuart.c

reviewed

··· 178 178 179 179 while (!uart_circ_empty(xmit)) { 180 180 linflex_put_char(sport, xmit->buf[xmit->tail]); 181 181 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 182 182 - sport->icount.tx++; 181 181 + uart_xmit_advance(sport, 1); 183 182 } 184 183 185 184 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+278 -122

drivers/tty/serial/fsl_lpuart.c

reviewed

··· 18 18 #include <linux/of.h> 19 19 #include <linux/of_device.h> 20 20 #include <linux/of_dma.h> 21 21 + #include <linux/pinctrl/consumer.h> 22 22 + #include <linux/pm_runtime.h> 21 23 #include <linux/serial_core.h> 22 24 #include <linux/slab.h> 23 25 #include <linux/tty_flip.h> ··· 234 232 235 233 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 236 234 #define DMA_RX_TIMEOUT (10) 235 235 + #define UART_AUTOSUSPEND_TIMEOUT 3000 237 236 238 237 #define DRIVER_NAME "fsl-lpuart" 239 238 #define DEV_NAME "ttyLP" ··· 512 509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 513 510 DMA_TO_DEVICE); 514 511 515 515 - xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 516 516 - 517 517 - sport->port.icount.tx += sport->dma_tx_bytes; 512 512 + uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 518 513 sport->dma_tx_in_progress = false; 519 514 spin_unlock_irqrestore(&sport->port.lock, flags); 520 515 ··· 583 582 sport->dma_tx_nents, DMA_TO_DEVICE); 584 583 sport->dma_tx_in_progress = false; 585 584 } 586 586 - dmaengine_terminate_all(chan); 585 585 + dmaengine_terminate_async(chan); 587 586 } 588 587 589 588 if (lpuart_is_32(sport)) { ··· 717 716 718 717 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 719 718 { 720 720 - struct circ_buf *xmit = &sport->port.state->xmit; 719 719 + struct uart_port *port = &sport->port; 720 720 + u8 ch; 721 721 722 722 - if (sport->port.x_char) { 723 723 - writeb(sport->port.x_char, sport->port.membase + UARTDR); 724 724 - sport->port.icount.tx++; 725 725 - sport->port.x_char = 0; 726 726 - return; 727 727 - } 728 728 - 729 729 - if (lpuart_stopped_or_empty(&sport->port)) { 730 730 - lpuart_stop_tx(&sport->port); 731 731 - return; 732 732 - } 733 733 - 734 734 - while (!uart_circ_empty(xmit) && 735 735 - (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 736 736 - writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 737 737 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 738 738 - sport->port.icount.tx++; 739 739 - } 740 740 - 741 741 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 742 742 - uart_write_wakeup(&sport->port); 743 743 - 744 744 - if (uart_circ_empty(xmit)) 745 745 - lpuart_stop_tx(&sport->port); 722 722 + uart_port_tx(port, ch, 723 723 + readb(port->membase + UARTTCFIFO) < sport->txfifo_size, 724 724 + writeb(ch, port->membase + UARTDR)); 746 725 } 747 726 748 727 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) ··· 747 766 txcnt &= UARTWATER_COUNT_MASK; 748 767 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 749 768 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 750 750 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 751 751 - sport->port.icount.tx++; 769 769 + uart_xmit_advance(&sport->port, 1); 752 770 txcnt = lpuart32_read(&sport->port, UARTWATER); 753 771 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 754 772 txcnt &= UARTWATER_COUNT_MASK; ··· 792 812 793 813 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 794 814 lpuart32_transmit_buffer(sport); 815 815 + } 816 816 + } 817 817 + 818 818 + static void 819 819 + lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 820 820 + { 821 821 + switch (state) { 822 822 + case UART_PM_STATE_OFF: 823 823 + pm_runtime_mark_last_busy(port->dev); 824 824 + pm_runtime_put_autosuspend(port->dev); 825 825 + break; 826 826 + default: 827 827 + pm_runtime_get_sync(port->dev); 828 828 + break; 795 829 } 796 830 } 797 831 ··· 1327 1333 struct lpuart_port, port); 1328 1334 struct dma_chan *chan = sport->dma_rx_chan; 1329 1335 1330 1330 - dmaengine_terminate_all(chan); 1336 1336 + dmaengine_terminate_sync(chan); 1331 1337 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1332 1338 kfree(sport->rx_ring.buf); 1333 1339 sport->rx_ring.tail = 0; ··· 1644 1650 sport->lpuart_dma_rx_use = false; 1645 1651 } 1646 1652 1653 1653 + static void lpuart_hw_setup(struct lpuart_port *sport) 1654 1654 + { 1655 1655 + unsigned long flags; 1656 1656 + 1657 1657 + spin_lock_irqsave(&sport->port.lock, flags); 1658 1658 + 1659 1659 + lpuart_setup_watermark_enable(sport); 1660 1660 + 1661 1661 + lpuart_rx_dma_startup(sport); 1662 1662 + lpuart_tx_dma_startup(sport); 1663 1663 + 1664 1664 + spin_unlock_irqrestore(&sport->port.lock, flags); 1665 1665 + } 1666 1666 + 1647 1667 static int lpuart_startup(struct uart_port *port) 1648 1668 { 1649 1669 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1650 1650 - unsigned long flags; 1651 1670 unsigned char temp; 1652 1671 1653 1672 /* determine FIFO size and enable FIFO mode */ ··· 1674 1667 UARTPFIFO_FIFOSIZE_MASK); 1675 1668 1676 1669 lpuart_request_dma(sport); 1677 1677 - 1678 1678 - spin_lock_irqsave(&sport->port.lock, flags); 1679 1679 - 1680 1680 - lpuart_setup_watermark_enable(sport); 1681 1681 - 1682 1682 - lpuart_rx_dma_startup(sport); 1683 1683 - lpuart_tx_dma_startup(sport); 1684 1684 - 1685 1685 - spin_unlock_irqrestore(&sport->port.lock, flags); 1670 1670 + lpuart_hw_setup(sport); 1686 1671 1687 1672 return 0; 1688 1673 } ··· 1697 1698 lpuart32_write(&sport->port, temp, UARTCTRL); 1698 1699 } 1699 1700 1701 1701 + static void lpuart32_hw_setup(struct lpuart_port *sport) 1702 1702 + { 1703 1703 + unsigned long flags; 1704 1704 + 1705 1705 + spin_lock_irqsave(&sport->port.lock, flags); 1706 1706 + 1707 1707 + lpuart32_setup_watermark_enable(sport); 1708 1708 + 1709 1709 + lpuart_rx_dma_startup(sport); 1710 1710 + lpuart_tx_dma_startup(sport); 1711 1711 + 1712 1712 + lpuart32_configure(sport); 1713 1713 + 1714 1714 + spin_unlock_irqrestore(&sport->port.lock, flags); 1715 1715 + } 1716 1716 + 1700 1717 static int lpuart32_startup(struct uart_port *port) 1701 1718 { 1702 1719 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1703 1703 - unsigned long flags; 1704 1720 unsigned long temp; 1705 1721 1706 1722 /* determine FIFO size */ ··· 1740 1726 } 1741 1727 1742 1728 lpuart_request_dma(sport); 1729 1729 + lpuart32_hw_setup(sport); 1743 1730 1744 1744 - spin_lock_irqsave(&sport->port.lock, flags); 1745 1745 - 1746 1746 - lpuart32_setup_watermark_enable(sport); 1747 1747 - 1748 1748 - lpuart_rx_dma_startup(sport); 1749 1749 - lpuart_tx_dma_startup(sport); 1750 1750 - 1751 1751 - lpuart32_configure(sport); 1752 1752 - 1753 1753 - spin_unlock_irqrestore(&sport->port.lock, flags); 1754 1731 return 0; 1755 1732 } 1756 1733 ··· 1757 1752 if (wait_event_interruptible_timeout(sport->dma_wait, 1758 1753 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1759 1754 sport->dma_tx_in_progress = false; 1760 1760 - dmaengine_terminate_all(sport->dma_tx_chan); 1755 1755 + dmaengine_terminate_sync(sport->dma_tx_chan); 1761 1756 } 1762 1757 sport->lpuart_dma_tx_use = false; 1763 1758 } ··· 2245 2240 .startup = lpuart_startup, 2246 2241 .shutdown = lpuart_shutdown, 2247 2242 .set_termios = lpuart_set_termios, 2243 2243 + .pm = lpuart_uart_pm, 2248 2244 .type = lpuart_type, 2249 2245 .request_port = lpuart_request_port, 2250 2246 .release_port = lpuart_release_port, ··· 2270 2264 .startup = lpuart32_startup, 2271 2265 .shutdown = lpuart32_shutdown, 2272 2266 .set_termios = lpuart32_set_termios, 2267 2267 + .pm = lpuart_uart_pm, 2273 2268 .type = lpuart_type, 2274 2269 .request_port = lpuart_request_port, 2275 2270 .release_port = lpuart_release_port, ··· 2751 2744 handler = lpuart_int; 2752 2745 } 2753 2746 2747 2747 + pm_runtime_use_autosuspend(&pdev->dev); 2748 2748 + pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 2749 2749 + pm_runtime_set_active(&pdev->dev); 2750 2750 + pm_runtime_enable(&pdev->dev); 2751 2751 + 2754 2752 ret = lpuart_global_reset(sport); 2755 2753 if (ret) 2756 2754 goto failed_reset; ··· 2780 2768 failed_attach_port: 2781 2769 failed_get_rs485: 2782 2770 failed_reset: 2771 2771 + pm_runtime_disable(&pdev->dev); 2772 2772 + pm_runtime_set_suspended(&pdev->dev); 2773 2773 + pm_runtime_dont_use_autosuspend(&pdev->dev); 2783 2774 lpuart_disable_clks(sport); 2784 2775 return ret; 2785 2776 } ··· 2801 2786 if (sport->dma_rx_chan) 2802 2787 dma_release_channel(sport->dma_rx_chan); 2803 2788 2789 2789 + pm_runtime_disable(&pdev->dev); 2790 2790 + pm_runtime_set_suspended(&pdev->dev); 2791 2791 + pm_runtime_dont_use_autosuspend(&pdev->dev); 2804 2792 return 0; 2805 2793 } 2806 2794 2807 2807 - static int __maybe_unused lpuart_suspend(struct device *dev) 2795 2795 + static int lpuart_runtime_suspend(struct device *dev) 2808 2796 { 2809 2809 - struct lpuart_port *sport = dev_get_drvdata(dev); 2810 2810 - unsigned long temp; 2811 2811 - bool irq_wake; 2797 2797 + struct platform_device *pdev = to_platform_device(dev); 2798 2798 + struct lpuart_port *sport = platform_get_drvdata(pdev); 2799 2799 + 2800 2800 + lpuart_disable_clks(sport); 2801 2801 + 2802 2802 + return 0; 2803 2803 + }; 2804 2804 + 2805 2805 + static int lpuart_runtime_resume(struct device *dev) 2806 2806 + { 2807 2807 + struct platform_device *pdev = to_platform_device(dev); 2808 2808 + struct lpuart_port *sport = platform_get_drvdata(pdev); 2809 2809 + 2810 2810 + return lpuart_enable_clks(sport); 2811 2811 + }; 2812 2812 + 2813 2813 + static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) 2814 2814 + { 2815 2815 + unsigned int val, baud; 2812 2816 2813 2817 if (lpuart_is_32(sport)) { 2814 2814 - /* disable Rx/Tx and interrupts */ 2815 2815 - temp = lpuart32_read(&sport->port, UARTCTRL); 2816 2816 - temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2817 2817 - lpuart32_write(&sport->port, temp, UARTCTRL); 2818 2818 - } else { 2819 2819 - /* disable Rx/Tx and interrupts */ 2820 2820 - temp = readb(sport->port.membase + UARTCR2); 2821 2821 - temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2822 2822 - writeb(temp, sport->port.membase + UARTCR2); 2823 2823 - } 2824 2824 - 2825 2825 - uart_suspend_port(&lpuart_reg, &sport->port); 2826 2826 - 2827 2827 - /* uart_suspend_port() might set wakeup flag */ 2828 2828 - irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2829 2829 - 2830 2830 - if (sport->lpuart_dma_rx_use) { 2831 2831 - /* 2832 2832 - * EDMA driver during suspend will forcefully release any 2833 2833 - * non-idle DMA channels. If port wakeup is enabled or if port 2834 2834 - * is console port or 'no_console_suspend' is set the Rx DMA 2835 2835 - * cannot resume as expected, hence gracefully release the 2836 2836 - * Rx DMA path before suspend and start Rx DMA path on resume. 2837 2837 - */ 2838 2838 - if (irq_wake) { 2839 2839 - del_timer_sync(&sport->lpuart_timer); 2840 2840 - lpuart_dma_rx_free(&sport->port); 2841 2841 - } 2842 2842 - 2843 2843 - /* Disable Rx DMA to use UART port as wakeup source */ 2844 2844 - if (lpuart_is_32(sport)) { 2845 2845 - temp = lpuart32_read(&sport->port, UARTBAUD); 2846 2846 - lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2847 2847 - UARTBAUD); 2818 2818 + val = lpuart32_read(&sport->port, UARTCTRL); 2819 2819 + baud = lpuart32_read(&sport->port, UARTBAUD); 2820 2820 + if (on) { 2821 2821 + /* set rx_watermark to 0 in wakeup source mode */ 2822 2822 + lpuart32_write(&sport->port, 0, UARTWATER); 2823 2823 + val |= UARTCTRL_RIE; 2824 2824 + /* clear RXEDGIF flag before enable RXEDGIE interrupt */ 2825 2825 + lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); 2826 2826 + baud |= UARTBAUD_RXEDGIE; 2848 2827 } else { 2849 2849 - writeb(readb(sport->port.membase + UARTCR5) & 2850 2850 - ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2828 2828 + val &= ~UARTCTRL_RIE; 2829 2829 + baud &= ~UARTBAUD_RXEDGIE; 2851 2830 } 2831 2831 + lpuart32_write(&sport->port, val, UARTCTRL); 2832 2832 + lpuart32_write(&sport->port, baud, UARTBAUD); 2833 2833 + } else { 2834 2834 + val = readb(sport->port.membase + UARTCR2); 2835 2835 + if (on) 2836 2836 + val |= UARTCR2_RIE; 2837 2837 + else 2838 2838 + val &= ~UARTCR2_RIE; 2839 2839 + writeb(val, sport->port.membase + UARTCR2); 2852 2840 } 2853 2853 - 2854 2854 - if (sport->lpuart_dma_tx_use) { 2855 2855 - sport->dma_tx_in_progress = false; 2856 2856 - dmaengine_terminate_all(sport->dma_tx_chan); 2857 2857 - } 2858 2858 - 2859 2859 - if (sport->port.suspended && !irq_wake) 2860 2860 - lpuart_disable_clks(sport); 2861 2861 - 2862 2862 - return 0; 2863 2841 } 2864 2842 2865 2865 - static int __maybe_unused lpuart_resume(struct device *dev) 2843 2843 + static bool lpuart_uport_is_active(struct lpuart_port *sport) 2844 2844 + { 2845 2845 + struct tty_port *port = &sport->port.state->port; 2846 2846 + struct tty_struct *tty; 2847 2847 + struct device *tty_dev; 2848 2848 + int may_wake = 0; 2849 2849 + 2850 2850 + tty = tty_port_tty_get(port); 2851 2851 + if (tty) { 2852 2852 + tty_dev = tty->dev; 2853 2853 + may_wake = device_may_wakeup(tty_dev); 2854 2854 + tty_kref_put(tty); 2855 2855 + } 2856 2856 + 2857 2857 + if ((tty_port_initialized(port) && may_wake) || 2858 2858 + (!console_suspend_enabled && uart_console(&sport->port))) 2859 2859 + return true; 2860 2860 + 2861 2861 + return false; 2862 2862 + } 2863 2863 + 2864 2864 + static int lpuart_suspend_noirq(struct device *dev) 2866 2865 { 2867 2866 struct lpuart_port *sport = dev_get_drvdata(dev); 2868 2867 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2869 2868 2870 2870 - if (sport->port.suspended && !irq_wake) 2871 2871 - lpuart_enable_clks(sport); 2869 2869 + if (lpuart_uport_is_active(sport)) 2870 2870 + serial_lpuart_enable_wakeup(sport, !!irq_wake); 2872 2871 2873 2873 - if (lpuart_is_32(sport)) 2874 2874 - lpuart32_setup_watermark_enable(sport); 2875 2875 - else 2876 2876 - lpuart_setup_watermark_enable(sport); 2872 2872 + pinctrl_pm_select_sleep_state(dev); 2877 2873 2878 2878 - if (sport->lpuart_dma_rx_use) { 2879 2879 - if (irq_wake) { 2880 2880 - if (!lpuart_start_rx_dma(sport)) 2881 2881 - rx_dma_timer_init(sport); 2882 2882 - else 2883 2883 - sport->lpuart_dma_rx_use = false; 2874 2874 + return 0; 2875 2875 + } 2876 2876 + 2877 2877 + static int lpuart_resume_noirq(struct device *dev) 2878 2878 + { 2879 2879 + struct lpuart_port *sport = dev_get_drvdata(dev); 2880 2880 + unsigned int val; 2881 2881 + 2882 2882 + pinctrl_pm_select_default_state(dev); 2883 2883 + 2884 2884 + if (lpuart_uport_is_active(sport)) { 2885 2885 + serial_lpuart_enable_wakeup(sport, false); 2886 2886 + 2887 2887 + /* clear the wakeup flags */ 2888 2888 + if (lpuart_is_32(sport)) { 2889 2889 + val = lpuart32_read(&sport->port, UARTSTAT); 2890 2890 + lpuart32_write(&sport->port, val, UARTSTAT); 2884 2891 } 2885 2892 } 2886 2893 2887 2887 - lpuart_tx_dma_startup(sport); 2894 2894 + return 0; 2895 2895 + } 2888 2896 2889 2889 - if (lpuart_is_32(sport)) 2890 2890 - lpuart32_configure(sport); 2897 2897 + static int lpuart_suspend(struct device *dev) 2898 2898 + { 2899 2899 + struct lpuart_port *sport = dev_get_drvdata(dev); 2900 2900 + unsigned long temp, flags; 2891 2901 2902 2902 + uart_suspend_port(&lpuart_reg, &sport->port); 2903 2903 + 2904 2904 + if (lpuart_uport_is_active(sport)) { 2905 2905 + spin_lock_irqsave(&sport->port.lock, flags); 2906 2906 + if (lpuart_is_32(sport)) { 2907 2907 + /* disable Rx/Tx and interrupts */ 2908 2908 + temp = lpuart32_read(&sport->port, UARTCTRL); 2909 2909 + temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2910 2910 + lpuart32_write(&sport->port, temp, UARTCTRL); 2911 2911 + } else { 2912 2912 + /* disable Rx/Tx and interrupts */ 2913 2913 + temp = readb(sport->port.membase + UARTCR2); 2914 2914 + temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2915 2915 + writeb(temp, sport->port.membase + UARTCR2); 2916 2916 + } 2917 2917 + spin_unlock_irqrestore(&sport->port.lock, flags); 2918 2918 + 2919 2919 + if (sport->lpuart_dma_rx_use) { 2920 2920 + /* 2921 2921 + * EDMA driver during suspend will forcefully release any 2922 2922 + * non-idle DMA channels. If port wakeup is enabled or if port 2923 2923 + * is console port or 'no_console_suspend' is set the Rx DMA 2924 2924 + * cannot resume as expected, hence gracefully release the 2925 2925 + * Rx DMA path before suspend and start Rx DMA path on resume. 2926 2926 + */ 2927 2927 + del_timer_sync(&sport->lpuart_timer); 2928 2928 + lpuart_dma_rx_free(&sport->port); 2929 2929 + 2930 2930 + /* Disable Rx DMA to use UART port as wakeup source */ 2931 2931 + spin_lock_irqsave(&sport->port.lock, flags); 2932 2932 + if (lpuart_is_32(sport)) { 2933 2933 + temp = lpuart32_read(&sport->port, UARTBAUD); 2934 2934 + lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2935 2935 + UARTBAUD); 2936 2936 + } else { 2937 2937 + writeb(readb(sport->port.membase + UARTCR5) & 2938 2938 + ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2939 2939 + } 2940 2940 + spin_unlock_irqrestore(&sport->port.lock, flags); 2941 2941 + } 2942 2942 + 2943 2943 + if (sport->lpuart_dma_tx_use) { 2944 2944 + spin_lock_irqsave(&sport->port.lock, flags); 2945 2945 + if (lpuart_is_32(sport)) { 2946 2946 + temp = lpuart32_read(&sport->port, UARTBAUD); 2947 2947 + temp &= ~UARTBAUD_TDMAE; 2948 2948 + lpuart32_write(&sport->port, temp, UARTBAUD); 2949 2949 + } else { 2950 2950 + temp = readb(sport->port.membase + UARTCR5); 2951 2951 + temp &= ~UARTCR5_TDMAS; 2952 2952 + writeb(temp, sport->port.membase + UARTCR5); 2953 2953 + } 2954 2954 + spin_unlock_irqrestore(&sport->port.lock, flags); 2955 2955 + sport->dma_tx_in_progress = false; 2956 2956 + dmaengine_terminate_sync(sport->dma_tx_chan); 2957 2957 + } 2958 2958 + } else if (pm_runtime_active(sport->port.dev)) { 2959 2959 + lpuart_disable_clks(sport); 2960 2960 + pm_runtime_disable(sport->port.dev); 2961 2961 + pm_runtime_set_suspended(sport->port.dev); 2962 2962 + } 2963 2963 + 2964 2964 + return 0; 2965 2965 + } 2966 2966 + 2967 2967 + static void lpuart_console_fixup(struct lpuart_port *sport) 2968 2968 + { 2969 2969 + struct tty_port *port = &sport->port.state->port; 2970 2970 + struct uart_port *uport = &sport->port; 2971 2971 + struct ktermios termios; 2972 2972 + 2973 2973 + /* i.MX7ULP enter VLLS mode that lpuart module power off and registers 2974 2974 + * all lost no matter the port is wakeup source. 2975 2975 + * For console port, console baud rate setting lost and print messy 2976 2976 + * log when enable the console port as wakeup source. To avoid the 2977 2977 + * issue happen, user should not enable uart port as wakeup source 2978 2978 + * in VLLS mode, or restore console setting here. 2979 2979 + */ 2980 2980 + if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && 2981 2981 + console_suspend_enabled && uart_console(&sport->port)) { 2982 2982 + 2983 2983 + mutex_lock(&port->mutex); 2984 2984 + memset(&termios, 0, sizeof(struct ktermios)); 2985 2985 + termios.c_cflag = uport->cons->cflag; 2986 2986 + if (port->tty && termios.c_cflag == 0) 2987 2987 + termios = port->tty->termios; 2988 2988 + uport->ops->set_termios(uport, &termios, NULL); 2989 2989 + mutex_unlock(&port->mutex); 2990 2990 + } 2991 2991 + } 2992 2992 + 2993 2993 + static int lpuart_resume(struct device *dev) 2994 2994 + { 2995 2995 + struct lpuart_port *sport = dev_get_drvdata(dev); 2996 2996 + int ret; 2997 2997 + 2998 2998 + if (lpuart_uport_is_active(sport)) { 2999 2999 + if (lpuart_is_32(sport)) 3000 3000 + lpuart32_hw_setup(sport); 3001 3001 + else 3002 3002 + lpuart_hw_setup(sport); 3003 3003 + } else if (pm_runtime_active(sport->port.dev)) { 3004 3004 + ret = lpuart_enable_clks(sport); 3005 3005 + if (ret) 3006 3006 + return ret; 3007 3007 + pm_runtime_set_active(sport->port.dev); 3008 3008 + pm_runtime_enable(sport->port.dev); 3009 3009 + } 3010 3010 + 3011 3011 + lpuart_console_fixup(sport); 2892 3012 uart_resume_port(&lpuart_reg, &sport->port); 2893 3013 2894 3014 return 0; 2895 3015 } 2896 3016 2897 2897 - static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 3017 3017 + static const struct dev_pm_ops lpuart_pm_ops = { 3018 3018 + RUNTIME_PM_OPS(lpuart_runtime_suspend, 3019 3019 + lpuart_runtime_resume, NULL) 3020 3020 + NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, 3021 3021 + lpuart_resume_noirq) 3022 3022 + SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) 3023 3023 + }; 2898 3024 2899 3025 static struct platform_driver lpuart_driver = { 2900 3026 .probe = lpuart_probe, ··· 3043 2887 .driver = { 3044 2888 .name = "fsl-lpuart", 3045 2889 .of_match_table = lpuart_dt_ids, 3046 3046 - .pm = &lpuart_pm_ops, 2890 2890 + .pm = pm_ptr(&lpuart_pm_ops), 3047 2891 }, 3048 2892 }; 3049 2893

+60 -11

drivers/tty/serial/imx.c

reviewed

··· 489 489 static void imx_uart_stop_rx(struct uart_port *port) 490 490 { 491 491 struct imx_port *sport = (struct imx_port *)port; 492 492 - u32 ucr1, ucr2, ucr4; 492 492 + u32 ucr1, ucr2, ucr4, uts; 493 493 494 494 ucr1 = imx_uart_readl(sport, UCR1); 495 495 ucr2 = imx_uart_readl(sport, UCR2); ··· 505 505 imx_uart_writel(sport, ucr1, UCR1); 506 506 imx_uart_writel(sport, ucr4, UCR4); 507 507 508 508 - ucr2 &= ~UCR2_RXEN; 508 508 + /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 509 509 + if (port->rs485.flags & SER_RS485_ENABLED && 510 510 + port->rs485.flags & SER_RS485_RTS_ON_SEND && 511 511 + sport->have_rtscts && !sport->have_rtsgpio) { 512 512 + uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 513 513 + uts |= UTS_LOOP; 514 514 + imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 515 515 + ucr2 |= UCR2_RXEN; 516 516 + } else { 517 517 + ucr2 &= ~UCR2_RXEN; 518 518 + } 519 519 + 509 520 imx_uart_writel(sport, ucr2, UCR2); 510 521 } 511 522 ··· 574 563 /* send xmit->buf[xmit->tail] 575 564 * out the port here */ 576 565 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 577 577 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 578 578 - sport->port.icount.tx++; 566 566 + uart_xmit_advance(&sport->port, 1); 579 567 } 580 568 581 569 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ··· 600 590 ucr1 &= ~UCR1_TXDMAEN; 601 591 imx_uart_writel(sport, ucr1, UCR1); 602 592 603 603 - /* update the stat */ 604 604 - xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 605 605 - sport->port.icount.tx += sport->tx_bytes; 593 593 + uart_xmit_advance(&sport->port, sport->tx_bytes); 606 594 607 595 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 608 596 ··· 1401 1393 int retval, i; 1402 1394 unsigned long flags; 1403 1395 int dma_is_inited = 0; 1404 1404 - u32 ucr1, ucr2, ucr3, ucr4; 1396 1396 + u32 ucr1, ucr2, ucr3, ucr4, uts; 1405 1397 1406 1398 retval = clk_prepare_enable(sport->clk_per); 1407 1399 if (retval) ··· 1506 1498 imx_uart_writel(sport, ucr2, UCR2); 1507 1499 } 1508 1500 1501 1501 + /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 1502 1502 + uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 1503 1503 + uts &= ~UTS_LOOP; 1504 1504 + imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1505 1505 + 1509 1506 spin_unlock_irqrestore(&sport->port.lock, flags); 1510 1507 1511 1508 return 0; ··· 1520 1507 { 1521 1508 struct imx_port *sport = (struct imx_port *)port; 1522 1509 unsigned long flags; 1523 1523 - u32 ucr1, ucr2, ucr4; 1510 1510 + u32 ucr1, ucr2, ucr4, uts; 1524 1511 1525 1512 if (sport->dma_is_enabled) { 1526 1513 dmaengine_terminate_sync(sport->dma_chan_tx); ··· 1564 1551 spin_lock_irqsave(&sport->port.lock, flags); 1565 1552 1566 1553 ucr1 = imx_uart_readl(sport, UCR1); 1567 1567 - ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1554 1554 + ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1555 1555 + /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 1556 1556 + if (port->rs485.flags & SER_RS485_ENABLED && 1557 1557 + port->rs485.flags & SER_RS485_RTS_ON_SEND && 1558 1558 + sport->have_rtscts && !sport->have_rtsgpio) { 1559 1559 + uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 1560 1560 + uts |= UTS_LOOP; 1561 1561 + imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1562 1562 + ucr1 |= UCR1_UARTEN; 1563 1563 + } else { 1564 1564 + ucr1 &= ~UCR1_UARTEN; 1565 1565 + } 1568 1566 imx_uart_writel(sport, ucr1, UCR1); 1569 1567 1570 1568 ucr4 = imx_uart_readl(sport, UCR4); ··· 2237 2213 void __iomem *base; 2238 2214 u32 dma_buf_conf[2]; 2239 2215 int ret = 0; 2240 2240 - u32 ucr1; 2216 2216 + u32 ucr1, ucr2, uts; 2241 2217 struct resource *res; 2242 2218 int txirq, rxirq, rtsirq; 2243 2219 ··· 2373 2349 ucr1 = imx_uart_readl(sport, UCR1); 2374 2350 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 2375 2351 imx_uart_writel(sport, ucr1, UCR1); 2352 2352 + 2353 2353 + /* 2354 2354 + * In case RS485 is enabled without GPIO RTS control, the UART IP 2355 2355 + * is used to control CTS signal. Keep both the UART and Receiver 2356 2356 + * enabled, otherwise the UART IP pulls CTS signal always HIGH no 2357 2357 + * matter how the UCR2 CTSC and CTS bits are set. To prevent any 2358 2358 + * data from being fed into the RX FIFO, enable loopback mode in 2359 2359 + * UTS register, which disconnects the RX path from external RXD 2360 2360 + * pin and connects it to the Transceiver, which is disabled, so 2361 2361 + * no data can be fed to the RX FIFO that way. 2362 2362 + */ 2363 2363 + if (sport->port.rs485.flags & SER_RS485_ENABLED && 2364 2364 + sport->have_rtscts && !sport->have_rtsgpio) { 2365 2365 + uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 2366 2366 + uts |= UTS_LOOP; 2367 2367 + imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 2368 2368 + 2369 2369 + ucr1 = imx_uart_readl(sport, UCR1); 2370 2370 + ucr1 |= UCR1_UARTEN; 2371 2371 + imx_uart_writel(sport, ucr1, UCR1); 2372 2372 + 2373 2373 + ucr2 = imx_uart_readl(sport, UCR2); 2374 2374 + ucr2 |= UCR2_RXEN; 2375 2375 + imx_uart_writel(sport, ucr2, UCR2); 2376 2376 + } 2376 2377 2377 2378 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2378 2379 /*

+2 -4

drivers/tty/serial/ip22zilog.c

reviewed

··· 409 409 ZSDELAY(); 410 410 ZS_WSYNC(channel); 411 411 412 412 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 413 413 - up->port.icount.tx++; 412 412 + uart_xmit_advance(&up->port, 1); 414 413 415 414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 416 415 uart_write_wakeup(&up->port); ··· 608 609 ZSDELAY(); 609 610 ZS_WSYNC(channel); 610 611 611 611 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 612 612 - port->icount.tx++; 612 612 + uart_xmit_advance(port, 1); 613 613 614 614 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 615 615 uart_write_wakeup(&up->port);

+4 -32

drivers/tty/serial/lantiq.c

reviewed

··· 95 95 #define ASCFSTAT_TXFFLMASK 0x3F00 96 96 #define ASCFSTAT_TXFREEMASK 0x3F000000 97 97 98 98 - static void lqasc_tx_chars(struct uart_port *port); 99 98 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 100 99 static struct uart_driver lqasc_reg; 101 100 ··· 150 151 { 151 152 unsigned long flags; 152 153 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 154 154 + u8 ch; 153 155 154 156 spin_lock_irqsave(&ltq_port->lock, flags); 155 155 - lqasc_tx_chars(port); 157 157 + uart_port_tx(port, ch, 158 158 + lqasc_tx_ready(port), 159 159 + writeb(ch, port->membase + LTQ_ASC_TBUF)); 156 160 spin_unlock_irqrestore(&ltq_port->lock, flags); 157 161 return; 158 162 } ··· 226 224 tty_flip_buffer_push(tport); 227 225 228 226 return 0; 229 229 - } 230 230 - 231 231 - static void 232 232 - lqasc_tx_chars(struct uart_port *port) 233 233 - { 234 234 - struct circ_buf *xmit = &port->state->xmit; 235 235 - if (uart_tx_stopped(port)) { 236 236 - lqasc_stop_tx(port); 237 237 - return; 238 238 - } 239 239 - 240 240 - while (lqasc_tx_ready(port)) { 241 241 - if (port->x_char) { 242 242 - writeb(port->x_char, port->membase + LTQ_ASC_TBUF); 243 243 - port->icount.tx++; 244 244 - port->x_char = 0; 245 245 - continue; 246 246 - } 247 247 - 248 248 - if (uart_circ_empty(xmit)) 249 249 - break; 250 250 - 251 251 - writeb(port->state->xmit.buf[port->state->xmit.tail], 252 252 - port->membase + LTQ_ASC_TBUF); 253 253 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 254 254 - port->icount.tx++; 255 255 - } 256 256 - 257 257 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 258 258 - uart_write_wakeup(port); 259 227 } 260 228 261 229 static irqreturn_t

+1 -2

drivers/tty/serial/liteuart.c

reviewed

··· 136 136 } else if (!uart_circ_empty(xmit)) { 137 137 while (xmit->head != xmit->tail) { 138 138 ch = xmit->buf[xmit->tail]; 139 139 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 140 140 - port->icount.tx++; 139 139 + uart_xmit_advance(port, 1); 141 140 liteuart_putchar(port, ch); 142 141 } 143 142 }

+4 -29

drivers/tty/serial/lpc32xx_hs.c

reviewed

··· 276 276 tty_flip_buffer_push(tport); 277 277 } 278 278 279 279 - static void serial_lpc32xx_stop_tx(struct uart_port *port); 280 280 - 281 279 static bool serial_lpc32xx_tx_ready(struct uart_port *port) 282 280 { 283 281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); ··· 285 287 286 288 static void __serial_lpc32xx_tx(struct uart_port *port) 287 289 { 288 288 - struct circ_buf *xmit = &port->state->xmit; 290 290 + u8 ch; 289 291 290 290 - if (port->x_char) { 291 291 - writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 292 292 - port->icount.tx++; 293 293 - port->x_char = 0; 294 294 - return; 295 295 - } 296 296 - 297 297 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 298 298 - goto exit_tx; 299 299 - 300 300 - /* Transfer data */ 301 301 - while (serial_lpc32xx_tx_ready(port)) { 302 302 - writel((u32) xmit->buf[xmit->tail], 303 303 - LPC32XX_HSUART_FIFO(port->membase)); 304 304 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 305 305 - port->icount.tx++; 306 306 - if (uart_circ_empty(xmit)) 307 307 - break; 308 308 - } 309 309 - 310 310 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 311 311 - uart_write_wakeup(port); 312 312 - 313 313 - exit_tx: 314 314 - if (uart_circ_empty(xmit)) 315 315 - serial_lpc32xx_stop_tx(port); 292 292 + uart_port_tx(port, ch, 293 293 + serial_lpc32xx_tx_ready(port), 294 294 + writel(ch, LPC32XX_HSUART_FIFO(port->membase))); 316 295 } 317 296 318 297 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)

+1 -3

drivers/tty/serial/max3100.c

reviewed

··· 292 292 } else if (!uart_circ_empty(xmit) && 293 293 !uart_tx_stopped(&s->port)) { 294 294 tx = xmit->buf[xmit->tail]; 295 295 - xmit->tail = (xmit->tail + 1) & 296 296 - (UART_XMIT_SIZE - 1); 297 297 - s->port.icount.tx++; 295 295 + uart_xmit_advance(&s->port, 1); 298 296 } 299 297 if (tx != 0xffff) { 300 298 max3100_calc_parity(s, &tx);

+1 -4

drivers/tty/serial/max310x.c

reviewed

··· 787 787 } else { 788 788 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 789 789 } 790 790 - 791 791 - /* Add data to send */ 792 792 - port->icount.tx += to_send; 793 793 - xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); 790 790 + uart_xmit_advance(port, to_send); 794 791 } 795 792 796 793 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+8 -26

drivers/tty/serial/mcf.c

reviewed

··· 327 327 static void mcf_tx_chars(struct mcf_uart *pp) 328 328 { 329 329 struct uart_port *port = &pp->port; 330 330 - struct circ_buf *xmit = &port->state->xmit; 330 330 + bool pending; 331 331 + u8 ch; 331 332 332 332 - if (port->x_char) { 333 333 - /* Send special char - probably flow control */ 334 334 - writeb(port->x_char, port->membase + MCFUART_UTB); 335 335 - port->x_char = 0; 336 336 - port->icount.tx++; 337 337 - return; 338 338 - } 333 333 + pending = uart_port_tx(port, ch, 334 334 + readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY, 335 335 + writeb(ch, port->membase + MCFUART_UTB)); 339 336 340 340 - while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) { 341 341 - if (uart_circ_empty(xmit)) 342 342 - break; 343 343 - writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB); 344 344 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); 345 345 - port->icount.tx++; 346 346 - } 347 347 - 348 348 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 349 349 - uart_write_wakeup(port); 350 350 - 351 351 - if (uart_circ_empty(xmit)) { 352 352 - mcf_stop_tx(port); 353 353 - /* Disable TX to negate RTS automatically */ 354 354 - if (port->rs485.flags & SER_RS485_ENABLED) 355 355 - writeb(MCFUART_UCR_TXDISABLE, 356 356 - port->membase + MCFUART_UCR); 357 357 - } 337 337 + /* Disable TX to negate RTS automatically */ 338 338 + if (!pending && (port->rs485.flags & SER_RS485_ENABLED)) 339 339 + writeb(MCFUART_UCR_TXDISABLE, port->membase + MCFUART_UCR); 358 340 } 359 341 360 342 /****************************************************************************/

+1 -4

drivers/tty/serial/men_z135_uart.c

reviewed

··· 352 352 n = min(n, s); 353 353 354 354 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); 355 355 - xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1); 356 356 - 357 355 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); 358 358 - 359 359 - port->icount.tx += n; 356 356 + uart_xmit_advance(port, n); 360 357 361 358 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 362 359 uart_write_wakeup(port);

+1 -2

drivers/tty/serial/meson_uart.c

reviewed

··· 162 162 163 163 ch = xmit->buf[xmit->tail]; 164 164 writel(ch, port->membase + AML_UART_WFIFO); 165 165 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 166 166 - port->icount.tx++; 165 165 + uart_xmit_advance(port, 1); 167 166 } 168 167 169 168 if (!uart_circ_empty(xmit)) {

+1 -2

drivers/tty/serial/milbeaut_usio.c

reviewed

··· 98 98 do { 99 99 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR); 100 100 101 101 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 102 102 - port->icount.tx++; 101 101 + uart_xmit_advance(port, 1); 103 102 if (uart_circ_empty(xmit)) 104 103 break; 105 104

+4 -35

drivers/tty/serial/mpc52xx_uart.c

reviewed

··· 1428 1428 static inline bool 1429 1429 mpc52xx_uart_int_tx_chars(struct uart_port *port) 1430 1430 { 1431 1431 - struct circ_buf *xmit = &port->state->xmit; 1431 1431 + u8 ch; 1432 1432 1433 1433 - /* Process out of band chars */ 1434 1434 - if (port->x_char) { 1435 1435 - psc_ops->write_char(port, port->x_char); 1436 1436 - port->icount.tx++; 1437 1437 - port->x_char = 0; 1438 1438 - return true; 1439 1439 - } 1440 1440 - 1441 1441 - /* Nothing to do ? */ 1442 1442 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 1443 1443 - mpc52xx_uart_stop_tx(port); 1444 1444 - return false; 1445 1445 - } 1446 1446 - 1447 1447 - /* Send chars */ 1448 1448 - while (psc_ops->raw_tx_rdy(port)) { 1449 1449 - psc_ops->write_char(port, xmit->buf[xmit->tail]); 1450 1450 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1451 1451 - port->icount.tx++; 1452 1452 - if (uart_circ_empty(xmit)) 1453 1453 - break; 1454 1454 - } 1455 1455 - 1456 1456 - /* Wake up */ 1457 1457 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1458 1458 - uart_write_wakeup(port); 1459 1459 - 1460 1460 - /* Maybe we're done after all */ 1461 1461 - if (uart_circ_empty(xmit)) { 1462 1462 - mpc52xx_uart_stop_tx(port); 1463 1463 - return false; 1464 1464 - } 1465 1465 - 1466 1466 - return true; 1433 1433 + return uart_port_tx(port, ch, 1434 1434 + psc_ops->raw_tx_rdy(port), 1435 1435 + psc_ops->write_char(port, ch)); 1467 1436 } 1468 1437 1469 1438 static irqreturn_t

+4 -22

drivers/tty/serial/mps2-uart.c

reviewed

··· 129 129 130 130 static void mps2_uart_tx_chars(struct uart_port *port) 131 131 { 132 132 - struct circ_buf *xmit = &port->state->xmit; 132 132 + u8 ch; 133 133 134 134 - while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) { 135 135 - if (port->x_char) { 136 136 - mps2_uart_write8(port, port->x_char, UARTn_DATA); 137 137 - port->x_char = 0; 138 138 - port->icount.tx++; 139 139 - continue; 140 140 - } 141 141 - 142 142 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 143 143 - break; 144 144 - 145 145 - mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA); 146 146 - xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; 147 147 - port->icount.tx++; 148 148 - } 149 149 - 150 150 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 151 151 - uart_write_wakeup(port); 152 152 - 153 153 - if (uart_circ_empty(xmit)) 154 154 - mps2_uart_stop_tx(port); 134 134 + uart_port_tx(port, ch, 135 135 + mps2_uart_tx_empty(port), 136 136 + mps2_uart_write8(port, ch, UARTn_DATA)); 155 137 } 156 138 157 139 static void mps2_uart_start_tx(struct uart_port *port)

+4 -9

drivers/tty/serial/msm_serial.c

reviewed

··· 464 464 } 465 465 466 466 count = dma->count - state.residue; 467 467 - port->icount.tx += count; 467 467 + uart_xmit_advance(port, count); 468 468 dma->count = 0; 469 469 - 470 470 - xmit->tail += count; 471 471 - xmit->tail &= UART_XMIT_SIZE - 1; 472 469 473 470 /* Restore "Tx FIFO below watermark" interrupt */ 474 471 msm_port->imr |= MSM_UART_IMR_TXLEV; ··· 816 819 port->icount.rx++; 817 820 } 818 821 819 819 - /* Mask conditions we're ignorning. */ 822 822 + /* Mask conditions we're ignoring. */ 820 823 sr &= port->read_status_mask; 821 824 822 825 if (sr & MSM_UART_SR_RX_BREAK) ··· 863 866 else 864 867 num_chars = 1; 865 868 866 866 - for (i = 0; i < num_chars; i++) { 869 869 + for (i = 0; i < num_chars; i++) 867 870 buf[i] = xmit->buf[xmit->tail + i]; 868 868 - port->icount.tx++; 869 869 - } 870 871 871 872 iowrite32_rep(tf, buf, 1); 872 872 - xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 873 873 + uart_xmit_advance(port, num_chars); 873 874 tf_pointer += num_chars; 874 875 } 875 876

+13 -32

drivers/tty/serial/mux.c

reviewed

··· 171 171 { 172 172 } 173 173 174 174 + static void mux_tx_done(struct uart_port *port) 175 175 + { 176 176 + /* FIXME js: really needs to wait? */ 177 177 + while (UART_GET_FIFO_CNT(port)) 178 178 + udelay(1); 179 179 + } 180 180 + 174 181 /** 175 182 * mux_write - Write chars to the mux fifo. 176 183 * @port: Ptr to the uart_port. ··· 187 180 */ 188 181 static void mux_write(struct uart_port *port) 189 182 { 190 190 - int count; 191 191 - struct circ_buf *xmit = &port->state->xmit; 183 183 + u8 ch; 192 184 193 193 - if(port->x_char) { 194 194 - UART_PUT_CHAR(port, port->x_char); 195 195 - port->icount.tx++; 196 196 - port->x_char = 0; 197 197 - return; 198 198 - } 199 199 - 200 200 - if(uart_circ_empty(xmit) || uart_tx_stopped(port)) { 201 201 - mux_stop_tx(port); 202 202 - return; 203 203 - } 204 204 - 205 205 - count = (port->fifosize) - UART_GET_FIFO_CNT(port); 206 206 - do { 207 207 - UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 208 208 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 209 209 - port->icount.tx++; 210 210 - if(uart_circ_empty(xmit)) 211 211 - break; 212 212 - 213 213 - } while(--count > 0); 214 214 - 215 215 - while(UART_GET_FIFO_CNT(port)) 216 216 - udelay(1); 217 217 - 218 218 - if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 219 219 - uart_write_wakeup(port); 220 220 - 221 221 - if (uart_circ_empty(xmit)) 222 222 - mux_stop_tx(port); 185 185 + uart_port_tx_limited(port, ch, 186 186 + port->fifosize - UART_GET_FIFO_CNT(port), 187 187 + true, 188 188 + UART_PUT_CHAR(port, ch), 189 189 + mux_tx_done(port)); 223 190 } 224 191 225 192 /**

+6 -35

drivers/tty/serial/mvebu-uart.c

reviewed

··· 223 223 224 224 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { 225 225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 226 226 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 227 227 - port->icount.tx++; 226 226 + uart_xmit_advance(port, 1); 228 227 } 229 228 230 229 ctl = readl(port->membase + UART_INTR(port)); ··· 334 335 335 336 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) 336 337 { 337 337 - struct circ_buf *xmit = &port->state->xmit; 338 338 - unsigned int count; 339 339 - unsigned int st; 338 338 + u8 ch; 340 339 341 341 - if (port->x_char) { 342 342 - writel(port->x_char, port->membase + UART_TSH(port)); 343 343 - port->icount.tx++; 344 344 - port->x_char = 0; 345 345 - return; 346 346 - } 347 347 - 348 348 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 349 349 - mvebu_uart_stop_tx(port); 350 350 - return; 351 351 - } 352 352 - 353 353 - for (count = 0; count < port->fifosize; count++) { 354 354 - writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 355 355 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 356 356 - port->icount.tx++; 357 357 - 358 358 - if (uart_circ_empty(xmit)) 359 359 - break; 360 360 - 361 361 - st = readl(port->membase + UART_STAT); 362 362 - if (st & STAT_TX_FIFO_FUL) 363 363 - break; 364 364 - } 365 365 - 366 366 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 367 367 - uart_write_wakeup(port); 368 368 - 369 369 - if (uart_circ_empty(xmit)) 370 370 - mvebu_uart_stop_tx(port); 340 340 + uart_port_tx_limited(port, ch, port->fifosize, 341 341 + !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), 342 342 + writel(ch, port->membase + UART_TSH(port)), 343 343 + ({})); 371 344 } 372 345 373 346 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)

+8 -24

drivers/tty/serial/mxs-auart.c

reviewed

··· 569 569 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 570 570 { 571 571 struct circ_buf *xmit = &s->port.state->xmit; 572 572 + bool pending; 573 573 + u8 ch; 572 574 573 575 if (auart_dma_enabled(s)) { 574 576 u32 i = 0; ··· 605 603 return; 606 604 } 607 605 608 608 - 609 609 - while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) { 610 610 - if (s->port.x_char) { 611 611 - s->port.icount.tx++; 612 612 - mxs_write(s->port.x_char, s, REG_DATA); 613 613 - s->port.x_char = 0; 614 614 - continue; 615 615 - } 616 616 - if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 617 617 - s->port.icount.tx++; 618 618 - mxs_write(xmit->buf[xmit->tail], s, REG_DATA); 619 619 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 620 620 - } else 621 621 - break; 622 622 - } 623 623 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 624 624 - uart_write_wakeup(&s->port); 625 625 - 626 626 - if (uart_circ_empty(&(s->port.state->xmit))) 627 627 - mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); 628 628 - else 606 606 + pending = uart_port_tx(&s->port, ch, 607 607 + !(mxs_read(s, REG_STAT) & AUART_STAT_TXFF), 608 608 + mxs_write(ch, s, REG_DATA)); 609 609 + if (pending) 629 610 mxs_set(AUART_INTR_TXIEN, s, REG_INTR); 630 630 - 631 631 - if (uart_tx_stopped(&s->port)) 632 632 - mxs_auart_stop_tx(&s->port); 611 611 + else 612 612 + mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); 633 613 } 634 614 635 615 static void mxs_auart_rx_char(struct mxs_auart_port *s)

+5 -27

drivers/tty/serial/omap-serial.c

reviewed

··· 347 347 348 348 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 349 349 { 350 350 - struct circ_buf *xmit = &up->port.state->xmit; 351 351 - int count; 350 350 + u8 ch; 352 351 353 353 - if (up->port.x_char) { 354 354 - serial_omap_put_char(up, up->port.x_char); 355 355 - up->port.icount.tx++; 356 356 - up->port.x_char = 0; 357 357 - return; 358 358 - } 359 359 - if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 360 360 - serial_omap_stop_tx(&up->port); 361 361 - return; 362 362 - } 363 363 - count = up->port.fifosize / 4; 364 364 - do { 365 365 - serial_omap_put_char(up, xmit->buf[xmit->tail]); 366 366 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 367 367 - up->port.icount.tx++; 368 368 - 369 369 - if (uart_circ_empty(xmit)) 370 370 - break; 371 371 - } while (--count > 0); 372 372 - 373 373 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 374 374 - uart_write_wakeup(&up->port); 375 375 - 376 376 - if (uart_circ_empty(xmit)) 377 377 - serial_omap_stop_tx(&up->port); 352 352 + uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4, 353 353 + true, 354 354 + serial_omap_put_char(up, ch), 355 355 + ({})); 378 356 } 379 357 380 358 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)

+4 -28

drivers/tty/serial/owl-uart.c

reviewed

··· 181 181 182 182 static void owl_uart_send_chars(struct uart_port *port) 183 183 { 184 184 - struct circ_buf *xmit = &port->state->xmit; 185 185 - unsigned int ch; 184 184 + u8 ch; 186 185 187 187 - if (port->x_char) { 188 188 - while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) 189 189 - cpu_relax(); 190 190 - owl_uart_write(port, port->x_char, OWL_UART_TXDAT); 191 191 - port->icount.tx++; 192 192 - port->x_char = 0; 193 193 - } 194 194 - 195 195 - if (uart_tx_stopped(port)) 196 196 - return; 197 197 - 198 198 - while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) { 199 199 - if (uart_circ_empty(xmit)) 200 200 - break; 201 201 - 202 202 - ch = xmit->buf[xmit->tail]; 203 203 - owl_uart_write(port, ch, OWL_UART_TXDAT); 204 204 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 205 205 - port->icount.tx++; 206 206 - } 207 207 - 208 208 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 209 209 - uart_write_wakeup(port); 210 210 - 211 211 - if (uart_circ_empty(xmit)) 212 212 - owl_uart_stop_tx(port); 186 186 + uart_port_tx(port, ch, 187 187 + !(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU), 188 188 + owl_uart_write(port, ch, OWL_UART_TXDAT)); 213 189 } 214 190 215 191 static void owl_uart_receive_chars(struct uart_port *port)

+8 -8

drivers/tty/serial/pch_uart.c

reviewed

··· 694 694 if (!chan) { 695 695 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 696 696 __func__); 697 697 + pci_dev_put(dma_dev); 697 698 return; 698 699 } 699 700 priv->chan_tx = chan; ··· 711 710 __func__); 712 711 dma_release_channel(priv->chan_tx); 713 712 priv->chan_tx = NULL; 713 713 + pci_dev_put(dma_dev); 714 714 return; 715 715 } 716 716 ··· 719 717 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 720 718 &priv->rx_buf_dma, GFP_KERNEL); 721 719 priv->chan_rx = chan; 720 720 + 721 721 + pci_dev_put(dma_dev); 722 722 } 723 723 724 724 static void pch_dma_rx_complete(void *arg) ··· 742 738 { 743 739 struct eg20t_port *priv = arg; 744 740 struct uart_port *port = &priv->port; 745 745 - struct circ_buf *xmit = &port->state->xmit; 746 741 struct scatterlist *sg = priv->sg_tx_p; 747 742 int i; 748 743 749 749 - for (i = 0; i < priv->nent; i++, sg++) { 750 750 - xmit->tail += sg_dma_len(sg); 751 751 - port->icount.tx += sg_dma_len(sg); 752 752 - } 753 753 - xmit->tail &= UART_XMIT_SIZE - 1; 744 744 + for (i = 0; i < priv->nent; i++, sg++) 745 745 + uart_xmit_advance(port, sg_dma_len(sg)); 746 746 + 754 747 async_tx_ack(priv->desc_tx); 755 748 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE); 756 749 priv->tx_dma_use = 0; ··· 844 843 845 844 while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) { 846 845 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR); 847 847 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 848 848 - port->icount.tx++; 846 846 + uart_xmit_advance(port, 1); 849 847 fifo_size--; 850 848 tx_empty = 0; 851 849 }

+1 -2

drivers/tty/serial/pic32_uart.c

reviewed

··· 376 376 377 377 pic32_uart_writel(sport, PIC32_UART_TX, c); 378 378 379 379 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 380 380 - port->icount.tx++; 379 379 + uart_xmit_advance(port, 1); 381 380 if (uart_circ_empty(xmit)) 382 381 break; 383 382 if (--max_count == 0)

+2 -4

drivers/tty/serial/pmac_zilog.c

reviewed

··· 410 410 write_zsdata(uap, xmit->buf[xmit->tail]); 411 411 zssync(uap); 412 412 413 413 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 414 414 - uap->port.icount.tx++; 413 413 + uart_xmit_advance(&uap->port, 1); 415 414 416 415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 417 416 uart_write_wakeup(&uap->port); ··· 626 627 return; 627 628 write_zsdata(uap, xmit->buf[xmit->tail]); 628 629 zssync(uap); 629 629 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 630 630 - port->icount.tx++; 630 630 + uart_xmit_advance(port, 1); 631 631 632 632 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 633 633 uart_write_wakeup(&uap->port);

+5 -28

drivers/tty/serial/pxa.c

reviewed

··· 174 174 175 175 static void transmit_chars(struct uart_pxa_port *up) 176 176 { 177 177 - struct circ_buf *xmit = &up->port.state->xmit; 178 178 - int count; 177 177 + u8 ch; 179 178 180 180 - if (up->port.x_char) { 181 181 - serial_out(up, UART_TX, up->port.x_char); 182 182 - up->port.icount.tx++; 183 183 - up->port.x_char = 0; 184 184 - return; 185 185 - } 186 186 - if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 187 187 - serial_pxa_stop_tx(&up->port); 188 188 - return; 189 189 - } 190 190 - 191 191 - count = up->port.fifosize / 2; 192 192 - do { 193 193 - serial_out(up, UART_TX, xmit->buf[xmit->tail]); 194 194 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 195 195 - up->port.icount.tx++; 196 196 - if (uart_circ_empty(xmit)) 197 197 - break; 198 198 - } while (--count > 0); 199 199 - 200 200 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 201 201 - uart_write_wakeup(&up->port); 202 202 - 203 203 - 204 204 - if (uart_circ_empty(xmit)) 205 205 - serial_pxa_stop_tx(&up->port); 179 179 + uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2, 180 180 + true, 181 181 + serial_out(up, UART_TX, ch), 182 182 + ({})); 206 183 } 207 184 208 185 static void serial_pxa_start_tx(struct uart_port *port)

+35

drivers/tty/serial/qcom_geni_serial.c

reviewed

··· 924 924 false, true, true); 925 925 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 926 926 geni_se_select_mode(&port->se, GENI_SE_FIFO); 927 927 + qcom_geni_serial_start_rx(uport); 927 928 port->setup = true; 928 929 929 930 return 0; ··· 1548 1547 return ret; 1549 1548 } 1550 1549 1550 1550 + static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1551 1551 + { 1552 1552 + int ret = 0; 1553 1553 + struct uart_port *uport; 1554 1554 + struct qcom_geni_private_data *private_data; 1555 1555 + struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1556 1556 + 1557 1557 + uport = &port->uport; 1558 1558 + private_data = uport->private_data; 1559 1559 + 1560 1560 + if (uart_console(uport)) { 1561 1561 + geni_icc_set_tag(&port->se, 0x7); 1562 1562 + geni_icc_set_bw(&port->se); 1563 1563 + ret = uart_resume_port(private_data->drv, uport); 1564 1564 + /* 1565 1565 + * For hibernation usecase clients for 1566 1566 + * console UART won't call port setup during restore, 1567 1567 + * hence call port setup for console uart. 1568 1568 + */ 1569 1569 + qcom_geni_serial_port_setup(uport); 1570 1570 + } else { 1571 1571 + /* 1572 1572 + * Peripheral register settings are lost during hibernation. 1573 1573 + * Update setup flag such that port setup happens again 1574 1574 + * during next session. Clients of HS-UART will close and 1575 1575 + * open the port during hibernation. 1576 1576 + */ 1577 1577 + port->setup = false; 1578 1578 + } 1579 1579 + return ret; 1580 1580 + } 1581 1581 + 1551 1582 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1552 1583 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1553 1584 qcom_geni_serial_sys_resume) 1585 1585 + .restore = qcom_geni_serial_sys_hib_resume, 1586 1586 + .thaw = qcom_geni_serial_sys_hib_resume, 1554 1587 }; 1555 1588 1556 1589 static const struct of_device_id qcom_geni_serial_match_table[] = {

+1 -2

drivers/tty/serial/rda-uart.c

reviewed

··· 353 353 354 354 ch = xmit->buf[xmit->tail]; 355 355 rda_uart_write(port, ch, RDA_UART_RXTX_BUFFER); 356 356 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 357 357 - port->icount.tx++; 356 356 + uart_xmit_advance(port, 1); 358 357 } 359 358 360 359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+6 -25

drivers/tty/serial/rp2.c

reviewed

··· 427 427 428 428 static void rp2_tx_chars(struct rp2_uart_port *up) 429 429 { 430 430 - u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT); 431 431 - struct circ_buf *xmit = &up->port.state->xmit; 430 430 + u8 ch; 432 431 433 433 - if (uart_tx_stopped(&up->port)) { 434 434 - rp2_uart_stop_tx(&up->port); 435 435 - return; 436 436 - } 437 437 - 438 438 - for (; max_tx != 0; max_tx--) { 439 439 - if (up->port.x_char) { 440 440 - writeb(up->port.x_char, up->base + RP2_DATA_BYTE); 441 441 - up->port.x_char = 0; 442 442 - up->port.icount.tx++; 443 443 - continue; 444 444 - } 445 445 - if (uart_circ_empty(xmit)) { 446 446 - rp2_uart_stop_tx(&up->port); 447 447 - break; 448 448 - } 449 449 - writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE); 450 450 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 451 451 - up->port.icount.tx++; 452 452 - } 453 453 - 454 454 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 455 455 - uart_write_wakeup(&up->port); 432 432 + uart_port_tx_limited(&up->port, ch, 433 433 + FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT), 434 434 + true, 435 435 + writeb(ch, up->base + RP2_DATA_BYTE), 436 436 + ({})); 456 437 } 457 438 458 439 static void rp2_ch_interrupt(struct rp2_uart_port *up)

+4 -30

drivers/tty/serial/sa1100.c

reviewed

··· 228 228 229 229 static void sa1100_tx_chars(struct sa1100_port *sport) 230 230 { 231 231 - struct circ_buf *xmit = &sport->port.state->xmit; 232 232 - 233 233 - if (sport->port.x_char) { 234 234 - UART_PUT_CHAR(sport, sport->port.x_char); 235 235 - sport->port.icount.tx++; 236 236 - sport->port.x_char = 0; 237 237 - return; 238 238 - } 231 231 + u8 ch; 239 232 240 233 /* 241 234 * Check the modem control lines before ··· 236 243 */ 237 244 sa1100_mctrl_check(sport); 238 245 239 239 - if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 240 240 - sa1100_stop_tx(&sport->port); 241 241 - return; 242 242 - } 243 243 - 244 244 - /* 245 245 - * Tried using FIFO (not checking TNF) for fifo fill: 246 246 - * still had the '4 bytes repeated' problem. 247 247 - */ 248 248 - while (UART_GET_UTSR1(sport) & UTSR1_TNF) { 249 249 - UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); 250 250 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 251 251 - sport->port.icount.tx++; 252 252 - if (uart_circ_empty(xmit)) 253 253 - break; 254 254 - } 255 255 - 256 256 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 257 257 - uart_write_wakeup(&sport->port); 258 258 - 259 259 - if (uart_circ_empty(xmit)) 260 260 - sa1100_stop_tx(&sport->port); 246 246 + uart_port_tx(&sport->port, ch, 247 247 + UART_GET_UTSR1(sport) & UTSR1_TNF, 248 248 + UART_PUT_CHAR(sport, ch)); 261 249 } 262 250 263 251 static irqreturn_t sa1100_int(int irq, void *dev_id)

+3 -7

drivers/tty/serial/samsung_tty.c

reviewed

··· 288 288 { 289 289 struct s3c24xx_uart_port *ourport = to_ourport(port); 290 290 struct s3c24xx_uart_dma *dma = ourport->dma; 291 291 - struct circ_buf *xmit = &port->state->xmit; 292 291 struct dma_tx_state state; 293 292 int count; 294 293 ··· 315 316 DMA_TO_DEVICE); 316 317 async_tx_ack(dma->tx_desc); 317 318 count = dma->tx_bytes_requested - state.residue; 318 318 - xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 319 319 - port->icount.tx += count; 319 319 + uart_xmit_advance(port, count); 320 320 } 321 321 322 322 ourport->tx_enabled = 0; ··· 349 351 350 352 spin_lock_irqsave(&port->lock, flags); 351 353 352 352 - xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 353 353 - port->icount.tx += count; 354 354 + uart_xmit_advance(port, count); 354 355 ourport->tx_in_progress = 0; 355 356 356 357 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ··· 913 916 break; 914 917 915 918 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 916 916 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 917 917 - port->icount.tx++; 919 919 + uart_xmit_advance(port, 1); 918 920 count--; 919 921 } 920 922

+1 -2

drivers/tty/serial/sb1250-duart.c

reviewed

··· 399 399 /* Send char. */ 400 400 if (!stop_tx) { 401 401 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]); 402 402 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 403 403 - sport->port.icount.tx++; 402 402 + uart_xmit_advance(&sport->port, 1); 404 403 405 404 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 406 405 uart_write_wakeup(&sport->port);

+1 -4

drivers/tty/serial/sc16is7xx.c

reviewed

··· 686 686 } 687 687 to_send = (to_send > txlen) ? txlen : to_send; 688 688 689 689 - /* Add data to send */ 690 690 - port->icount.tx += to_send; 691 691 - 692 689 /* Convert to linear buffer */ 693 690 for (i = 0; i < to_send; ++i) { 694 691 s->buf[i] = xmit->buf[xmit->tail]; 695 695 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 692 692 + uart_xmit_advance(port, 1); 696 693 } 697 694 698 695 sc16is7xx_fifo_write(port, to_send);

+1 -2

drivers/tty/serial/sccnxp.c

reviewed

··· 468 468 break; 469 469 470 470 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 471 471 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 472 472 - port->icount.tx++; 471 471 + uart_xmit_advance(port, 1); 473 472 } 474 473 475 474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+5 -4

drivers/tty/serial/serial-tegra.c

reviewed

··· 496 496 break; 497 497 } 498 498 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 499 499 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 500 500 - tup->uport.icount.tx++; 499 499 + uart_xmit_advance(&tup->uport, 1); 501 500 } 502 501 } 503 502 ··· 618 619 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 619 620 return; 620 621 621 621 - dmaengine_terminate_all(tup->tx_dma_chan); 622 622 + dmaengine_pause(tup->tx_dma_chan); 622 623 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 624 624 + dmaengine_terminate_all(tup->tx_dma_chan); 623 625 count = tup->tx_bytes_requested - state.residue; 624 626 async_tx_ack(tup->tx_dma_desc); 625 627 uart_xmit_advance(&tup->uport, count); ··· 763 763 return; 764 764 } 765 765 766 766 - dmaengine_terminate_all(tup->rx_dma_chan); 766 766 + dmaengine_pause(tup->rx_dma_chan); 767 767 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 768 768 + dmaengine_terminate_all(tup->rx_dma_chan); 768 769 769 770 tegra_uart_rx_buffer_push(tup, state.residue); 770 771 tup->rx_dma_active = false;

+5 -27

drivers/tty/serial/serial_txx9.c

reviewed

··· 321 321 322 322 static inline void transmit_chars(struct uart_port *up) 323 323 { 324 324 - struct circ_buf *xmit = &up->state->xmit; 325 325 - int count; 324 324 + u8 ch; 326 325 327 327 - if (up->x_char) { 328 328 - sio_out(up, TXX9_SITFIFO, up->x_char); 329 329 - up->icount.tx++; 330 330 - up->x_char = 0; 331 331 - return; 332 332 - } 333 333 - if (uart_circ_empty(xmit) || uart_tx_stopped(up)) { 334 334 - serial_txx9_stop_tx(up); 335 335 - return; 336 336 - } 337 337 - 338 338 - count = TXX9_SIO_TX_FIFO; 339 339 - do { 340 340 - sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]); 341 341 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 342 342 - up->icount.tx++; 343 343 - if (uart_circ_empty(xmit)) 344 344 - break; 345 345 - } while (--count > 0); 346 346 - 347 347 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 348 348 - uart_write_wakeup(up); 349 349 - 350 350 - if (uart_circ_empty(xmit)) 351 351 - serial_txx9_stop_tx(up); 326 326 + uart_port_tx_limited(up, ch, TXX9_SIO_TX_FIFO, 327 327 + true, 328 328 + sio_out(up, TXX9_SITFIFO, ch), 329 329 + ({})); 352 330 } 353 331 354 332 static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)

+1 -4

drivers/tty/serial/sh-sci.c

reviewed

··· 1181 1181 1182 1182 spin_lock_irqsave(&port->lock, flags); 1183 1183 1184 1184 - xmit->tail += s->tx_dma_len; 1185 1185 - xmit->tail &= UART_XMIT_SIZE - 1; 1186 1186 - 1187 1187 - port->icount.tx += s->tx_dma_len; 1184 1184 + uart_xmit_advance(port, s->tx_dma_len); 1188 1185 1189 1186 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1190 1187 uart_write_wakeup(port);

+5 -26

drivers/tty/serial/sifive.c

reviewed

··· 288 288 */ 289 289 static void __ssp_transmit_chars(struct sifive_serial_port *ssp) 290 290 { 291 291 - struct circ_buf *xmit = &ssp->port.state->xmit; 292 292 - int count; 291 291 + u8 ch; 293 292 294 294 - if (ssp->port.x_char) { 295 295 - __ssp_transmit_char(ssp, ssp->port.x_char); 296 296 - ssp->port.icount.tx++; 297 297 - ssp->port.x_char = 0; 298 298 - return; 299 299 - } 300 300 - if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) { 301 301 - sifive_serial_stop_tx(&ssp->port); 302 302 - return; 303 303 - } 304 304 - count = SIFIVE_TX_FIFO_DEPTH; 305 305 - do { 306 306 - __ssp_transmit_char(ssp, xmit->buf[xmit->tail]); 307 307 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 308 308 - ssp->port.icount.tx++; 309 309 - if (uart_circ_empty(xmit)) 310 310 - break; 311 311 - } while (--count > 0); 312 312 - 313 313 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 314 314 - uart_write_wakeup(&ssp->port); 315 315 - 316 316 - if (uart_circ_empty(xmit)) 317 317 - sifive_serial_stop_tx(&ssp->port); 293 293 + uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH, 294 294 + true, 295 295 + __ssp_transmit_char(ssp, ch), 296 296 + ({})); 318 297 } 319 298 320 299 /**

+7 -33

drivers/tty/serial/sprd_serial.c

reviewed

··· 206 206 { 207 207 struct sprd_uart_port *sp = 208 208 container_of(port, struct sprd_uart_port, port); 209 209 - struct circ_buf *xmit = &port->state->xmit; 210 209 struct dma_tx_state state; 211 210 u32 trans_len; 212 211 ··· 214 215 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state); 215 216 if (state.residue) { 216 217 trans_len = state.residue - sp->tx_dma.phys_addr; 217 217 - xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1); 218 218 - port->icount.tx += trans_len; 218 218 + uart_xmit_advance(port, trans_len); 219 219 dma_unmap_single(port->dev, sp->tx_dma.phys_addr, 220 220 sp->tx_dma.trans_len, DMA_TO_DEVICE); 221 221 } ··· 251 253 dma_unmap_single(port->dev, sp->tx_dma.phys_addr, 252 254 sp->tx_dma.trans_len, DMA_TO_DEVICE); 253 255 254 254 - xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1); 255 255 - port->icount.tx += sp->tx_dma.trans_len; 256 256 + uart_xmit_advance(port, sp->tx_dma.trans_len); 256 257 257 258 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 258 259 uart_write_wakeup(port); ··· 623 626 624 627 static inline void sprd_tx(struct uart_port *port) 625 628 { 626 626 - struct circ_buf *xmit = &port->state->xmit; 627 627 - int count; 629 629 + u8 ch; 628 630 629 629 - if (port->x_char) { 630 630 - serial_out(port, SPRD_TXD, port->x_char); 631 631 - port->icount.tx++; 632 632 - port->x_char = 0; 633 633 - return; 634 634 - } 635 635 - 636 636 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 637 637 - sprd_stop_tx(port); 638 638 - return; 639 639 - } 640 640 - 641 641 - count = THLD_TX_EMPTY; 642 642 - do { 643 643 - serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]); 644 644 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 645 645 - port->icount.tx++; 646 646 - if (uart_circ_empty(xmit)) 647 647 - break; 648 648 - } while (--count > 0); 649 649 - 650 650 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 651 651 - uart_write_wakeup(port); 652 652 - 653 653 - if (uart_circ_empty(xmit)) 654 654 - sprd_stop_tx(port); 631 631 + uart_port_tx_limited(port, ch, THLD_TX_EMPTY, 632 632 + true, 633 633 + serial_out(port, SPRD_TXD, ch), 634 634 + ({})); 655 635 } 656 636 657 637 /* this handles the interrupt from one port */

+5 -43

drivers/tty/serial/st-asc.c

reviewed

··· 237 237 */ 238 238 static void asc_transmit_chars(struct uart_port *port) 239 239 { 240 240 - struct circ_buf *xmit = &port->state->xmit; 241 241 - int txroom; 242 242 - unsigned char c; 240 240 + u8 ch; 243 241 244 244 - txroom = asc_hw_txroom(port); 245 245 - 246 246 - if ((txroom != 0) && port->x_char) { 247 247 - c = port->x_char; 248 248 - port->x_char = 0; 249 249 - asc_out(port, ASC_TXBUF, c); 250 250 - port->icount.tx++; 251 251 - txroom = asc_hw_txroom(port); 252 252 - } 253 253 - 254 254 - if (uart_tx_stopped(port)) { 255 255 - /* 256 256 - * We should try and stop the hardware here, but I 257 257 - * don't think the ASC has any way to do that. 258 258 - */ 259 259 - asc_disable_tx_interrupts(port); 260 260 - return; 261 261 - } 262 262 - 263 263 - if (uart_circ_empty(xmit)) { 264 264 - asc_disable_tx_interrupts(port); 265 265 - return; 266 266 - } 267 267 - 268 268 - if (txroom == 0) 269 269 - return; 270 270 - 271 271 - do { 272 272 - c = xmit->buf[xmit->tail]; 273 273 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 274 274 - asc_out(port, ASC_TXBUF, c); 275 275 - port->icount.tx++; 276 276 - txroom--; 277 277 - } while ((txroom > 0) && (!uart_circ_empty(xmit))); 278 278 - 279 279 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 280 280 - uart_write_wakeup(port); 281 281 - 282 282 - if (uart_circ_empty(xmit)) 283 283 - asc_disable_tx_interrupts(port); 242 242 + uart_port_tx_limited(port, ch, asc_hw_txroom(port), 243 243 + true, 244 244 + asc_out(port, ASC_TXBUF, ch), 245 245 + ({})); 284 246 } 285 247 286 248 static void asc_receive_chars(struct uart_port *port)

+26 -28

drivers/tty/serial/stm32-usart.c

reviewed

··· 596 596 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 597 597 break; 598 598 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 599 599 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 600 600 - port->icount.tx++; 599 599 + uart_xmit_advance(port, 1); 601 600 } 602 601 603 602 /* rely on TXE irq (mask or unmask) for sending remaining data */ ··· 672 673 673 674 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 674 675 675 675 - xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 676 676 - port->icount.tx += count; 676 676 + uart_xmit_advance(port, count); 677 677 + 677 678 return; 678 679 679 680 fallback_err: ··· 1680 1681 if (!stm32port->info) 1681 1682 return -EINVAL; 1682 1683 1683 1683 - ret = stm32_usart_init_port(stm32port, pdev); 1684 1684 - if (ret) 1685 1685 - return ret; 1686 1686 - 1687 1687 - if (stm32port->wakeup_src) { 1688 1688 - device_set_wakeup_capable(&pdev->dev, true); 1689 1689 - ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1690 1690 - if (ret) 1691 1691 - goto err_deinit_port; 1692 1692 - } 1693 1693 - 1694 1684 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); 1695 1695 - if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) { 1696 1696 - ret = -EPROBE_DEFER; 1697 1697 - goto err_wakeirq; 1698 1698 - } 1685 1685 + if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) 1686 1686 + return -EPROBE_DEFER; 1687 1687 + 1699 1688 /* Fall back in interrupt mode for any non-deferral error */ 1700 1689 if (IS_ERR(stm32port->rx_ch)) 1701 1690 stm32port->rx_ch = NULL; ··· 1696 1709 /* Fall back in interrupt mode for any non-deferral error */ 1697 1710 if (IS_ERR(stm32port->tx_ch)) 1698 1711 stm32port->tx_ch = NULL; 1712 1712 + 1713 1713 + ret = stm32_usart_init_port(stm32port, pdev); 1714 1714 + if (ret) 1715 1715 + goto err_dma_tx; 1716 1716 + 1717 1717 + if (stm32port->wakeup_src) { 1718 1718 + device_set_wakeup_capable(&pdev->dev, true); 1719 1719 + ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1720 1720 + if (ret) 1721 1721 + goto err_deinit_port; 1722 1722 + } 1699 1723 1700 1724 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { 1701 1725 /* Fall back in interrupt mode */ ··· 1744 1746 pm_runtime_set_suspended(&pdev->dev); 1745 1747 pm_runtime_put_noidle(&pdev->dev); 1746 1748 1747 1747 - if (stm32port->tx_ch) { 1749 1749 + if (stm32port->tx_ch) 1748 1750 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1749 1749 - dma_release_channel(stm32port->tx_ch); 1750 1750 - } 1751 1751 - 1752 1751 if (stm32port->rx_ch) 1753 1752 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1754 1753 1755 1755 - err_dma_rx: 1756 1756 - if (stm32port->rx_ch) 1757 1757 - dma_release_channel(stm32port->rx_ch); 1758 1758 - 1759 1759 - err_wakeirq: 1760 1754 if (stm32port->wakeup_src) 1761 1755 dev_pm_clear_wake_irq(&pdev->dev); 1762 1756 ··· 1757 1767 device_set_wakeup_capable(&pdev->dev, false); 1758 1768 1759 1769 stm32_usart_deinit_port(stm32port); 1770 1770 + 1771 1771 + err_dma_tx: 1772 1772 + if (stm32port->tx_ch) 1773 1773 + dma_release_channel(stm32port->tx_ch); 1774 1774 + 1775 1775 + err_dma_rx: 1776 1776 + if (stm32port->rx_ch) 1777 1777 + dma_release_channel(stm32port->rx_ch); 1760 1778 1761 1779 return ret; 1762 1780 }

+2 -4

drivers/tty/serial/sunhv.c

reviewed

··· 47 47 if (status != HV_EOK) 48 48 break; 49 49 50 50 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 51 51 - port->icount.tx++; 50 50 + uart_xmit_advance(port, 1); 52 51 } 53 52 } 54 53 ··· 62 63 status = sun4v_con_write(ra, len, &sent); 63 64 if (status != HV_EOK) 64 65 break; 65 65 - xmit->tail = (xmit->tail + sent) & (UART_XMIT_SIZE - 1); 66 66 - port->icount.tx += sent; 66 66 + uart_xmit_advance(port, sent); 67 67 } 68 68 } 69 69

+1 -3

drivers/tty/serial/sunplus-uart.c

reviewed

··· 216 216 217 217 do { 218 218 sp_uart_put_char(port, xmit->buf[xmit->tail]); 219 219 - xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; 220 220 - port->icount.tx++; 221 221 - 219 219 + uart_xmit_advance(port, 1); 222 220 if (uart_circ_empty(xmit)) 223 221 break; 224 222 } while (sunplus_tx_buf_not_full(port));

+9 -5

drivers/tty/serial/sunsab.c

reviewed

··· 266 266 for (i = 0; i < up->port.fifosize; i++) { 267 267 writeb(xmit->buf[xmit->tail], 268 268 &up->regs->w.xfifo[i]); 269 269 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 270 270 - up->port.icount.tx++; 269 269 + uart_xmit_advance(&up->port, 1); 271 270 if (uart_circ_empty(xmit)) 272 271 break; 273 272 } ··· 452 453 for (i = 0; i < up->port.fifosize; i++) { 453 454 writeb(xmit->buf[xmit->tail], 454 455 &up->regs->w.xfifo[i]); 455 455 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 456 456 - up->port.icount.tx++; 456 456 + uart_xmit_advance(&up->port, 1); 457 457 if (uart_circ_empty(xmit)) 458 458 break; 459 459 } ··· 1131 1133 } 1132 1134 } 1133 1135 1134 1134 - return platform_driver_register(&sab_driver); 1136 1136 + err = platform_driver_register(&sab_driver); 1137 1137 + if (err) { 1138 1138 + kfree(sunsab_ports); 1139 1139 + sunsab_ports = NULL; 1140 1140 + } 1141 1141 + 1142 1142 + return err; 1135 1143 } 1136 1144 1137 1145 static void __exit sunsab_exit(void)

+1 -2

drivers/tty/serial/sunsu.c

reviewed

··· 417 417 count = up->port.fifosize; 418 418 do { 419 419 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 420 420 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 421 421 - up->port.icount.tx++; 420 420 + uart_xmit_advance(&up->port, 1); 422 421 if (uart_circ_empty(xmit)) 423 422 break; 424 423 } while (--count > 0);

+2 -4

drivers/tty/serial/sunzilog.c

reviewed

··· 508 508 ZSDELAY(); 509 509 ZS_WSYNC(channel); 510 510 511 511 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 512 512 - up->port.icount.tx++; 511 511 + uart_xmit_advance(&up->port, 1); 513 512 514 513 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 515 514 uart_write_wakeup(&up->port); ··· 708 709 ZSDELAY(); 709 710 ZS_WSYNC(channel); 710 711 711 711 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 712 712 - port->icount.tx++; 712 712 + uart_xmit_advance(port, 1); 713 713 714 714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 715 715 uart_write_wakeup(&up->port);

+1 -2

drivers/tty/serial/timbuart.c

reviewed

··· 101 101 !uart_circ_empty(xmit)) { 102 102 iowrite8(xmit->buf[xmit->tail], 103 103 port->membase + TIMBUART_TXFIFO); 104 104 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 105 105 - port->icount.tx++; 104 104 + uart_xmit_advance(port, 1); 106 105 } 107 106 108 107 dev_dbg(port->dev,

+1 -2

drivers/tty/serial/uartlite.c

reviewed

··· 203 203 return 0; 204 204 205 205 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 206 206 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 207 207 - port->icount.tx++; 206 206 + uart_xmit_advance(port, 1); 208 207 209 208 /* wake up */ 210 209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)

+1 -2

drivers/tty/serial/ucc_uart.c

reviewed

··· 372 372 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port); 373 373 while (count < qe_port->tx_fifosize) { 374 374 *p++ = xmit->buf[xmit->tail]; 375 375 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 376 376 - port->icount.tx++; 375 375 + uart_xmit_advance(port, 1); 377 376 count++; 378 377 if (xmit->head == xmit->tail) 379 378 break;

+5 -27

drivers/tty/serial/vt8500_serial.c

reviewed

··· 168 168 169 169 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff; 170 170 171 171 - /* Mask conditions we're ignorning. */ 171 171 + /* Mask conditions we're ignoring. */ 172 172 c &= ~port->read_status_mask; 173 173 174 174 if (c & FER) { ··· 196 196 197 197 static void handle_tx(struct uart_port *port) 198 198 { 199 199 - struct circ_buf *xmit = &port->state->xmit; 199 199 + u8 ch; 200 200 201 201 - if (port->x_char) { 202 202 - writeb(port->x_char, port->membase + VT8500_TXFIFO); 203 203 - port->icount.tx++; 204 204 - port->x_char = 0; 205 205 - } 206 206 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 207 207 - vt8500_stop_tx(port); 208 208 - return; 209 209 - } 210 210 - 211 211 - while (vt8500_tx_empty(port)) { 212 212 - if (uart_circ_empty(xmit)) 213 213 - break; 214 214 - 215 215 - writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO); 216 216 - 217 217 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 218 218 - port->icount.tx++; 219 219 - } 220 220 - 221 221 - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 222 222 - uart_write_wakeup(port); 223 223 - 224 224 - if (uart_circ_empty(xmit)) 225 225 - vt8500_stop_tx(port); 201 201 + uart_port_tx(port, ch, 202 202 + vt8500_tx_empty(port), 203 203 + writeb(ch, port->membase + VT8500_TXFIFO)); 226 204 } 227 205 228 206 static void vt8500_start_tx(struct uart_port *port)

+1 -3

drivers/tty/serial/xilinx_uartps.c

reviewed

··· 326 326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 327 327 328 328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO); 329 329 - 330 330 - port->icount.tx++; 331 331 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 329 329 + uart_xmit_advance(port, 1); 332 330 numbytes--; 333 331 } 334 332

+1 -2

drivers/tty/serial/zs.c

reviewed

··· 623 623 624 624 /* Send char. */ 625 625 write_zsdata(zport, xmit->buf[xmit->tail]); 626 626 - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 627 627 - zport->port.icount.tx++; 626 626 + uart_xmit_advance(&zport->port, 1); 628 627 629 628 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 630 629 uart_write_wakeup(&zport->port);

+10 -9

drivers/tty/synclink_gt.c

reviewed

··· 1433 1433 int rc; 1434 1434 unsigned long flags; 1435 1435 1436 1436 - if (!try_module_get(THIS_MODULE)) 1437 1437 - return -EBUSY; 1438 1438 - 1439 1436 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1440 1440 - 1441 1441 - /* generic HDLC layer open processing */ 1442 1442 - rc = hdlc_open(dev); 1443 1443 - if (rc) 1444 1444 - return rc; 1445 1437 1446 1438 /* arbitrate between network and tty opens */ 1447 1439 spin_lock_irqsave(&info->netlock, flags); ··· 1449 1457 if ((rc = startup(info)) != 0) { 1450 1458 spin_lock_irqsave(&info->netlock, flags); 1451 1459 info->netcount=0; 1460 1460 + spin_unlock_irqrestore(&info->netlock, flags); 1461 1461 + return rc; 1462 1462 + } 1463 1463 + 1464 1464 + /* generic HDLC layer open processing */ 1465 1465 + rc = hdlc_open(dev); 1466 1466 + if (rc) { 1467 1467 + shutdown(info); 1468 1468 + spin_lock_irqsave(&info->netlock, flags); 1469 1469 + info->netcount = 0; 1452 1470 spin_unlock_irqrestore(&info->netlock, flags); 1453 1471 return rc; 1454 1472 } ··· 1508 1506 info->netcount=0; 1509 1507 spin_unlock_irqrestore(&info->netlock, flags); 1510 1508 1511 1511 - module_put(THIS_MODULE); 1512 1509 return 0; 1513 1510 } 1514 1511

+1 -1

drivers/tty/tty.h

reviewed

··· 93 93 int __must_check tty_ldisc_init(struct tty_struct *tty); 94 94 void tty_ldisc_deinit(struct tty_struct *tty); 95 95 96 96 - void tty_sysctl_init(void); 96 96 + extern int tty_ldisc_autoload; 97 97 98 98 /* tty_audit.c */ 99 99 #ifdef CONFIG_AUDIT

+16 -16

drivers/tty/tty_buffer.c

reviewed

··· 21 21 #include "tty.h" 22 22 23 23 #define MIN_TTYB_SIZE 256 24 24 - #define TTYB_ALIGN_MASK 255 24 24 + #define TTYB_ALIGN_MASK 0xff 25 25 26 26 /* 27 27 * Byte threshold to limit memory consumption for flip buffers. ··· 37 37 * logic this must match. 38 38 */ 39 39 40 40 - #define TTY_BUFFER_PAGE (((PAGE_SIZE - sizeof(struct tty_buffer)) / 2) & ~0xFF) 40 40 + #define TTY_BUFFER_PAGE (((PAGE_SIZE - sizeof(struct tty_buffer)) / 2) & ~TTYB_ALIGN_MASK) 41 41 42 42 /** 43 43 * tty_buffer_lock_exclusive - gain exclusive access to buffer ··· 107 107 p->commit = 0; 108 108 p->lookahead = 0; 109 109 p->read = 0; 110 110 - p->flags = 0; 110 110 + p->flags = true; 111 111 } 112 112 113 113 /** ··· 249 249 * __tty_buffer_request_room - grow tty buffer if needed 250 250 * @port: tty port 251 251 * @size: size desired 252 252 - * @flags: buffer flags if new buffer allocated (default = 0) 252 252 + * @flags: buffer has to store flags along character data 253 253 * 254 254 * Make at least @size bytes of linear space available for the tty buffer. 255 255 * ··· 260 260 * Returns: the size we managed to find. 261 261 */ 262 262 static int __tty_buffer_request_room(struct tty_port *port, size_t size, 263 263 - int flags) 263 263 + bool flags) 264 264 { 265 265 struct tty_bufhead *buf = &port->buf; 266 266 struct tty_buffer *b, *n; 267 267 int left, change; 268 268 269 269 b = buf->tail; 270 270 - if (b->flags & TTYB_NORMAL) 270 270 + if (!b->flags) 271 271 left = 2 * b->size - b->used; 272 272 else 273 273 left = b->size - b->used; 274 274 275 275 - change = (b->flags & TTYB_NORMAL) && (~flags & TTYB_NORMAL); 275 275 + change = !b->flags && flags; 276 276 if (change || left < size) { 277 277 /* This is the slow path - looking for new buffers to use */ 278 278 n = tty_buffer_alloc(port, size); ··· 300 300 301 301 int tty_buffer_request_room(struct tty_port *port, size_t size) 302 302 { 303 303 - return __tty_buffer_request_room(port, size, 0); 303 303 + return __tty_buffer_request_room(port, size, true); 304 304 } 305 305 EXPORT_SYMBOL_GPL(tty_buffer_request_room); 306 306 ··· 320 320 const unsigned char *chars, char flag, size_t size) 321 321 { 322 322 int copied = 0; 323 323 + bool flags = flag != TTY_NORMAL; 323 324 324 325 do { 325 326 int goal = min_t(size_t, size - copied, TTY_BUFFER_PAGE); 326 326 - int flags = (flag == TTY_NORMAL) ? TTYB_NORMAL : 0; 327 327 int space = __tty_buffer_request_room(port, goal, flags); 328 328 struct tty_buffer *tb = port->buf.tail; 329 329 330 330 if (unlikely(space == 0)) 331 331 break; 332 332 memcpy(char_buf_ptr(tb, tb->used), chars, space); 333 333 - if (~tb->flags & TTYB_NORMAL) 333 333 + if (tb->flags) 334 334 memset(flag_buf_ptr(tb, tb->used), flag, space); 335 335 tb->used += space; 336 336 copied += space; ··· 393 393 int __tty_insert_flip_char(struct tty_port *port, unsigned char ch, char flag) 394 394 { 395 395 struct tty_buffer *tb; 396 396 - int flags = (flag == TTY_NORMAL) ? TTYB_NORMAL : 0; 396 396 + bool flags = flag != TTY_NORMAL; 397 397 398 398 if (!__tty_buffer_request_room(port, 1, flags)) 399 399 return 0; 400 400 401 401 tb = port->buf.tail; 402 402 - if (~tb->flags & TTYB_NORMAL) 402 402 + if (tb->flags) 403 403 *flag_buf_ptr(tb, tb->used) = flag; 404 404 *char_buf_ptr(tb, tb->used++) = ch; 405 405 ··· 424 424 int tty_prepare_flip_string(struct tty_port *port, unsigned char **chars, 425 425 size_t size) 426 426 { 427 427 - int space = __tty_buffer_request_room(port, size, TTYB_NORMAL); 427 427 + int space = __tty_buffer_request_room(port, size, false); 428 428 429 429 if (likely(space)) { 430 430 struct tty_buffer *tb = port->buf.tail; 431 431 432 432 *chars = char_buf_ptr(tb, tb->used); 433 433 - if (~tb->flags & TTYB_NORMAL) 433 433 + if (tb->flags) 434 434 memset(flag_buf_ptr(tb, tb->used), TTY_NORMAL, space); 435 435 tb->used += space; 436 436 } ··· 492 492 unsigned char *p, *f = NULL; 493 493 494 494 p = char_buf_ptr(head, head->lookahead); 495 495 - if (~head->flags & TTYB_NORMAL) 495 495 + if (head->flags) 496 496 f = flag_buf_ptr(head, head->lookahead); 497 497 498 498 port->client_ops->lookahead_buf(port, p, f, count); ··· 509 509 const char *f = NULL; 510 510 int n; 511 511 512 512 - if (~head->flags & TTYB_NORMAL) 512 512 + if (head->flags) 513 513 f = flag_buf_ptr(head, head->read); 514 514 515 515 n = port->client_ops->receive_buf(port, p, f, count);

+43 -2

drivers/tty/tty_io.c

reviewed

··· 2255 2255 return retval; 2256 2256 } 2257 2257 2258 2258 + static bool tty_legacy_tiocsti __read_mostly = IS_ENABLED(CONFIG_LEGACY_TIOCSTI); 2258 2259 /** 2259 2260 * tiocsti - fake input character 2260 2261 * @tty: tty to fake input into ··· 2273 2272 { 2274 2273 char ch, mbz = 0; 2275 2274 struct tty_ldisc *ld; 2275 2275 + 2276 2276 + if (!tty_legacy_tiocsti) 2277 2277 + return -EIO; 2276 2278 2277 2279 if ((current->signal->tty != tty) && !capable(CAP_SYS_ADMIN)) 2278 2280 return -EPERM; ··· 3592 3588 sysfs_notify(&consdev->kobj, NULL, "active"); 3593 3589 } 3594 3590 3591 3591 + static struct ctl_table tty_table[] = { 3592 3592 + { 3593 3593 + .procname = "legacy_tiocsti", 3594 3594 + .data = &tty_legacy_tiocsti, 3595 3595 + .maxlen = sizeof(tty_legacy_tiocsti), 3596 3596 + .mode = 0644, 3597 3597 + .proc_handler = proc_dobool, 3598 3598 + }, 3599 3599 + { 3600 3600 + .procname = "ldisc_autoload", 3601 3601 + .data = &tty_ldisc_autoload, 3602 3602 + .maxlen = sizeof(tty_ldisc_autoload), 3603 3603 + .mode = 0644, 3604 3604 + .proc_handler = proc_dointvec, 3605 3605 + .extra1 = SYSCTL_ZERO, 3606 3606 + .extra2 = SYSCTL_ONE, 3607 3607 + }, 3608 3608 + { } 3609 3609 + }; 3610 3610 + 3611 3611 + static struct ctl_table tty_dir_table[] = { 3612 3612 + { 3613 3613 + .procname = "tty", 3614 3614 + .mode = 0555, 3615 3615 + .child = tty_table, 3616 3616 + }, 3617 3617 + { } 3618 3618 + }; 3619 3619 + 3620 3620 + static struct ctl_table tty_root_table[] = { 3621 3621 + { 3622 3622 + .procname = "dev", 3623 3623 + .mode = 0555, 3624 3624 + .child = tty_dir_table, 3625 3625 + }, 3626 3626 + { } 3627 3627 + }; 3628 3628 + 3595 3629 /* 3596 3630 * Ok, now we can initialize the rest of the tty devices and can count 3597 3631 * on memory allocations, interrupts etc.. 3598 3632 */ 3599 3633 int __init tty_init(void) 3600 3634 { 3601 3601 - tty_sysctl_init(); 3635 3635 + register_sysctl_table(tty_root_table); 3602 3636 cdev_init(&tty_cdev, &tty_fops); 3603 3637 if (cdev_add(&tty_cdev, MKDEV(TTYAUX_MAJOR, 0), 1) || 3604 3638 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 0), 1, "/dev/tty") < 0) ··· 3658 3616 #endif 3659 3617 return 0; 3660 3618 } 3661 3661 -

+1 -37

drivers/tty/tty_ldisc.c

reviewed

··· 117 117 raw_spin_unlock_irqrestore(&tty_ldiscs_lock, flags); 118 118 } 119 119 120 120 - static int tty_ldisc_autoload = IS_BUILTIN(CONFIG_LDISC_AUTOLOAD); 120 120 + int tty_ldisc_autoload = IS_BUILTIN(CONFIG_LDISC_AUTOLOAD); 121 121 122 122 /** 123 123 * tty_ldisc_get - take a reference to an ldisc ··· 816 816 if (tty->ldisc) 817 817 tty_ldisc_put(tty->ldisc); 818 818 tty->ldisc = NULL; 819 819 - } 820 820 - 821 821 - static struct ctl_table tty_table[] = { 822 822 - { 823 823 - .procname = "ldisc_autoload", 824 824 - .data = &tty_ldisc_autoload, 825 825 - .maxlen = sizeof(tty_ldisc_autoload), 826 826 - .mode = 0644, 827 827 - .proc_handler = proc_dointvec, 828 828 - .extra1 = SYSCTL_ZERO, 829 829 - .extra2 = SYSCTL_ONE, 830 830 - }, 831 831 - { } 832 832 - }; 833 833 - 834 834 - static struct ctl_table tty_dir_table[] = { 835 835 - { 836 836 - .procname = "tty", 837 837 - .mode = 0555, 838 838 - .child = tty_table, 839 839 - }, 840 840 - { } 841 841 - }; 842 842 - 843 843 - static struct ctl_table tty_root_table[] = { 844 844 - { 845 845 - .procname = "dev", 846 846 - .mode = 0555, 847 847 - .child = tty_dir_table, 848 848 - }, 849 849 - { } 850 850 - }; 851 851 - 852 852 - void tty_sysctl_init(void) 853 853 - { 854 854 - register_sysctl_table(tty_root_table); 855 819 }

+3 -10

include/linux/serdev.h

reviewed

··· 7 7 8 8 #include <linux/types.h> 9 9 #include <linux/device.h> 10 10 + #include <linux/iopoll.h> 10 11 #include <linux/uaccess.h> 11 12 #include <linux/termios.h> 12 13 #include <linux/delay.h> ··· 280 279 281 280 static inline int serdev_device_wait_for_cts(struct serdev_device *serdev, bool state, int timeout_ms) 282 281 { 283 283 - unsigned long timeout; 284 282 bool signal; 285 283 286 286 - timeout = jiffies + msecs_to_jiffies(timeout_ms); 287 287 - while (time_is_after_jiffies(timeout)) { 288 288 - signal = serdev_device_get_cts(serdev); 289 289 - if (signal == state) 290 290 - return 0; 291 291 - usleep_range(1000, 2000); 292 292 - } 293 293 - 294 294 - return -ETIMEDOUT; 284 284 + return readx_poll_timeout(serdev_device_get_cts, serdev, signal, signal == state, 285 285 + 2000, timeout_ms * 1000); 295 286 } 296 287 297 288 static inline int serdev_device_set_rts(struct serdev_device *serdev, bool enable)

+80

include/linux/serial_core.h

reviewed

··· 664 664 665 665 void uart_write_wakeup(struct uart_port *port); 666 666 667 667 + #define __uart_port_tx(uport, ch, tx_ready, put_char, tx_done, for_test, \ 668 668 + for_post) \ 669 669 + ({ \ 670 670 + struct uart_port *__port = (uport); \ 671 671 + struct circ_buf *xmit = &__port->state->xmit; \ 672 672 + unsigned int pending; \ 673 673 + \ 674 674 + for (; (for_test) && (tx_ready); (for_post), __port->icount.tx++) { \ 675 675 + if (__port->x_char) { \ 676 676 + (ch) = __port->x_char; \ 677 677 + (put_char); \ 678 678 + __port->x_char = 0; \ 679 679 + continue; \ 680 680 + } \ 681 681 + \ 682 682 + if (uart_circ_empty(xmit) || uart_tx_stopped(__port)) \ 683 683 + break; \ 684 684 + \ 685 685 + (ch) = xmit->buf[xmit->tail]; \ 686 686 + (put_char); \ 687 687 + xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; \ 688 688 + } \ 689 689 + \ 690 690 + (tx_done); \ 691 691 + \ 692 692 + pending = uart_circ_chars_pending(xmit); \ 693 693 + if (pending < WAKEUP_CHARS) { \ 694 694 + uart_write_wakeup(__port); \ 695 695 + \ 696 696 + if (pending == 0) \ 697 697 + __port->ops->stop_tx(__port); \ 698 698 + } \ 699 699 + \ 700 700 + pending; \ 701 701 + }) 702 702 + 703 703 + /** 704 704 + * uart_port_tx_limited -- transmit helper for uart_port with count limiting 705 705 + * @port: uart port 706 706 + * @ch: variable to store a character to be written to the HW 707 707 + * @count: a limit of characters to send 708 708 + * @tx_ready: can HW accept more data function 709 709 + * @put_char: function to write a character 710 710 + * @tx_done: function to call after the loop is done 711 711 + * 712 712 + * This helper transmits characters from the xmit buffer to the hardware using 713 713 + * @put_char(). It does so until @count characters are sent and while @tx_ready 714 714 + * evaluates to true. 715 715 + * 716 716 + * Returns: the number of characters in the xmit buffer when done. 717 717 + * 718 718 + * The expression in macro parameters shall be designed as follows: 719 719 + * * **tx_ready:** should evaluate to true if the HW can accept more data to 720 720 + * be sent. This parameter can be %true, which means the HW is always ready. 721 721 + * * **put_char:** shall write @ch to the device of @port. 722 722 + * * **tx_done:** when the write loop is done, this can perform arbitrary 723 723 + * action before potential invocation of ops->stop_tx() happens. If the 724 724 + * driver does not need to do anything, use e.g. ({}). 725 725 + * 726 726 + * For all of them, @port->lock is held, interrupts are locally disabled and 727 727 + * the expressions must not sleep. 728 728 + */ 729 729 + #define uart_port_tx_limited(port, ch, count, tx_ready, put_char, tx_done) ({ \ 730 730 + unsigned int __count = (count); \ 731 731 + __uart_port_tx(port, ch, tx_ready, put_char, tx_done, __count, \ 732 732 + __count--); \ 733 733 + }) 734 734 + 735 735 + /** 736 736 + * uart_port_tx -- transmit helper for uart_port 737 737 + * @port: uart port 738 738 + * @ch: variable to store a character to be written to the HW 739 739 + * @tx_ready: can HW accept more data function 740 740 + * @put_char: function to write a character 741 741 + * 742 742 + * See uart_port_tx_limited() for more details. 743 743 + */ 744 744 + #define uart_port_tx(port, ch, tx_ready, put_char) \ 745 745 + __uart_port_tx(port, ch, tx_ready, put_char, ({}), true, ({})) 746 746 + 667 747 /* 668 748 * Baud rate helpers. 669 749 */

+1 -4

include/linux/tty_buffer.h

reviewed

··· 17 17 int commit; 18 18 int lookahead; /* Lazy update on recv, can become less than "read" */ 19 19 int read; 20 20 - int flags; 20 20 + bool flags; 21 21 /* Data points here */ 22 22 unsigned long data[]; 23 23 }; 24 24 - 25 25 - /* Values for .flags field of tty_buffer */ 26 26 - #define TTYB_NORMAL 1 /* buffer has no flags buffer */ 27 24 28 25 static inline unsigned char *char_buf_ptr(struct tty_buffer *b, int ofs) 29 26 {

+2 -2

include/linux/tty_flip.h

reviewed

··· 25 25 struct tty_buffer *tb = port->buf.tail; 26 26 int change; 27 27 28 28 - change = (tb->flags & TTYB_NORMAL) && (flag != TTY_NORMAL); 28 28 + change = !tb->flags && (flag != TTY_NORMAL); 29 29 if (!change && tb->used < tb->size) { 30 30 - if (~tb->flags & TTYB_NORMAL) 30 30 + if (tb->flags) 31 31 *flag_buf_ptr(tb, tb->used) = flag; 32 32 *char_buf_ptr(tb, tb->used++) = ch; 33 33 return 1;

+36 -19

include/uapi/linux/serial.h

reviewed

··· 107 107 int reserved[9]; 108 108 }; 109 109 110 110 - /* 110 110 + /** 111 111 + * struct serial_rs485 - serial interface for controlling RS485 settings. 112 112 + * @flags: RS485 feature flags. 113 113 + * @delay_rts_before_send: Delay before send (milliseconds). 114 114 + * @delay_rts_after_send: Delay after send (milliseconds). 115 115 + * @addr_recv: Receive filter for RS485 addressing mode 116 116 + * (used only when %SER_RS485_ADDR_RECV is set). 117 117 + * @addr_dest: Destination address for RS485 addressing mode 118 118 + * (used only when %SER_RS485_ADDR_DEST is set). 119 119 + * @padding0: Padding (set to zero). 120 120 + * @padding1: Padding (set to zero). 121 121 + * @padding: Deprecated, use @padding0 and @padding1 instead. 122 122 + * Do not use with @addr_recv and @addr_dest (due to 123 123 + * overlap). 124 124 + * 111 125 * Serial interface for controlling RS485 settings on chips with suitable 112 126 * support. Set with TIOCSRS485 and get with TIOCGRS485 if supported by your 113 127 * platform. The set function returns the new state, with any unsupported bits 114 128 * reverted appropriately. 129 129 + * 130 130 + * The flag bits are: 131 131 + * 132 132 + * * %SER_RS485_ENABLED - RS485 enabled. 133 133 + * * %SER_RS485_RTS_ON_SEND - Logical level for RTS pin when sending. 134 134 + * * %SER_RS485_RTS_AFTER_SEND - Logical level for RTS pin after sent. 135 135 + * * %SER_RS485_RX_DURING_TX - Full-duplex RS485 line. 136 136 + * * %SER_RS485_TERMINATE_BUS - Enable bus termination (if supported). 137 137 + * * %SER_RS485_ADDRB - Enable RS485 addressing mode. 138 138 + * * %SER_RS485_ADDR_RECV - Receive address filter (enables @addr_recv). Requires %SER_RS485_ADDRB. 139 139 + * * %SER_RS485_ADDR_DEST - Destination address (enables @addr_dest). Requires %SER_RS485_ADDRB. 115 140 */ 116 116 - 117 141 struct serial_rs485 { 118 118 - __u32 flags; /* RS485 feature flags */ 119 119 - #define SER_RS485_ENABLED (1 << 0) /* If enabled */ 120 120 - #define SER_RS485_RTS_ON_SEND (1 << 1) /* Logical level for 121 121 - RTS pin when 122 122 - sending */ 123 123 - #define SER_RS485_RTS_AFTER_SEND (1 << 2) /* Logical level for 124 124 - RTS pin after sent*/ 142 142 + __u32 flags; 143 143 + #define SER_RS485_ENABLED (1 << 0) 144 144 + #define SER_RS485_RTS_ON_SEND (1 << 1) 145 145 + #define SER_RS485_RTS_AFTER_SEND (1 << 2) 125 146 #define SER_RS485_RX_DURING_TX (1 << 4) 126 126 - #define SER_RS485_TERMINATE_BUS (1 << 5) /* Enable bus 127 127 - termination 128 128 - (if supported) */ 147 147 + #define SER_RS485_TERMINATE_BUS (1 << 5) 148 148 + #define SER_RS485_ADDRB (1 << 6) 149 149 + #define SER_RS485_ADDR_RECV (1 << 7) 150 150 + #define SER_RS485_ADDR_DEST (1 << 8) 129 151 130 130 - /* RS-485 addressing mode */ 131 131 - #define SER_RS485_ADDRB (1 << 6) /* Enable addressing mode */ 132 132 - #define SER_RS485_ADDR_RECV (1 << 7) /* Receive address filter */ 133 133 - #define SER_RS485_ADDR_DEST (1 << 8) /* Destination address */ 134 134 - 135 135 - __u32 delay_rts_before_send; /* Delay before send (milliseconds) */ 136 136 - __u32 delay_rts_after_send; /* Delay after send (milliseconds) */ 152 152 + __u32 delay_rts_before_send; 153 153 + __u32 delay_rts_after_send; 137 154 138 155 /* The fields below are defined by flags */ 139 156 union {