Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-misc-next-2025-08-28' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.18:
UAPI Changes:
atomic:
- Reallow no-op async page flips
Cross-subsystem Changes:
hid:
- i2c-hid: Make elan touch controllers power on after panel is enabled
video:
- Improve pixel-format handling for struct screen_info
Core Changes:
display:
- dp: Fix command length
Driver Changes:
amdxdna:
- Fixes
bridge:
- Add support for Radxa Ra620 plus DT bindings
msm:
- Fix VMA allocation
panel:
- ilitek-ili9881c: Refactor mode setting; Add support for Bestar
BSD1218-A101KL68 LCD plus DT bindings
- lvds: Add support for Ampire AMP19201200B5TZQW-T03 to DT bindings
rockchip:
- dsi2: Add support for RK3576 plus DT bindings
stm:
- Clean up logging
vesadrm:
- Support 8-bit palette mode
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://lore.kernel.org/r/20250828065714.GA11906@linux.fritz.box
+817
-221
+5
-5
Documentation/accel/amdxdna/amdnpu.rst
+5
-5
Documentation/accel/amdxdna/amdnpu.rst
···
223
223
Compiler
224
224
--------
225
225
226
-
Peano is an LLVM based open-source compiler for AMD XDNA Array compute tile
227
-
available at:
226
+
Peano is an LLVM based open-source single core compiler for AMD XDNA Array
227
+
compute tile. Peano is available at:
228
228
https://github.com/Xilinx/llvm-aie
229
229
230
-
The open-source IREE compiler supports graph compilation of ML models for AMD
231
-
NPU and uses Peano underneath. It is available at:
232
-
https://github.com/nod-ai/iree-amd-aie
230
+
IRON is an open-source array compiler for AMD XDNA Array based NPU which uses
231
+
Peano underneath. IRON is available at:
232
+
https://github.com/Xilinx/mlir-aie
233
233
234
234
Usermode Driver (UMD)
235
235
---------------------
+1
Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml
+1
Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml
+1
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
+1
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
+2
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
+2
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
+1
Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
+1
Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
221
221
description: BeagleBoard.org Foundation
222
222
"^belling,.*":
223
223
description: Shanghai Belling Co., Ltd.
224
+
"^bestar,.*":
225
+
description: Shenzhen Bestar Electronic Technology Co., Ltd.
224
226
"^bhf,.*":
225
227
description: Beckhoff Automation GmbH & Co. KG
226
228
"^bigtreetech,.*":
+2
-1
drivers/accel/amdxdna/aie2_pci.c
+2
-1
drivers/accel/amdxdna/aie2_pci.c
···
785
785
786
786
static int aie2_hwctx_status_cb(struct amdxdna_hwctx *hwctx, void *arg)
787
787
{
788
-
struct amdxdna_drm_query_hwctx __user *buf, *tmp __free(kfree) = NULL;
788
+
struct amdxdna_drm_query_hwctx *tmp __free(kfree) = NULL;
789
789
struct amdxdna_drm_get_info *get_info_args = arg;
790
+
struct amdxdna_drm_query_hwctx __user *buf;
790
791
791
792
if (get_info_args->buffer_size < sizeof(*tmp))
792
793
return -EINVAL;
+5
drivers/gpu/drm/bridge/simple-bridge.c
+5
drivers/gpu/drm/bridge/simple-bridge.c
···
262
262
.connector_type = DRM_MODE_CONNECTOR_VGA,
263
263
},
264
264
}, {
265
+
.compatible = "radxa,ra620",
266
+
.data = &(const struct simple_bridge_info) {
267
+
.connector_type = DRM_MODE_CONNECTOR_HDMIA,
268
+
},
269
+
}, {
265
270
.compatible = "ti,opa362",
266
271
.data = &(const struct simple_bridge_info) {
267
272
.connector_type = DRM_MODE_CONNECTOR_Composite,
+3
-1
drivers/gpu/drm/display/drm_dp_helper.c
+3
-1
drivers/gpu/drm/display/drm_dp_helper.c
···
3962
3962
int ret;
3963
3963
unsigned int offset = DP_EDP_BACKLIGHT_BRIGHTNESS_MSB;
3964
3964
u8 buf[3] = { 0 };
3965
+
size_t len = 2;
3965
3966
3966
3967
/* The panel uses the PWM for controlling brightness levels */
3967
3968
if (!(bl->aux_set || bl->luminance_set))
···
3975
3974
buf[1] = (level & 0x00ff00) >> 8;
3976
3975
buf[2] = (level & 0xff0000) >> 16;
3977
3976
offset = DP_EDP_PANEL_TARGET_LUMINANCE_VALUE;
3977
+
len = 3;
3978
3978
} else if (bl->lsb_reg_used) {
3979
3979
buf[0] = (level & 0xff00) >> 8;
3980
3980
buf[1] = (level & 0x00ff);
···
3983
3981
buf[0] = level;
3984
3982
}
3985
3983
3986
-
ret = drm_dp_dpcd_write_data(aux, offset, buf, sizeof(buf));
3984
+
ret = drm_dp_dpcd_write_data(aux, offset, buf, len);
3987
3985
if (ret < 0) {
3988
3986
drm_err(aux->drm_dev,
3989
3987
"%s: Failed to write aux backlight level: %d\n",
+12
-11
drivers/gpu/drm/drm_atomic_uapi.c
+12
-11
drivers/gpu/drm/drm_atomic_uapi.c
···
1078
1078
}
1079
1079
1080
1080
if (async_flip) {
1081
-
/* check if the prop does a nop change */
1082
-
if ((prop != config->prop_fb_id &&
1083
-
prop != config->prop_in_fence_fd &&
1084
-
prop != config->prop_fb_damage_clips)) {
1085
-
ret = drm_atomic_plane_get_property(plane, plane_state,
1086
-
prop, &old_val);
1087
-
ret = drm_atomic_check_prop_changes(ret, old_val, prop_value, prop);
1081
+
/* no-op changes are always allowed */
1082
+
ret = drm_atomic_plane_get_property(plane, plane_state,
1083
+
prop, &old_val);
1084
+
ret = drm_atomic_check_prop_changes(ret, old_val, prop_value, prop);
1085
+
1086
+
/* fail everything that isn't no-op or a pure flip */
1087
+
if (ret && prop != config->prop_fb_id &&
1088
+
prop != config->prop_in_fence_fd &&
1089
+
prop != config->prop_fb_damage_clips) {
1090
+
break;
1088
1091
}
1089
1092
1090
-
/* ask the driver if this non-primary plane is supported */
1091
-
if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
1092
-
ret = -EINVAL;
1093
-
1093
+
if (ret && plane->type != DRM_PLANE_TYPE_PRIMARY) {
1094
+
/* ask the driver if this non-primary plane is supported */
1094
1095
if (plane_funcs && plane_funcs->atomic_async_check)
1095
1096
ret = plane_funcs->atomic_async_check(plane, state, true);
1096
1097
+34
drivers/gpu/drm/drm_color_mgmt.c
+34
drivers/gpu/drm/drm_color_mgmt.c
···
817
817
}
818
818
EXPORT_SYMBOL(drm_crtc_load_palette_8);
819
819
820
+
static void fill_palette_332(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
821
+
drm_crtc_set_lut_func set_palette)
822
+
{
823
+
unsigned int i = (r << 5) | (g << 2) | b; /* 8-bit palette index */
824
+
825
+
/* Expand R (3-bit) G (3-bit) and B (2-bit) values to 16-bit values */
826
+
r = (r << 13) | (r << 10) | (r << 7) | (r << 4) | (r << 1) | (r >> 2);
827
+
g = (g << 13) | (g << 10) | (g << 7) | (g << 4) | (g << 1) | (g >> 2);
828
+
b = (b << 14) | (b << 12) | (b << 10) | (b << 8) | (b << 6) | (b << 4) | (b << 2) | b;
829
+
830
+
set_palette(crtc, i, r, g, b);
831
+
}
832
+
833
+
/**
834
+
* drm_crtc_fill_palette_332 - Programs a default palette for R332-like formats
835
+
* @crtc: The displaying CRTC
836
+
* @set_palette: Callback for programming the hardware gamma LUT
837
+
*
838
+
* Programs an RGB332 palette to hardware.
839
+
*/
840
+
void drm_crtc_fill_palette_332(struct drm_crtc *crtc, drm_crtc_set_lut_func set_palette)
841
+
{
842
+
unsigned int r, g, b;
843
+
844
+
/* Limits of 8-8-4 are the maximum number of values for each channel. */
845
+
for (r = 0; r < 8; ++r) {
846
+
for (g = 0; g < 8; ++g) {
847
+
for (b = 0; b < 4; ++b)
848
+
fill_palette_332(crtc, r, g, b, set_palette);
849
+
}
850
+
}
851
+
}
852
+
EXPORT_SYMBOL(drm_crtc_fill_palette_332);
853
+
820
854
static void fill_palette_8(struct drm_crtc *crtc, unsigned int i,
821
855
drm_crtc_set_lut_func set_palette)
822
856
{
+3
drivers/gpu/drm/drm_format_helper.c
+3
drivers/gpu/drm/drm_format_helper.c
···
1243
1243
} else if (dst_format == DRM_FORMAT_BGRX8888) {
1244
1244
drm_fb_swab(dst, dst_pitch, src, fb, clip, false, state);
1245
1245
return 0;
1246
+
} else if (dst_format == DRM_FORMAT_RGB332) {
1247
+
drm_fb_xrgb8888_to_rgb332(dst, dst_pitch, src, fb, clip, state);
1248
+
return 0;
1246
1249
}
1247
1250
}
1248
1251
+5
-2
drivers/gpu/drm/drm_of.c
+5
-2
drivers/gpu/drm/drm_of.c
···
55
55
* and generate the DRM mask of CRTCs which may be attached to this
56
56
* encoder.
57
57
*
58
-
* See Documentation/devicetree/bindings/graph.txt for the bindings.
58
+
* See https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/graph.yaml
59
+
* for the bindings.
59
60
*/
60
61
uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
61
62
struct device_node *port)
···
107
106
* Parse the platform device OF node and bind all the components associated
108
107
* with the master. Interface ports are added before the encoders in order to
109
108
* satisfy their .bind requirements
110
-
* See Documentation/devicetree/bindings/graph.txt for the bindings.
109
+
*
110
+
* See https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/graph.yaml
111
+
* for the bindings.
111
112
*
112
113
* Returns zero if successful, or one of the standard error codes if it fails.
113
114
*/
+62
-11
drivers/gpu/drm/drm_panel.c
+62
-11
drivers/gpu/drm/drm_panel.c
···
134
134
panel->prepared = true;
135
135
136
136
list_for_each_entry(follower, &panel->followers, list) {
137
+
if (!follower->funcs->panel_prepared)
138
+
continue;
139
+
137
140
ret = follower->funcs->panel_prepared(follower);
138
141
if (ret < 0)
139
142
dev_info(panel->dev, "%ps failed: %d\n",
···
182
179
mutex_lock(&panel->follower_lock);
183
180
184
181
list_for_each_entry(follower, &panel->followers, list) {
182
+
if (!follower->funcs->panel_unpreparing)
183
+
continue;
184
+
185
185
ret = follower->funcs->panel_unpreparing(follower);
186
186
if (ret < 0)
187
187
dev_info(panel->dev, "%ps failed: %d\n",
···
215
209
*/
216
210
void drm_panel_enable(struct drm_panel *panel)
217
211
{
212
+
struct drm_panel_follower *follower;
218
213
int ret;
219
214
220
215
if (!panel)
···
226
219
return;
227
220
}
228
221
222
+
mutex_lock(&panel->follower_lock);
223
+
229
224
if (panel->funcs && panel->funcs->enable) {
230
225
ret = panel->funcs->enable(panel);
231
226
if (ret < 0)
232
-
return;
227
+
goto exit;
233
228
}
234
229
panel->enabled = true;
235
230
···
239
230
if (ret < 0)
240
231
DRM_DEV_INFO(panel->dev, "failed to enable backlight: %d\n",
241
232
ret);
233
+
234
+
list_for_each_entry(follower, &panel->followers, list) {
235
+
if (!follower->funcs->panel_enabled)
236
+
continue;
237
+
238
+
ret = follower->funcs->panel_enabled(follower);
239
+
if (ret < 0)
240
+
dev_info(panel->dev, "%ps failed: %d\n",
241
+
follower->funcs->panel_enabled, ret);
242
+
}
243
+
244
+
exit:
245
+
mutex_unlock(&panel->follower_lock);
242
246
}
243
247
EXPORT_SYMBOL(drm_panel_enable);
244
248
···
265
243
*/
266
244
void drm_panel_disable(struct drm_panel *panel)
267
245
{
246
+
struct drm_panel_follower *follower;
268
247
int ret;
269
248
270
249
if (!panel)
···
285
262
return;
286
263
}
287
264
265
+
mutex_lock(&panel->follower_lock);
266
+
267
+
list_for_each_entry(follower, &panel->followers, list) {
268
+
if (!follower->funcs->panel_disabling)
269
+
continue;
270
+
271
+
ret = follower->funcs->panel_disabling(follower);
272
+
if (ret < 0)
273
+
dev_info(panel->dev, "%ps failed: %d\n",
274
+
follower->funcs->panel_disabling, ret);
275
+
}
276
+
288
277
ret = backlight_disable(panel->backlight);
289
278
if (ret < 0)
290
279
DRM_DEV_INFO(panel->dev, "failed to disable backlight: %d\n",
···
305
270
if (panel->funcs && panel->funcs->disable) {
306
271
ret = panel->funcs->disable(panel);
307
272
if (ret < 0)
308
-
return;
273
+
goto exit;
309
274
}
310
275
panel->enabled = false;
276
+
277
+
exit:
278
+
mutex_unlock(&panel->follower_lock);
311
279
}
312
280
EXPORT_SYMBOL(drm_panel_disable);
313
281
···
577
539
* @follower_dev: The 'struct device' for the follower.
578
540
* @follower: The panel follower descriptor for the follower.
579
541
*
580
-
* A panel follower is called right after preparing the panel and right before
581
-
* unpreparing the panel. It's primary intention is to power on an associated
582
-
* touchscreen, though it could be used for any similar devices. Multiple
583
-
* devices are allowed the follow the same panel.
542
+
* A panel follower is called right after preparing/enabling the panel and right
543
+
* before unpreparing/disabling the panel. It's primary intention is to power on
544
+
* an associated touchscreen, though it could be used for any similar devices.
545
+
* Multiple devices are allowed the follow the same panel.
584
546
*
585
-
* If a follower is added to a panel that's already been turned on, the
586
-
* follower's prepare callback is called right away.
547
+
* If a follower is added to a panel that's already been prepared/enabled, the
548
+
* follower's prepared/enabled callback is called right away.
587
549
*
588
550
* The "panel" property of the follower points to the panel to be followed.
589
551
*
···
607
569
mutex_lock(&panel->follower_lock);
608
570
609
571
list_add_tail(&follower->list, &panel->followers);
610
-
if (panel->prepared) {
572
+
if (panel->prepared && follower->funcs->panel_prepared) {
611
573
ret = follower->funcs->panel_prepared(follower);
612
574
if (ret < 0)
613
575
dev_info(panel->dev, "%ps failed: %d\n",
614
576
follower->funcs->panel_prepared, ret);
577
+
}
578
+
if (panel->enabled && follower->funcs->panel_enabled) {
579
+
ret = follower->funcs->panel_enabled(follower);
580
+
if (ret < 0)
581
+
dev_info(panel->dev, "%ps failed: %d\n",
582
+
follower->funcs->panel_enabled, ret);
615
583
}
616
584
617
585
mutex_unlock(&panel->follower_lock);
···
631
587
* @follower: The panel follower descriptor for the follower.
632
588
*
633
589
* Undo drm_panel_add_follower(). This includes calling the follower's
634
-
* unprepare function if we're removed from a panel that's currently prepared.
590
+
* unpreparing/disabling function if we're removed from a panel that's currently
591
+
* prepared/enabled.
635
592
*
636
593
* Return: 0 or an error code.
637
594
*/
···
643
598
644
599
mutex_lock(&panel->follower_lock);
645
600
646
-
if (panel->prepared) {
601
+
if (panel->enabled && follower->funcs->panel_disabling) {
602
+
ret = follower->funcs->panel_disabling(follower);
603
+
if (ret < 0)
604
+
dev_info(panel->dev, "%ps failed: %d\n",
605
+
follower->funcs->panel_disabling, ret);
606
+
}
607
+
if (panel->prepared && follower->funcs->panel_unpreparing) {
647
608
ret = follower->funcs->panel_unpreparing(follower);
648
609
if (ret < 0)
649
610
dev_info(panel->dev, "%ps failed: %d\n",
+7
-6
drivers/gpu/drm/msm/msm_gem_vma.c
+7
-6
drivers/gpu/drm/msm/msm_gem_vma.c
···
371
371
msm_gem_vma_new(struct drm_gpuvm *gpuvm, struct drm_gem_object *obj,
372
372
u64 offset, u64 range_start, u64 range_end)
373
373
{
374
-
struct drm_gpuva_op_map op_map = {
375
-
.va.addr = range_start,
376
-
.va.range = range_end - range_start,
377
-
.gem.obj = obj,
378
-
.gem.offset = offset,
379
-
};
380
374
struct msm_gem_vm *vm = to_msm_vm(gpuvm);
381
375
struct drm_gpuvm_bo *vm_bo;
382
376
struct msm_gem_vma *vma;
···
398
404
399
405
if (obj)
400
406
GEM_WARN_ON((range_end - range_start) > obj->size);
407
+
408
+
struct drm_gpuva_op_map op_map = {
409
+
.va.addr = range_start,
410
+
.va.range = range_end - range_start,
411
+
.gem.obj = obj,
412
+
.gem.offset = offset,
413
+
};
401
414
402
415
drm_gpuva_init_from_op(&vma->base, &op_map);
403
416
vma->mapped = false;
+245
-57
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
+245
-57
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
···
1417
1417
ILI9881C_COMMAND_INSTR(0xD3, 0x39),
1418
1418
};
1419
1419
1420
+
static const struct ili9881c_instr bsd1218_a101kl68_init[] = {
1421
+
ILI9881C_SWITCH_PAGE_INSTR(3),
1422
+
ILI9881C_COMMAND_INSTR(0x01, 0x00),
1423
+
ILI9881C_COMMAND_INSTR(0x02, 0x00),
1424
+
ILI9881C_COMMAND_INSTR(0x03, 0x55),
1425
+
ILI9881C_COMMAND_INSTR(0x04, 0x55),
1426
+
ILI9881C_COMMAND_INSTR(0x05, 0x03),
1427
+
ILI9881C_COMMAND_INSTR(0x06, 0x06),
1428
+
ILI9881C_COMMAND_INSTR(0x07, 0x00),
1429
+
ILI9881C_COMMAND_INSTR(0x08, 0x07),
1430
+
ILI9881C_COMMAND_INSTR(0x09, 0x00),
1431
+
ILI9881C_COMMAND_INSTR(0x0a, 0x00),
1432
+
ILI9881C_COMMAND_INSTR(0x0b, 0x00),
1433
+
ILI9881C_COMMAND_INSTR(0x0c, 0x00),
1434
+
ILI9881C_COMMAND_INSTR(0x0d, 0x00),
1435
+
ILI9881C_COMMAND_INSTR(0x0e, 0x00),
1436
+
ILI9881C_COMMAND_INSTR(0x0f, 0x00),
1437
+
ILI9881C_COMMAND_INSTR(0x10, 0x00),
1438
+
ILI9881C_COMMAND_INSTR(0x11, 0x00),
1439
+
ILI9881C_COMMAND_INSTR(0x12, 0x00),
1440
+
ILI9881C_COMMAND_INSTR(0x13, 0x00),
1441
+
ILI9881C_COMMAND_INSTR(0x14, 0x00),
1442
+
ILI9881C_COMMAND_INSTR(0x15, 0x00),
1443
+
ILI9881C_COMMAND_INSTR(0x16, 0x00),
1444
+
ILI9881C_COMMAND_INSTR(0x17, 0x00),
1445
+
ILI9881C_COMMAND_INSTR(0x18, 0x00),
1446
+
ILI9881C_COMMAND_INSTR(0x19, 0x00),
1447
+
ILI9881C_COMMAND_INSTR(0x1a, 0x00),
1448
+
ILI9881C_COMMAND_INSTR(0x1b, 0x00),
1449
+
ILI9881C_COMMAND_INSTR(0x1c, 0x00),
1450
+
ILI9881C_COMMAND_INSTR(0x1d, 0x00),
1451
+
ILI9881C_COMMAND_INSTR(0x1e, 0xc0),
1452
+
ILI9881C_COMMAND_INSTR(0x1f, 0x80),
1453
+
ILI9881C_COMMAND_INSTR(0x20, 0x04),
1454
+
ILI9881C_COMMAND_INSTR(0x21, 0x03),
1455
+
ILI9881C_COMMAND_INSTR(0x22, 0x00),
1456
+
ILI9881C_COMMAND_INSTR(0x23, 0x00),
1457
+
ILI9881C_COMMAND_INSTR(0x24, 0x00),
1458
+
ILI9881C_COMMAND_INSTR(0x25, 0x00),
1459
+
ILI9881C_COMMAND_INSTR(0x26, 0x00),
1460
+
ILI9881C_COMMAND_INSTR(0x27, 0x00),
1461
+
ILI9881C_COMMAND_INSTR(0x28, 0x33),
1462
+
ILI9881C_COMMAND_INSTR(0x29, 0x33),
1463
+
ILI9881C_COMMAND_INSTR(0x2a, 0x00),
1464
+
ILI9881C_COMMAND_INSTR(0x2b, 0x00),
1465
+
ILI9881C_COMMAND_INSTR(0x2c, 0x00),
1466
+
ILI9881C_COMMAND_INSTR(0x2d, 0x00),
1467
+
ILI9881C_COMMAND_INSTR(0x2e, 0x00),
1468
+
ILI9881C_COMMAND_INSTR(0x2f, 0x00),
1469
+
ILI9881C_COMMAND_INSTR(0x30, 0x00),
1470
+
ILI9881C_COMMAND_INSTR(0x31, 0x00),
1471
+
ILI9881C_COMMAND_INSTR(0x32, 0x00),
1472
+
ILI9881C_COMMAND_INSTR(0x33, 0x00),
1473
+
ILI9881C_COMMAND_INSTR(0x34, 0x04),
1474
+
ILI9881C_COMMAND_INSTR(0x35, 0x00),
1475
+
ILI9881C_COMMAND_INSTR(0x36, 0x00),
1476
+
ILI9881C_COMMAND_INSTR(0x37, 0x00),
1477
+
ILI9881C_COMMAND_INSTR(0x38, 0x3c),
1478
+
ILI9881C_COMMAND_INSTR(0x39, 0x00),
1479
+
ILI9881C_COMMAND_INSTR(0x3a, 0x00),
1480
+
ILI9881C_COMMAND_INSTR(0x3b, 0x00),
1481
+
ILI9881C_COMMAND_INSTR(0x3c, 0x00),
1482
+
ILI9881C_COMMAND_INSTR(0x3d, 0x00),
1483
+
ILI9881C_COMMAND_INSTR(0x3e, 0x00),
1484
+
ILI9881C_COMMAND_INSTR(0x3f, 0x00),
1485
+
ILI9881C_COMMAND_INSTR(0x40, 0x00),
1486
+
ILI9881C_COMMAND_INSTR(0x41, 0x00),
1487
+
ILI9881C_COMMAND_INSTR(0x42, 0x00),
1488
+
ILI9881C_COMMAND_INSTR(0x43, 0x00),
1489
+
ILI9881C_COMMAND_INSTR(0x44, 0x00),
1490
+
ILI9881C_COMMAND_INSTR(0x50, 0x00),
1491
+
ILI9881C_COMMAND_INSTR(0x51, 0x11),
1492
+
ILI9881C_COMMAND_INSTR(0x52, 0x44),
1493
+
ILI9881C_COMMAND_INSTR(0x53, 0x55),
1494
+
ILI9881C_COMMAND_INSTR(0x54, 0x88),
1495
+
ILI9881C_COMMAND_INSTR(0x55, 0xab),
1496
+
ILI9881C_COMMAND_INSTR(0x56, 0x00),
1497
+
ILI9881C_COMMAND_INSTR(0x57, 0x11),
1498
+
ILI9881C_COMMAND_INSTR(0x58, 0x22),
1499
+
ILI9881C_COMMAND_INSTR(0x59, 0x33),
1500
+
ILI9881C_COMMAND_INSTR(0x5a, 0x44),
1501
+
ILI9881C_COMMAND_INSTR(0x5b, 0x55),
1502
+
ILI9881C_COMMAND_INSTR(0x5c, 0x66),
1503
+
ILI9881C_COMMAND_INSTR(0x5d, 0x77),
1504
+
ILI9881C_COMMAND_INSTR(0x5e, 0x00),
1505
+
ILI9881C_COMMAND_INSTR(0x5f, 0x02),
1506
+
ILI9881C_COMMAND_INSTR(0x60, 0x02),
1507
+
ILI9881C_COMMAND_INSTR(0x61, 0x0a),
1508
+
ILI9881C_COMMAND_INSTR(0x62, 0x09),
1509
+
ILI9881C_COMMAND_INSTR(0x63, 0x08),
1510
+
ILI9881C_COMMAND_INSTR(0x64, 0x13),
1511
+
ILI9881C_COMMAND_INSTR(0x65, 0x12),
1512
+
ILI9881C_COMMAND_INSTR(0x66, 0x11),
1513
+
ILI9881C_COMMAND_INSTR(0x67, 0x10),
1514
+
ILI9881C_COMMAND_INSTR(0x68, 0x0f),
1515
+
ILI9881C_COMMAND_INSTR(0x69, 0x0e),
1516
+
ILI9881C_COMMAND_INSTR(0x6a, 0x0d),
1517
+
ILI9881C_COMMAND_INSTR(0x6b, 0x0c),
1518
+
ILI9881C_COMMAND_INSTR(0x6c, 0x06),
1519
+
ILI9881C_COMMAND_INSTR(0x6d, 0x07),
1520
+
ILI9881C_COMMAND_INSTR(0x6e, 0x02),
1521
+
ILI9881C_COMMAND_INSTR(0x6f, 0x02),
1522
+
ILI9881C_COMMAND_INSTR(0x70, 0x02),
1523
+
ILI9881C_COMMAND_INSTR(0x71, 0x02),
1524
+
ILI9881C_COMMAND_INSTR(0x72, 0x02),
1525
+
ILI9881C_COMMAND_INSTR(0x73, 0x02),
1526
+
ILI9881C_COMMAND_INSTR(0x74, 0x02),
1527
+
ILI9881C_COMMAND_INSTR(0x75, 0x02),
1528
+
ILI9881C_COMMAND_INSTR(0x76, 0x02),
1529
+
ILI9881C_COMMAND_INSTR(0x77, 0x0a),
1530
+
ILI9881C_COMMAND_INSTR(0x78, 0x06),
1531
+
ILI9881C_COMMAND_INSTR(0x79, 0x07),
1532
+
ILI9881C_COMMAND_INSTR(0x7a, 0x10),
1533
+
ILI9881C_COMMAND_INSTR(0x7b, 0x11),
1534
+
ILI9881C_COMMAND_INSTR(0x7c, 0x12),
1535
+
ILI9881C_COMMAND_INSTR(0x7d, 0x13),
1536
+
ILI9881C_COMMAND_INSTR(0x7e, 0x0c),
1537
+
ILI9881C_COMMAND_INSTR(0x7f, 0x0d),
1538
+
ILI9881C_COMMAND_INSTR(0x80, 0x0e),
1539
+
ILI9881C_COMMAND_INSTR(0x81, 0x0f),
1540
+
ILI9881C_COMMAND_INSTR(0x82, 0x09),
1541
+
ILI9881C_COMMAND_INSTR(0x83, 0x08),
1542
+
ILI9881C_COMMAND_INSTR(0x84, 0x02),
1543
+
ILI9881C_COMMAND_INSTR(0x85, 0x02),
1544
+
ILI9881C_COMMAND_INSTR(0x86, 0x02),
1545
+
ILI9881C_COMMAND_INSTR(0x87, 0x02),
1546
+
ILI9881C_COMMAND_INSTR(0x88, 0x02),
1547
+
ILI9881C_COMMAND_INSTR(0x89, 0x02),
1548
+
ILI9881C_COMMAND_INSTR(0x8a, 0x02),
1549
+
1550
+
ILI9881C_SWITCH_PAGE_INSTR(4),
1551
+
ILI9881C_COMMAND_INSTR(0x6e, 0x2a),
1552
+
ILI9881C_COMMAND_INSTR(0x6f, 0x37),
1553
+
ILI9881C_COMMAND_INSTR(0x3a, 0x24),
1554
+
ILI9881C_COMMAND_INSTR(0x8d, 0x19),
1555
+
ILI9881C_COMMAND_INSTR(0x87, 0xba),
1556
+
ILI9881C_COMMAND_INSTR(0xb2, 0xd1),
1557
+
ILI9881C_COMMAND_INSTR(0x88, 0x0b),
1558
+
ILI9881C_COMMAND_INSTR(0x38, 0x01),
1559
+
ILI9881C_COMMAND_INSTR(0x39, 0x00),
1560
+
ILI9881C_COMMAND_INSTR(0xb5, 0x02),
1561
+
ILI9881C_COMMAND_INSTR(0x31, 0x25),
1562
+
ILI9881C_COMMAND_INSTR(0x3b, 0x98),
1563
+
1564
+
ILI9881C_SWITCH_PAGE_INSTR(1),
1565
+
ILI9881C_COMMAND_INSTR(0x22, 0x0a),
1566
+
ILI9881C_COMMAND_INSTR(0x31, 0x0c),
1567
+
ILI9881C_COMMAND_INSTR(0x53, 0x40),
1568
+
ILI9881C_COMMAND_INSTR(0x55, 0x45),
1569
+
ILI9881C_COMMAND_INSTR(0x50, 0xb7),
1570
+
ILI9881C_COMMAND_INSTR(0x51, 0xb2),
1571
+
ILI9881C_COMMAND_INSTR(0x60, 0x07),
1572
+
ILI9881C_COMMAND_INSTR(0xa0, 0x22),
1573
+
ILI9881C_COMMAND_INSTR(0xa1, 0x3f),
1574
+
ILI9881C_COMMAND_INSTR(0xa2, 0x4e),
1575
+
ILI9881C_COMMAND_INSTR(0xa3, 0x17),
1576
+
ILI9881C_COMMAND_INSTR(0xa4, 0x1a),
1577
+
ILI9881C_COMMAND_INSTR(0xa5, 0x2d),
1578
+
ILI9881C_COMMAND_INSTR(0xa6, 0x21),
1579
+
ILI9881C_COMMAND_INSTR(0xa7, 0x22),
1580
+
ILI9881C_COMMAND_INSTR(0xa8, 0xc4),
1581
+
ILI9881C_COMMAND_INSTR(0xa9, 0x1b),
1582
+
ILI9881C_COMMAND_INSTR(0xaa, 0x25),
1583
+
ILI9881C_COMMAND_INSTR(0xab, 0xa7),
1584
+
ILI9881C_COMMAND_INSTR(0xac, 0x1a),
1585
+
ILI9881C_COMMAND_INSTR(0xad, 0x19),
1586
+
ILI9881C_COMMAND_INSTR(0xae, 0x4b),
1587
+
ILI9881C_COMMAND_INSTR(0xaf, 0x1f),
1588
+
ILI9881C_COMMAND_INSTR(0xb0, 0x2a),
1589
+
ILI9881C_COMMAND_INSTR(0xb1, 0x59),
1590
+
ILI9881C_COMMAND_INSTR(0xb2, 0x64),
1591
+
ILI9881C_COMMAND_INSTR(0xb3, 0x3f),
1592
+
ILI9881C_COMMAND_INSTR(0xc0, 0x22),
1593
+
ILI9881C_COMMAND_INSTR(0xc1, 0x48),
1594
+
ILI9881C_COMMAND_INSTR(0xc2, 0x59),
1595
+
ILI9881C_COMMAND_INSTR(0xc3, 0x15),
1596
+
ILI9881C_COMMAND_INSTR(0xc4, 0x15),
1597
+
ILI9881C_COMMAND_INSTR(0xc5, 0x28),
1598
+
ILI9881C_COMMAND_INSTR(0xc6, 0x1c),
1599
+
ILI9881C_COMMAND_INSTR(0xc7, 0x1e),
1600
+
ILI9881C_COMMAND_INSTR(0xc8, 0xc4),
1601
+
ILI9881C_COMMAND_INSTR(0xc9, 0x1c),
1602
+
ILI9881C_COMMAND_INSTR(0xca, 0x2b),
1603
+
ILI9881C_COMMAND_INSTR(0xcb, 0xa3),
1604
+
ILI9881C_COMMAND_INSTR(0xcc, 0x1f),
1605
+
ILI9881C_COMMAND_INSTR(0xcd, 0x1e),
1606
+
ILI9881C_COMMAND_INSTR(0xce, 0x52),
1607
+
ILI9881C_COMMAND_INSTR(0xcf, 0x24),
1608
+
ILI9881C_COMMAND_INSTR(0xd0, 0x2a),
1609
+
ILI9881C_COMMAND_INSTR(0xd1, 0x58),
1610
+
ILI9881C_COMMAND_INSTR(0xd2, 0x68),
1611
+
ILI9881C_COMMAND_INSTR(0xd3, 0x3f),
1612
+
};
1613
+
1420
1614
static inline struct ili9881c *panel_to_ili9881c(struct drm_panel *panel)
1421
1615
{
1422
1616
return container_of(panel, struct ili9881c, panel);
···
1627
1433
* So before any attempt at sending a command or data, we have to be
1628
1434
* sure if we're in the right page or not.
1629
1435
*/
1630
-
static int ili9881c_switch_page(struct ili9881c *ctx, u8 page)
1436
+
static void ili9881c_switch_page(struct mipi_dsi_multi_context *mctx, u8 page)
1631
1437
{
1632
1438
u8 buf[4] = { 0xff, 0x98, 0x81, page };
1633
-
int ret;
1634
1439
1635
-
ret = mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
1636
-
if (ret < 0)
1637
-
return ret;
1638
-
1639
-
return 0;
1440
+
mipi_dsi_dcs_write_buffer_multi(mctx, buf, sizeof(buf));
1640
1441
}
1641
1442
1642
-
static int ili9881c_send_cmd_data(struct ili9881c *ctx, u8 cmd, u8 data)
1443
+
static void ili9881c_send_cmd_data(struct mipi_dsi_multi_context *mctx, u8 cmd, u8 data)
1643
1444
{
1644
1445
u8 buf[2] = { cmd, data };
1645
-
int ret;
1646
1446
1647
-
ret = mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
1648
-
if (ret < 0)
1649
-
return ret;
1650
-
1651
-
return 0;
1447
+
mipi_dsi_dcs_write_buffer_multi(mctx, buf, sizeof(buf));
1652
1448
}
1653
1449
1654
1450
static int ili9881c_prepare(struct drm_panel *panel)
1655
1451
{
1656
1452
struct ili9881c *ctx = panel_to_ili9881c(panel);
1453
+
struct mipi_dsi_multi_context mctx = { .dsi = ctx->dsi };
1657
1454
unsigned int i;
1658
1455
int ret;
1659
1456
···
1665
1480
const struct ili9881c_instr *instr = &ctx->desc->init[i];
1666
1481
1667
1482
if (instr->op == ILI9881C_SWITCH_PAGE)
1668
-
ret = ili9881c_switch_page(ctx, instr->arg.page);
1483
+
ili9881c_switch_page(&mctx, instr->arg.page);
1669
1484
else if (instr->op == ILI9881C_COMMAND)
1670
-
ret = ili9881c_send_cmd_data(ctx, instr->arg.cmd.cmd,
1671
-
instr->arg.cmd.data);
1672
-
1673
-
if (ret)
1674
-
return ret;
1485
+
ili9881c_send_cmd_data(&mctx, instr->arg.cmd.cmd,
1486
+
instr->arg.cmd.data);
1675
1487
}
1676
1488
1677
-
ret = ili9881c_switch_page(ctx, 0);
1678
-
if (ret)
1679
-
return ret;
1489
+
ili9881c_switch_page(&mctx, 0);
1680
1490
1681
-
if (ctx->address_mode) {
1682
-
ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_ADDRESS_MODE,
1683
-
&ctx->address_mode,
1684
-
sizeof(ctx->address_mode));
1685
-
if (ret < 0)
1686
-
return ret;
1687
-
}
1491
+
if (ctx->address_mode)
1492
+
ili9881c_send_cmd_data(&mctx, MIPI_DCS_SET_ADDRESS_MODE,
1493
+
ctx->address_mode);
1688
1494
1689
-
ret = mipi_dsi_dcs_set_tear_on(ctx->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
1690
-
if (ret)
1691
-
return ret;
1692
-
1693
-
ret = mipi_dsi_dcs_exit_sleep_mode(ctx->dsi);
1694
-
if (ret)
1695
-
return ret;
1495
+
mipi_dsi_dcs_set_tear_on_multi(&mctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
1496
+
mipi_dsi_dcs_exit_sleep_mode_multi(&mctx);
1497
+
mipi_dsi_msleep(&mctx, 120);
1498
+
mipi_dsi_dcs_set_display_on_multi(&mctx);
1499
+
if (mctx.accum_err)
1500
+
goto disable_power;
1696
1501
1697
1502
return 0;
1698
-
}
1699
1503
1700
-
static int ili9881c_enable(struct drm_panel *panel)
1701
-
{
1702
-
struct ili9881c *ctx = panel_to_ili9881c(panel);
1703
-
1704
-
msleep(120);
1705
-
1706
-
mipi_dsi_dcs_set_display_on(ctx->dsi);
1707
-
1708
-
return 0;
1709
-
}
1710
-
1711
-
static int ili9881c_disable(struct drm_panel *panel)
1712
-
{
1713
-
struct ili9881c *ctx = panel_to_ili9881c(panel);
1714
-
1715
-
return mipi_dsi_dcs_set_display_off(ctx->dsi);
1504
+
disable_power:
1505
+
regulator_disable(ctx->power);
1506
+
return mctx.accum_err;
1716
1507
}
1717
1508
1718
1509
static int ili9881c_unprepare(struct drm_panel *panel)
1719
1510
{
1720
1511
struct ili9881c *ctx = panel_to_ili9881c(panel);
1512
+
struct mipi_dsi_multi_context mctx = { .dsi = ctx->dsi };
1721
1513
1722
-
mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
1514
+
mipi_dsi_dcs_set_display_off_multi(&mctx);
1515
+
mipi_dsi_dcs_enter_sleep_mode_multi(&mctx);
1723
1516
regulator_disable(ctx->power);
1724
1517
gpiod_set_value_cansleep(ctx->reset, 1);
1725
1518
···
1823
1660
.height_mm = 151,
1824
1661
};
1825
1662
1663
+
static const struct drm_display_mode bsd1218_a101kl68_default_mode = {
1664
+
.clock = 70000,
1665
+
1666
+
.hdisplay = 800,
1667
+
.hsync_start = 800 + 40,
1668
+
.hsync_end = 800 + 40 + 20,
1669
+
.htotal = 800 + 40 + 20 + 20,
1670
+
1671
+
.vdisplay = 1280,
1672
+
.vsync_start = 1280 + 20,
1673
+
.vsync_end = 1280 + 20 + 4,
1674
+
.vtotal = 1280 + 20 + 4 + 20,
1675
+
1676
+
.width_mm = 120,
1677
+
.height_mm = 170,
1678
+
};
1679
+
1826
1680
static int ili9881c_get_modes(struct drm_panel *panel,
1827
1681
struct drm_connector *connector)
1828
1682
{
···
1886
1706
static const struct drm_panel_funcs ili9881c_funcs = {
1887
1707
.prepare = ili9881c_prepare,
1888
1708
.unprepare = ili9881c_unprepare,
1889
-
.enable = ili9881c_enable,
1890
-
.disable = ili9881c_disable,
1891
1709
.get_modes = ili9881c_get_modes,
1892
1710
.get_orientation = ili9881c_get_orientation,
1893
1711
};
···
2008
1830
.lanes = 2,
2009
1831
};
2010
1832
1833
+
static const struct ili9881c_desc bsd1218_a101kl68_desc = {
1834
+
.init = bsd1218_a101kl68_init,
1835
+
.init_length = ARRAY_SIZE(bsd1218_a101kl68_init),
1836
+
.mode = &bsd1218_a101kl68_default_mode,
1837
+
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1838
+
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
1839
+
.lanes = 4,
1840
+
};
1841
+
2011
1842
static const struct of_device_id ili9881c_of_match[] = {
2012
1843
{ .compatible = "bananapi,lhr050h41", .data = &lhr050h41_desc },
1844
+
{ .compatible = "bestar,bsd1218-a101kl68", .data = &bsd1218_a101kl68_desc },
2013
1845
{ .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc },
2014
1846
{ .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc },
2015
1847
{ .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc },
+3
-1
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
+3
-1
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
···
233
233
mipi_dsi_dual(mipi_dsi_dcs_set_display_on_multi,
234
234
&dsi_ctx, jdi->link1, jdi->link2);
235
235
236
-
if (dsi_ctx.accum_err < 0)
236
+
if (dsi_ctx.accum_err < 0) {
237
+
err = dsi_ctx.accum_err;
237
238
goto poweroff;
239
+
}
238
240
239
241
jdi->link1->mode_flags &= ~MIPI_DSI_MODE_LPM;
240
242
jdi->link2->mode_flags &= ~MIPI_DSI_MODE_LPM;
+21
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
+21
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
···
437
437
dw_mipi_dsi2_remove(dsi2->dmd);
438
438
}
439
439
440
+
static const struct dsigrf_reg rk3576_dsi_grf_reg_fields[MAX_FIELDS] = {
441
+
[TXREQCLKHS_EN] = { 0x0028, 1, 1 },
442
+
[GATING_EN] = { 0x0028, 0, 0 },
443
+
[IPI_SHUTDN] = { 0x0028, 3, 3 },
444
+
[IPI_COLORM] = { 0x0028, 2, 2 },
445
+
[IPI_COLOR_DEPTH] = { 0x0028, 8, 11 },
446
+
[IPI_FORMAT] = { 0x0028, 4, 7 },
447
+
};
448
+
440
449
static const struct dsigrf_reg rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = {
441
450
[TXREQCLKHS_EN] = { 0x0000, 11, 11 },
442
451
[GATING_EN] = { 0x0000, 10, 10 },
···
464
455
[IPI_FORMAT] = { 0x0004, 0, 3 },
465
456
};
466
457
458
+
static const struct rockchip_dw_dsi2_chip_data rk3576_chip_data[] = {
459
+
{
460
+
.reg = 0x27d80000,
461
+
.grf_regs = rk3576_dsi_grf_reg_fields,
462
+
.max_bit_rate_per_lane = 2500000ULL,
463
+
},
464
+
{ /* sentinel */ }
465
+
};
466
+
467
467
static const struct rockchip_dw_dsi2_chip_data rk3588_chip_data[] = {
468
468
{
469
469
.reg = 0xfde20000,
···
488
470
489
471
static const struct of_device_id dw_mipi_dsi2_rockchip_dt_ids[] = {
490
472
{
473
+
.compatible = "rockchip,rk3576-mipi-dsi2",
474
+
.data = &rk3576_chip_data,
475
+
}, {
491
476
.compatible = "rockchip,rk3588-mipi-dsi2",
492
477
.data = &rk3588_chip_data,
493
478
},
+70
-69
drivers/gpu/drm/stm/ltdc.c
+70
-69
drivers/gpu/drm/stm/ltdc.c
···
641
641
break;
642
642
default:
643
643
/* RGB or not a YCbCr supported format */
644
-
DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
644
+
drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt);
645
645
return;
646
646
}
647
647
···
664
664
u32 lofs = plane->index * LAY_OFS;
665
665
666
666
if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
667
-
DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
667
+
drm_err(plane->dev, "color encoding %d not supported, use bt601 by default\n", enc);
668
668
/* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
669
669
enc = DRM_COLOR_YCBCR_BT601;
670
670
}
671
671
672
672
if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
673
-
DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
673
+
drm_err(plane->dev,
674
+
"color range %d not supported, use limited range by default\n", ran);
674
675
/* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
675
676
ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
676
677
}
677
678
678
-
DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
679
+
drm_err(plane->dev, "Color encoding=%d, range=%d\n", enc, ran);
679
680
regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
680
681
ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
681
682
regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
···
775
774
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
776
775
struct drm_device *ddev = crtc->dev;
777
776
778
-
DRM_DEBUG_DRIVER("\n");
777
+
drm_dbg_driver(crtc->dev, "\n");
779
778
780
779
pm_runtime_get_sync(ddev->dev);
781
780
···
799
798
struct drm_device *ddev = crtc->dev;
800
799
int layer_index = 0;
801
800
802
-
DRM_DEBUG_DRIVER("\n");
801
+
drm_dbg_driver(crtc->dev, "\n");
803
802
804
803
drm_crtc_vblank_off(crtc);
805
804
···
838
837
839
838
result = clk_round_rate(ldev->pixel_clk, target);
840
839
841
-
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
840
+
drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, result);
842
841
843
842
/* Filter modes according to the max frequency supported by the pads */
844
843
if (result > ldev->caps.pad_max_freq_hz)
···
873
872
int rate = mode->clock * 1000;
874
873
875
874
if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
876
-
DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
875
+
drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate);
877
876
return false;
878
877
}
879
878
880
879
adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
881
880
882
-
DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
883
-
mode->clock, adjusted_mode->clock);
881
+
drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n",
882
+
mode->clock, adjusted_mode->clock);
884
883
885
884
return true;
886
885
}
···
935
934
if (!pm_runtime_active(ddev->dev)) {
936
935
ret = pm_runtime_get_sync(ddev->dev);
937
936
if (ret) {
938
-
DRM_ERROR("Failed to set mode, cannot get sync\n");
937
+
drm_err(crtc->dev, "Failed to set mode, cannot get sync\n");
939
938
return;
940
939
}
941
940
}
942
941
943
-
DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
944
-
DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
945
-
DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
946
-
mode->hsync_start - mode->hdisplay,
947
-
mode->htotal - mode->hsync_end,
948
-
mode->hsync_end - mode->hsync_start,
949
-
mode->vsync_start - mode->vdisplay,
950
-
mode->vtotal - mode->vsync_end,
951
-
mode->vsync_end - mode->vsync_start);
942
+
drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name);
943
+
drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
944
+
drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
945
+
mode->hsync_start - mode->hdisplay,
946
+
mode->htotal - mode->hsync_end,
947
+
mode->hsync_end - mode->hsync_start,
948
+
mode->vsync_start - mode->vdisplay,
949
+
mode->vtotal - mode->vsync_end,
950
+
mode->vsync_end - mode->vsync_start);
952
951
953
952
/* Convert video timings to ltdc timings */
954
953
hsync = mode->hsync_end - mode->hsync_start - 1;
···
1034
1033
struct drm_device *ddev = crtc->dev;
1035
1034
struct drm_pending_vblank_event *event = crtc->state->event;
1036
1035
1037
-
DRM_DEBUG_ATOMIC("\n");
1036
+
drm_dbg_atomic(crtc->dev, "\n");
1038
1037
1039
1038
ltdc_crtc_update_clut(crtc);
1040
1039
···
1122
1121
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1123
1122
struct drm_crtc_state *state = crtc->state;
1124
1123
1125
-
DRM_DEBUG_DRIVER("\n");
1124
+
drm_dbg_driver(crtc->dev, "\n");
1126
1125
1127
1126
if (state->enable)
1128
1127
regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
···
1136
1135
{
1137
1136
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1138
1137
1139
-
DRM_DEBUG_DRIVER("\n");
1138
+
drm_dbg_driver(crtc->dev, "\n");
1140
1139
regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1141
1140
}
1142
1141
···
1145
1144
struct ltdc_device *ldev;
1146
1145
int ret;
1147
1146
1148
-
DRM_DEBUG_DRIVER("\n");
1149
-
1150
1147
if (!crtc)
1151
1148
return -ENODEV;
1149
+
1150
+
drm_dbg_driver(crtc->dev, "\n");
1152
1151
1153
1152
ldev = crtc_to_ltdc(crtc);
1154
1153
···
1169
1168
static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
1170
1169
const char *source, size_t *values_cnt)
1171
1170
{
1172
-
DRM_DEBUG_DRIVER("\n");
1173
-
1174
1171
if (!crtc)
1175
1172
return -ENODEV;
1176
1173
1174
+
drm_dbg_driver(crtc->dev, "\n");
1175
+
1177
1176
if (source && strcmp(source, "auto") != 0) {
1178
-
DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
1179
-
source, crtc->name);
1177
+
drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n",
1178
+
source, crtc->name);
1180
1179
return -EINVAL;
1181
1180
}
1182
1181
···
1234
1233
struct drm_framebuffer *fb = new_plane_state->fb;
1235
1234
u32 src_w, src_h;
1236
1235
1237
-
DRM_DEBUG_DRIVER("\n");
1236
+
drm_dbg_driver(plane->dev, "\n");
1238
1237
1239
1238
if (!fb)
1240
1239
return 0;
···
1245
1244
1246
1245
/* Reject scaling */
1247
1246
if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
1248
-
DRM_DEBUG_DRIVER("Scaling is not supported");
1247
+
drm_dbg_driver(plane->dev, "Scaling is not supported");
1249
1248
1250
1249
return -EINVAL;
1251
1250
}
···
1271
1270
enum ltdc_pix_fmt pf;
1272
1271
1273
1272
if (!newstate->crtc || !fb) {
1274
-
DRM_DEBUG_DRIVER("fb or crtc NULL");
1273
+
drm_dbg_driver(plane->dev, "fb or crtc NULL");
1275
1274
return;
1276
1275
}
1277
1276
···
1281
1280
src_w = newstate->src_w >> 16;
1282
1281
src_h = newstate->src_h >> 16;
1283
1282
1284
-
DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1285
-
plane->base.id, fb->base.id,
1286
-
src_w, src_h, src_x, src_y,
1287
-
newstate->crtc_w, newstate->crtc_h,
1288
-
newstate->crtc_x, newstate->crtc_y);
1283
+
drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1284
+
plane->base.id, fb->base.id,
1285
+
src_w, src_h, src_x, src_y,
1286
+
newstate->crtc_w, newstate->crtc_h,
1287
+
newstate->crtc_x, newstate->crtc_y);
1289
1288
1290
1289
regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1291
1290
···
1313
1312
val = ltdc_set_flexible_pixel_format(plane, pf);
1314
1313
1315
1314
if (val == NB_PF) {
1316
-
DRM_ERROR("Pixel format %.4s not supported\n",
1317
-
(char *)&fb->format->format);
1315
+
drm_err(fb->dev, "Pixel format %.4s not supported\n",
1316
+
(char *)&fb->format->format);
1318
1317
val = 0; /* set by default ARGB 32 bits */
1319
1318
}
1320
1319
regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
···
1351
1350
if (newstate->rotation & DRM_MODE_REFLECT_Y)
1352
1351
paddr += (fb->pitches[0] * (y1 - y0));
1353
1352
1354
-
DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
1353
+
drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr);
1355
1354
regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1356
1355
1357
1356
/* Configures the color frame buffer pitch in bytes & line length */
···
1518
1517
regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1519
1518
LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1520
1519
1521
-
DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
1522
-
oldstate->crtc->base.id, plane->base.id);
1520
+
drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n",
1521
+
oldstate->crtc->base.id, plane->base.id);
1523
1522
}
1524
1523
1525
1524
static void ltdc_plane_atomic_print_state(struct drm_printer *p,
···
1633
1632
1634
1633
drm_plane_create_alpha_property(plane);
1635
1634
1636
-
DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1635
+
drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id);
1637
1636
1638
1637
return plane;
1639
1638
}
···
1648
1647
1649
1648
primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
1650
1649
if (!primary) {
1651
-
DRM_ERROR("Can not create primary plane\n");
1650
+
drm_err(ddev, "Can not create primary plane\n");
1652
1651
return -EINVAL;
1653
1652
}
1654
1653
···
1669
1668
ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1670
1669
<dc_crtc_funcs, NULL);
1671
1670
if (ret) {
1672
-
DRM_ERROR("Can not initialize CRTC\n");
1671
+
drm_err(ddev, "Can not initialize CRTC\n");
1673
1672
return ret;
1674
1673
}
1675
1674
···
1678
1677
drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1679
1678
drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1680
1679
1681
-
DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1680
+
drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id);
1682
1681
1683
1682
/* Add planes. Note : the first layer is used by primary plane */
1684
1683
for (i = 1; i < ldev->caps.nb_layers; i++) {
1685
1684
overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
1686
1685
if (!overlay) {
1687
-
DRM_ERROR("Can not create overlay plane %d\n", i);
1686
+
drm_err(ddev, "Can not create overlay plane %d\n", i);
1688
1687
return -ENOMEM;
1689
1688
}
1690
1689
if (ldev->caps.dynamic_zorder)
···
1705
1704
struct drm_device *ddev = encoder->dev;
1706
1705
struct ltdc_device *ldev = ddev->dev_private;
1707
1706
1708
-
DRM_DEBUG_DRIVER("\n");
1707
+
drm_dbg_driver(encoder->dev, "\n");
1709
1708
1710
1709
/* Disable LTDC */
1711
1710
regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
···
1719
1718
struct drm_device *ddev = encoder->dev;
1720
1719
struct ltdc_device *ldev = ddev->dev_private;
1721
1720
1722
-
DRM_DEBUG_DRIVER("\n");
1721
+
drm_dbg_driver(encoder->dev, "\n");
1723
1722
1724
1723
/* set fifo underrun threshold register */
1725
1724
if (ldev->caps.fifo_threshold)
···
1735
1734
{
1736
1735
struct drm_device *ddev = encoder->dev;
1737
1736
1738
-
DRM_DEBUG_DRIVER("\n");
1737
+
drm_dbg_driver(encoder->dev, "\n");
1739
1738
1740
1739
/*
1741
1740
* Set to default state the pinctrl only with DPI type.
···
1771
1770
if (ret)
1772
1771
return ret;
1773
1772
1774
-
DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1773
+
drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base.id);
1775
1774
1776
1775
return 0;
1777
1776
}
···
1871
1870
{
1872
1871
struct ltdc_device *ldev = ddev->dev_private;
1873
1872
1874
-
DRM_DEBUG_DRIVER("\n");
1873
+
drm_dbg_driver(ddev, "\n");
1875
1874
clk_disable_unprepare(ldev->pixel_clk);
1876
1875
}
1877
1876
···
1880
1879
struct ltdc_device *ldev = ddev->dev_private;
1881
1880
int ret;
1882
1881
1883
-
DRM_DEBUG_DRIVER("\n");
1882
+
drm_dbg_driver(ddev, "\n");
1884
1883
1885
1884
ret = clk_prepare_enable(ldev->pixel_clk);
1886
1885
if (ret) {
1887
-
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1886
+
drm_err(ddev, "failed to enable pixel clock (%d)\n", ret);
1888
1887
return ret;
1889
1888
}
1890
1889
···
1904
1903
int irq, i, nb_endpoints;
1905
1904
int ret = -ENODEV;
1906
1905
1907
-
DRM_DEBUG_DRIVER("\n");
1906
+
drm_dbg_driver(ddev, "\n");
1908
1907
1909
1908
/* Get number of endpoints */
1910
1909
nb_endpoints = of_graph_get_endpoint_count(np);
···
1914
1913
ldev->pixel_clk = devm_clk_get(dev, "lcd");
1915
1914
if (IS_ERR(ldev->pixel_clk)) {
1916
1915
if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1917
-
DRM_ERROR("Unable to get lcd clock\n");
1916
+
drm_err(ddev, "Unable to get lcd clock\n");
1918
1917
return PTR_ERR(ldev->pixel_clk);
1919
1918
}
1920
1919
1921
1920
if (clk_prepare_enable(ldev->pixel_clk)) {
1922
-
DRM_ERROR("Unable to prepare pixel clock\n");
1921
+
drm_err(ddev, "Unable to prepare pixel clock\n");
1923
1922
return -ENODEV;
1924
1923
}
1925
1924
···
1940
1939
if (panel) {
1941
1940
bridge = drmm_panel_bridge_add(ddev, panel);
1942
1941
if (IS_ERR(bridge)) {
1943
-
DRM_ERROR("panel-bridge endpoint %d\n", i);
1942
+
drm_err(ddev, "panel-bridge endpoint %d\n", i);
1944
1943
ret = PTR_ERR(bridge);
1945
1944
goto err;
1946
1945
}
···
1950
1949
ret = ltdc_encoder_init(ddev, bridge);
1951
1950
if (ret) {
1952
1951
if (ret != -EPROBE_DEFER)
1953
-
DRM_ERROR("init encoder endpoint %d\n", i);
1952
+
drm_err(ddev, "init encoder endpoint %d\n", i);
1954
1953
goto err;
1955
1954
}
1956
1955
}
···
1968
1967
1969
1968
ldev->regs = devm_platform_ioremap_resource(pdev, 0);
1970
1969
if (IS_ERR(ldev->regs)) {
1971
-
DRM_ERROR("Unable to get ltdc registers\n");
1970
+
drm_err(ddev, "Unable to get ltdc registers\n");
1972
1971
ret = PTR_ERR(ldev->regs);
1973
1972
goto err;
1974
1973
}
1975
1974
1976
1975
ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
1977
1976
if (IS_ERR(ldev->regmap)) {
1978
-
DRM_ERROR("Unable to regmap ltdc registers\n");
1977
+
drm_err(ddev, "Unable to regmap ltdc registers\n");
1979
1978
ret = PTR_ERR(ldev->regmap);
1980
1979
goto err;
1981
1980
}
1982
1981
1983
1982
ret = ltdc_get_caps(ddev);
1984
1983
if (ret) {
1985
-
DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1986
-
ldev->caps.hw_version);
1984
+
drm_err(ddev, "hardware identifier (0x%08x) not supported!\n",
1985
+
ldev->caps.hw_version);
1987
1986
goto err;
1988
1987
}
1989
1988
1990
1989
/* Disable all interrupts */
1991
1990
regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK);
1992
1991
1993
-
DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1992
+
drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1994
1993
1995
1994
/* initialize default value for fifo underrun threshold & clear interrupt error counters */
1996
1995
ldev->transfer_err = 0;
···
2009
2008
ltdc_irq_thread, IRQF_ONESHOT,
2010
2009
dev_name(dev), ddev);
2011
2010
if (ret) {
2012
-
DRM_ERROR("Failed to register LTDC interrupt\n");
2011
+
drm_err(ddev, "Failed to register LTDC interrupt\n");
2013
2012
goto err;
2014
2013
}
2015
2014
}
2016
2015
2017
2016
crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL);
2018
2017
if (!crtc) {
2019
-
DRM_ERROR("Failed to allocate crtc\n");
2018
+
drm_err(ddev, "Failed to allocate crtc\n");
2020
2019
ret = -ENOMEM;
2021
2020
goto err;
2022
2021
}
2023
2022
2024
2023
ret = ltdc_crtc_init(ddev, crtc);
2025
2024
if (ret) {
2026
-
DRM_ERROR("Failed to init crtc\n");
2025
+
drm_err(ddev, "Failed to init crtc\n");
2027
2026
goto err;
2028
2027
}
2029
2028
2030
2029
ret = drm_vblank_init(ddev, NB_CRTC);
2031
2030
if (ret) {
2032
-
DRM_ERROR("Failed calling drm_vblank_init()\n");
2031
+
drm_err(ddev, "Failed calling drm_vblank_init()\n");
2033
2032
goto err;
2034
2033
}
2035
2034
···
2048
2047
2049
2048
void ltdc_unload(struct drm_device *ddev)
2050
2049
{
2051
-
DRM_DEBUG_DRIVER("\n");
2050
+
drm_dbg_driver(ddev, "\n");
2052
2051
2053
2052
pm_runtime_disable(ddev->dev);
2054
2053
}
+1
-1
drivers/gpu/drm/sysfb/drm_sysfb_helper.h
+1
-1
drivers/gpu/drm/sysfb/drm_sysfb_helper.h
+15
-9
drivers/gpu/drm/sysfb/drm_sysfb_modeset.c
+15
-9
drivers/gpu/drm/sysfb/drm_sysfb_modeset.c
···
210
210
else if (!new_plane_state->visible)
211
211
return 0;
212
212
213
-
if (new_fb->format != sysfb->fb_format) {
213
+
new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc);
214
+
215
+
new_sysfb_crtc_state = to_drm_sysfb_crtc_state(new_crtc_state);
216
+
new_sysfb_crtc_state->format = sysfb->fb_format;
217
+
218
+
if (new_fb->format != new_sysfb_crtc_state->format) {
214
219
void *buf;
215
220
216
221
/* format conversion necessary; reserve buffer */
···
224
219
if (!buf)
225
220
return -ENOMEM;
226
221
}
227
-
228
-
new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc);
229
-
230
-
new_sysfb_crtc_state = to_drm_sysfb_crtc_state(new_crtc_state);
231
-
new_sysfb_crtc_state->format = new_fb->format;
232
222
233
223
return 0;
234
224
}
···
238
238
struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
239
239
struct drm_framebuffer *fb = plane_state->fb;
240
240
unsigned int dst_pitch = sysfb->fb_pitch;
241
-
const struct drm_format_info *dst_format = sysfb->fb_format;
241
+
struct drm_crtc_state *crtc_state = crtc_state =
242
+
drm_atomic_get_new_crtc_state(state, plane_state->crtc);
243
+
struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);
244
+
const struct drm_format_info *dst_format = sysfb_crtc_state->format;
242
245
struct drm_atomic_helper_damage_iter iter;
243
246
struct drm_rect damage;
244
247
int ret, idx;
···
373
370
374
371
void drm_sysfb_crtc_reset(struct drm_crtc *crtc)
375
372
{
373
+
struct drm_sysfb_device *sysfb = to_drm_sysfb_device(crtc->dev);
376
374
struct drm_sysfb_crtc_state *sysfb_crtc_state;
377
375
378
376
if (crtc->state)
379
377
drm_sysfb_crtc_state_destroy(to_drm_sysfb_crtc_state(crtc->state));
380
378
381
379
sysfb_crtc_state = kzalloc(sizeof(*sysfb_crtc_state), GFP_KERNEL);
382
-
if (sysfb_crtc_state)
380
+
if (sysfb_crtc_state) {
381
+
sysfb_crtc_state->format = sysfb->fb_format;
383
382
__drm_atomic_helper_crtc_reset(crtc, &sysfb_crtc_state->base);
384
-
else
383
+
} else {
385
384
__drm_atomic_helper_crtc_reset(crtc, NULL);
385
+
}
386
386
}
387
387
EXPORT_SYMBOL(drm_sysfb_crtc_reset);
388
388
+8
-11
drivers/gpu/drm/sysfb/drm_sysfb_screen_info.c
+8
-11
drivers/gpu/drm/sysfb/drm_sysfb_screen_info.c
···
79
79
const struct screen_info *si)
80
80
{
81
81
const struct drm_format_info *format = NULL;
82
-
u32 bits_per_pixel;
82
+
struct pixel_format pixel;
83
83
size_t i;
84
+
int ret;
84
85
85
-
bits_per_pixel = __screen_info_lfb_bits_per_pixel(si);
86
+
ret = screen_info_pixel_format(si, &pixel);
87
+
if (ret)
88
+
return NULL;
86
89
87
90
for (i = 0; i < nformats; ++i) {
88
-
const struct pixel_format *f = &formats[i].pixel;
91
+
const struct drm_sysfb_format *f = &formats[i];
89
92
90
-
if (bits_per_pixel == f->bits_per_pixel &&
91
-
si->red_size == f->red.length &&
92
-
si->red_pos == f->red.offset &&
93
-
si->green_size == f->green.length &&
94
-
si->green_pos == f->green.offset &&
95
-
si->blue_size == f->blue.length &&
96
-
si->blue_pos == f->blue.offset) {
97
-
format = drm_format_info(formats[i].fourcc);
93
+
if (pixel_format_equal(&pixel, &f->pixel)) {
94
+
format = drm_format_info(f->fourcc);
98
95
break;
99
96
}
100
97
}
+136
-17
drivers/gpu/drm/sysfb/vesadrm.c
+136
-17
drivers/gpu/drm/sysfb/vesadrm.c
···
46
46
{ PIXEL_FORMAT_RGB888, DRM_FORMAT_RGB888, },
47
47
{ PIXEL_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888, },
48
48
{ PIXEL_FORMAT_XBGR8888, DRM_FORMAT_XBGR8888, },
49
+
{ PIXEL_FORMAT_C8, DRM_FORMAT_C8, },
49
50
};
50
51
51
52
return drm_sysfb_get_format_si(dev, formats, ARRAY_SIZE(formats), si);
···
83
82
}
84
83
85
84
/*
86
-
* Palette
85
+
* Color LUT
87
86
*/
88
87
89
88
static void vesadrm_vga_cmap_write(struct vesadrm_device *vesa, unsigned int index,
···
129
128
}
130
129
#endif
131
130
132
-
static void vesadrm_set_gamma_lut(struct drm_crtc *crtc, unsigned int index,
131
+
static void vesadrm_set_color_lut(struct drm_crtc *crtc, unsigned int index,
133
132
u16 red, u16 green, u16 blue)
134
133
{
135
134
struct drm_device *dev = crtc->dev;
···
150
149
151
150
switch (format->format) {
152
151
case DRM_FORMAT_XRGB1555:
153
-
drm_crtc_fill_gamma_555(crtc, vesadrm_set_gamma_lut);
152
+
drm_crtc_fill_gamma_555(crtc, vesadrm_set_color_lut);
154
153
break;
155
154
case DRM_FORMAT_RGB565:
156
-
drm_crtc_fill_gamma_565(crtc, vesadrm_set_gamma_lut);
155
+
drm_crtc_fill_gamma_565(crtc, vesadrm_set_color_lut);
157
156
break;
158
157
case DRM_FORMAT_RGB888:
159
158
case DRM_FORMAT_XRGB8888:
160
159
case DRM_FORMAT_BGRX8888:
161
-
drm_crtc_fill_gamma_888(crtc, vesadrm_set_gamma_lut);
160
+
drm_crtc_fill_gamma_888(crtc, vesadrm_set_color_lut);
162
161
break;
163
162
default:
164
163
drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n",
···
176
175
177
176
switch (format->format) {
178
177
case DRM_FORMAT_XRGB1555:
179
-
drm_crtc_load_gamma_555_from_888(crtc, lut, vesadrm_set_gamma_lut);
178
+
drm_crtc_load_gamma_555_from_888(crtc, lut, vesadrm_set_color_lut);
180
179
break;
181
180
case DRM_FORMAT_RGB565:
182
-
drm_crtc_load_gamma_565_from_888(crtc, lut, vesadrm_set_gamma_lut);
181
+
drm_crtc_load_gamma_565_from_888(crtc, lut, vesadrm_set_color_lut);
183
182
break;
184
183
case DRM_FORMAT_RGB888:
185
184
case DRM_FORMAT_XRGB8888:
186
185
case DRM_FORMAT_BGRX8888:
187
-
drm_crtc_load_gamma_888(crtc, lut, vesadrm_set_gamma_lut);
186
+
drm_crtc_load_gamma_888(crtc, lut, vesadrm_set_color_lut);
187
+
break;
188
+
default:
189
+
drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n",
190
+
&format->format);
191
+
break;
192
+
}
193
+
}
194
+
195
+
static void vesadrm_fill_palette_lut(struct vesadrm_device *vesa,
196
+
const struct drm_format_info *format)
197
+
{
198
+
struct drm_device *dev = &vesa->sysfb.dev;
199
+
struct drm_crtc *crtc = &vesa->crtc;
200
+
201
+
switch (format->format) {
202
+
case DRM_FORMAT_C8:
203
+
drm_crtc_fill_palette_8(crtc, vesadrm_set_color_lut);
204
+
break;
205
+
case DRM_FORMAT_RGB332:
206
+
drm_crtc_fill_palette_332(crtc, vesadrm_set_color_lut);
207
+
break;
208
+
default:
209
+
drm_warn_once(dev, "Unsupported format %p4cc for palette\n",
210
+
&format->format);
211
+
break;
212
+
}
213
+
}
214
+
215
+
static void vesadrm_load_palette_lut(struct vesadrm_device *vesa,
216
+
const struct drm_format_info *format,
217
+
struct drm_color_lut *lut)
218
+
{
219
+
struct drm_device *dev = &vesa->sysfb.dev;
220
+
struct drm_crtc *crtc = &vesa->crtc;
221
+
222
+
switch (format->format) {
223
+
case DRM_FORMAT_C8:
224
+
drm_crtc_load_palette_8(crtc, lut, vesadrm_set_color_lut);
188
225
break;
189
226
default:
190
227
drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n",
···
239
200
DRM_SYSFB_PLANE_FORMAT_MODIFIERS,
240
201
};
241
202
203
+
static int vesadrm_primary_plane_helper_atomic_check(struct drm_plane *plane,
204
+
struct drm_atomic_state *new_state)
205
+
{
206
+
struct drm_sysfb_device *sysfb = to_drm_sysfb_device(plane->dev);
207
+
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane);
208
+
struct drm_framebuffer *new_fb = new_plane_state->fb;
209
+
struct drm_crtc_state *new_crtc_state;
210
+
struct drm_sysfb_crtc_state *new_sysfb_crtc_state;
211
+
int ret;
212
+
213
+
ret = drm_sysfb_plane_helper_atomic_check(plane, new_state);
214
+
if (ret)
215
+
return ret;
216
+
else if (!new_plane_state->visible)
217
+
return 0;
218
+
219
+
/*
220
+
* Fix up format conversion for specific cases
221
+
*/
222
+
223
+
switch (sysfb->fb_format->format) {
224
+
case DRM_FORMAT_C8:
225
+
new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc);
226
+
new_sysfb_crtc_state = to_drm_sysfb_crtc_state(new_crtc_state);
227
+
228
+
switch (new_fb->format->format) {
229
+
case DRM_FORMAT_XRGB8888:
230
+
/*
231
+
* Reduce XRGB8888 to RGB332. Each resulting pixel is an index
232
+
* into the C8 hardware palette, which stores RGB332 colors.
233
+
*/
234
+
if (new_sysfb_crtc_state->format->format != DRM_FORMAT_RGB332) {
235
+
new_sysfb_crtc_state->format =
236
+
drm_format_info(DRM_FORMAT_RGB332);
237
+
new_crtc_state->color_mgmt_changed = true;
238
+
}
239
+
break;
240
+
case DRM_FORMAT_C8:
241
+
/*
242
+
* Restore original output. Emulation of XRGB8888 set RBG332
243
+
* output format and hardware palette. This needs to be undone
244
+
* when we switch back to DRM_FORMAT_C8.
245
+
*/
246
+
if (new_sysfb_crtc_state->format->format == DRM_FORMAT_RGB332) {
247
+
new_sysfb_crtc_state->format = sysfb->fb_format;
248
+
new_crtc_state->color_mgmt_changed = true;
249
+
}
250
+
break;
251
+
}
252
+
break;
253
+
};
254
+
255
+
return 0;
256
+
}
257
+
242
258
static const struct drm_plane_helper_funcs vesadrm_primary_plane_helper_funcs = {
243
-
DRM_SYSFB_PLANE_HELPER_FUNCS,
259
+
DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
260
+
.atomic_check = vesadrm_primary_plane_helper_atomic_check,
261
+
.atomic_update = drm_sysfb_plane_helper_atomic_update,
262
+
.atomic_disable = drm_sysfb_plane_helper_atomic_disable,
263
+
.get_scanout_buffer = drm_sysfb_plane_helper_get_scanout_buffer,
244
264
};
245
265
246
266
static const struct drm_plane_funcs vesadrm_primary_plane_funcs = {
···
321
223
* plane's color format.
322
224
*/
323
225
if (crtc_state->enable && crtc_state->color_mgmt_changed) {
324
-
if (sysfb_crtc_state->format == sysfb->fb_format) {
325
-
if (crtc_state->gamma_lut)
326
-
vesadrm_load_gamma_lut(vesa,
327
-
sysfb_crtc_state->format,
328
-
crtc_state->gamma_lut->data);
329
-
else
226
+
switch (sysfb->fb_format->format) {
227
+
/*
228
+
* Index formats
229
+
*/
230
+
case DRM_FORMAT_C8:
231
+
if (sysfb_crtc_state->format->format == DRM_FORMAT_RGB332) {
232
+
vesadrm_fill_palette_lut(vesa, sysfb_crtc_state->format);
233
+
} else if (crtc->state->gamma_lut) {
234
+
vesadrm_load_palette_lut(vesa,
235
+
sysfb_crtc_state->format,
236
+
crtc_state->gamma_lut->data);
237
+
} else {
238
+
vesadrm_fill_palette_lut(vesa, sysfb_crtc_state->format);
239
+
}
240
+
break;
241
+
/*
242
+
* Component formats
243
+
*/
244
+
default:
245
+
if (sysfb_crtc_state->format == sysfb->fb_format) {
246
+
if (crtc_state->gamma_lut)
247
+
vesadrm_load_gamma_lut(vesa,
248
+
sysfb_crtc_state->format,
249
+
crtc_state->gamma_lut->data);
250
+
else
251
+
vesadrm_fill_gamma_lut(vesa, sysfb_crtc_state->format);
252
+
} else {
330
253
vesadrm_fill_gamma_lut(vesa, sysfb_crtc_state->format);
331
-
} else {
332
-
vesadrm_fill_gamma_lut(vesa, sysfb_crtc_state->format);
254
+
}
255
+
break;
333
256
}
334
257
}
335
258
}
+28
-18
drivers/hid/i2c-hid/i2c-hid-core.c
+28
-18
drivers/hid/i2c-hid/i2c-hid-core.c
···
112
112
113
113
struct i2chid_ops *ops;
114
114
struct drm_panel_follower panel_follower;
115
-
struct work_struct panel_follower_prepare_work;
115
+
struct work_struct panel_follower_work;
116
116
bool is_panel_follower;
117
-
bool prepare_work_finished;
117
+
bool panel_follower_work_finished;
118
118
};
119
119
120
120
static const struct i2c_hid_quirks {
···
1110
1110
return ret;
1111
1111
}
1112
1112
1113
-
static void ihid_core_panel_prepare_work(struct work_struct *work)
1113
+
static void ihid_core_panel_follower_work(struct work_struct *work)
1114
1114
{
1115
1115
struct i2c_hid *ihid = container_of(work, struct i2c_hid,
1116
-
panel_follower_prepare_work);
1116
+
panel_follower_work);
1117
1117
struct hid_device *hid = ihid->hid;
1118
1118
int ret;
1119
1119
···
1130
1130
if (ret)
1131
1131
dev_warn(&ihid->client->dev, "Power on failed: %d\n", ret);
1132
1132
else
1133
-
WRITE_ONCE(ihid->prepare_work_finished, true);
1133
+
WRITE_ONCE(ihid->panel_follower_work_finished, true);
1134
1134
1135
1135
/*
1136
1136
* The work APIs provide a number of memory ordering guarantees
···
1139
1139
* guarantee that a write that happened in the work is visible after
1140
1140
* cancel_work_sync(). We'll add a write memory barrier here to match
1141
1141
* with i2c_hid_core_panel_unpreparing() to ensure that our write to
1142
-
* prepare_work_finished is visible there.
1142
+
* panel_follower_work_finished is visible there.
1143
1143
*/
1144
1144
smp_wmb();
1145
1145
}
1146
1146
1147
-
static int i2c_hid_core_panel_prepared(struct drm_panel_follower *follower)
1147
+
static int i2c_hid_core_panel_follower_resume(struct drm_panel_follower *follower)
1148
1148
{
1149
1149
struct i2c_hid *ihid = container_of(follower, struct i2c_hid, panel_follower);
1150
1150
···
1152
1152
* Powering on a touchscreen can be a slow process. Queue the work to
1153
1153
* the system workqueue so we don't block the panel's power up.
1154
1154
*/
1155
-
WRITE_ONCE(ihid->prepare_work_finished, false);
1156
-
schedule_work(&ihid->panel_follower_prepare_work);
1155
+
WRITE_ONCE(ihid->panel_follower_work_finished, false);
1156
+
schedule_work(&ihid->panel_follower_work);
1157
1157
1158
1158
return 0;
1159
1159
}
1160
1160
1161
-
static int i2c_hid_core_panel_unpreparing(struct drm_panel_follower *follower)
1161
+
static int i2c_hid_core_panel_follower_suspend(struct drm_panel_follower *follower)
1162
1162
{
1163
1163
struct i2c_hid *ihid = container_of(follower, struct i2c_hid, panel_follower);
1164
1164
1165
-
cancel_work_sync(&ihid->panel_follower_prepare_work);
1165
+
cancel_work_sync(&ihid->panel_follower_work);
1166
1166
1167
-
/* Match with ihid_core_panel_prepare_work() */
1167
+
/* Match with ihid_core_panel_follower_work() */
1168
1168
smp_rmb();
1169
-
if (!READ_ONCE(ihid->prepare_work_finished))
1169
+
if (!READ_ONCE(ihid->panel_follower_work_finished))
1170
1170
return 0;
1171
1171
1172
1172
return i2c_hid_core_suspend(ihid, true);
1173
1173
}
1174
1174
1175
-
static const struct drm_panel_follower_funcs i2c_hid_core_panel_follower_funcs = {
1176
-
.panel_prepared = i2c_hid_core_panel_prepared,
1177
-
.panel_unpreparing = i2c_hid_core_panel_unpreparing,
1175
+
static const struct drm_panel_follower_funcs
1176
+
i2c_hid_core_panel_follower_prepare_funcs = {
1177
+
.panel_prepared = i2c_hid_core_panel_follower_resume,
1178
+
.panel_unpreparing = i2c_hid_core_panel_follower_suspend,
1179
+
};
1180
+
1181
+
static const struct drm_panel_follower_funcs
1182
+
i2c_hid_core_panel_follower_enable_funcs = {
1183
+
.panel_enabled = i2c_hid_core_panel_follower_resume,
1184
+
.panel_disabling = i2c_hid_core_panel_follower_suspend,
1178
1185
};
1179
1186
1180
1187
static int i2c_hid_core_register_panel_follower(struct i2c_hid *ihid)
···
1189
1182
struct device *dev = &ihid->client->dev;
1190
1183
int ret;
1191
1184
1192
-
ihid->panel_follower.funcs = &i2c_hid_core_panel_follower_funcs;
1185
+
if (ihid->hid->initial_quirks & HID_QUIRK_POWER_ON_AFTER_BACKLIGHT)
1186
+
ihid->panel_follower.funcs = &i2c_hid_core_panel_follower_enable_funcs;
1187
+
else
1188
+
ihid->panel_follower.funcs = &i2c_hid_core_panel_follower_prepare_funcs;
1193
1189
1194
1190
/*
1195
1191
* If we're not in control of our own power up/power down then we can't
···
1247
1237
init_waitqueue_head(&ihid->wait);
1248
1238
mutex_init(&ihid->cmd_lock);
1249
1239
mutex_init(&ihid->reset_lock);
1250
-
INIT_WORK(&ihid->panel_follower_prepare_work, ihid_core_panel_prepare_work);
1240
+
INIT_WORK(&ihid->panel_follower_work, ihid_core_panel_follower_work);
1251
1241
1252
1242
/* we need to allocate the command buffer without knowing the maximum
1253
1243
* size of the reports. Let's use HID_MIN_BUFFER_SIZE, then we do the
+10
-1
drivers/hid/i2c-hid/i2c-hid-of-elan.c
+10
-1
drivers/hid/i2c-hid/i2c-hid-of-elan.c
···
8
8
#include <linux/delay.h>
9
9
#include <linux/device.h>
10
10
#include <linux/gpio/consumer.h>
11
+
#include <linux/hid.h>
11
12
#include <linux/i2c.h>
12
13
#include <linux/kernel.h>
13
14
#include <linux/module.h>
···
24
23
unsigned int post_power_delay_ms;
25
24
u16 hid_descriptor_address;
26
25
const char *main_supply_name;
26
+
bool power_after_backlight;
27
27
};
28
28
29
29
struct i2c_hid_of_elan {
···
99
97
{
100
98
struct i2c_hid_of_elan *ihid_elan;
101
99
int ret;
100
+
u32 quirks = 0;
102
101
103
102
ihid_elan = devm_kzalloc(&client->dev, sizeof(*ihid_elan), GFP_KERNEL);
104
103
if (!ihid_elan)
···
134
131
}
135
132
}
136
133
134
+
if (ihid_elan->chip_data->power_after_backlight)
135
+
quirks = HID_QUIRK_POWER_ON_AFTER_BACKLIGHT;
136
+
137
137
ret = i2c_hid_core_probe(client, &ihid_elan->ops,
138
-
ihid_elan->chip_data->hid_descriptor_address, 0);
138
+
ihid_elan->chip_data->hid_descriptor_address,
139
+
quirks);
139
140
if (ret)
140
141
goto err_deassert_reset;
141
142
···
157
150
.post_gpio_reset_on_delay_ms = 300,
158
151
.hid_descriptor_address = 0x0001,
159
152
.main_supply_name = "vcc33",
153
+
.power_after_backlight = true,
160
154
};
161
155
162
156
static const struct elan_i2c_hid_chip_data elan_ekth6a12nay_chip_data = {
···
165
157
.post_gpio_reset_on_delay_ms = 300,
166
158
.hid_descriptor_address = 0x0001,
167
159
.main_supply_name = "vcc33",
160
+
.power_after_backlight = true,
168
161
};
169
162
170
163
static const struct elan_i2c_hid_chip_data ilitek_ili9882t_chip_data = {
+55
drivers/video/screen_info_generic.c
+55
drivers/video/screen_info_generic.c
···
5
5
#include <linux/screen_info.h>
6
6
#include <linux/string.h>
7
7
8
+
#include <video/pixel_format.h>
9
+
8
10
static void resource_init_named(struct resource *r,
9
11
resource_size_t start, resource_size_t size,
10
12
const char *name, unsigned int flags)
···
182
180
return bits_per_pixel;
183
181
}
184
182
EXPORT_SYMBOL(__screen_info_lfb_bits_per_pixel);
183
+
184
+
static int __screen_info_lfb_pixel_format(const struct screen_info *si, struct pixel_format *f)
185
+
{
186
+
u32 bits_per_pixel = __screen_info_lfb_bits_per_pixel(si);
187
+
188
+
if (bits_per_pixel > U8_MAX)
189
+
return -EINVAL;
190
+
191
+
f->bits_per_pixel = bits_per_pixel;
192
+
193
+
if (si->lfb_depth > 8) {
194
+
f->indexed = false;
195
+
f->alpha.offset = 0;
196
+
f->alpha.length = 0;
197
+
f->red.offset = si->red_pos;
198
+
f->red.length = si->red_size;
199
+
f->green.offset = si->green_pos;
200
+
f->green.length = si->green_size;
201
+
f->blue.offset = si->blue_pos;
202
+
f->blue.length = si->blue_size;
203
+
} else {
204
+
f->indexed = true;
205
+
f->index.offset = 0;
206
+
f->index.length = si->lfb_depth;
207
+
}
208
+
209
+
return 0;
210
+
}
211
+
212
+
/**
213
+
* screen_info_pixel_format - Returns the screen-info format as pixel-format description
214
+
*
215
+
* @si: the screen_info
216
+
* @f: pointer to return pixel-format description
217
+
*
218
+
* Returns:
219
+
* 0 on success, or a negative errno code otherwise.
220
+
*/
221
+
int screen_info_pixel_format(const struct screen_info *si, struct pixel_format *f)
222
+
{
223
+
unsigned int type = screen_info_video_type(si);
224
+
225
+
/* TODO: Add support for additional types as needed. */
226
+
switch (type) {
227
+
case VIDEO_TYPE_VLFB:
228
+
case VIDEO_TYPE_EFI:
229
+
return __screen_info_lfb_pixel_format(si, f);
230
+
}
231
+
232
+
/* not supported */
233
+
return -EINVAL;
234
+
}
235
+
EXPORT_SYMBOL(screen_info_pixel_format);
+1
include/drm/drm_color_mgmt.h
+1
include/drm/drm_color_mgmt.h
···
143
143
void drm_crtc_load_palette_8(struct drm_crtc *crtc, const struct drm_color_lut *lut,
144
144
drm_crtc_set_lut_func set_palette);
145
145
146
+
void drm_crtc_fill_palette_332(struct drm_crtc *crtc, drm_crtc_set_lut_func set_palette);
146
147
void drm_crtc_fill_palette_8(struct drm_crtc *crtc, drm_crtc_set_lut_func set_palette);
147
148
148
149
#endif
+14
include/drm/drm_panel.h
+14
include/drm/drm_panel.h
···
160
160
* Called before the panel is powered off.
161
161
*/
162
162
int (*panel_unpreparing)(struct drm_panel_follower *follower);
163
+
164
+
/**
165
+
* @panel_enabled:
166
+
*
167
+
* Called after the panel and the backlight have been enabled.
168
+
*/
169
+
int (*panel_enabled)(struct drm_panel_follower *follower);
170
+
171
+
/**
172
+
* @panel_disabling:
173
+
*
174
+
* Called before the panel and the backlight are disabled.
175
+
*/
176
+
int (*panel_disabling)(struct drm_panel_follower *follower);
163
177
};
164
178
165
179
struct drm_panel_follower {
+2
include/linux/hid.h
+2
include/linux/hid.h
···
364
364
* | @HID_QUIRK_HAVE_SPECIAL_DRIVER:
365
365
* | @HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE:
366
366
* | @HID_QUIRK_IGNORE_SPECIAL_DRIVER
367
+
* | @HID_QUIRK_POWER_ON_AFTER_BACKLIGHT
367
368
* | @HID_QUIRK_FULLSPEED_INTERVAL:
368
369
* | @HID_QUIRK_NO_INIT_REPORTS:
369
370
* | @HID_QUIRK_NO_IGNORE:
···
392
391
#define HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE BIT(20)
393
392
#define HID_QUIRK_NOINVERT BIT(21)
394
393
#define HID_QUIRK_IGNORE_SPECIAL_DRIVER BIT(22)
394
+
#define HID_QUIRK_POWER_ON_AFTER_BACKLIGHT BIT(23)
395
395
#define HID_QUIRK_FULLSPEED_INTERVAL BIT(28)
396
396
#define HID_QUIRK_NO_INIT_REPORTS BIT(29)
397
397
#define HID_QUIRK_NO_IGNORE BIT(30)
+2
include/linux/screen_info.h
+2
include/linux/screen_info.h
···
12
12
#define SCREEN_INFO_MAX_RESOURCES 3
13
13
14
14
struct pci_dev;
15
+
struct pixel_format;
15
16
struct resource;
16
17
17
18
static inline bool __screen_info_has_lfb(unsigned int type)
···
137
136
ssize_t screen_info_resources(const struct screen_info *si, struct resource *r, size_t num);
138
137
139
138
u32 __screen_info_lfb_bits_per_pixel(const struct screen_info *si);
139
+
int screen_info_pixel_format(const struct screen_info *si, struct pixel_format *f);
140
140
141
141
#if defined(CONFIG_PCI)
142
142
void screen_info_apply_fixups(void);
+61
include/video/pixel_format.h
+61
include/video/pixel_format.h
···
20
20
};
21
21
};
22
22
23
+
#define PIXEL_FORMAT_C8 \
24
+
{ 8, true, { .index = {0, 8}, } }
25
+
23
26
#define PIXEL_FORMAT_XRGB1555 \
24
27
{ 16, false, { .alpha = {0, 0}, .red = {10, 5}, .green = {5, 5}, .blue = {0, 5} } }
25
28
···
40
37
41
38
#define PIXEL_FORMAT_XRGB2101010 \
42
39
{ 32, false, { .alpha = {0, 0}, .red = {20, 10}, .green = {10, 10}, .blue = {0, 10} } }
40
+
41
+
#define __pixel_format_cmp_field(lhs, rhs, name) \
42
+
{ \
43
+
int ret = ((lhs)->name) - ((rhs)->name); \
44
+
if (ret) \
45
+
return ret; \
46
+
}
47
+
48
+
#define __pixel_format_cmp_bitfield(lhs, rhs, name) \
49
+
{ \
50
+
__pixel_format_cmp_field(lhs, rhs, name.offset); \
51
+
__pixel_format_cmp_field(lhs, rhs, name.length); \
52
+
}
53
+
54
+
/**
55
+
* pixel_format_cmp - Compares two pixel-format descriptions
56
+
*
57
+
* @lhs: a pixel-format description
58
+
* @rhs: a pixel-format description
59
+
*
60
+
* Compares two pixel-format descriptions for their order. The semantics
61
+
* are equivalent to memcmp().
62
+
*
63
+
* Returns:
64
+
* 0 if both arguments describe the same pixel format, less-than-zero if lhs < rhs,
65
+
* or greater-than-zero if lhs > rhs.
66
+
*/
67
+
static inline int pixel_format_cmp(const struct pixel_format *lhs, const struct pixel_format *rhs)
68
+
{
69
+
__pixel_format_cmp_field(lhs, rhs, bits_per_pixel);
70
+
__pixel_format_cmp_field(lhs, rhs, indexed);
71
+
72
+
if (lhs->indexed) {
73
+
__pixel_format_cmp_bitfield(lhs, rhs, index);
74
+
} else {
75
+
__pixel_format_cmp_bitfield(lhs, rhs, alpha);
76
+
__pixel_format_cmp_bitfield(lhs, rhs, red);
77
+
__pixel_format_cmp_bitfield(lhs, rhs, green);
78
+
__pixel_format_cmp_bitfield(lhs, rhs, blue);
79
+
}
80
+
81
+
return 0;
82
+
}
83
+
84
+
/**
85
+
* pixel_format_equal - Compares two pixel-format descriptions for equality
86
+
*
87
+
* @lhs: a pixel-format description
88
+
* @rhs: a pixel-format description
89
+
*
90
+
* Returns:
91
+
* True if both arguments describe the same pixel format, or false otherwise.
92
+
*/
93
+
static inline bool pixel_format_equal(const struct pixel_format *lhs,
94
+
const struct pixel_format *rhs)
95
+
{
96
+
return !pixel_format_cmp(lhs, rhs);
97
+
}
43
98
44
99
#endif