Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'pci/controller/mediatek-gen3'
- Add optional sys clock ready time setting to avoid sys_clk_rdy signal
glitching in MT6991 and MT8196 (AngeloGioacchino Del Regno)
- Add DT binding and driver support for MT6991 and MT8196 (AngeloGioacchino
Del Regno)
* pci/controller/mediatek-gen3:
PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC
dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
PCI: mediatek-gen3: Implement sys clock ready time setting
+58
+35
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+35
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
···
52
52
- mediatek,mt8188-pcie
53
53
- mediatek,mt8195-pcie
54
54
- const: mediatek,mt8192-pcie
55
+
- items:
56
+
- enum:
57
+
- mediatek,mt6991-pcie
58
+
- const: mediatek,mt8196-pcie
55
59
- const: mediatek,mt8192-pcie
60
+
- const: mediatek,mt8196-pcie
56
61
- const: airoha,en7581-pcie
57
62
58
63
reg:
···
214
209
reset-names:
215
210
minItems: 1
216
211
maxItems: 2
212
+
213
+
mediatek,pbus-csr: false
214
+
215
+
- if:
216
+
properties:
217
+
compatible:
218
+
contains:
219
+
enum:
220
+
- mediatek,mt8196-pcie
221
+
then:
222
+
properties:
223
+
clocks:
224
+
minItems: 6
225
+
226
+
clock-names:
227
+
items:
228
+
- const: pl_250m
229
+
- const: tl_26m
230
+
- const: bus
231
+
- const: low_power
232
+
- const: peri_26m
233
+
- const: peri_mem
234
+
235
+
resets:
236
+
minItems: 2
237
+
238
+
reset-names:
239
+
items:
240
+
- const: phy
241
+
- const: mac
217
242
218
243
mediatek,pbus-csr: false
219
244
+23
drivers/pci/controller/pcie-mediatek-gen3.c
+23
drivers/pci/controller/pcie-mediatek-gen3.c
···
102
102
#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
103
103
#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
104
104
105
+
#define PCIE_RESOURCE_CTRL_REG 0xd2c
106
+
#define PCIE_RSRC_SYS_CLK_RDY_TIME_MASK GENMASK(7, 0)
107
+
105
108
#define PCIE_ICMD_PM_REG 0x198
106
109
#define PCIE_TURN_OFF_LINK BIT(4)
107
110
···
152
149
* struct mtk_gen3_pcie_pdata - differentiate between host generations
153
150
* @power_up: pcie power_up callback
154
151
* @phy_resets: phy reset lines SoC data.
152
+
* @sys_clk_rdy_time_us: System clock ready time override (microseconds)
155
153
* @flags: pcie device flags.
156
154
*/
157
155
struct mtk_gen3_pcie_pdata {
···
161
157
const char *id[MAX_NUM_PHY_RESETS];
162
158
int num_resets;
163
159
} phy_resets;
160
+
u8 sys_clk_rdy_time_us;
164
161
u32 flags;
165
162
};
166
163
···
438
433
val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
439
434
val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
440
435
writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
436
+
}
437
+
438
+
/* If parameter is present, adjust SYS_CLK_RDY_TIME to avoid glitching */
439
+
if (pcie->soc->sys_clk_rdy_time_us) {
440
+
val = readl_relaxed(pcie->base + PCIE_RESOURCE_CTRL_REG);
441
+
FIELD_MODIFY(PCIE_RSRC_SYS_CLK_RDY_TIME_MASK, &val,
442
+
pcie->soc->sys_clk_rdy_time_us);
443
+
writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG);
441
444
}
442
445
443
446
/* Set class code */
···
1340
1327
},
1341
1328
};
1342
1329
1330
+
static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8196 = {
1331
+
.power_up = mtk_pcie_power_up,
1332
+
.phy_resets = {
1333
+
.id[0] = "phy",
1334
+
.num_resets = 1,
1335
+
},
1336
+
.sys_clk_rdy_time_us = 10,
1337
+
};
1338
+
1343
1339
static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
1344
1340
.power_up = mtk_pcie_en7581_power_up,
1345
1341
.phy_resets = {
···
1363
1341
static const struct of_device_id mtk_pcie_of_match[] = {
1364
1342
{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
1365
1343
{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
1344
+
{ .compatible = "mediatek,mt8196-pcie", .data = &mtk_pcie_soc_mt8196 },
1366
1345
{},
1367
1346
};
1368
1347
MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);