Merge tag 'iommu-fixes-v5.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

+2 -2

drivers/iommu/amd_iommu.c

··· 3826 3826 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; 3827 3827 3828 3828 return modify_irte_ga(ir_data->irq_2_irte.devid, 3829 - ir_data->irq_2_irte.index, entry, NULL); 3829 + ir_data->irq_2_irte.index, entry, ir_data); 3830 3830 } 3831 3831 EXPORT_SYMBOL(amd_iommu_activate_guest_mode); 3832 3832 ··· 3852 3852 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); 3853 3853 3854 3854 return modify_irte_ga(ir_data->irq_2_irte.devid, 3855 - ir_data->irq_2_irte.index, entry, NULL); 3855 + ir_data->irq_2_irte.index, entry, ir_data); 3856 3856 } 3857 3857 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); 3858 3858

+8 -8

drivers/iommu/dma-iommu.c

··· 177 177 start -= iova_offset(iovad, start); 178 178 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); 179 179 180 - msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); 181 - if (!msi_page) 182 - return -ENOMEM; 183 - 184 180 for (i = 0; i < num_pages; i++) { 185 - msi_page[i].phys = start; 186 - msi_page[i].iova = start; 187 - INIT_LIST_HEAD(&msi_page[i].list); 188 - list_add(&msi_page[i].list, &cookie->msi_page_list); 181 + msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL); 182 + if (!msi_page) 183 + return -ENOMEM; 184 + 185 + msi_page->phys = start; 186 + msi_page->iova = start; 187 + INIT_LIST_HEAD(&msi_page->list); 188 + list_add(&msi_page->list, &cookie->msi_page_list); 189 189 start += iovad->granule; 190 190 } 191 191

+17 -7

drivers/iommu/dmar.c

··· 28 28 #include <linux/slab.h> 29 29 #include <linux/iommu.h> 30 30 #include <linux/numa.h> 31 + #include <linux/limits.h> 31 32 #include <asm/irq_remapping.h> 32 33 #include <asm/iommu_table.h> 33 34 ··· 128 127 struct dmar_pci_notify_info *info; 129 128 130 129 BUG_ON(dev->is_virtfn); 130 + 131 + /* 132 + * Ignore devices that have a domain number higher than what can 133 + * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000 134 + */ 135 + if (pci_domain_nr(dev->bus) > U16_MAX) 136 + return NULL; 131 137 132 138 /* Only generate path[] for device addition event */ 133 139 if (event == BUS_NOTIFY_ADD_DEVICE) ··· 371 363 { 372 364 struct dmar_drhd_unit *dmaru; 373 365 374 - list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list) 366 + list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list, 367 + dmar_rcu_check()) 375 368 if (dmaru->segment == drhd->segment && 376 369 dmaru->reg_base_addr == drhd->address) 377 370 return dmaru; ··· 449 440 450 441 /* Check for NUL termination within the designated length */ 451 442 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { 452 - WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND, 443 + pr_warn(FW_BUG 453 444 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" 454 445 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 455 446 dmi_get_system_info(DMI_BIOS_VENDOR), 456 447 dmi_get_system_info(DMI_BIOS_VERSION), 457 448 dmi_get_system_info(DMI_PRODUCT_VERSION)); 449 + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 458 450 return -EINVAL; 459 451 } 460 452 pr_info("ANDD device: %x name: %s\n", andd->device_number, ··· 481 471 return 0; 482 472 } 483 473 } 484 - WARN_TAINT( 485 - 1, TAINT_FIRMWARE_WORKAROUND, 474 + pr_warn(FW_BUG 486 475 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" 487 476 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 488 - drhd->reg_base_addr, 477 + rhsa->base_address, 489 478 dmi_get_system_info(DMI_BIOS_VENDOR), 490 479 dmi_get_system_info(DMI_BIOS_VERSION), 491 480 dmi_get_system_info(DMI_PRODUCT_VERSION)); 481 + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 492 482 493 483 return 0; 494 484 } ··· 837 827 838 828 static void warn_invalid_dmar(u64 addr, const char *message) 839 829 { 840 - WARN_TAINT_ONCE( 841 - 1, TAINT_FIRMWARE_WORKAROUND, 830 + pr_warn_once(FW_BUG 842 831 "Your BIOS is broken; DMAR reported at address %llx%s!\n" 843 832 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 844 833 addr, message, 845 834 dmi_get_system_info(DMI_BIOS_VENDOR), 846 835 dmi_get_system_info(DMI_BIOS_VERSION), 847 836 dmi_get_system_info(DMI_PRODUCT_VERSION)); 837 + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 848 838 } 849 839 850 840 static int __ref

+38 -19

drivers/iommu/intel-iommu-debugfs.c

··· 33 33 34 34 #define IOMMU_REGSET_ENTRY(_reg_) \ 35 35 { DMAR_##_reg_##_REG, __stringify(_reg_) } 36 - static const struct iommu_regset iommu_regs[] = { 36 + 37 + static const struct iommu_regset iommu_regs_32[] = { 37 38 IOMMU_REGSET_ENTRY(VER), 38 - IOMMU_REGSET_ENTRY(CAP), 39 - IOMMU_REGSET_ENTRY(ECAP), 40 39 IOMMU_REGSET_ENTRY(GCMD), 41 40 IOMMU_REGSET_ENTRY(GSTS), 42 - IOMMU_REGSET_ENTRY(RTADDR), 43 - IOMMU_REGSET_ENTRY(CCMD), 44 41 IOMMU_REGSET_ENTRY(FSTS), 45 42 IOMMU_REGSET_ENTRY(FECTL), 46 43 IOMMU_REGSET_ENTRY(FEDATA), 47 44 IOMMU_REGSET_ENTRY(FEADDR), 48 45 IOMMU_REGSET_ENTRY(FEUADDR), 49 - IOMMU_REGSET_ENTRY(AFLOG), 50 46 IOMMU_REGSET_ENTRY(PMEN), 51 47 IOMMU_REGSET_ENTRY(PLMBASE), 52 48 IOMMU_REGSET_ENTRY(PLMLIMIT), 53 - IOMMU_REGSET_ENTRY(PHMBASE), 54 - IOMMU_REGSET_ENTRY(PHMLIMIT), 55 - IOMMU_REGSET_ENTRY(IQH), 56 - IOMMU_REGSET_ENTRY(IQT), 57 - IOMMU_REGSET_ENTRY(IQA), 58 49 IOMMU_REGSET_ENTRY(ICS), 59 - IOMMU_REGSET_ENTRY(IRTA), 60 - IOMMU_REGSET_ENTRY(PQH), 61 - IOMMU_REGSET_ENTRY(PQT), 62 - IOMMU_REGSET_ENTRY(PQA), 63 50 IOMMU_REGSET_ENTRY(PRS), 64 51 IOMMU_REGSET_ENTRY(PECTL), 65 52 IOMMU_REGSET_ENTRY(PEDATA), 66 53 IOMMU_REGSET_ENTRY(PEADDR), 67 54 IOMMU_REGSET_ENTRY(PEUADDR), 55 + }; 56 + 57 + static const struct iommu_regset iommu_regs_64[] = { 58 + IOMMU_REGSET_ENTRY(CAP), 59 + IOMMU_REGSET_ENTRY(ECAP), 60 + IOMMU_REGSET_ENTRY(RTADDR), 61 + IOMMU_REGSET_ENTRY(CCMD), 62 + IOMMU_REGSET_ENTRY(AFLOG), 63 + IOMMU_REGSET_ENTRY(PHMBASE), 64 + IOMMU_REGSET_ENTRY(PHMLIMIT), 65 + IOMMU_REGSET_ENTRY(IQH), 66 + IOMMU_REGSET_ENTRY(IQT), 67 + IOMMU_REGSET_ENTRY(IQA), 68 + IOMMU_REGSET_ENTRY(IRTA), 69 + IOMMU_REGSET_ENTRY(PQH), 70 + IOMMU_REGSET_ENTRY(PQT), 71 + IOMMU_REGSET_ENTRY(PQA), 68 72 IOMMU_REGSET_ENTRY(MTRRCAP), 69 73 IOMMU_REGSET_ENTRY(MTRRDEF), 70 74 IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000), ··· 131 127 * by adding the offset to the pointer (virtual address). 132 128 */ 133 129 raw_spin_lock_irqsave(&iommu->register_lock, flag); 134 - for (i = 0 ; i < ARRAY_SIZE(iommu_regs); i++) { 135 - value = dmar_readq(iommu->reg + iommu_regs[i].offset); 130 + for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) { 131 + value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); 136 132 seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", 137 - iommu_regs[i].regs, iommu_regs[i].offset, 133 + iommu_regs_32[i].regs, iommu_regs_32[i].offset, 134 + value); 135 + } 136 + for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) { 137 + value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); 138 + seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", 139 + iommu_regs_64[i].regs, iommu_regs_64[i].offset, 138 140 value); 139 141 } 140 142 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); ··· 282 272 { 283 273 struct dmar_drhd_unit *drhd; 284 274 struct intel_iommu *iommu; 275 + u32 sts; 285 276 286 277 rcu_read_lock(); 287 278 for_each_active_iommu(iommu, drhd) { 279 + sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); 280 + if (!(sts & DMA_GSTS_TES)) { 281 + seq_printf(m, "DMA Remapping is not enabled on %s\n", 282 + iommu->name); 283 + continue; 284 + } 288 285 root_tbl_walk(m, iommu); 289 286 seq_putc(m, '\n'); 290 287 } ··· 432 415 struct dmar_drhd_unit *drhd; 433 416 struct intel_iommu *iommu; 434 417 u64 irta; 418 + u32 sts; 435 419 436 420 rcu_read_lock(); 437 421 for_each_active_iommu(iommu, drhd) { ··· 442 424 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", 443 425 iommu->name); 444 426 445 - if (iommu->ir_table) { 427 + sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); 428 + if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { 446 429 irta = virt_to_phys(iommu->ir_table->base); 447 430 seq_printf(m, " IR table address:%llx\n", irta); 448 431 ir_tbl_remap_entry_show(m, iommu);

+19 -9

drivers/iommu/intel-iommu.c

··· 4261 4261 4262 4262 /* we know that the this iommu should be at offset 0xa000 from vtbar */ 4263 4263 drhd = dmar_find_matched_drhd_unit(pdev); 4264 - if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, 4265 - TAINT_FIRMWARE_WORKAROUND, 4266 - "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) 4264 + if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) { 4265 + pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"); 4266 + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 4267 4267 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; 4268 + } 4268 4269 } 4269 4270 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); 4270 4271 ··· 4461 4460 struct dmar_rmrr_unit *rmrru; 4462 4461 4463 4462 rmrr = (struct acpi_dmar_reserved_memory *)header; 4464 - if (rmrr_sanity_check(rmrr)) 4465 - WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND, 4463 + if (rmrr_sanity_check(rmrr)) { 4464 + pr_warn(FW_BUG 4466 4465 "Your BIOS is broken; bad RMRR [%#018Lx-%#018Lx]\n" 4467 4466 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 4468 4467 rmrr->base_address, rmrr->end_address, 4469 4468 dmi_get_system_info(DMI_BIOS_VENDOR), 4470 4469 dmi_get_system_info(DMI_BIOS_VERSION), 4471 4470 dmi_get_system_info(DMI_PRODUCT_VERSION)); 4471 + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 4472 + } 4472 4473 4473 4474 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); 4474 4475 if (!rmrru) ··· 5133 5130 5134 5131 down_write(&dmar_global_lock); 5135 5132 5133 + if (!no_iommu) 5134 + intel_iommu_debugfs_init(); 5135 + 5136 5136 if (no_iommu || dmar_disabled) { 5137 5137 /* 5138 5138 * We exit the function here to ensure IOMMU's remapping and ··· 5199 5193 5200 5194 init_iommu_pm_ops(); 5201 5195 5196 + down_read(&dmar_global_lock); 5202 5197 for_each_active_iommu(iommu, drhd) { 5203 5198 iommu_device_sysfs_add(&iommu->iommu, NULL, 5204 5199 intel_iommu_groups, ··· 5207 5200 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); 5208 5201 iommu_device_register(&iommu->iommu); 5209 5202 } 5203 + up_read(&dmar_global_lock); 5210 5204 5211 5205 bus_set_iommu(&pci_bus_type, &intel_iommu_ops); 5212 5206 if (si_domain && !hw_pass_through) ··· 5218 5210 down_read(&dmar_global_lock); 5219 5211 if (probe_acpi_namespace_devices()) 5220 5212 pr_warn("ACPI name space devices didn't probe correctly\n"); 5221 - up_read(&dmar_global_lock); 5222 5213 5223 5214 /* Finally, we enable the DMA remapping hardware. */ 5224 5215 for_each_iommu(iommu, drhd) { ··· 5226 5219 5227 5220 iommu_disable_protect_mem_regions(iommu); 5228 5221 } 5222 + up_read(&dmar_global_lock); 5223 + 5229 5224 pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); 5230 5225 5231 5226 intel_iommu_enabled = 1; 5232 - intel_iommu_debugfs_init(); 5233 5227 5234 5228 return 0; 5235 5229 ··· 5708 5700 u64 phys = 0; 5709 5701 5710 5702 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); 5711 - if (pte) 5712 - phys = dma_pte_addr(pte); 5703 + if (pte && dma_pte_present(pte)) 5704 + phys = dma_pte_addr(pte) + 5705 + (iova & (BIT_MASK(level_to_offset_bits(level) + 5706 + VTD_PAGE_SHIFT) - 1)); 5713 5707 5714 5708 return phys; 5715 5709 }

+2 -2

drivers/iommu/io-pgtable-arm.c

··· 468 468 arm_lpae_iopte *ptep = data->pgd; 469 469 int ret, lvl = data->start_level; 470 470 arm_lpae_iopte prot; 471 - long iaext = (long)iova >> cfg->ias; 471 + long iaext = (s64)iova >> cfg->ias; 472 472 473 473 /* If no access, then nothing to do */ 474 474 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) ··· 645 645 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); 646 646 struct io_pgtable_cfg *cfg = &data->iop.cfg; 647 647 arm_lpae_iopte *ptep = data->pgd; 648 - long iaext = (long)iova >> cfg->ias; 648 + long iaext = (s64)iova >> cfg->ias; 649 649 650 650 if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) 651 651 return 0;

+9 -5

include/linux/dmar.h

··· 69 69 extern struct rw_semaphore dmar_global_lock; 70 70 extern struct list_head dmar_drhd_units; 71 71 72 - #define for_each_drhd_unit(drhd) \ 73 - list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) 72 + #define for_each_drhd_unit(drhd) \ 73 + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ 74 + dmar_rcu_check()) 74 75 75 76 #define for_each_active_drhd_unit(drhd) \ 76 - list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ 77 + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ 78 + dmar_rcu_check()) \ 77 79 if (drhd->ignored) {} else 78 80 79 81 #define for_each_active_iommu(i, drhd) \ 80 - list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ 82 + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ 83 + dmar_rcu_check()) \ 81 84 if (i=drhd->iommu, drhd->ignored) {} else 82 85 83 86 #define for_each_iommu(i, drhd) \ 84 - list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ 87 + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ 88 + dmar_rcu_check()) \ 85 89 if (i=drhd->iommu, 0) {} else 86 90 87 91 static inline bool dmar_rcu_check(void)

+2

include/linux/intel-iommu.h

··· 123 123 124 124 #define dmar_readq(a) readq(a) 125 125 #define dmar_writeq(a,v) writeq(v,a) 126 + #define dmar_readl(a) readl(a) 127 + #define dmar_writel(a, v) writel(v, a) 126 128 127 129 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) 128 130 #define DMAR_VER_MINOR(v) ((v) & 0x0f)

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