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linux
dt-bindings: memory: tegra20: emc: Convert to schema
Convert Tegra20 External Memory Controller binding to schema.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210510212320.3255-1-digetx@gmail.com
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Dmitry Osipenko
and committed by
Rob Herring
de3d7018
d30e82a6
+230
-130
-130
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
-130
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
···
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Embedded Memory Controller
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Properties:
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- name : Should be emc
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- #address-cells : Should be 1
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- #size-cells : Should be 0
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- compatible : Should contain "nvidia,tegra20-emc".
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- reg : Offset and length of the register set for the device
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- nvidia,use-ram-code : If present, the sub-nodes will be addressed
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and chosen using the ramcode board selector. If omitted, only one
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set of tables can be present and said tables will be used
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irrespective of ram-code configuration.
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- interrupts : Should contain EMC General interrupt.
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- clocks : Should contain EMC clock.
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- nvidia,memory-controller : Phandle of the Memory Controller node.
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- #interconnect-cells : Should be 0.
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- operating-points-v2: See ../bindings/opp/opp.txt for details.
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-
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For each opp entry in 'operating-points-v2' table:
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- opp-supported-hw: One bitfield indicating SoC process ID mask
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A bitwise AND is performed against this value and if any bit
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matches, the OPP gets enabled.
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-
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Optional properties:
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- power-domains: Phandle of the SoC "core" power domain.
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-
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Child device nodes describe the memory settings for different configurations and clock rates.
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Example:
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opp_table: opp-table {
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compatible = "operating-points-v2";
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-
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opp@36000000 {
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opp-microvolt = <950000 950000 1300000>;
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opp-hz = /bits/ 64 <36000000>;
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};
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...
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};
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memory-controller@7000f400 {
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#address-cells = < 1 >;
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#size-cells = < 0 >;
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#interconnect-cells = <0>;
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f400 0x400>;
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interrupts = <0 78 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_EMC>;
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nvidia,memory-controller = <&mc>;
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power-domains = <&domain>;
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operating-points-v2 = <&opp_table>;
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}
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Embedded Memory Controller ram-code table
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If the emc node has the nvidia,use-ram-code property present, then the
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next level of nodes below the emc table are used to specify which settings
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apply for which ram-code settings.
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If the emc node lacks the nvidia,use-ram-code property, this level is omitted
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and the tables are stored directly under the emc node (see below).
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Properties:
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- name : Should be emc-tables
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- nvidia,ram-code : the binary representation of the ram-code board strappings
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for which this node (and children) are valid.
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Embedded Memory Controller configuration table
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This is a table containing the EMC register settings for the various
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operating speeds of the memory controller. They are always located as
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subnodes of the emc controller node.
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There are two ways of specifying which tables to use:
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* The simplest is if there is just one set of tables in the device tree,
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and they will always be used (based on which frequency is used).
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This is the preferred method, especially when firmware can fill in
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this information based on the specific system information and just
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pass it on to the kernel.
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* The slightly more complex one is when more than one memory configuration
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might exist on the system. The Tegra20 platform handles this during
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early boot by selecting one out of possible 4 memory settings based
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on a 2-pin "ram code" bootstrap setting on the board. The values of
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these strappings can be read through a register in the SoC, and thus
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used to select which tables to use.
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Properties:
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- name : Should be emc-table
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- compatible : Should contain "nvidia,tegra20-emc-table".
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- reg : either an opaque enumerator to tell different tables apart, or
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the valid frequency for which the table should be used (in kHz).
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- clock-frequency : the clock frequency for the EMC at which this
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table should be used (in kHz).
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- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
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for operation at the 'clock-frequency' setting.
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The order and contents of the registers are:
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RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
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WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
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PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
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TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
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ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
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ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
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CFG_CLKTRIM_1, CFG_CLKTRIM_2
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emc-table@166000 {
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reg = <166000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 166000 >;
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nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 >;
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};
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emc-table@333000 {
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reg = <333000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 333000 >;
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nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 >;
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};
+230
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
+230
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra20 SoC External Memory Controller
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maintainers:
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- Dmitry Osipenko <digetx@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
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service the request stream sent from Memory Controller. The EMC also has
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various performance-affecting settings beyond the obvious SDRAM configuration
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parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
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standard protocols: DDR1, LPDDR2 and DDR2.
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properties:
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compatible:
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const: nvidia,tegra20-emc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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"#interconnect-cells":
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const: 0
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nvidia,memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle of the Memory Controller node.
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power-domains:
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maxItems: 1
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description:
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Phandle of the SoC "core" power domain.
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operating-points-v2:
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description:
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Should contain freqs and voltages and opp-supported-hw property, which
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is a bitfield indicating SoC process ID mask.
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nvidia,use-ram-code:
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type: boolean
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description:
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If present, the emc-tables@ sub-nodes will be addressed.
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$defs:
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emc-table:
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type: object
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properties:
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compatible:
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const: nvidia,tegra20-emc-table
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clock-frequency:
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description:
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Memory clock rate in kHz.
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minimum: 1000
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maximum: 900000
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reg:
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maxItems: 1
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description:
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Either an opaque enumerator to tell different tables apart, or
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the valid frequency for which the table should be used (in kHz).
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nvidia,emc-registers:
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description:
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EMC timing characterization data. These are the registers
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(see section "15.4.1 EMC Registers" in the TRM) whose values
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need to be specified, according to the board documentation.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: EMC_RC
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- description: EMC_RFC
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- description: EMC_RAS
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- description: EMC_RP
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- description: EMC_R2W
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- description: EMC_W2R
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- description: EMC_R2P
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- description: EMC_W2P
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- description: EMC_RD_RCD
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- description: EMC_WR_RCD
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- description: EMC_RRD
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- description: EMC_REXT
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- description: EMC_WDV
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- description: EMC_QUSE
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- description: EMC_QRST
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- description: EMC_QSAFE
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- description: EMC_RDV
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- description: EMC_REFRESH
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- description: EMC_BURST_REFRESH_NUM
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- description: EMC_PDEX2WR
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- description: EMC_PDEX2RD
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- description: EMC_PCHG2PDEN
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- description: EMC_ACT2PDEN
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- description: EMC_AR2PDEN
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- description: EMC_RW2PDEN
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- description: EMC_TXSR
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- description: EMC_TCKE
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- description: EMC_TFAW
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- description: EMC_TRPAB
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- description: EMC_TCLKSTABLE
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- description: EMC_TCLKSTOP
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- description: EMC_TREFBW
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- description: EMC_QUSE_EXTRA
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- description: EMC_FBIO_CFG6
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- description: EMC_ODT_WRITE
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- description: EMC_ODT_READ
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- description: EMC_FBIO_CFG5
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- description: EMC_CFG_DIG_DLL
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- description: EMC_DLL_XFORM_DQS
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- description: EMC_DLL_XFORM_QUSE
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- description: EMC_ZCAL_REF_CNT
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- description: EMC_ZCAL_WAIT_CNT
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- description: EMC_AUTO_CAL_INTERVAL
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- description: EMC_CFG_CLKTRIM_0
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- description: EMC_CFG_CLKTRIM_1
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- description: EMC_CFG_CLKTRIM_2
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required:
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- clock-frequency
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- compatible
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- reg
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- nvidia,emc-registers
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additionalProperties: false
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+
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patternProperties:
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"^emc-table@[0-9]+$":
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$ref: "#/$defs/emc-table"
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+
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"^emc-tables@[a-z0-9-]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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description:
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An opaque enumerator to tell different tables apart.
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nvidia,ram-code:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Value of RAM_CODE this timing set is used for.
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"#address-cells":
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const: 1
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+
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"#size-cells":
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const: 0
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+
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patternProperties:
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"^emc-table@[0-9]+$":
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$ref: "#/$defs/emc-table"
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+
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required:
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- nvidia,ram-code
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+
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- nvidia,memory-controller
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- "#interconnect-cells"
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- operating-points-v2
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+
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additionalProperties: false
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examples:
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- |
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external-memory-controller@7000f400 {
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f400 0x400>;
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interrupts = <0 78 4>;
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clocks = <&clock_controller 57>;
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+
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nvidia,memory-controller = <&mc>;
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operating-points-v2 = <&dvfs_opp_table>;
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power-domains = <&domain>;
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+
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#interconnect-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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nvidia,use-ram-code;
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+
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emc-tables@0 {
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nvidia,ram-code = <0>;
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reg = <0>;
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+
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#address-cells = <1>;
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#size-cells = <0>;
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+
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emc-table@333000 {
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reg = <333000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = <333000>;
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nvidia,emc-registers = <0x00000018 0x00000033
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0x00000012 0x00000004 0x00000004 0x00000005
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0x00000003 0x0000000c 0x00000006 0x00000006
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0x00000003 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x00000bff
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0x00000000 0x00000003 0x00000003 0x00000006
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0x00000006 0x00000001 0x00000011 0x000000c8
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0x00000003 0x0000000e 0x00000007 0x00000008
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xf0440303
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0x007fe010 0x00001414 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000>;
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};
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};
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};