Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655403/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-23-3b2085a07884@oss.qualcomm.com
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
de723462
4115a680
+21
-43
+4
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+4
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
···
286
286
{
287
287
.name = "dce_0_0", .id = DSC_0,
288
288
.base = 0x80000, .len = 0x6,
289
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
289
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
290
290
.sblk = &dsc_sblk_0,
291
291
}, {
292
292
.name = "dce_0_1", .id = DSC_1,
293
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.base = 0x80000, .len = 0x6,
294
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
294
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
295
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.sblk = &dsc_sblk_1,
296
296
}, {
297
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.name = "dce_1_0", .id = DSC_2,
298
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.base = 0x81000, .len = 0x6,
299
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
299
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
300
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.sblk = &dsc_sblk_0,
301
301
}, {
302
302
.name = "dce_1_1", .id = DSC_3,
303
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.base = 0x81000, .len = 0x6,
304
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
304
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
305
305
.sblk = &dsc_sblk_1,
306
306
}, {
307
307
.name = "dce_2_0", .id = DSC_4,
308
308
.base = 0x82000, .len = 0x6,
309
-
.features = BIT(DPU_DSC_HW_REV_1_2),
310
309
.sblk = &dsc_sblk_0,
311
310
}, {
312
311
.name = "dce_2_1", .id = DSC_5,
313
312
.base = 0x82000, .len = 0x6,
314
-
.features = BIT(DPU_DSC_HW_REV_1_2),
315
313
.sblk = &dsc_sblk_1,
316
314
},
317
315
};
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
···
263
263
{
264
264
.name = "dce_0_0", .id = DSC_0,
265
265
.base = 0x80000, .len = 0x4,
266
-
.features = BIT(DPU_DSC_HW_REV_1_2),
267
266
.sblk = &dsc_sblk_0,
268
267
}, {
269
268
.name = "dce_0_1", .id = DSC_1,
270
269
.base = 0x80000, .len = 0x4,
271
-
.features = BIT(DPU_DSC_HW_REV_1_2),
272
270
.sblk = &dsc_sblk_1,
273
271
}, {
274
272
.name = "dce_1_0", .id = DSC_2,
275
273
.base = 0x81000, .len = 0x4,
276
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
274
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
277
275
.sblk = &dsc_sblk_0,
278
276
}, {
279
277
.name = "dce_1_1", .id = DSC_3,
280
278
.base = 0x81000, .len = 0x4,
281
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
279
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
282
280
.sblk = &dsc_sblk_1,
283
281
},
284
282
};
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+2
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+2
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
···
262
262
{
263
263
.name = "dce_0_0", .id = DSC_0,
264
264
.base = 0x80000, .len = 0x4,
265
-
.features = BIT(DPU_DSC_HW_REV_1_2),
266
265
.sblk = &dsc_sblk_0,
267
266
}, {
268
267
.name = "dce_0_1", .id = DSC_1,
269
268
.base = 0x80000, .len = 0x4,
270
-
.features = BIT(DPU_DSC_HW_REV_1_2),
271
269
.sblk = &dsc_sblk_1,
272
270
}, {
273
271
.name = "dce_1_0", .id = DSC_2,
274
272
.base = 0x81000, .len = 0x4,
275
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
273
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
276
274
.sblk = &dsc_sblk_0,
277
275
}, {
278
276
.name = "dce_1_1", .id = DSC_3,
279
277
.base = 0x81000, .len = 0x4,
280
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
278
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
281
279
.sblk = &dsc_sblk_1,
282
280
}, {
283
281
.name = "dce_2_0", .id = DSC_4,
284
282
.base = 0x82000, .len = 0x4,
285
-
.features = BIT(DPU_DSC_HW_REV_1_2),
286
283
.sblk = &dsc_sblk_0,
287
284
}, {
288
285
.name = "dce_2_1", .id = DSC_5,
289
286
.base = 0x82000, .len = 0x4,
290
-
.features = BIT(DPU_DSC_HW_REV_1_2),
291
287
.sblk = &dsc_sblk_1,
292
288
},
293
289
};
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
···
276
276
{
277
277
.name = "dce_0_0", .id = DSC_0,
278
278
.base = 0x80000, .len = 0x4,
279
-
.features = BIT(DPU_DSC_HW_REV_1_2),
280
279
.sblk = &dsc_sblk_0,
281
280
}, {
282
281
.name = "dce_0_1", .id = DSC_1,
283
282
.base = 0x80000, .len = 0x4,
284
-
.features = BIT(DPU_DSC_HW_REV_1_2),
285
283
.sblk = &dsc_sblk_1,
286
284
}, {
287
285
.name = "dce_1_0", .id = DSC_2,
288
286
.base = 0x81000, .len = 0x4,
289
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
287
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
290
288
.sblk = &dsc_sblk_0,
291
289
}, {
292
290
.name = "dce_1_1", .id = DSC_3,
293
291
.base = 0x81000, .len = 0x4,
294
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
292
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
295
293
.sblk = &dsc_sblk_1,
296
294
},
297
295
};
+2
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+2
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
···
275
275
{
276
276
.name = "dce_0_0", .id = DSC_0,
277
277
.base = 0x80000, .len = 0x4,
278
-
.features = BIT(DPU_DSC_HW_REV_1_2),
279
278
.sblk = &dsc_sblk_0,
280
279
}, {
281
280
.name = "dce_0_1", .id = DSC_1,
282
281
.base = 0x80000, .len = 0x4,
283
-
.features = BIT(DPU_DSC_HW_REV_1_2),
284
282
.sblk = &dsc_sblk_1,
285
283
}, {
286
284
.name = "dce_1_0", .id = DSC_2,
287
285
.base = 0x81000, .len = 0x4,
288
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
286
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
289
287
.sblk = &dsc_sblk_0,
290
288
}, {
291
289
.name = "dce_1_1", .id = DSC_3,
292
290
.base = 0x81000, .len = 0x4,
293
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
291
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
294
292
.sblk = &dsc_sblk_1,
295
293
}, {
296
294
.name = "dce_2_0", .id = DSC_4,
297
295
.base = 0x82000, .len = 0x4,
298
-
.features = BIT(DPU_DSC_HW_REV_1_2),
299
296
.sblk = &dsc_sblk_0,
300
297
}, {
301
298
.name = "dce_2_1", .id = DSC_5,
302
299
.base = 0x82000, .len = 0x4,
303
-
.features = BIT(DPU_DSC_HW_REV_1_2),
304
300
.sblk = &dsc_sblk_1,
305
301
},
306
302
};
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
···
272
272
{
273
273
.name = "dce_0_0", .id = DSC_0,
274
274
.base = 0x80000, .len = 0x4,
275
-
.features = BIT(DPU_DSC_HW_REV_1_2),
276
275
.sblk = &dsc_sblk_0,
277
276
}, {
278
277
.name = "dce_0_1", .id = DSC_1,
279
278
.base = 0x80000, .len = 0x4,
280
-
.features = BIT(DPU_DSC_HW_REV_1_2),
281
279
.sblk = &dsc_sblk_1,
282
280
}, {
283
281
.name = "dce_1_0", .id = DSC_2,
284
282
.base = 0x81000, .len = 0x4,
285
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
283
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
286
284
.sblk = &dsc_sblk_0,
287
285
}, {
288
286
.name = "dce_1_1", .id = DSC_3,
289
287
.base = 0x81000, .len = 0x4,
290
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
288
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
291
289
.sblk = &dsc_sblk_1,
292
290
},
293
291
};
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
···
272
272
{
273
273
.name = "dce_0_0", .id = DSC_0,
274
274
.base = 0x80000, .len = 0x4,
275
-
.features = BIT(DPU_DSC_HW_REV_1_2),
276
275
.sblk = &dsc_sblk_0,
277
276
}, {
278
277
.name = "dce_0_1", .id = DSC_1,
279
278
.base = 0x80000, .len = 0x4,
280
-
.features = BIT(DPU_DSC_HW_REV_1_2),
281
279
.sblk = &dsc_sblk_1,
282
280
}, {
283
281
.name = "dce_1_0", .id = DSC_2,
284
282
.base = 0x81000, .len = 0x4,
285
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
283
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
286
284
.sblk = &dsc_sblk_0,
287
285
}, {
288
286
.name = "dce_1_1", .id = DSC_3,
289
287
.base = 0x81000, .len = 0x4,
290
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
288
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
291
289
.sblk = &dsc_sblk_1,
292
290
},
293
291
};
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+2
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
···
272
272
{
273
273
.name = "dce_0_0", .id = DSC_0,
274
274
.base = 0x80000, .len = 0x4,
275
-
.features = BIT(DPU_DSC_HW_REV_1_2),
276
275
.sblk = &dsc_sblk_0,
277
276
}, {
278
277
.name = "dce_0_1", .id = DSC_1,
279
278
.base = 0x80000, .len = 0x4,
280
-
.features = BIT(DPU_DSC_HW_REV_1_2),
281
279
.sblk = &dsc_sblk_1,
282
280
}, {
283
281
.name = "dce_1_0", .id = DSC_2,
284
282
.base = 0x81000, .len = 0x4,
285
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
283
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
286
284
.sblk = &dsc_sblk_0,
287
285
}, {
288
286
.name = "dce_1_1", .id = DSC_3,
289
287
.base = 0x81000, .len = 0x4,
290
-
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
288
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
291
289
.sblk = &dsc_sblk_1,
292
290
},
293
291
};
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
176
176
* DSC sub-blocks/features
177
177
* @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
178
178
* the pixel output from this DSC.
179
-
* @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2
180
179
* @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
181
180
* @DPU_DSC_MAX
182
181
*/
183
182
enum {
184
183
DPU_DSC_OUTPUT_CTRL = 0x1,
185
-
DPU_DSC_HW_REV_1_2,
186
184
DPU_DSC_NATIVE_42x_EN,
187
185
DPU_DSC_MAX
188
186
};
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1043
1043
msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
1044
1044
"%s", cat->dsc[i].name);
1045
1045
1046
-
if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
1046
+
if (cat->mdss_ver->core_major_ver >= 7) {
1047
1047
struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
1048
1048
struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
1049
1049
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
168
168
struct dpu_hw_dsc *hw;
169
169
const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
170
170
171
-
if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features))
171
+
if (cat->mdss_ver->core_major_ver >= 7)
172
172
hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
173
173
else
174
174
hw = dpu_hw_dsc_init(dev, dsc, mmio);