Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (55 commits)
Revert "drm/i915: Try enabling RC6 by default (again)"
drm/radeon: Extended DDC Probing for ECS A740GM-M DVI-D Connector
drm/radeon: Log Subsystem Vendor and Device Information
drm/radeon: Extended DDC Probing for Connectors with Improperly Wired DDC Lines (here: Asus M2A-VM HDMI)
drm: Separate EDID Header Check from EDID Block Check
drm: Add NULL check about irq functions
drm: Fix irq install error handling
drm/radeon: fix potential NULL dereference in drivers/gpu/drm/radeon/atom.c
drm/radeon: clean reg header files
drm/debugfs: Initialise empty variable
drm/radeon/kms: add thermal chip quirk for asus 9600xt
drm/radeon: off by one in check_reg() functions
drm/radeon/kms: fix version comment due to merge timing
drm/i915: allow cache sharing policy control
drm/i915/hdmi: HDMI source product description infoframe support
drm/i915/hdmi: split infoframe setting from infoframe type code
drm: track CEA version number if present
drm/i915: Try enabling RC6 by default (again)
Revert "drm/i915/dp: Zero the DPCD data before connection probe"
drm/i915/dp: wait for previous AUX channel activity to clear
...
+753
-139
+3
-1
drivers/gpu/drm/drm_debugfs.c
+3
-1
drivers/gpu/drm/drm_debugfs.c
···
90
90
struct drm_device *dev = minor->dev;
91
91
struct dentry *ent;
92
92
struct drm_info_node *tmp;
93
-
char name[64];
94
93
int i, ret;
95
94
96
95
for (i = 0; i < count; i++) {
···
107
108
ent = debugfs_create_file(files[i].name, S_IFREG | S_IRUGO,
108
109
root, tmp, &drm_debugfs_fops);
109
110
if (!ent) {
111
+
char name[64];
112
+
strncpy(name, root->d_name.name,
113
+
min(root->d_name.len, 64U));
110
114
DRM_ERROR("Cannot create /sys/kernel/debug/dri/%s/%s\n",
111
115
name, files[i].name);
112
116
kfree(tmp);
+27
-6
drivers/gpu/drm/drm_edid.c
+27
-6
drivers/gpu/drm/drm_edid.c
···
127
127
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
128
128
};
129
129
130
+
/*
131
+
* Sanity check the header of the base EDID block. Return 8 if the header
132
+
* is perfect, down to 0 if it's totally wrong.
133
+
*/
134
+
int drm_edid_header_is_valid(const u8 *raw_edid)
135
+
{
136
+
int i, score = 0;
137
+
138
+
for (i = 0; i < sizeof(edid_header); i++)
139
+
if (raw_edid[i] == edid_header[i])
140
+
score++;
141
+
142
+
return score;
143
+
}
144
+
EXPORT_SYMBOL(drm_edid_header_is_valid);
145
+
146
+
130
147
/*
131
148
* Sanity check the EDID block (base or extension). Return 0 if the block
132
149
* doesn't check out, or 1 if it's valid.
···
156
139
struct edid *edid = (struct edid *)raw_edid;
157
140
158
141
if (raw_edid[0] == 0x00) {
159
-
int score = 0;
160
-
161
-
for (i = 0; i < sizeof(edid_header); i++)
162
-
if (raw_edid[i] == edid_header[i])
163
-
score++;
164
-
142
+
int score = drm_edid_header_is_valid(raw_edid);
165
143
if (score == 8) ;
166
144
else if (score >= 6) {
167
145
DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
···
1451
1439
static void drm_add_display_info(struct edid *edid,
1452
1440
struct drm_display_info *info)
1453
1441
{
1442
+
u8 *edid_ext;
1443
+
1454
1444
info->width_mm = edid->width_cm * 10;
1455
1445
info->height_mm = edid->height_cm * 10;
1456
1446
···
1497
1483
info->color_formats = DRM_COLOR_FORMAT_YCRCB444;
1498
1484
if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422)
1499
1485
info->color_formats = DRM_COLOR_FORMAT_YCRCB422;
1486
+
1487
+
/* Get data from CEA blocks if present */
1488
+
edid_ext = drm_find_cea_extension(edid);
1489
+
if (!edid_ext)
1490
+
return;
1491
+
1492
+
info->cea_rev = edid_ext[1];
1500
1493
}
1501
1494
1502
1495
/**
+18
-8
drivers/gpu/drm/drm_irq.c
+18
-8
drivers/gpu/drm/drm_irq.c
···
291
291
if (!dev->irq_enabled)
292
292
return;
293
293
294
-
if (state)
295
-
dev->driver->irq_uninstall(dev);
296
-
else {
297
-
dev->driver->irq_preinstall(dev);
298
-
dev->driver->irq_postinstall(dev);
294
+
if (state) {
295
+
if (dev->driver->irq_uninstall)
296
+
dev->driver->irq_uninstall(dev);
297
+
} else {
298
+
if (dev->driver->irq_preinstall)
299
+
dev->driver->irq_preinstall(dev);
300
+
if (dev->driver->irq_postinstall)
301
+
dev->driver->irq_postinstall(dev);
299
302
}
300
303
}
301
304
···
341
338
DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
342
339
343
340
/* Before installing handler */
344
-
dev->driver->irq_preinstall(dev);
341
+
if (dev->driver->irq_preinstall)
342
+
dev->driver->irq_preinstall(dev);
345
343
346
344
/* Install handler */
347
345
if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
···
367
363
vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL);
368
364
369
365
/* After installing handler */
370
-
ret = dev->driver->irq_postinstall(dev);
366
+
if (dev->driver->irq_postinstall)
367
+
ret = dev->driver->irq_postinstall(dev);
368
+
371
369
if (ret < 0) {
372
370
mutex_lock(&dev->struct_mutex);
373
371
dev->irq_enabled = 0;
374
372
mutex_unlock(&dev->struct_mutex);
373
+
if (!drm_core_check_feature(dev, DRIVER_MODESET))
374
+
vga_client_register(dev->pdev, NULL, NULL, NULL);
375
+
free_irq(drm_dev_to_irq(dev), dev);
375
376
}
376
377
377
378
return ret;
···
422
413
if (!drm_core_check_feature(dev, DRIVER_MODESET))
423
414
vga_client_register(dev->pdev, NULL, NULL, NULL);
424
415
425
-
dev->driver->irq_uninstall(dev);
416
+
if (dev->driver->irq_uninstall)
417
+
dev->driver->irq_uninstall(dev);
426
418
427
419
free_irq(drm_dev_to_irq(dev), dev);
428
420
+189
drivers/gpu/drm/i915/i915_debugfs.c
+189
drivers/gpu/drm/i915/i915_debugfs.c
···
1338
1338
.llseek = default_llseek,
1339
1339
};
1340
1340
1341
+
static int
1342
+
i915_max_freq_open(struct inode *inode,
1343
+
struct file *filp)
1344
+
{
1345
+
filp->private_data = inode->i_private;
1346
+
return 0;
1347
+
}
1348
+
1349
+
static ssize_t
1350
+
i915_max_freq_read(struct file *filp,
1351
+
char __user *ubuf,
1352
+
size_t max,
1353
+
loff_t *ppos)
1354
+
{
1355
+
struct drm_device *dev = filp->private_data;
1356
+
drm_i915_private_t *dev_priv = dev->dev_private;
1357
+
char buf[80];
1358
+
int len;
1359
+
1360
+
len = snprintf(buf, sizeof (buf),
1361
+
"max freq: %d\n", dev_priv->max_delay * 50);
1362
+
1363
+
if (len > sizeof (buf))
1364
+
len = sizeof (buf);
1365
+
1366
+
return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1367
+
}
1368
+
1369
+
static ssize_t
1370
+
i915_max_freq_write(struct file *filp,
1371
+
const char __user *ubuf,
1372
+
size_t cnt,
1373
+
loff_t *ppos)
1374
+
{
1375
+
struct drm_device *dev = filp->private_data;
1376
+
struct drm_i915_private *dev_priv = dev->dev_private;
1377
+
char buf[20];
1378
+
int val = 1;
1379
+
1380
+
if (cnt > 0) {
1381
+
if (cnt > sizeof (buf) - 1)
1382
+
return -EINVAL;
1383
+
1384
+
if (copy_from_user(buf, ubuf, cnt))
1385
+
return -EFAULT;
1386
+
buf[cnt] = 0;
1387
+
1388
+
val = simple_strtoul(buf, NULL, 0);
1389
+
}
1390
+
1391
+
DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1392
+
1393
+
/*
1394
+
* Turbo will still be enabled, but won't go above the set value.
1395
+
*/
1396
+
dev_priv->max_delay = val / 50;
1397
+
1398
+
gen6_set_rps(dev, val / 50);
1399
+
1400
+
return cnt;
1401
+
}
1402
+
1403
+
static const struct file_operations i915_max_freq_fops = {
1404
+
.owner = THIS_MODULE,
1405
+
.open = i915_max_freq_open,
1406
+
.read = i915_max_freq_read,
1407
+
.write = i915_max_freq_write,
1408
+
.llseek = default_llseek,
1409
+
};
1410
+
1411
+
static int
1412
+
i915_cache_sharing_open(struct inode *inode,
1413
+
struct file *filp)
1414
+
{
1415
+
filp->private_data = inode->i_private;
1416
+
return 0;
1417
+
}
1418
+
1419
+
static ssize_t
1420
+
i915_cache_sharing_read(struct file *filp,
1421
+
char __user *ubuf,
1422
+
size_t max,
1423
+
loff_t *ppos)
1424
+
{
1425
+
struct drm_device *dev = filp->private_data;
1426
+
drm_i915_private_t *dev_priv = dev->dev_private;
1427
+
char buf[80];
1428
+
u32 snpcr;
1429
+
int len;
1430
+
1431
+
mutex_lock(&dev_priv->dev->struct_mutex);
1432
+
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1433
+
mutex_unlock(&dev_priv->dev->struct_mutex);
1434
+
1435
+
len = snprintf(buf, sizeof (buf),
1436
+
"%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1437
+
GEN6_MBC_SNPCR_SHIFT);
1438
+
1439
+
if (len > sizeof (buf))
1440
+
len = sizeof (buf);
1441
+
1442
+
return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1443
+
}
1444
+
1445
+
static ssize_t
1446
+
i915_cache_sharing_write(struct file *filp,
1447
+
const char __user *ubuf,
1448
+
size_t cnt,
1449
+
loff_t *ppos)
1450
+
{
1451
+
struct drm_device *dev = filp->private_data;
1452
+
struct drm_i915_private *dev_priv = dev->dev_private;
1453
+
char buf[20];
1454
+
u32 snpcr;
1455
+
int val = 1;
1456
+
1457
+
if (cnt > 0) {
1458
+
if (cnt > sizeof (buf) - 1)
1459
+
return -EINVAL;
1460
+
1461
+
if (copy_from_user(buf, ubuf, cnt))
1462
+
return -EFAULT;
1463
+
buf[cnt] = 0;
1464
+
1465
+
val = simple_strtoul(buf, NULL, 0);
1466
+
}
1467
+
1468
+
if (val < 0 || val > 3)
1469
+
return -EINVAL;
1470
+
1471
+
DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1472
+
1473
+
/* Update the cache sharing policy here as well */
1474
+
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1475
+
snpcr &= ~GEN6_MBC_SNPCR_MASK;
1476
+
snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1477
+
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1478
+
1479
+
return cnt;
1480
+
}
1481
+
1482
+
static const struct file_operations i915_cache_sharing_fops = {
1483
+
.owner = THIS_MODULE,
1484
+
.open = i915_cache_sharing_open,
1485
+
.read = i915_cache_sharing_read,
1486
+
.write = i915_cache_sharing_write,
1487
+
.llseek = default_llseek,
1488
+
};
1489
+
1341
1490
/* As the drm_debugfs_init() routines are called before dev->dev_private is
1342
1491
* allocated we need to hook into the minor for release. */
1343
1492
static int
···
1586
1437
return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1587
1438
}
1588
1439
1440
+
static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
1441
+
{
1442
+
struct drm_device *dev = minor->dev;
1443
+
struct dentry *ent;
1444
+
1445
+
ent = debugfs_create_file("i915_max_freq",
1446
+
S_IRUGO | S_IWUSR,
1447
+
root, dev,
1448
+
&i915_max_freq_fops);
1449
+
if (IS_ERR(ent))
1450
+
return PTR_ERR(ent);
1451
+
1452
+
return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
1453
+
}
1454
+
1455
+
static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
1456
+
{
1457
+
struct drm_device *dev = minor->dev;
1458
+
struct dentry *ent;
1459
+
1460
+
ent = debugfs_create_file("i915_cache_sharing",
1461
+
S_IRUGO | S_IWUSR,
1462
+
root, dev,
1463
+
&i915_cache_sharing_fops);
1464
+
if (IS_ERR(ent))
1465
+
return PTR_ERR(ent);
1466
+
1467
+
return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
1468
+
}
1469
+
1589
1470
static struct drm_info_list i915_debugfs_list[] = {
1590
1471
{"i915_capabilities", i915_capabilities, 0},
1591
1472
{"i915_gem_objects", i915_gem_object_info, 0},
···
1669
1490
ret = i915_forcewake_create(minor->debugfs_root, minor);
1670
1491
if (ret)
1671
1492
return ret;
1493
+
ret = i915_max_freq_create(minor->debugfs_root, minor);
1494
+
if (ret)
1495
+
return ret;
1496
+
ret = i915_cache_sharing_create(minor->debugfs_root, minor);
1497
+
if (ret)
1498
+
return ret;
1672
1499
1673
1500
return drm_debugfs_create_files(i915_debugfs_list,
1674
1501
I915_DEBUGFS_ENTRIES,
···
1688
1503
drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1689
1504
1, minor);
1690
1505
drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1506
+
1, minor);
1507
+
drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
1508
+
1, minor);
1509
+
drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
1691
1510
1, minor);
1692
1511
}
1693
1512
+2
-4
drivers/gpu/drm/i915/i915_dma.c
+2
-4
drivers/gpu/drm/i915/i915_dma.c
···
61
61
static int i915_init_phys_hws(struct drm_device *dev)
62
62
{
63
63
drm_i915_private_t *dev_priv = dev->dev_private;
64
-
struct intel_ring_buffer *ring = LP_RING(dev_priv);
65
64
66
65
/* Program Hardware Status Page */
67
66
dev_priv->status_page_dmah =
···
70
71
DRM_ERROR("Can not allocate hardware status page\n");
71
72
return -ENOMEM;
72
73
}
73
-
ring->status_page.page_addr =
74
-
(void __force __iomem *)dev_priv->status_page_dmah->vaddr;
75
74
76
-
memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
75
+
memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
76
+
0, PAGE_SIZE);
77
77
78
78
i915_write_hws_pga(dev);
79
79
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
+1
-1
drivers/gpu/drm/i915/i915_gem.c
+1
-1
drivers/gpu/drm/i915/i915_gem.c
+3
drivers/gpu/drm/i915/i915_irq.c
+3
drivers/gpu/drm/i915/i915_irq.c
···
306
306
struct drm_mode_config *mode_config = &dev->mode_config;
307
307
struct intel_encoder *encoder;
308
308
309
+
mutex_lock(&mode_config->mutex);
309
310
DRM_DEBUG_KMS("running encoder hotplug functions\n");
310
311
311
312
list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
312
313
if (encoder->hot_plug)
313
314
encoder->hot_plug(encoder);
315
+
316
+
mutex_unlock(&mode_config->mutex);
314
317
315
318
/* Just fire off a uevent and let userspace tell us what to do */
316
319
drm_helper_hpd_irq_event(dev);
+33
-3
drivers/gpu/drm/i915/i915_reg.h
+33
-3
drivers/gpu/drm/i915/i915_reg.h
···
78
78
#define GRDOM_RENDER (1<<2)
79
79
#define GRDOM_MEDIA (3<<2)
80
80
81
+
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82
+
#define GEN6_MBC_SNPCR_SHIFT 21
83
+
#define GEN6_MBC_SNPCR_MASK (3<<21)
84
+
#define GEN6_MBC_SNPCR_MAX (0<<21)
85
+
#define GEN6_MBC_SNPCR_MED (1<<21)
86
+
#define GEN6_MBC_SNPCR_LOW (2<<21)
87
+
#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
+
81
89
#define GEN6_GDRST 0x941c
82
90
#define GEN6_GRDOM_FULL (1 << 0)
83
91
#define GEN6_GRDOM_RENDER (1 << 1)
···
1514
1506
#define VIDEO_DIP_SELECT_AVI (0 << 19)
1515
1507
#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1516
1508
#define VIDEO_DIP_SELECT_SPD (3 << 19)
1509
+
#define VIDEO_DIP_SELECT_MASK (3 << 19)
1517
1510
#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1518
1511
#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1519
1512
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
···
2092
2083
#define DP_PORT_EN (1 << 31)
2093
2084
#define DP_PIPEB_SELECT (1 << 30)
2094
2085
#define DP_PIPE_MASK (1 << 30)
2095
-
2096
-
#define DP_PIPE_ENABLED(V, P) \
2097
-
(((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
2098
2086
2099
2087
/* Link training mode - select a suitable mode for each stage */
2100
2088
#define DP_LINK_TRAIN_PAT_1 (0 << 28)
···
3030
3024
#define _TRANSA_DP_LINK_M2 0xe0048
3031
3025
#define _TRANSA_DP_LINK_N2 0xe004c
3032
3026
3027
+
/* Per-transcoder DIP controls */
3028
+
3029
+
#define _VIDEO_DIP_CTL_A 0xe0200
3030
+
#define _VIDEO_DIP_DATA_A 0xe0208
3031
+
#define _VIDEO_DIP_GCP_A 0xe0210
3032
+
3033
+
#define _VIDEO_DIP_CTL_B 0xe1200
3034
+
#define _VIDEO_DIP_DATA_B 0xe1208
3035
+
#define _VIDEO_DIP_GCP_B 0xe1210
3036
+
3037
+
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3038
+
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3039
+
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3040
+
3033
3041
#define _TRANS_HTOTAL_B 0xe1000
3034
3042
#define _TRANS_HBLANK_B 0xe1004
3035
3043
#define _TRANS_HSYNC_B 0xe1008
···
3096
3076
#define TRANS_6BPC (2<<5)
3097
3077
#define TRANS_12BPC (3<<5)
3098
3078
3079
+
#define _TRANSA_CHICKEN2 0xf0064
3080
+
#define _TRANSB_CHICKEN2 0xf1064
3081
+
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3082
+
#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3083
+
3084
+
#define SOUTH_CHICKEN1 0xc2000
3085
+
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3086
+
#define FDIA_PHASE_SYNC_SHIFT_EN 18
3087
+
#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3088
+
#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3099
3089
#define SOUTH_CHICKEN2 0xc2004
3100
3090
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3101
3091
+2
drivers/gpu/drm/i915/i915_suspend.c
+2
drivers/gpu/drm/i915/i915_suspend.c
···
812
812
dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
813
813
dev_priv->saveMCHBAR_RENDER_STANDBY =
814
814
I915_READ(RSTDBYCTL);
815
+
dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
815
816
} else {
816
817
dev_priv->saveIER = I915_READ(IER);
817
818
dev_priv->saveIMR = I915_READ(IMR);
···
864
863
I915_WRITE(GTIMR, dev_priv->saveGTIMR);
865
864
I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
866
865
I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
866
+
I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
867
867
} else {
868
868
I915_WRITE(IER, dev_priv->saveIER);
869
869
I915_WRITE(IMR, dev_priv->saveIMR);
+108
-30
drivers/gpu/drm/i915/intel_display.c
+108
-30
drivers/gpu/drm/i915/intel_display.c
···
980
980
pipe_name(pipe));
981
981
}
982
982
983
+
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
984
+
int reg, u32 port_sel, u32 val)
985
+
{
986
+
if ((val & DP_PORT_EN) == 0)
987
+
return false;
988
+
989
+
if (HAS_PCH_CPT(dev_priv->dev)) {
990
+
u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991
+
u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992
+
if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
993
+
return false;
994
+
} else {
995
+
if ((val & DP_PIPE_MASK) != (pipe << 30))
996
+
return false;
997
+
}
998
+
return true;
999
+
}
1000
+
983
1001
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984
-
enum pipe pipe, int reg)
1002
+
enum pipe pipe, int reg, u32 port_sel)
985
1003
{
986
1004
u32 val = I915_READ(reg);
987
-
WARN(DP_PIPE_ENABLED(val, pipe),
1005
+
WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
988
1006
"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
989
1007
reg, pipe_name(pipe));
990
1008
}
···
1022
1004
int reg;
1023
1005
u32 val;
1024
1006
1025
-
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1026
-
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1027
-
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1007
+
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1008
+
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1009
+
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1028
1010
1029
1011
reg = PCH_ADPA;
1030
1012
val = I915_READ(reg);
···
1294
1276
intel_wait_for_pipe_off(dev_priv->dev, pipe);
1295
1277
}
1296
1278
1279
+
/*
1280
+
* Plane regs are double buffered, going from enabled->disabled needs a
1281
+
* trigger in order to latch. The display address reg provides this.
1282
+
*/
1283
+
static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1284
+
enum plane plane)
1285
+
{
1286
+
I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1287
+
I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1288
+
}
1289
+
1297
1290
/**
1298
1291
* intel_enable_plane - enable a display plane on a given pipe
1299
1292
* @dev_priv: i915 private structure
···
1328
1299
return;
1329
1300
1330
1301
I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302
+
intel_flush_display_plane(dev_priv, plane);
1331
1303
intel_wait_for_vblank(dev_priv->dev, pipe);
1332
-
}
1333
-
1334
-
/*
1335
-
* Plane regs are double buffered, going from enabled->disabled needs a
1336
-
* trigger in order to latch. The display address reg provides this.
1337
-
*/
1338
-
static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1339
-
enum plane plane)
1340
-
{
1341
-
u32 reg = DSPADDR(plane);
1342
-
I915_WRITE(reg, I915_READ(reg));
1343
1304
}
1344
1305
1345
1306
/**
···
1357
1338
}
1358
1339
1359
1340
static void disable_pch_dp(struct drm_i915_private *dev_priv,
1360
-
enum pipe pipe, int reg)
1341
+
enum pipe pipe, int reg, u32 port_sel)
1361
1342
{
1362
1343
u32 val = I915_READ(reg);
1363
-
if (DP_PIPE_ENABLED(val, pipe))
1344
+
if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1345
+
DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1364
1346
I915_WRITE(reg, val & ~DP_PORT_EN);
1347
+
}
1365
1348
}
1366
1349
1367
1350
static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1368
1351
enum pipe pipe, int reg)
1369
1352
{
1370
1353
u32 val = I915_READ(reg);
1371
-
if (HDMI_PIPE_ENABLED(val, pipe))
1354
+
if (HDMI_PIPE_ENABLED(val, pipe)) {
1355
+
DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1356
+
reg, pipe);
1372
1357
I915_WRITE(reg, val & ~PORT_ENABLE);
1358
+
}
1373
1359
}
1374
1360
1375
1361
/* Disable any ports connected to this transcoder */
···
1386
1362
val = I915_READ(PCH_PP_CONTROL);
1387
1363
I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1388
1364
1389
-
disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1390
-
disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1391
-
disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1365
+
disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1366
+
disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1367
+
disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1392
1368
1393
1369
reg = PCH_ADPA;
1394
1370
val = I915_READ(reg);
···
2120
2096
2121
2097
/* no fb bound */
2122
2098
if (!crtc->fb) {
2123
-
DRM_DEBUG_KMS("No FB bound\n");
2099
+
DRM_ERROR("No FB bound\n");
2124
2100
return 0;
2125
2101
}
2126
2102
···
2129
2105
case 1:
2130
2106
break;
2131
2107
default:
2108
+
DRM_ERROR("no plane for crtc\n");
2132
2109
return -EINVAL;
2133
2110
}
2134
2111
···
2139
2114
NULL);
2140
2115
if (ret != 0) {
2141
2116
mutex_unlock(&dev->struct_mutex);
2117
+
DRM_ERROR("pin & fence failed\n");
2142
2118
return ret;
2143
2119
}
2144
2120
···
2168
2142
if (ret) {
2169
2143
i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2170
2144
mutex_unlock(&dev->struct_mutex);
2145
+
DRM_ERROR("failed to update base address\n");
2171
2146
return ret;
2172
2147
}
2173
2148
···
2273
2246
if (IS_IVYBRIDGE(dev))
2274
2247
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2275
2248
FDI_FE_ERRC_ENABLE);
2249
+
}
2250
+
2251
+
static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2252
+
{
2253
+
struct drm_i915_private *dev_priv = dev->dev_private;
2254
+
u32 flags = I915_READ(SOUTH_CHICKEN1);
2255
+
2256
+
flags |= FDI_PHASE_SYNC_OVR(pipe);
2257
+
I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2258
+
flags |= FDI_PHASE_SYNC_EN(pipe);
2259
+
I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2260
+
POSTING_READ(SOUTH_CHICKEN1);
2276
2261
}
2277
2262
2278
2263
/* The FDI link training functions for ILK/Ibexpeak. */
···
2437
2398
POSTING_READ(reg);
2438
2399
udelay(150);
2439
2400
2401
+
if (HAS_PCH_CPT(dev))
2402
+
cpt_phase_pointer_enable(dev, pipe);
2403
+
2440
2404
for (i = 0; i < 4; i++ ) {
2441
2405
reg = FDI_TX_CTL(pipe);
2442
2406
temp = I915_READ(reg);
···
2556
2514
POSTING_READ(reg);
2557
2515
udelay(150);
2558
2516
2517
+
if (HAS_PCH_CPT(dev))
2518
+
cpt_phase_pointer_enable(dev, pipe);
2519
+
2559
2520
for (i = 0; i < 4; i++ ) {
2560
2521
reg = FDI_TX_CTL(pipe);
2561
2522
temp = I915_READ(reg);
···
2668
2623
}
2669
2624
}
2670
2625
2626
+
static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2627
+
{
2628
+
struct drm_i915_private *dev_priv = dev->dev_private;
2629
+
u32 flags = I915_READ(SOUTH_CHICKEN1);
2630
+
2631
+
flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2632
+
I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2633
+
flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2634
+
I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2635
+
POSTING_READ(SOUTH_CHICKEN1);
2636
+
}
2671
2637
static void ironlake_fdi_disable(struct drm_crtc *crtc)
2672
2638
{
2673
2639
struct drm_device *dev = crtc->dev;
···
2708
2652
I915_WRITE(FDI_RX_CHICKEN(pipe),
2709
2653
I915_READ(FDI_RX_CHICKEN(pipe) &
2710
2654
~FDI_RX_PHASE_SYNC_POINTER_EN));
2655
+
} else if (HAS_PCH_CPT(dev)) {
2656
+
cpt_phase_pointer_disable(dev, pipe);
2711
2657
}
2712
2658
2713
2659
/* still set train pattern 1 */
···
2920
2862
I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2921
2863
}
2922
2864
2865
+
/*
2866
+
* On ILK+ LUT must be loaded before the pipe is running but with
2867
+
* clocks enabled
2868
+
*/
2869
+
intel_crtc_load_lut(crtc);
2870
+
2923
2871
intel_enable_pipe(dev_priv, pipe, is_pch_port);
2924
2872
intel_enable_plane(dev_priv, plane, pipe);
2925
2873
2926
2874
if (is_pch_port)
2927
2875
ironlake_pch_enable(crtc);
2928
-
2929
-
intel_crtc_load_lut(crtc);
2930
2876
2931
2877
mutex_lock(&dev->struct_mutex);
2932
2878
intel_update_fbc(dev);
···
4600
4538
if (connector->encoder != encoder)
4601
4539
continue;
4602
4540
4603
-
if (connector->display_info.bpc < display_bpc) {
4541
+
/* Don't use an invalid EDID bpc value */
4542
+
if (connector->display_info.bpc &&
4543
+
connector->display_info.bpc < display_bpc) {
4604
4544
DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4605
4545
display_bpc = connector->display_info.bpc;
4606
4546
}
···
5217
5153
temp |= PIPE_12BPC;
5218
5154
break;
5219
5155
default:
5220
-
WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5156
+
WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5157
+
pipe_bpp);
5221
5158
temp |= PIPE_8BPC;
5222
5159
pipe_bpp = 24;
5223
5160
break;
···
5303
5238
} else if (is_sdvo && is_tv)
5304
5239
factor = 20;
5305
5240
5306
-
if (clock.m1 < factor * clock.n)
5241
+
if (clock.m < factor * clock.n)
5307
5242
fp |= FP_CB_TUNE;
5308
5243
5309
5244
dpll = 0;
···
5580
5515
x, y, old_fb);
5581
5516
5582
5517
drm_vblank_post_modeset(dev, pipe);
5518
+
5519
+
intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5583
5520
5584
5521
return ret;
5585
5522
}
···
7781
7714
ILK_DPARB_CLK_GATE |
7782
7715
ILK_DPFD_CLK_GATE);
7783
7716
7784
-
for_each_pipe(pipe)
7717
+
for_each_pipe(pipe) {
7785
7718
I915_WRITE(DSPCNTR(pipe),
7786
7719
I915_READ(DSPCNTR(pipe)) |
7787
7720
DISPPLANE_TRICKLE_FEED_DISABLE);
7721
+
intel_flush_display_plane(dev_priv, pipe);
7722
+
}
7788
7723
}
7789
7724
7790
7725
static void ivybridge_init_clock_gating(struct drm_device *dev)
···
7803
7734
7804
7735
I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7805
7736
7806
-
for_each_pipe(pipe)
7737
+
for_each_pipe(pipe) {
7807
7738
I915_WRITE(DSPCNTR(pipe),
7808
7739
I915_READ(DSPCNTR(pipe)) |
7809
7740
DISPPLANE_TRICKLE_FEED_DISABLE);
7741
+
intel_flush_display_plane(dev_priv, pipe);
7742
+
}
7810
7743
}
7811
7744
7812
7745
static void g4x_init_clock_gating(struct drm_device *dev)
···
7891
7820
static void cpt_init_clock_gating(struct drm_device *dev)
7892
7821
{
7893
7822
struct drm_i915_private *dev_priv = dev->dev_private;
7823
+
int pipe;
7894
7824
7895
7825
/*
7896
7826
* On Ibex Peak and Cougar Point, we need to disable clock
···
7901
7829
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7902
7830
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7903
7831
DPLS_EDP_PPS_FIX_DIS);
7832
+
/* Without this, mode sets may fail silently on FDI */
7833
+
for_each_pipe(pipe)
7834
+
I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7904
7835
}
7905
7836
7906
7837
static void ironlake_teardown_rc6(struct drm_device *dev)
···
8253
8178
8254
8179
/* Lenovo U160 cannot use SSC on LVDS */
8255
8180
{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8181
+
8182
+
/* Sony Vaio Y cannot use SSC on LVDS */
8183
+
{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8256
8184
};
8257
8185
8258
8186
static void intel_init_quirks(struct drm_device *dev)
+70
-41
drivers/gpu/drm/i915/intel_dp.c
+70
-41
drivers/gpu/drm/i915/intel_dp.c
···
50
50
bool has_audio;
51
51
int force_audio;
52
52
uint32_t color_range;
53
+
int dpms_mode;
53
54
uint8_t link_bw;
54
55
uint8_t lane_count;
55
-
uint8_t dpcd[4];
56
+
uint8_t dpcd[8];
56
57
struct i2c_adapter adapter;
57
58
struct i2c_algo_dp_aux_data algo;
58
59
bool is_pch_edp;
···
317
316
else
318
317
precharge = 5;
319
318
320
-
if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
321
-
DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
322
-
I915_READ(ch_ctl));
319
+
/* Try to wait for any previous AUX channel activity */
320
+
for (try = 0; try < 3; try++) {
321
+
status = I915_READ(ch_ctl);
322
+
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
323
+
break;
324
+
msleep(1);
325
+
}
326
+
327
+
if (try == 3) {
328
+
WARN(1, "dp_aux_ch not started status 0x%08x\n",
329
+
I915_READ(ch_ctl));
323
330
return -EBUSY;
324
331
}
325
332
···
779
770
memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
780
771
intel_dp->link_configuration[0] = intel_dp->link_bw;
781
772
intel_dp->link_configuration[1] = intel_dp->lane_count;
773
+
intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
782
774
783
775
/*
784
776
* Check for DPCD version > 1.1 and enhanced framing support
···
1021
1011
1022
1012
if (is_edp(intel_dp))
1023
1013
ironlake_edp_backlight_on(dev);
1014
+
1015
+
intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1024
1016
}
1025
1017
1026
1018
static void
···
1057
1045
if (is_edp(intel_dp))
1058
1046
ironlake_edp_backlight_on(dev);
1059
1047
}
1048
+
intel_dp->dpms_mode = mode;
1060
1049
}
1061
1050
1062
1051
/*
···
1347
1334
u32 reg;
1348
1335
uint32_t DP = intel_dp->DP;
1349
1336
1350
-
/* Enable output, wait for it to become active */
1351
-
I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1352
-
POSTING_READ(intel_dp->output_reg);
1353
-
intel_wait_for_vblank(dev, intel_crtc->pipe);
1337
+
/*
1338
+
* On CPT we have to enable the port in training pattern 1, which
1339
+
* will happen below in intel_dp_set_link_train. Otherwise, enable
1340
+
* the port and wait for it to become active.
1341
+
*/
1342
+
if (!HAS_PCH_CPT(dev)) {
1343
+
I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1344
+
POSTING_READ(intel_dp->output_reg);
1345
+
intel_wait_for_vblank(dev, intel_crtc->pipe);
1346
+
}
1354
1347
1355
1348
/* Write the link configuration data */
1356
1349
intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
···
1389
1370
reg = DP | DP_LINK_TRAIN_PAT_1;
1390
1371
1391
1372
if (!intel_dp_set_link_train(intel_dp, reg,
1392
-
DP_TRAINING_PATTERN_1))
1373
+
DP_TRAINING_PATTERN_1 |
1374
+
DP_LINK_SCRAMBLING_DISABLE))
1393
1375
break;
1394
1376
/* Set training pattern 1 */
1395
1377
···
1465
1445
1466
1446
/* channel eq pattern */
1467
1447
if (!intel_dp_set_link_train(intel_dp, reg,
1468
-
DP_TRAINING_PATTERN_2))
1448
+
DP_TRAINING_PATTERN_2 |
1449
+
DP_LINK_SCRAMBLING_DISABLE))
1469
1450
break;
1470
1451
1471
1452
udelay(400);
···
1580
1559
POSTING_READ(intel_dp->output_reg);
1581
1560
}
1582
1561
1562
+
static bool
1563
+
intel_dp_get_dpcd(struct intel_dp *intel_dp)
1564
+
{
1565
+
if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1566
+
sizeof (intel_dp->dpcd)) &&
1567
+
(intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1568
+
return true;
1569
+
}
1570
+
1571
+
return false;
1572
+
}
1573
+
1583
1574
/*
1584
1575
* According to DP spec
1585
1576
* 5.1.2:
···
1604
1571
static void
1605
1572
intel_dp_check_link_status(struct intel_dp *intel_dp)
1606
1573
{
1607
-
int ret;
1574
+
if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1575
+
return;
1608
1576
1609
1577
if (!intel_dp->base.base.crtc)
1610
1578
return;
1611
1579
1580
+
/* Try to read receiver status if the link appears to be up */
1612
1581
if (!intel_dp_get_link_status(intel_dp)) {
1613
1582
intel_dp_link_down(intel_dp);
1614
1583
return;
1615
1584
}
1616
1585
1617
-
/* Try to read receiver status if the link appears to be up */
1618
-
ret = intel_dp_aux_native_read(intel_dp,
1619
-
0x000, intel_dp->dpcd,
1620
-
sizeof (intel_dp->dpcd));
1621
-
if (ret != sizeof(intel_dp->dpcd)) {
1586
+
/* Now read the DPCD to see if it's actually running */
1587
+
if (!intel_dp_get_dpcd(intel_dp)) {
1622
1588
intel_dp_link_down(intel_dp);
1623
1589
return;
1624
1590
}
1625
1591
1626
1592
if (!intel_channel_eq_ok(intel_dp)) {
1593
+
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1594
+
drm_get_encoder_name(&intel_dp->base.base));
1627
1595
intel_dp_start_link_train(intel_dp);
1628
1596
intel_dp_complete_link_train(intel_dp);
1629
1597
}
1630
1598
}
1631
1599
1632
1600
static enum drm_connector_status
1601
+
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1602
+
{
1603
+
if (intel_dp_get_dpcd(intel_dp))
1604
+
return connector_status_connected;
1605
+
return connector_status_disconnected;
1606
+
}
1607
+
1608
+
static enum drm_connector_status
1633
1609
ironlake_dp_detect(struct intel_dp *intel_dp)
1634
1610
{
1635
1611
enum drm_connector_status status;
1636
-
bool ret;
1637
1612
1638
1613
/* Can't disconnect eDP, but you can close the lid... */
1639
1614
if (is_edp(intel_dp)) {
···
1651
1610
return status;
1652
1611
}
1653
1612
1654
-
status = connector_status_disconnected;
1655
-
ret = intel_dp_aux_native_read_retry(intel_dp,
1656
-
0x000, intel_dp->dpcd,
1657
-
sizeof (intel_dp->dpcd));
1658
-
if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1659
-
status = connector_status_connected;
1660
-
DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1661
-
intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1662
-
return status;
1613
+
return intel_dp_detect_dpcd(intel_dp);
1663
1614
}
1664
1615
1665
1616
static enum drm_connector_status
···
1659
1626
{
1660
1627
struct drm_device *dev = intel_dp->base.base.dev;
1661
1628
struct drm_i915_private *dev_priv = dev->dev_private;
1662
-
enum drm_connector_status status;
1663
1629
uint32_t temp, bit;
1664
1630
1665
1631
switch (intel_dp->output_reg) {
···
1680
1648
if ((temp & bit) == 0)
1681
1649
return connector_status_disconnected;
1682
1650
1683
-
status = connector_status_disconnected;
1684
-
if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1685
-
sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1686
-
{
1687
-
if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1688
-
status = connector_status_connected;
1689
-
}
1690
-
1691
-
return status;
1651
+
return intel_dp_detect_dpcd(intel_dp);
1692
1652
}
1693
1653
1694
1654
/**
···
1703
1679
status = ironlake_dp_detect(intel_dp);
1704
1680
else
1705
1681
status = g4x_dp_detect(intel_dp);
1682
+
1683
+
DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1684
+
intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1685
+
intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1686
+
intel_dp->dpcd[6], intel_dp->dpcd[7]);
1687
+
1706
1688
if (status != connector_status_connected)
1707
1689
return status;
1708
1690
···
1954
1924
return;
1955
1925
1956
1926
intel_dp->output_reg = output_reg;
1927
+
intel_dp->dpms_mode = -1;
1957
1928
1958
1929
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1959
1930
if (!intel_connector) {
···
2031
2000
2032
2001
/* Cache some DPCD data in the eDP case */
2033
2002
if (is_edp(intel_dp)) {
2034
-
int ret;
2003
+
bool ret;
2035
2004
u32 pp_on, pp_div;
2036
2005
2037
2006
pp_on = I915_READ(PCH_PP_ON_DELAYS);
···
2044
2013
dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2045
2014
2046
2015
ironlake_edp_panel_vdd_on(intel_dp);
2047
-
ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
2048
-
intel_dp->dpcd,
2049
-
sizeof(intel_dp->dpcd));
2016
+
ret = intel_dp_get_dpcd(intel_dp);
2050
2017
ironlake_edp_panel_vdd_off(intel_dp);
2051
-
if (ret == sizeof(intel_dp->dpcd)) {
2018
+
if (ret) {
2052
2019
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2053
2020
dev_priv->no_aux_handshake =
2054
2021
intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+23
drivers/gpu/drm/i915/intel_drv.h
+23
drivers/gpu/drm/i915/intel_drv.h
···
178
178
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
179
179
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
180
180
181
+
#define DIP_HEADER_SIZE 5
182
+
181
183
#define DIP_TYPE_AVI 0x82
182
184
#define DIP_VERSION_AVI 0x2
183
185
#define DIP_LEN_AVI 13
186
+
187
+
#define DIP_TYPE_SPD 0x3
188
+
#define DIP_VERSION_SPD 0x1
189
+
#define DIP_LEN_SPD 25
190
+
#define DIP_SPD_UNKNOWN 0
191
+
#define DIP_SPD_DSTB 0x1
192
+
#define DIP_SPD_DVDP 0x2
193
+
#define DIP_SPD_DVHS 0x3
194
+
#define DIP_SPD_HDDVR 0x4
195
+
#define DIP_SPD_DVC 0x5
196
+
#define DIP_SPD_DSC 0x6
197
+
#define DIP_SPD_VCD 0x7
198
+
#define DIP_SPD_GAME 0x8
199
+
#define DIP_SPD_PC 0x9
200
+
#define DIP_SPD_BD 0xa
201
+
#define DIP_SPD_SCD 0xb
184
202
185
203
struct dip_infoframe {
186
204
uint8_t type; /* HB0 */
···
224
206
uint16_t left_bar_end;
225
207
uint16_t right_bar_start;
226
208
} avi;
209
+
struct {
210
+
uint8_t vn[8];
211
+
uint8_t pd[16];
212
+
uint8_t sdi;
213
+
} spd;
227
214
uint8_t payload[27];
228
215
} __attribute__ ((packed)) body;
229
216
} __attribute__((packed));
+134
-24
drivers/gpu/drm/i915/intel_hdmi.c
+134
-24
drivers/gpu/drm/i915/intel_hdmi.c
···
45
45
bool has_hdmi_sink;
46
46
bool has_audio;
47
47
int force_audio;
48
+
void (*write_infoframe)(struct drm_encoder *encoder,
49
+
struct dip_infoframe *frame);
48
50
};
49
51
50
52
static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
···
60
58
struct intel_hdmi, base);
61
59
}
62
60
63
-
void intel_dip_infoframe_csum(struct dip_infoframe *avi_if)
61
+
void intel_dip_infoframe_csum(struct dip_infoframe *frame)
64
62
{
65
-
uint8_t *data = (uint8_t *)avi_if;
63
+
uint8_t *data = (uint8_t *)frame;
66
64
uint8_t sum = 0;
67
65
unsigned i;
68
66
69
-
avi_if->checksum = 0;
70
-
avi_if->ecc = 0;
67
+
frame->checksum = 0;
68
+
frame->ecc = 0;
71
69
72
-
for (i = 0; i < sizeof(*avi_if); i++)
70
+
/* Header isn't part of the checksum */
71
+
for (i = 5; i < frame->len; i++)
73
72
sum += data[i];
74
73
75
-
avi_if->checksum = 0x100 - sum;
74
+
frame->checksum = 0x100 - sum;
76
75
}
77
76
78
-
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
77
+
static u32 intel_infoframe_index(struct dip_infoframe *frame)
79
78
{
80
-
struct dip_infoframe avi_if = {
81
-
.type = DIP_TYPE_AVI,
82
-
.ver = DIP_VERSION_AVI,
83
-
.len = DIP_LEN_AVI,
84
-
};
85
-
uint32_t *data = (uint32_t *)&avi_if;
79
+
u32 flags = 0;
80
+
81
+
switch (frame->type) {
82
+
case DIP_TYPE_AVI:
83
+
flags |= VIDEO_DIP_SELECT_AVI;
84
+
break;
85
+
case DIP_TYPE_SPD:
86
+
flags |= VIDEO_DIP_SELECT_SPD;
87
+
break;
88
+
default:
89
+
DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
90
+
break;
91
+
}
92
+
93
+
return flags;
94
+
}
95
+
96
+
static u32 intel_infoframe_flags(struct dip_infoframe *frame)
97
+
{
98
+
u32 flags = 0;
99
+
100
+
switch (frame->type) {
101
+
case DIP_TYPE_AVI:
102
+
flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
103
+
break;
104
+
case DIP_TYPE_SPD:
105
+
flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC;
106
+
break;
107
+
default:
108
+
DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
109
+
break;
110
+
}
111
+
112
+
return flags;
113
+
}
114
+
115
+
static void i9xx_write_infoframe(struct drm_encoder *encoder,
116
+
struct dip_infoframe *frame)
117
+
{
118
+
uint32_t *data = (uint32_t *)frame;
86
119
struct drm_device *dev = encoder->dev;
87
120
struct drm_i915_private *dev_priv = dev->dev_private;
88
121
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
89
-
u32 port;
90
-
unsigned i;
122
+
u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
123
+
unsigned i, len = DIP_HEADER_SIZE + frame->len;
91
124
92
-
if (!intel_hdmi->has_hdmi_sink)
93
-
return;
94
125
95
126
/* XXX first guess at handling video port, is this corrent? */
96
127
if (intel_hdmi->sdvox_reg == SDVOB)
···
133
98
else
134
99
return;
135
100
136
-
I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
137
-
VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC);
101
+
flags = intel_infoframe_index(frame);
138
102
139
-
intel_dip_infoframe_csum(&avi_if);
140
-
for (i = 0; i < sizeof(avi_if); i += 4) {
103
+
val &= ~VIDEO_DIP_SELECT_MASK;
104
+
105
+
I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
106
+
107
+
for (i = 0; i < len; i += 4) {
141
108
I915_WRITE(VIDEO_DIP_DATA, *data);
142
109
data++;
143
110
}
144
111
145
-
I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
146
-
VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC |
147
-
VIDEO_DIP_ENABLE_AVI);
112
+
flags |= intel_infoframe_flags(frame);
113
+
114
+
I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
115
+
}
116
+
117
+
static void ironlake_write_infoframe(struct drm_encoder *encoder,
118
+
struct dip_infoframe *frame)
119
+
{
120
+
uint32_t *data = (uint32_t *)frame;
121
+
struct drm_device *dev = encoder->dev;
122
+
struct drm_i915_private *dev_priv = dev->dev_private;
123
+
struct drm_crtc *crtc = encoder->crtc;
124
+
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
125
+
int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
126
+
unsigned i, len = DIP_HEADER_SIZE + frame->len;
127
+
u32 flags, val = I915_READ(reg);
128
+
129
+
intel_wait_for_vblank(dev, intel_crtc->pipe);
130
+
131
+
flags = intel_infoframe_index(frame);
132
+
133
+
val &= ~VIDEO_DIP_SELECT_MASK;
134
+
135
+
I915_WRITE(reg, val | flags);
136
+
137
+
for (i = 0; i < len; i += 4) {
138
+
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
139
+
data++;
140
+
}
141
+
142
+
flags |= intel_infoframe_flags(frame);
143
+
144
+
I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
145
+
}
146
+
static void intel_set_infoframe(struct drm_encoder *encoder,
147
+
struct dip_infoframe *frame)
148
+
{
149
+
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
150
+
151
+
if (!intel_hdmi->has_hdmi_sink)
152
+
return;
153
+
154
+
intel_dip_infoframe_csum(frame);
155
+
intel_hdmi->write_infoframe(encoder, frame);
156
+
}
157
+
158
+
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
159
+
{
160
+
struct dip_infoframe avi_if = {
161
+
.type = DIP_TYPE_AVI,
162
+
.ver = DIP_VERSION_AVI,
163
+
.len = DIP_LEN_AVI,
164
+
};
165
+
166
+
intel_set_infoframe(encoder, &avi_if);
167
+
}
168
+
169
+
static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
170
+
{
171
+
struct dip_infoframe spd_if;
172
+
173
+
memset(&spd_if, 0, sizeof(spd_if));
174
+
spd_if.type = DIP_TYPE_SPD;
175
+
spd_if.ver = DIP_VERSION_SPD;
176
+
spd_if.len = DIP_LEN_SPD;
177
+
strcpy(spd_if.body.spd.vn, "Intel");
178
+
strcpy(spd_if.body.spd.pd, "Integrated gfx");
179
+
spd_if.body.spd.sdi = DIP_SPD_PC;
180
+
181
+
intel_set_infoframe(encoder, &spd_if);
148
182
}
149
183
150
184
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
···
260
156
POSTING_READ(intel_hdmi->sdvox_reg);
261
157
262
158
intel_hdmi_set_avi_infoframe(encoder);
159
+
intel_hdmi_set_spd_infoframe(encoder);
263
160
}
264
161
265
162
static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
···
537
432
}
538
433
539
434
intel_hdmi->sdvox_reg = sdvox_reg;
435
+
436
+
if (!HAS_PCH_SPLIT(dev))
437
+
intel_hdmi->write_infoframe = i9xx_write_infoframe;
438
+
else
439
+
intel_hdmi->write_infoframe = ironlake_write_infoframe;
540
440
541
441
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
542
442
+8
drivers/gpu/drm/i915/intel_lvds.c
+8
drivers/gpu/drm/i915/intel_lvds.c
···
690
690
},
691
691
{
692
692
.callback = intel_no_lvds_dmi_callback,
693
+
.ident = "Dell OptiPlex FX170",
694
+
.matches = {
695
+
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
696
+
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
697
+
},
698
+
},
699
+
{
700
+
.callback = intel_no_lvds_dmi_callback,
693
701
.ident = "AOpen Mini PC",
694
702
.matches = {
695
703
DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
+4
drivers/gpu/drm/i915/intel_panel.c
+4
drivers/gpu/drm/i915/intel_panel.c
···
83
83
u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
84
84
if (scaled_width > scaled_height) { /* pillar */
85
85
width = scaled_height / mode->vdisplay;
86
+
if (width & 1)
87
+
width++;
86
88
x = (adjusted_mode->hdisplay - width + 1) / 2;
87
89
y = 0;
88
90
height = adjusted_mode->vdisplay;
89
91
} else if (scaled_width < scaled_height) { /* letter */
90
92
height = scaled_width / mode->hdisplay;
93
+
if (height & 1)
94
+
height++;
91
95
y = (adjusted_mode->vdisplay - height + 1) / 2;
92
96
x = 0;
93
97
width = adjusted_mode->hdisplay;
+3
drivers/gpu/drm/i915/intel_ringbuffer.c
+3
drivers/gpu/drm/i915/intel_ringbuffer.c
···
1321
1321
ring->get_seqno = pc_render_get_seqno;
1322
1322
}
1323
1323
1324
+
if (!I915_NEED_GFX_HWS(dev))
1325
+
ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1326
+
1324
1327
ring->dev = dev;
1325
1328
INIT_LIST_HEAD(&ring->active_list);
1326
1329
INIT_LIST_HEAD(&ring->request_list);
+1
drivers/gpu/drm/radeon/Makefile
+1
drivers/gpu/drm/radeon/Makefile
···
5
5
ccflags-y := -Iinclude/drm
6
6
7
7
hostprogs-y := mkregtable
8
+
clean-files := rn50_reg_safe.h r100_reg_safe.h r200_reg_safe.h rv515_reg_safe.h r300_reg_safe.h r420_reg_safe.h rs600_reg_safe.h r600_reg_safe.h evergreen_reg_safe.h cayman_reg_safe.h
8
9
9
10
quiet_cmd_mkregtable = MKREGTABLE $@
10
11
cmd_mkregtable = $(obj)/mkregtable $< > $@
+3
drivers/gpu/drm/radeon/atom.c
+3
drivers/gpu/drm/radeon/atom.c
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
+1
-2
drivers/gpu/drm/radeon/r600_cs.c
+1
-2
drivers/gpu/drm/radeon/r600_cs.c
···
915
915
{
916
916
struct r600_cs_track *track = (struct r600_cs_track *)p->track;
917
917
struct radeon_cs_reloc *reloc;
918
-
u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
919
918
u32 m, i, tmp, *ib;
920
919
int r;
921
920
922
921
i = (reg >> 7);
923
-
if (i > last_reg) {
922
+
if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
924
923
dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
925
924
return -EINVAL;
926
925
}
+20
-1
drivers/gpu/drm/radeon/radeon_combios.c
+20
-1
drivers/gpu/drm/radeon/radeon_combios.c
···
2557
2557
u16 offset, misc, misc2 = 0;
2558
2558
u8 rev, blocks, tmp;
2559
2559
int state_index = 0;
2560
+
struct radeon_i2c_bus_rec i2c_bus;
2560
2561
2561
2562
rdev->pm.default_power_state_index = -1;
2562
2563
···
2576
2575
offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2577
2576
if (offset) {
2578
2577
u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2579
-
struct radeon_i2c_bus_rec i2c_bus;
2580
2578
2581
2579
rev = RBIOS8(offset);
2582
2580
···
2615
2615
info.addr = i2c_addr >> 1;
2616
2616
strlcpy(info.type, name, sizeof(info.type));
2617
2617
i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2618
+
}
2619
+
}
2620
+
} else {
2621
+
/* boards with a thermal chip, but no overdrive table */
2622
+
2623
+
/* Asus 9600xt has an f75375 on the monid bus */
2624
+
if ((dev->pdev->device == 0x4152) &&
2625
+
(dev->pdev->subsystem_vendor == 0x1043) &&
2626
+
(dev->pdev->subsystem_device == 0xc002)) {
2627
+
i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2628
+
rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2629
+
if (rdev->pm.i2c_bus) {
2630
+
struct i2c_board_info info = { };
2631
+
const char *name = "f75375";
2632
+
info.addr = 0x28;
2633
+
strlcpy(info.type, name, sizeof(info.type));
2634
+
i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2635
+
DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2636
+
name, info.addr);
2618
2637
}
2619
2638
}
2620
2639
}
+51
-3
drivers/gpu/drm/radeon/radeon_connectors.c
+51
-3
drivers/gpu/drm/radeon/radeon_connectors.c
···
430
430
return 0;
431
431
}
432
432
433
+
/*
434
+
* Some integrated ATI Radeon chipset implementations (e. g.
435
+
* Asus M2A-VM HDMI) may indicate the availability of a DDC,
436
+
* even when there's no monitor connected. For these connectors
437
+
* following DDC probe extension will be applied: check also for the
438
+
* availability of EDID with at least a correct EDID header. Only then,
439
+
* DDC is assumed to be available. This prevents drm_get_edid() and
440
+
* drm_edid_block_valid() from periodically dumping data and kernel
441
+
* errors into the logs and onto the terminal.
442
+
*/
443
+
static bool radeon_connector_needs_extended_probe(struct radeon_device *dev,
444
+
uint32_t supported_device,
445
+
int connector_type)
446
+
{
447
+
/* Asus M2A-VM HDMI board sends data to i2c bus even,
448
+
* if HDMI add-on card is not plugged in or HDMI is disabled in
449
+
* BIOS. Valid DDC can only be assumed, if also a valid EDID header
450
+
* can be retrieved via i2c bus during DDC probe */
451
+
if ((dev->pdev->device == 0x791e) &&
452
+
(dev->pdev->subsystem_vendor == 0x1043) &&
453
+
(dev->pdev->subsystem_device == 0x826d)) {
454
+
if ((connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
455
+
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
456
+
return true;
457
+
}
458
+
/* ECS A740GM-M with ATI RADEON 2100 sends data to i2c bus
459
+
* for a DVI connector that is not implemented */
460
+
if ((dev->pdev->device == 0x796e) &&
461
+
(dev->pdev->subsystem_vendor == 0x1019) &&
462
+
(dev->pdev->subsystem_device == 0x2615)) {
463
+
if ((connector_type == DRM_MODE_CONNECTOR_DVID) &&
464
+
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
465
+
return true;
466
+
}
467
+
468
+
/* Default: no EDID header probe required for DDC probing */
469
+
return false;
470
+
}
471
+
433
472
static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
434
473
struct drm_connector *connector)
435
474
{
···
700
661
ret = connector_status_disconnected;
701
662
702
663
if (radeon_connector->ddc_bus)
703
-
dret = radeon_ddc_probe(radeon_connector);
664
+
dret = radeon_ddc_probe(radeon_connector,
665
+
radeon_connector->requires_extended_probe);
704
666
if (dret) {
705
667
if (radeon_connector->edid) {
706
668
kfree(radeon_connector->edid);
···
873
833
bool dret = false;
874
834
875
835
if (radeon_connector->ddc_bus)
876
-
dret = radeon_ddc_probe(radeon_connector);
836
+
dret = radeon_ddc_probe(radeon_connector,
837
+
radeon_connector->requires_extended_probe);
877
838
if (dret) {
878
839
if (radeon_connector->edid) {
879
840
kfree(radeon_connector->edid);
···
1292
1251
if (radeon_dp_getdpcd(radeon_connector))
1293
1252
ret = connector_status_connected;
1294
1253
} else {
1295
-
if (radeon_ddc_probe(radeon_connector))
1254
+
if (radeon_ddc_probe(radeon_connector,
1255
+
radeon_connector->requires_extended_probe))
1296
1256
ret = connector_status_connected;
1297
1257
}
1298
1258
}
···
1448
1406
radeon_connector->shared_ddc = shared_ddc;
1449
1407
radeon_connector->connector_object_id = connector_object_id;
1450
1408
radeon_connector->hpd = *hpd;
1409
+
radeon_connector->requires_extended_probe =
1410
+
radeon_connector_needs_extended_probe(rdev, supported_device,
1411
+
connector_type);
1451
1412
radeon_connector->router = *router;
1452
1413
if (router->ddc_valid || router->cd_valid) {
1453
1414
radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
···
1797
1752
radeon_connector->devices = supported_device;
1798
1753
radeon_connector->connector_object_id = connector_object_id;
1799
1754
radeon_connector->hpd = *hpd;
1755
+
radeon_connector->requires_extended_probe =
1756
+
radeon_connector_needs_extended_probe(rdev, supported_device,
1757
+
connector_type);
1800
1758
switch (connector_type) {
1801
1759
case DRM_MODE_CONNECTOR_VGA:
1802
1760
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+3
-2
drivers/gpu/drm/radeon/radeon_device.c
+3
-2
drivers/gpu/drm/radeon/radeon_device.c
···
704
704
rdev->gpu_lockup = false;
705
705
rdev->accel_working = false;
706
706
707
-
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
708
-
radeon_family_name[rdev->family], pdev->vendor, pdev->device);
707
+
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
708
+
radeon_family_name[rdev->family], pdev->vendor, pdev->device,
709
+
pdev->subsystem_vendor, pdev->subsystem_device);
709
710
710
711
/* mutex initialization are all done here so we
711
712
* can recall function without having locking issues */
+9
drivers/gpu/drm/radeon/radeon_display.c
+9
drivers/gpu/drm/radeon/radeon_display.c
···
751
751
if (!radeon_connector->ddc_bus)
752
752
return -1;
753
753
edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
754
+
/* Log EDID retrieval status here. In particular with regard to
755
+
* connectors with requires_extended_probe flag set, that will prevent
756
+
* function radeon_dvi_detect() to fetch EDID on this connector,
757
+
* as long as there is no valid EDID header found */
754
758
if (edid) {
759
+
DRM_INFO("Radeon display connector %s: Found valid EDID",
760
+
drm_get_connector_name(connector));
755
761
kfree(edid);
762
+
} else {
763
+
DRM_INFO("Radeon display connector %s: No monitor connected or invalid EDID",
764
+
drm_get_connector_name(connector));
756
765
}
757
766
return ret;
758
767
}
+2
-2
drivers/gpu/drm/radeon/radeon_drv.c
+2
-2
drivers/gpu/drm/radeon/radeon_drv.c
···
50
50
* 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
51
51
* 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
52
52
* 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
53
-
* 2.10.0 - fusion 2D tiling, initial compute support for the CS checker
54
-
* 2.11.0 - backend map
53
+
* 2.10.0 - fusion 2D tiling
54
+
* 2.11.0 - backend map, initial compute support for the CS checker
55
55
*/
56
56
#define KMS_DRIVER_MAJOR 2
57
57
#define KMS_DRIVER_MINOR 11
+24
-8
drivers/gpu/drm/radeon/radeon_i2c.c
+24
-8
drivers/gpu/drm/radeon/radeon_i2c.c
···
32
32
* radeon_ddc_probe
33
33
*
34
34
*/
35
-
bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
35
+
bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe)
36
36
{
37
-
u8 out_buf[] = { 0x0, 0x0};
38
-
u8 buf[2];
37
+
u8 out = 0x0;
38
+
u8 buf[8];
39
39
int ret;
40
40
struct i2c_msg msgs[] = {
41
41
{
42
42
.addr = 0x50,
43
43
.flags = 0,
44
44
.len = 1,
45
-
.buf = out_buf,
45
+
.buf = &out,
46
46
},
47
47
{
48
48
.addr = 0x50,
···
52
52
}
53
53
};
54
54
55
+
/* Read 8 bytes from i2c for extended probe of EDID header */
56
+
if (requires_extended_probe)
57
+
msgs[1].len = 8;
58
+
55
59
/* on hw with routers, select right port */
56
60
if (radeon_connector->router.ddc_valid)
57
61
radeon_router_select_ddc_port(radeon_connector);
58
62
59
63
ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
60
-
if (ret == 2)
61
-
return true;
62
-
63
-
return false;
64
+
if (ret != 2)
65
+
/* Couldn't find an accessible DDC on this connector */
66
+
return false;
67
+
if (requires_extended_probe) {
68
+
/* Probe also for valid EDID header
69
+
* EDID header starts with:
70
+
* 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
71
+
* Only the first 6 bytes must be valid as
72
+
* drm_edid_block_valid() can fix the last 2 bytes */
73
+
if (drm_edid_header_is_valid(buf) < 6) {
74
+
/* Couldn't find an accessible EDID on this
75
+
* connector */
76
+
return false;
77
+
}
78
+
}
79
+
return true;
64
80
}
65
81
66
82
/* bit banging i2c */
+5
-1
drivers/gpu/drm/radeon/radeon_mode.h
+5
-1
drivers/gpu/drm/radeon/radeon_mode.h
···
438
438
struct radeon_i2c_chan *ddc_bus;
439
439
/* some systems have an hdmi and vga port with a shared ddc line */
440
440
bool shared_ddc;
441
+
/* for some Radeon chip families we apply an additional EDID header
442
+
check as part of the DDC probe */
443
+
bool requires_extended_probe;
441
444
bool use_digital;
442
445
/* we need to mind the EDID between detect
443
446
and get modes due to analog/digital/tvencoder */
···
517
514
u8 val);
518
515
extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
519
516
extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
520
-
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
517
+
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector,
518
+
bool requires_extended_probe);
521
519
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
522
520
523
521
extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
+3
include/drm/drm_crtc.h
+3
include/drm/drm_crtc.h
···
205
205
enum subpixel_order subpixel_order;
206
206
u32 color_formats;
207
207
208
+
u8 cea_rev;
209
+
208
210
char *raw_edid; /* if any */
209
211
};
210
212
···
804
802
extern int drm_add_modes_noedid(struct drm_connector *connector,
805
803
int hdisplay, int vdisplay);
806
804
805
+
extern int drm_edid_header_is_valid(const u8 *raw_edid);
807
806
extern bool drm_edid_is_valid(struct edid *edid);
808
807
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
809
808
int hsize, int vsize, int fresh);
+1
-1
include/drm/i915_drm.h
+1
-1
include/drm/i915_drm.h
···
237
237
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
238
238
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
239
239
#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
240
-
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
240
+
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
241
241
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
242
242
243
243
/* Allow drivers to submit batchbuffers directly to hardware, relying