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arm64: Provide basic EL2 setup for FEAT_{LS64, LS64_V} usage at EL0/1

Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.

This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor still have the control at
runtime.

Acked-by: Will Deacon <will@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Will Deacon <will@kernel.org>

authored by

Yicong Yang and committed by
Will Deacon dea58da4 2937aeec

+11 -1
+11 -1
arch/arm64/include/asm/el2_setup.h
··· 83 83 /* Enable GCS if supported */ 84 84 mrs_s x1, SYS_ID_AA64PFR1_EL1 85 85 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 86 - cbz x1, .Lset_hcrx_\@ 86 + cbz x1, .Lskip_gcs_hcrx_\@ 87 87 orr x0, x0, #HCRX_EL2_GCSEn 88 + 89 + .Lskip_gcs_hcrx_\@: 90 + /* Enable LS64, LS64_V if supported */ 91 + mrs_s x1, SYS_ID_AA64ISAR1_EL1 92 + ubfx x1, x1, #ID_AA64ISAR1_EL1_LS64_SHIFT, #4 93 + cbz x1, .Lset_hcrx_\@ 94 + orr x0, x0, #HCRX_EL2_EnALS 95 + cmp x1, #ID_AA64ISAR1_EL1_LS64_LS64_V 96 + b.lt .Lset_hcrx_\@ 97 + orr x0, x0, #HCRX_EL2_EnASR 88 98 89 99 .Lset_hcrx_\@: 90 100 msr_s SYS_HCRX_EL2, x0