Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
"Nothing that really stands out, just a bunch of fixes that have come
in in the last couple of weeks.
None of these are actually fixes for code that is new in 4.13. It's
roughly half older bugs, with fixes going to stable, and half
fixes/updates for Power9.
Thanks to: Aneesh Kumar K.V, Anton Blanchard, Balbir Singh, Benjamin
Herrenschmidt, Madhavan Srinivasan, Michael Neuling, Nicholas Piggin,
Oliver O'Halloran"
* tag 'powerpc-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/64: Fix atomic64_inc_not_zero() to return an int
powerpc: Fix emulation of mfocrf in emulate_step()
powerpc: Fix emulation of mcrf in emulate_step()
powerpc/perf: Add POWER9 alternate PM_RUN_CYC and PM_RUN_INST_CMPL events
powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9
powerpc/asm: Mark cr0 as clobbered in mftb()
powerpc/powernv: Fix local TLB flush for boot and MCE on POWER9
powerpc/mm/radix: Synchronize updates to the process table
powerpc/mm/radix: Properly clear process table entry
powerpc/powernv: Tell OPAL about our MMU mode on POWER9
powerpc/kexec: Fix radix to hash kexec due to IAMR/AMOR
+162
-31
+2
-2
arch/powerpc/include/asm/atomic.h
+2
-2
arch/powerpc/include/asm/atomic.h
···
560
560
* Atomically increments @v by 1, so long as @v is non-zero.
561
561
* Returns non-zero if @v was non-zero, and zero otherwise.
562
562
*/
563
-
static __inline__ long atomic64_inc_not_zero(atomic64_t *v)
563
+
static __inline__ int atomic64_inc_not_zero(atomic64_t *v)
564
564
{
565
565
long t1, t2;
566
566
···
579
579
: "r" (&v->counter)
580
580
: "cc", "xer", "memory");
581
581
582
-
return t1;
582
+
return t1 != 0;
583
583
}
584
584
585
585
#endif /* __powerpc64__ */
+9
arch/powerpc/include/asm/opal-api.h
+9
arch/powerpc/include/asm/opal-api.h
···
876
876
enum {
877
877
OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
878
878
OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
879
+
880
+
/* These two define the base MMU mode of the host on P9
881
+
*
882
+
* On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
883
+
* create hash guests in "radix" mode with care (full core
884
+
* switch only).
885
+
*/
886
+
OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
887
+
OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
879
888
};
880
889
881
890
typedef struct oppanel_line {
+1
-1
arch/powerpc/include/asm/reg.h
+1
-1
arch/powerpc/include/asm/reg.h
+10
-3
arch/powerpc/kernel/cpu_setup_power.S
+10
-3
arch/powerpc/kernel/cpu_setup_power.S
···
218
218
ptesync
219
219
1: blr
220
220
221
+
/*
222
+
* Flush the TLB in hash mode. Hash must flush with RIC=2 once for process
223
+
* and one for partition scope to clear process and partition table entries.
224
+
*/
221
225
__init_tlb_power9:
222
-
li r6,POWER9_TLB_SETS_HASH
226
+
li r6,POWER9_TLB_SETS_HASH - 1
223
227
mtctr r6
224
228
li r7,0xc00 /* IS field = 0b11 */
229
+
li r8,0
225
230
ptesync
226
-
2: tlbiel r7
227
-
addi r7,r7,0x1000
231
+
PPC_TLBIEL(7, 8, 2, 1, 0)
232
+
PPC_TLBIEL(7, 8, 2, 0, 0)
233
+
2: addi r7,r7,0x1000
234
+
PPC_TLBIEL(7, 8, 0, 0, 0)
228
235
bdnz 2b
229
236
ptesync
230
237
1: blr
+2
-14
arch/powerpc/kernel/dt_cpu_ftrs.c
+2
-14
arch/powerpc/kernel/dt_cpu_ftrs.c
···
94
94
95
95
static void cpufeatures_flush_tlb(void)
96
96
{
97
-
unsigned long rb;
98
-
unsigned int i, num_sets;
99
-
100
97
/*
101
98
* This is a temporary measure to keep equivalent TLB flush as the
102
99
* cputable based setup code.
···
102
105
case PVR_POWER8:
103
106
case PVR_POWER8E:
104
107
case PVR_POWER8NVL:
105
-
num_sets = POWER8_TLB_SETS;
108
+
__flush_tlb_power8(POWER8_TLB_SETS);
106
109
break;
107
110
case PVR_POWER9:
108
-
num_sets = POWER9_TLB_SETS_HASH;
111
+
__flush_tlb_power9(POWER9_TLB_SETS_HASH);
109
112
break;
110
113
default:
111
-
num_sets = 1;
112
114
pr_err("unknown CPU version for boot TLB flush\n");
113
115
break;
114
116
}
115
-
116
-
asm volatile("ptesync" : : : "memory");
117
-
rb = TLBIEL_INVAL_SET;
118
-
for (i = 0; i < num_sets; i++) {
119
-
asm volatile("tlbiel %0" : : "r" (rb));
120
-
rb += 1 << TLBIEL_INVAL_SET_SHIFT;
121
-
}
122
-
asm volatile("ptesync" : : : "memory");
123
117
}
124
118
125
119
static void __restore_cpu_cpufeatures(void)
+55
-1
arch/powerpc/kernel/mce_power.c
+55
-1
arch/powerpc/kernel/mce_power.c
···
53
53
asm volatile("ptesync" : : : "memory");
54
54
}
55
55
56
+
static void flush_tlb_300(unsigned int num_sets, unsigned int action)
57
+
{
58
+
unsigned long rb;
59
+
unsigned int i;
60
+
unsigned int r;
61
+
62
+
switch (action) {
63
+
case TLB_INVAL_SCOPE_GLOBAL:
64
+
rb = TLBIEL_INVAL_SET;
65
+
break;
66
+
case TLB_INVAL_SCOPE_LPID:
67
+
rb = TLBIEL_INVAL_SET_LPID;
68
+
break;
69
+
default:
70
+
BUG();
71
+
break;
72
+
}
73
+
74
+
asm volatile("ptesync" : : : "memory");
75
+
76
+
if (early_radix_enabled())
77
+
r = 1;
78
+
else
79
+
r = 0;
80
+
81
+
/*
82
+
* First flush table/PWC caches with set 0, then flush the
83
+
* rest of the sets, partition scope. Radix must then do it
84
+
* all again with process scope. Hash just has to flush
85
+
* process table.
86
+
*/
87
+
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) : :
88
+
"r"(rb), "r"(0), "i"(2), "i"(0), "r"(r));
89
+
for (i = 1; i < num_sets; i++) {
90
+
unsigned long set = i * (1<<TLBIEL_INVAL_SET_SHIFT);
91
+
92
+
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) : :
93
+
"r"(rb+set), "r"(0), "i"(2), "i"(0), "r"(r));
94
+
}
95
+
96
+
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) : :
97
+
"r"(rb), "r"(0), "i"(2), "i"(1), "r"(r));
98
+
if (early_radix_enabled()) {
99
+
for (i = 1; i < num_sets; i++) {
100
+
unsigned long set = i * (1<<TLBIEL_INVAL_SET_SHIFT);
101
+
102
+
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) : :
103
+
"r"(rb+set), "r"(0), "i"(2), "i"(1), "r"(r));
104
+
}
105
+
}
106
+
107
+
asm volatile("ptesync" : : : "memory");
108
+
}
109
+
56
110
/*
57
111
* Generic routines to flush TLB on POWER processors. These routines
58
112
* are used as flush_tlb hook in the cpu_spec.
···
133
79
else
134
80
num_sets = POWER9_TLB_SETS_HASH;
135
81
136
-
flush_tlb_206(num_sets, action);
82
+
flush_tlb_300(num_sets, action);
137
83
}
138
84
139
85
+12
arch/powerpc/kernel/misc_64.S
+12
arch/powerpc/kernel/misc_64.S
···
614
614
li r0,0
615
615
std r0,16(r1)
616
616
617
+
BEGIN_FTR_SECTION
618
+
/*
619
+
* This is the best time to turn AMR/IAMR off.
620
+
* key 0 is used in radix for supervisor<->user
621
+
* protection, but on hash key 0 is reserved
622
+
* ideally we want to enter with a clean state.
623
+
* NOTE, we rely on r0 being 0 from above.
624
+
*/
625
+
mtspr SPRN_IAMR,r0
626
+
mtspr SPRN_AMOR,r0
627
+
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
628
+
617
629
/* save regs for local vars on new stack.
618
630
* yes, we won't go back, but ...
619
631
*/
+17
-2
arch/powerpc/lib/sstep.c
+17
-2
arch/powerpc/lib/sstep.c
···
683
683
case 19:
684
684
switch ((instr >> 1) & 0x3ff) {
685
685
case 0: /* mcrf */
686
-
rd = (instr >> 21) & 0x1c;
687
-
ra = (instr >> 16) & 0x1c;
686
+
rd = 7 - ((instr >> 23) & 0x7);
687
+
ra = 7 - ((instr >> 18) & 0x7);
688
+
rd *= 4;
689
+
ra *= 4;
688
690
val = (regs->ccr >> ra) & 0xf;
689
691
regs->ccr = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
690
692
goto instr_done;
···
966
964
#endif
967
965
968
966
case 19: /* mfcr */
967
+
if ((instr >> 20) & 1) {
968
+
imm = 0xf0000000UL;
969
+
for (sh = 0; sh < 8; ++sh) {
970
+
if (instr & (0x80000 >> sh)) {
971
+
regs->gpr[rd] = regs->ccr & imm;
972
+
break;
973
+
}
974
+
imm >>= 4;
975
+
}
976
+
977
+
goto instr_done;
978
+
}
979
+
969
980
regs->gpr[rd] = regs->ccr;
970
981
regs->gpr[rd] &= 0xffffffffUL;
971
982
goto instr_done;
+17
-3
arch/powerpc/mm/mmu_context_book3s64.c
+17
-3
arch/powerpc/mm/mmu_context_book3s64.c
···
138
138
rts_field = radix__get_tree_size();
139
139
process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE);
140
140
141
+
/*
142
+
* Order the above store with subsequent update of the PID
143
+
* register (at which point HW can start loading/caching
144
+
* the entry) and the corresponding load by the MMU from
145
+
* the L2 cache.
146
+
*/
147
+
asm volatile("ptesync;isync" : : : "memory");
148
+
141
149
mm->context.npu_context = NULL;
142
150
143
151
return index;
···
231
223
mm->context.cop_lockp = NULL;
232
224
#endif /* CONFIG_PPC_ICSWX */
233
225
234
-
if (radix_enabled())
235
-
process_tb[mm->context.id].prtb1 = 0;
236
-
else
226
+
if (radix_enabled()) {
227
+
/*
228
+
* Radix doesn't have a valid bit in the process table
229
+
* entries. However we know that at least P9 implementation
230
+
* will avoid caching an entry with an invalid RTS field,
231
+
* and 0 is invalid. So this will do.
232
+
*/
233
+
process_tb[mm->context.id].prtb0 = 0;
234
+
} else
237
235
subpage_prot_free(mm);
238
236
destroy_pagetable_page(mm);
239
237
__destroy_context(mm->context.id);
+4
-2
arch/powerpc/perf/isa207-common.c
+4
-2
arch/powerpc/perf/isa207-common.c
···
90
90
* MMCRA[SDAR_MODE] will be set to 0b01
91
91
* For rest
92
92
* MMCRA[SDAR_MODE] will be set from event code.
93
+
* If sdar_mode from event is zero, default to 0b01. Hardware
94
+
* requires that we set a non-zero value.
93
95
*/
94
96
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
95
97
if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
96
98
*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
97
-
else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
99
+
else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
98
100
*mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
99
-
else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
101
+
else
100
102
*mmcra |= MMCRA_SDAR_MODE_TLB;
101
103
} else
102
104
*mmcra |= MMCRA_SDAR_MODE_TLB;
+4
arch/powerpc/perf/power9-events-list.h
+4
arch/powerpc/perf/power9-events-list.h
···
51
51
EVENT(PM_ITLB_MISS, 0x400fc)
52
52
/* Run_Instructions */
53
53
EVENT(PM_RUN_INST_CMPL, 0x500fa)
54
+
/* Alternate event code for PM_RUN_INST_CMPL */
55
+
EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa)
54
56
/* Run_cycles */
55
57
EVENT(PM_RUN_CYC, 0x600f4)
58
+
/* Alternate event code for Run_cycles */
59
+
EVENT(PM_RUN_CYC_ALT, 0x200f4)
56
60
/* Instruction Dispatched */
57
61
EVENT(PM_INST_DISP, 0x200f2)
58
62
EVENT(PM_INST_DISP_ALT, 0x300f2)
+2
arch/powerpc/perf/power9-pmu.c
+2
arch/powerpc/perf/power9-pmu.c
···
107
107
/* Table of alternatives, sorted by column 0 */
108
108
static const unsigned int power9_event_alternatives[][MAX_ALT] = {
109
109
{ PM_INST_DISP, PM_INST_DISP_ALT },
110
+
{ PM_RUN_CYC_ALT, PM_RUN_CYC },
111
+
{ PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
110
112
};
111
113
112
114
static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+17
-2
arch/powerpc/platforms/powernv/opal.c
+17
-2
arch/powerpc/platforms/powernv/opal.c
···
59
59
60
60
void opal_configure_cores(void)
61
61
{
62
+
u64 reinit_flags = 0;
63
+
62
64
/* Do the actual re-init, This will clobber all FPRs, VRs, etc...
63
65
*
64
66
* It will preserve non volatile GPRs and HSPRG0/1. It will
···
68
66
* but it might clobber a bunch.
69
67
*/
70
68
#ifdef __BIG_ENDIAN__
71
-
opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
69
+
reinit_flags |= OPAL_REINIT_CPUS_HILE_BE;
72
70
#else
73
-
opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_LE);
71
+
reinit_flags |= OPAL_REINIT_CPUS_HILE_LE;
74
72
#endif
73
+
74
+
/*
75
+
* POWER9 always support running hash:
76
+
* ie. Host hash supports hash guests
77
+
* Host radix supports hash/radix guests
78
+
*/
79
+
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
80
+
reinit_flags |= OPAL_REINIT_CPUS_MMU_HASH;
81
+
if (early_radix_enabled())
82
+
reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX;
83
+
}
84
+
85
+
opal_reinit_cpus(reinit_flags);
75
86
76
87
/* Restore some bits */
77
88
if (cur_cpu_spec->cpu_restore)
+10
-1
arch/powerpc/platforms/powernv/setup.c
+10
-1
arch/powerpc/platforms/powernv/setup.c
···
225
225
226
226
static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
227
227
{
228
+
u64 reinit_flags;
229
+
228
230
if (xive_enabled())
229
231
xive_kexec_teardown_cpu(secondary);
230
232
else
···
256
254
* We might be running as little-endian - now that interrupts
257
255
* are disabled, reset the HILE bit to big-endian so we don't
258
256
* take interrupts in the wrong endian later
257
+
*
258
+
* We reinit to enable both radix and hash on P9 to ensure
259
+
* the mode used by the next kernel is always supported.
259
260
*/
260
-
opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
261
+
reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
262
+
if (cpu_has_feature(CPU_FTR_ARCH_300))
263
+
reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
264
+
OPAL_REINIT_CPUS_MMU_HASH;
265
+
opal_reinit_cpus(reinit_flags);
261
266
}
262
267
}
263
268
#endif /* CONFIG_KEXEC_CORE */