drm/amdgpu: add multi-xcc support to amdgpu_gfx interfaces (v4)

+42 -33

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 267 267 } 268 268 269 269 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 270 - struct amdgpu_ring *ring) 270 + struct amdgpu_ring *ring, int xcc_id) 271 271 { 272 272 int queue_bit; 273 273 int mec, pipe, queue; ··· 277 277 * adev->gfx.mec.num_queue_per_pipe; 278 278 279 279 while (--queue_bit >= 0) { 280 - if (test_bit(queue_bit, adev->gfx.mec_bitmap[0].queue_bitmap)) 280 + if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) 281 281 continue; 282 282 283 283 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); ··· 303 303 304 304 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 305 305 struct amdgpu_ring *ring, 306 - struct amdgpu_irq_src *irq) 306 + struct amdgpu_irq_src *irq, int xcc_id) 307 307 { 308 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 308 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 309 309 int r = 0; 310 310 311 311 spin_lock_init(&kiq->ring_lock); ··· 314 314 ring->ring_obj = NULL; 315 315 ring->use_doorbell = true; 316 316 ring->doorbell_index = adev->doorbell_index.kiq; 317 + ring->xcc_id = xcc_id; 317 318 ring->vm_hub = AMDGPU_GFXHUB_0; 318 319 319 - r = amdgpu_gfx_kiq_acquire(adev, ring); 320 + r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); 320 321 if (r) 321 322 return r; 322 323 323 324 ring->eop_gpu_addr = kiq->eop_gpu_addr; 324 325 ring->no_scheduler = true; 325 - sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); 326 + sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue); 326 327 r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, 327 328 AMDGPU_RING_PRIO_DEFAULT, NULL); 328 329 if (r) ··· 337 336 amdgpu_ring_fini(ring); 338 337 } 339 338 340 - void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) 339 + void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id) 341 340 { 342 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 341 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 343 342 344 343 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 345 344 } 346 345 347 346 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 348 - unsigned hpd_size) 347 + unsigned hpd_size, int xcc_id) 349 348 { 350 349 int r; 351 350 u32 *hpd; 352 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 351 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 353 352 354 353 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, 355 354 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, ··· 372 371 373 372 /* create MQD for each compute/gfx queue */ 374 373 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 375 - unsigned mqd_size) 374 + unsigned mqd_size, int xcc_id) 376 375 { 377 - struct amdgpu_ring *ring = NULL; 378 376 int r, i; 377 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 378 + struct amdgpu_ring *ring = &kiq->ring; 379 379 380 380 /* create MQD for KIQ */ 381 - ring = &adev->gfx.kiq[0].ring; 382 381 if (!adev->enable_mes_kiq && !ring->mqd_obj) { 383 382 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must 384 383 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD ··· 397 396 } 398 397 399 398 /* prepare MQD backup */ 400 - adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); 401 - if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) 399 + kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL); 400 + if (!kiq->mqd_backup) 402 401 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 403 402 } 404 403 ··· 425 424 426 425 /* create MQD for each KCQ */ 427 426 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 428 - ring = &adev->gfx.compute_ring[i]; 427 + ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 429 428 if (!ring->mqd_obj) { 430 429 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 431 430 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, ··· 436 435 } 437 436 438 437 /* prepare MQD backup */ 439 - adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 438 + adev->gfx.mec.mqd_backup[i + xcc_id * adev->gfx.num_compute_rings] = kmalloc(mqd_size, GFP_KERNEL); 440 439 if (!adev->gfx.mec.mqd_backup[i]) 441 440 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 442 441 } ··· 445 444 return 0; 446 445 } 447 446 448 - void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev) 447 + void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id) 449 448 { 450 449 struct amdgpu_ring *ring = NULL; 451 - int i; 450 + int i, j; 451 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 452 452 453 453 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 454 454 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ··· 462 460 } 463 461 464 462 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 463 + j = i + xcc_id * adev->gfx.num_compute_rings; 465 464 ring = &adev->gfx.compute_ring[i]; 466 465 kfree(adev->gfx.mec.mqd_backup[i]); 467 466 amdgpu_bo_free_kernel(&ring->mqd_obj, ··· 470 467 &ring->mqd_ptr); 471 468 } 472 469 473 - ring = &adev->gfx.kiq[0].ring; 470 + ring = &kiq->ring; 471 + kfree(kiq->mqd_backup); 474 472 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); 475 473 amdgpu_bo_free_kernel(&ring->mqd_obj, 476 474 &ring->mqd_gpu_addr, 477 475 &ring->mqd_ptr); 478 476 } 479 477 480 - int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) 478 + int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) 481 479 { 482 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 480 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 483 481 struct amdgpu_ring *kiq_ring = &kiq->ring; 484 482 int i, r = 0; 483 + int j; 485 484 486 485 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 487 486 return -EINVAL; 488 487 489 - spin_lock(&adev->gfx.kiq[0].ring_lock); 488 + spin_lock(&kiq->ring_lock); 490 489 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 491 490 adev->gfx.num_compute_rings)) { 492 491 spin_unlock(&adev->gfx.kiq[0].ring_lock); 493 492 return -ENOMEM; 494 493 } 495 494 496 - for (i = 0; i < adev->gfx.num_compute_rings; i++) 495 + for (i = 0; i < adev->gfx.num_compute_rings; i++) { 496 + j = i + xcc_id * adev->gfx.num_compute_rings; 497 497 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], 498 498 RESET_QUEUES, 0, 0); 499 + } 499 500 500 501 if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang) 501 502 r = amdgpu_ring_test_helper(kiq_ring); 502 - spin_unlock(&adev->gfx.kiq[0].ring_lock); 503 + spin_unlock(&kiq->ring_lock); 503 504 504 505 return r; 505 506 } ··· 521 514 return set_resource_bit; 522 515 } 523 516 524 - int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) 517 + int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) 525 518 { 526 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 527 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 519 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 520 + struct amdgpu_ring *kiq_ring = &kiq->ring; 528 521 uint64_t queue_mask = 0; 529 - int r, i; 522 + int r, i, j; 530 523 531 524 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources) 532 525 return -EINVAL; 533 526 534 527 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 535 - if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap)) 528 + if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) 536 529 continue; 537 530 538 531 /* This situation may be hit in the future if a new HW ··· 548 541 549 542 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, 550 543 kiq_ring->queue); 551 - spin_lock(&adev->gfx.kiq[0].ring_lock); 544 + spin_lock(&kiq->ring_lock); 552 545 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 553 546 adev->gfx.num_compute_rings + 554 547 kiq->pmf->set_resources_size); ··· 562 555 queue_mask = ~0ULL; 563 556 564 557 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); 565 - for (i = 0; i < adev->gfx.num_compute_rings; i++) 558 + for (i = 0; i < adev->gfx.num_compute_rings; i++) { 559 + j = i + xcc_id * adev->gfx.num_compute_rings; 566 560 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); 561 + } 567 562 568 563 r = amdgpu_ring_test_helper(kiq_ring); 569 - spin_unlock(&adev->gfx.kiq[0].ring_lock); 564 + spin_unlock(&kiq->ring_lock); 570 565 if (r) 571 566 DRM_ERROR("KCQ enable failed\n"); 572 567

+8 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

··· 408 408 409 409 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 410 410 struct amdgpu_ring *ring, 411 - struct amdgpu_irq_src *irq); 411 + struct amdgpu_irq_src *irq, int xcc_id); 412 412 413 413 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 414 414 415 - void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 415 + void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 416 416 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 417 - unsigned hpd_size); 417 + unsigned hpd_size, int xcc_id); 418 418 419 419 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 420 - unsigned mqd_size); 421 - void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 422 - int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 423 - int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 420 + unsigned mqd_size, int xcc_id); 421 + void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 422 + int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 423 + int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 424 424 425 425 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 426 426 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); ··· 429 429 int pipe, int queue); 430 430 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 431 431 int *mec, int *pipe, int *queue); 432 - bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int inst, 432 + bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 433 433 int mec, int pipe, int queue); 434 434 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 435 435 struct amdgpu_ring *ring);

+11 -12

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

··· 4629 4629 } 4630 4630 4631 4631 if (!adev->enable_mes_kiq) { 4632 - r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4632 + r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4633 4633 if (r) { 4634 4634 DRM_ERROR("Failed to init KIQ BOs!\n"); 4635 4635 return r; 4636 4636 } 4637 4637 4638 4638 kiq = &adev->gfx.kiq[0]; 4639 - r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4639 + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4640 4640 if (r) 4641 4641 return r; 4642 4642 } 4643 4643 4644 - r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4644 + r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4645 4645 if (r) 4646 4646 return r; 4647 4647 ··· 4690 4690 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4691 4691 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4692 4692 4693 - amdgpu_gfx_mqd_sw_fini(adev); 4693 + amdgpu_gfx_mqd_sw_fini(adev, 0); 4694 4694 4695 4695 if (!adev->enable_mes_kiq) { 4696 4696 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4697 - amdgpu_gfx_kiq_fini(adev); 4697 + amdgpu_gfx_kiq_fini(adev, 0); 4698 4698 } 4699 4699 4700 4700 gfx_v10_0_pfp_fini(adev); ··· 6812 6812 { 6813 6813 struct amdgpu_device *adev = ring->adev; 6814 6814 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6815 - int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6816 6815 6817 6816 gfx_v10_0_kiq_setting(ring); 6818 6817 6819 6818 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6820 6819 /* reset MQD to a clean status */ 6821 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 6822 - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6820 + if (adev->gfx.kiq[0].mqd_backup) 6821 + memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6823 6822 6824 6823 /* reset ring buffer */ 6825 6824 ring->wptr = 0; ··· 6840 6841 nv_grbm_select(adev, 0, 0, 0, 0); 6841 6842 mutex_unlock(&adev->srbm_mutex); 6842 6843 6843 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 6844 - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6844 + if (adev->gfx.kiq[0].mqd_backup) 6845 + memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6845 6846 } 6846 6847 6847 6848 return 0; ··· 6926 6927 goto done; 6927 6928 } 6928 6929 6929 - r = amdgpu_gfx_enable_kcq(adev); 6930 + r = amdgpu_gfx_enable_kcq(adev, 0); 6930 6931 done: 6931 6932 return r; 6932 6933 } ··· 7279 7280 DRM_ERROR("KGQ disable failed\n"); 7280 7281 } 7281 7282 #endif 7282 - if (amdgpu_gfx_disable_kcq(adev)) 7283 + if (amdgpu_gfx_disable_kcq(adev, 0)) 7283 7284 DRM_ERROR("KCQ disable failed\n"); 7284 7285 } 7285 7286

+11 -12

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 1389 1389 } 1390 1390 1391 1391 if (!adev->enable_mes_kiq) { 1392 - r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1392 + r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1393 1393 if (r) { 1394 1394 DRM_ERROR("Failed to init KIQ BOs!\n"); 1395 1395 return r; 1396 1396 } 1397 1397 1398 1398 kiq = &adev->gfx.kiq[0]; 1399 - r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1399 + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 1400 1400 if (r) 1401 1401 return r; 1402 1402 } 1403 1403 1404 - r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1404 + r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1405 1405 if (r) 1406 1406 return r; 1407 1407 ··· 1463 1463 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1464 1464 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1465 1465 1466 - amdgpu_gfx_mqd_sw_fini(adev); 1466 + amdgpu_gfx_mqd_sw_fini(adev, 0); 1467 1467 1468 1468 if (!adev->enable_mes_kiq) { 1469 1469 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1470 - amdgpu_gfx_kiq_fini(adev); 1470 + amdgpu_gfx_kiq_fini(adev, 0); 1471 1471 } 1472 1472 1473 1473 gfx_v11_0_pfp_fini(adev); ··· 4035 4035 { 4036 4036 struct amdgpu_device *adev = ring->adev; 4037 4037 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4038 - int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4039 4038 4040 4039 gfx_v11_0_kiq_setting(ring); 4041 4040 4042 4041 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4043 4042 /* reset MQD to a clean status */ 4044 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 4045 - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4043 + if (adev->gfx.kiq[0].mqd_backup) 4044 + memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4046 4045 4047 4046 /* reset ring buffer */ 4048 4047 ring->wptr = 0; ··· 4063 4064 soc21_grbm_select(adev, 0, 0, 0, 0); 4064 4065 mutex_unlock(&adev->srbm_mutex); 4065 4066 4066 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 4067 - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4067 + if (adev->gfx.kiq[0].mqd_backup) 4068 + memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4068 4069 } 4069 4070 4070 4071 return 0; ··· 4152 4153 goto done; 4153 4154 } 4154 4155 4155 - r = amdgpu_gfx_enable_kcq(adev); 4156 + r = amdgpu_gfx_enable_kcq(adev, 0); 4156 4157 done: 4157 4158 return r; 4158 4159 } ··· 4455 4456 DRM_ERROR("KGQ disable failed\n"); 4456 4457 } 4457 4458 #endif 4458 - if (amdgpu_gfx_disable_kcq(adev)) 4459 + if (amdgpu_gfx_disable_kcq(adev, 0)) 4459 4460 DRM_ERROR("KCQ disable failed\n"); 4460 4461 4461 4462 amdgpu_mes_kiq_hw_fini(adev);

+9 -10

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

··· 2016 2016 } 2017 2017 } 2018 2018 2019 - r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE); 2019 + r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0); 2020 2020 if (r) { 2021 2021 DRM_ERROR("Failed to init KIQ BOs!\n"); 2022 2022 return r; 2023 2023 } 2024 2024 2025 2025 kiq = &adev->gfx.kiq[0]; 2026 - r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2026 + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 2027 2027 if (r) 2028 2028 return r; 2029 2029 2030 2030 /* create MQD for all compute queues as well as KIQ for SRIOV case */ 2031 - r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation)); 2031 + r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0); 2032 2032 if (r) 2033 2033 return r; 2034 2034 ··· 2051 2051 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2052 2052 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2053 2053 2054 - amdgpu_gfx_mqd_sw_fini(adev); 2054 + amdgpu_gfx_mqd_sw_fini(adev, 0); 2055 2055 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2056 - amdgpu_gfx_kiq_fini(adev); 2056 + amdgpu_gfx_kiq_fini(adev, 0); 2057 2057 2058 2058 gfx_v8_0_mec_fini(adev); 2059 2059 amdgpu_gfx_rlc_fini(adev); ··· 4596 4596 { 4597 4597 struct amdgpu_device *adev = ring->adev; 4598 4598 struct vi_mqd *mqd = ring->mqd_ptr; 4599 - int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4600 4599 4601 4600 gfx_v8_0_kiq_setting(ring); 4602 4601 4603 4602 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4604 4603 /* reset MQD to a clean status */ 4605 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 4606 - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); 4604 + if (adev->gfx.kiq[0].mqd_backup) 4605 + memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation)); 4607 4606 4608 4607 /* reset ring buffer */ 4609 4608 ring->wptr = 0; ··· 4625 4626 vi_srbm_select(adev, 0, 0, 0, 0); 4626 4627 mutex_unlock(&adev->srbm_mutex); 4627 4628 4628 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 4629 - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); 4629 + if (adev->gfx.kiq[0].mqd_backup) 4630 + memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation)); 4630 4631 } 4631 4632 4632 4633 return 0;

+12 -13

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 2169 2169 } 2170 2170 } 2171 2171 2172 - r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2172 + r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); 2173 2173 if (r) { 2174 2174 DRM_ERROR("Failed to init KIQ BOs!\n"); 2175 2175 return r; 2176 2176 } 2177 2177 2178 2178 kiq = &adev->gfx.kiq[0]; 2179 - r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2179 + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 2180 2180 if (r) 2181 2181 return r; 2182 2182 2183 2183 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2184 - r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2184 + r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0); 2185 2185 if (r) 2186 2186 return r; 2187 2187 ··· 2216 2216 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2217 2217 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2218 2218 2219 - amdgpu_gfx_mqd_sw_fini(adev); 2219 + amdgpu_gfx_mqd_sw_fini(adev, 0); 2220 2220 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2221 - amdgpu_gfx_kiq_fini(adev); 2221 + amdgpu_gfx_kiq_fini(adev, 0); 2222 2222 2223 2223 gfx_v9_0_mec_fini(adev); 2224 2224 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, ··· 3520 3520 { 3521 3521 struct amdgpu_device *adev = ring->adev; 3522 3522 struct v9_mqd *mqd = ring->mqd_ptr; 3523 - int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3524 3523 struct v9_mqd *tmp_mqd; 3525 3524 3526 3525 gfx_v9_0_kiq_setting(ring); ··· 3529 3530 * driver need to re-init the mqd. 3530 3531 * check mqd->cp_hqd_pq_control since this value should not be 0 3531 3532 */ 3532 - tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3533 + tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; 3533 3534 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3534 3535 /* for GPU_RESET case , reset MQD to a clean status */ 3535 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 3536 - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3536 + if (adev->gfx.kiq[0].mqd_backup) 3537 + memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); 3537 3538 3538 3539 /* reset ring buffer */ 3539 3540 ring->wptr = 0; ··· 3557 3558 soc15_grbm_select(adev, 0, 0, 0, 0); 3558 3559 mutex_unlock(&adev->srbm_mutex); 3559 3560 3560 - if (adev->gfx.mec.mqd_backup[mqd_idx]) 3561 - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3561 + if (adev->gfx.kiq[0].mqd_backup) 3562 + memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 3562 3563 } 3563 3564 3564 3565 return 0; ··· 3652 3653 goto done; 3653 3654 } 3654 3655 3655 - r = amdgpu_gfx_enable_kcq(adev); 3656 + r = amdgpu_gfx_enable_kcq(adev, 0); 3656 3657 done: 3657 3658 return r; 3658 3659 } ··· 3771 3772 /* DF freeze and kcq disable will fail */ 3772 3773 if (!amdgpu_ras_intr_triggered()) 3773 3774 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3774 - amdgpu_gfx_disable_kcq(adev); 3775 + amdgpu_gfx_disable_kcq(adev, 0); 3775 3776 3776 3777 if (amdgpu_sriov_vf(adev)) { 3777 3778 gfx_v9_0_cp_gfx_enable(adev, false);

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