tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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riscv: zicfiss / zicfilp enumeration

This patch adds support for detecting the RISC-V ISA extensions
Zicfiss and Zicfilp. Zicfiss and Zicfilp stand for the unprivileged
integer spec extensions for shadow stack and indirect branch tracking,
respectively.

This patch looks for Zicfiss and Zicfilp in the device tree and
accordingly lights up the corresponding bits in the cpu feature
bitmap. Furthermore this patch adds detection utility functions to
return whether shadow stack or landing pads are supported by the cpu.

Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6
Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com>
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-3-b55691eacf4f@rivosinc.com
[pjw@kernel.org: updated to apply; cleaned up patch description]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

authored by

Deepak Gupta and committed by
Paul Walmsley df117085 f94645fc

+36
+12
arch/riscv/include/asm/cpufeature.h
··· 152 152 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); 153 153 } 154 154 155 + static inline bool cpu_supports_shadow_stack(void) 156 + { 157 + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && 158 + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS)); 159 + } 160 + 161 + static inline bool cpu_supports_indirect_br_lp_instr(void) 162 + { 163 + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && 164 + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFILP)); 165 + } 166 + 155 167 #endif
+2
arch/riscv/include/asm/hwcap.h
··· 110 110 #define RISCV_ISA_EXT_ZALASR 101 111 111 #define RISCV_ISA_EXT_ZILSD 102 112 112 #define RISCV_ISA_EXT_ZCLSD 103 113 + #define RISCV_ISA_EXT_ZICFILP 104 114 + #define RISCV_ISA_EXT_ZICFISS 105 113 115 114 116 #define RISCV_ISA_EXT_XLINUXENVCFG 127 115 117
+22
arch/riscv/kernel/cpufeature.c
··· 296 296 return 0; 297 297 } 298 298 299 + static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data, 300 + const unsigned long *isa_bitmap) 301 + { 302 + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) 303 + return -EINVAL; 304 + 305 + return 0; 306 + } 307 + 308 + static int riscv_cfiss_validate(const struct riscv_isa_ext_data *data, 309 + const unsigned long *isa_bitmap) 310 + { 311 + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) 312 + return -EINVAL; 313 + 314 + return 0; 315 + } 316 + 299 317 static const unsigned int riscv_a_exts[] = { 300 318 RISCV_ISA_EXT_ZAAMO, 301 319 RISCV_ISA_EXT_ZALRSC, ··· 500 482 __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate), 501 483 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), 502 484 __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), 485 + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts, 486 + riscv_cfilp_validate), 487 + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts, 488 + riscv_cfiss_validate), 503 489 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 504 490 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), 505 491 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),