drm/msm/mdp5: drop split display support

-42

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

··· 158 158 159 159 mdp5_cmd_enc->enabled = true; 160 160 } 161 - 162 - int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, 163 - struct drm_encoder *slave_encoder) 164 - { 165 - struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); 166 - struct mdp5_kms *mdp5_kms; 167 - struct device *dev; 168 - int intf_num; 169 - u32 data = 0; 170 - 171 - if (!encoder || !slave_encoder) 172 - return -EINVAL; 173 - 174 - mdp5_kms = get_kms(encoder); 175 - intf_num = mdp5_cmd_enc->intf->num; 176 - 177 - /* Switch slave encoder's trigger MUX, to use the master's 178 - * start signal for the slave encoder 179 - */ 180 - if (intf_num == 1) 181 - data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; 182 - else if (intf_num == 2) 183 - data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; 184 - else 185 - return -EINVAL; 186 - 187 - /* Smart Panel, Sync mode */ 188 - data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; 189 - 190 - dev = &mdp5_kms->pdev->dev; 191 - 192 - /* Make sure clocks are on when connectors calling this function. */ 193 - pm_runtime_get_sync(dev); 194 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); 195 - 196 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, 197 - MDP5_SPLIT_DPL_LOWER_SMART_PANEL); 198 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); 199 - pm_runtime_put_sync(dev); 200 - 201 - return 0; 202 - } 203 161 #endif /* CONFIG_DRM_MSM_DSI */

-42

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

··· 263 263 return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf)); 264 264 } 265 265 266 - int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, 267 - struct drm_encoder *slave_encoder) 268 - { 269 - struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 270 - struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder); 271 - struct mdp5_kms *mdp5_kms; 272 - struct device *dev; 273 - int intf_num; 274 - u32 data = 0; 275 - 276 - if (!encoder || !slave_encoder) 277 - return -EINVAL; 278 - 279 - mdp5_kms = get_kms(encoder); 280 - intf_num = mdp5_encoder->intf->num; 281 - 282 - /* Switch slave encoder's TimingGen Sync mode, 283 - * to use the master's enable signal for the slave encoder. 284 - */ 285 - if (intf_num == 1) 286 - data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; 287 - else if (intf_num == 2) 288 - data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; 289 - else 290 - return -EINVAL; 291 - 292 - dev = &mdp5_kms->pdev->dev; 293 - /* Make sure clocks are on when connectors calling this function. */ 294 - pm_runtime_get_sync(dev); 295 - 296 - /* Dumb Panel, Sync mode */ 297 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); 298 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); 299 - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); 300 - 301 - mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); 302 - 303 - pm_runtime_put_sync(dev); 304 - 305 - return 0; 306 - } 307 - 308 266 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode) 309 267 { 310 268 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);

-14

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

··· 190 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 191 } 192 192 193 - static int mdp5_set_split_display(struct msm_kms *kms, 194 - struct drm_encoder *encoder, 195 - struct drm_encoder *slave_encoder, 196 - bool is_cmd_mode) 197 - { 198 - if (is_cmd_mode) 199 - return mdp5_cmd_encoder_set_split_display(encoder, 200 - slave_encoder); 201 - else 202 - return mdp5_vid_encoder_set_split_display(encoder, 203 - slave_encoder); 204 - } 205 - 206 193 static void mdp5_destroy(struct mdp5_kms *mdp5_kms); 207 194 208 195 static void mdp5_kms_destroy(struct msm_kms *kms) ··· 255 268 .wait_flush = mdp5_wait_flush, 256 269 .complete_commit = mdp5_complete_commit, 257 270 .get_format = mdp_get_format, 258 - .set_split_display = mdp5_set_split_display, 259 271 .destroy = mdp5_kms_destroy, 260 272 #ifdef CONFIG_DEBUG_FS 261 273 .debugfs_init = mdp5_kms_debugfs_init,

-9

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

··· 291 291 292 292 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, 293 293 struct mdp5_interface *intf, struct mdp5_ctl *ctl); 294 - int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, 295 - struct drm_encoder *slave_encoder); 296 294 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode); 297 295 int mdp5_encoder_get_linecount(struct drm_encoder *encoder); 298 296 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder); ··· 301 303 struct drm_display_mode *adjusted_mode); 302 304 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder); 303 305 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder); 304 - int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, 305 - struct drm_encoder *slave_encoder); 306 306 #else 307 307 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, 308 308 struct drm_display_mode *mode, ··· 312 316 } 313 317 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder) 314 318 { 315 - } 316 - static inline int mdp5_cmd_encoder_set_split_display( 317 - struct drm_encoder *encoder, struct drm_encoder *slave_encoder) 318 - { 319 - return -EINVAL; 320 319 } 321 320 #endif 322 321

-4

drivers/gpu/drm/msm/msm_kms.h

··· 105 105 /* misc: */ 106 106 long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, 107 107 struct drm_encoder *encoder); 108 - int (*set_split_display)(struct msm_kms *kms, 109 - struct drm_encoder *encoder, 110 - struct drm_encoder *slave_encoder, 111 - bool is_cmd_mode); 112 108 /* cleanup: */ 113 109 void (*destroy)(struct msm_kms *kms); 114 110

Configure Feed

Configure Feed