Merge tag 'x86-urgent-2025-09-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+14 -11

arch/x86/kernel/cpu/topology_amd.c

··· 175 175 176 176 static void parse_topology_amd(struct topo_scan *tscan) 177 177 { 178 - bool has_topoext = false; 179 - 180 178 /* 181 - * If the extended topology leaf 0x8000_001e is available 182 - * try to get SMT, CORE, TILE, and DIE shifts from extended 179 + * Try to get SMT, CORE, TILE, and DIE shifts from extended 183 180 * CPUID leaf 0x8000_0026 on supported processors first. If 184 181 * extended CPUID leaf 0x8000_0026 is not supported, try to 185 - * get SMT and CORE shift from leaf 0xb first, then try to 186 - * get the CORE shift from leaf 0x8000_0008. 182 + * get SMT and CORE shift from leaf 0xb. If either leaf is 183 + * available, cpu_parse_topology_ext() will return true. 187 184 */ 188 - if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) 189 - has_topoext = cpu_parse_topology_ext(tscan); 185 + bool has_xtopology = cpu_parse_topology_ext(tscan); 190 186 191 187 if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) 192 188 tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); 193 189 194 - if (!has_topoext && !parse_8000_0008(tscan)) 190 + /* 191 + * If XTOPOLOGY leaves (0x26/0xb) are not available, try to 192 + * get the CORE shift from leaf 0x8000_0008 first. 193 + */ 194 + if (!has_xtopology && !parse_8000_0008(tscan)) 195 195 return; 196 196 197 - /* Prefer leaf 0x8000001e if available */ 198 - if (parse_8000_001e(tscan, has_topoext)) 197 + /* 198 + * Prefer leaf 0x8000001e if available to get the SMT shift and 199 + * the initial APIC ID if XTOPOLOGY leaves are not available. 200 + */ 201 + if (parse_8000_001e(tscan, has_xtopology)) 199 202 return; 200 203 201 204 /* Try the NODEID MSR */

+1 -1

fs/resctrl/ctrlmondata.c

··· 625 625 */ 626 626 list_for_each_entry(d, &r->mon_domains, hdr.list) { 627 627 if (d->ci_id == domid) { 628 - rr.ci_id = d->ci_id; 629 628 cpu = cpumask_any(&d->hdr.cpu_mask); 630 629 ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); 631 630 if (!ci) 632 631 continue; 632 + rr.ci = ci; 633 633 mon_event_read(&rr, r, NULL, rdtgrp, 634 634 &ci->shared_cpu_map, evtid, false); 635 635 goto checkresult;

+2 -2

fs/resctrl/internal.h

··· 98 98 * domains in @r sharing L3 @ci.id 99 99 * @evtid: Which monitor event to read. 100 100 * @first: Initialize MBM counter when true. 101 - * @ci_id: Cacheinfo id for L3. Only set when @d is NULL. Used when summing domains. 101 + * @ci: Cacheinfo for L3. Only set when @d is NULL. Used when summing domains. 102 102 * @err: Error encountered when reading counter. 103 103 * @val: Returned value of event counter. If @rgrp is a parent resource group, 104 104 * @val includes the sum of event counts from its child resource groups. ··· 112 112 struct rdt_mon_domain *d; 113 113 enum resctrl_event_id evtid; 114 114 bool first; 115 - unsigned int ci_id; 115 + struct cacheinfo *ci; 116 116 int err; 117 117 u64 val; 118 118 void *arch_mon_ctx;

+2 -4

fs/resctrl/monitor.c

··· 361 361 { 362 362 int cpu = smp_processor_id(); 363 363 struct rdt_mon_domain *d; 364 - struct cacheinfo *ci; 365 364 struct mbm_state *m; 366 365 int err, ret; 367 366 u64 tval = 0; ··· 388 389 } 389 390 390 391 /* Summing domains that share a cache, must be on a CPU for that cache. */ 391 - ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); 392 - if (!ci || ci->id != rr->ci_id) 392 + if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) 393 393 return -EINVAL; 394 394 395 395 /* ··· 400 402 */ 401 403 ret = -EINVAL; 402 404 list_for_each_entry(d, &rr->r->mon_domains, hdr.list) { 403 - if (d->ci_id != rr->ci_id) 405 + if (d->ci_id != rr->ci->id) 404 406 continue; 405 407 err = resctrl_arch_rmid_read(rr->r, d, closid, rmid, 406 408 rr->evtid, &tval, rr->arch_mon_ctx);

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