Merge master.kernel.org:/home/rmk/linux-2.6-mmc

+35 -34

drivers/mmc/imxmmc.c

··· 91 91 int dma_allocated; 92 92 93 93 unsigned char actual_bus_width; 94 + 95 + int prev_cmd_code; 94 96 }; 95 97 96 98 #define IMXMCI_PEND_IRQ_b 0 ··· 250 248 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple. 251 249 * This is required for SCR read at least. 252 250 */ 253 - if (datasz < 64) { 251 + if (datasz < 512) { 254 252 host->dma_size = datasz; 255 253 if (data->flags & MMC_DATA_READ) { 256 254 host->dma_dir = DMA_FROM_DEVICE; 257 255 258 256 /* Hack to enable read SCR */ 259 - if(datasz < 16) { 260 - MMC_NOB = 1; 261 - MMC_BLK_LEN = 16; 262 - } 257 + MMC_NOB = 1; 258 + MMC_BLK_LEN = 512; 263 259 } else { 264 260 host->dma_dir = DMA_TO_DEVICE; 265 261 } ··· 409 409 410 410 spin_unlock_irqrestore(&host->lock, flags); 411 411 412 + if(req && req->cmd) 413 + host->prev_cmd_code = req->cmd->opcode; 414 + 412 415 host->req = NULL; 413 416 host->cmd = NULL; 414 417 host->data = NULL; ··· 556 553 { 557 554 int i; 558 555 int burst_len; 559 - int flush_len; 560 556 int trans_done = 0; 561 557 unsigned int stat = *pstat; 562 558 ··· 568 566 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n", 569 567 stat); 570 568 569 + udelay(20); /* required for clocks < 8MHz*/ 570 + 571 571 if(host->dma_dir == DMA_FROM_DEVICE) { 572 572 imxmci_busy_wait_for_status(host, &stat, 573 573 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE, 574 - 20, "imxmci_cpu_driven_data read"); 574 + 50, "imxmci_cpu_driven_data read"); 575 575 576 576 while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && 577 - (host->data_cnt < host->dma_size)) { 578 - if(burst_len >= host->dma_size - host->data_cnt) { 579 - flush_len = burst_len; 580 - burst_len = host->dma_size - host->data_cnt; 581 - flush_len -= burst_len; 582 - host->data_cnt = host->dma_size; 583 - trans_done = 1; 584 - } else { 585 - flush_len = 0; 586 - host->data_cnt += burst_len; 587 - } 577 + (host->data_cnt < 512)) { 578 + 579 + udelay(20); /* required for clocks < 8MHz*/ 588 580 589 581 for(i = burst_len; i>=2 ; i-=2) { 590 - *(host->data_ptr++) = MMC_BUFFER_ACCESS; 591 - udelay(20); /* required for clocks < 8MHz*/ 582 + u16 data; 583 + data = MMC_BUFFER_ACCESS; 584 + udelay(10); /* required for clocks < 8MHz*/ 585 + if(host->data_cnt+2 <= host->dma_size) { 586 + *(host->data_ptr++) = data; 587 + } else { 588 + if(host->data_cnt < host->dma_size) 589 + *(u8*)(host->data_ptr) = data; 590 + } 591 + host->data_cnt += 2; 592 592 } 593 - 594 - if(i == 1) 595 - *(u8*)(host->data_ptr) = MMC_BUFFER_ACCESS; 596 593 597 594 stat = MMC_STATUS; 598 595 599 - /* Flush extra bytes from FIFO */ 600 - while(flush_len && !(stat & STATUS_DATA_TRANS_DONE)){ 601 - i = MMC_BUFFER_ACCESS; 602 - stat = MMC_STATUS; 603 - stat &= ~STATUS_CRC_READ_ERR; /* Stupid but required there */ 604 - } 605 - 606 - dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read burst %d STATUS = 0x%x\n", 607 - burst_len, stat); 596 + dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", 597 + host->data_cnt, burst_len, stat); 608 598 } 599 + 600 + if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) 601 + trans_done = 1; 602 + 603 + if(host->dma_size & 0x1ff) 604 + stat &= ~STATUS_CRC_READ_ERR; 605 + 609 606 } else { 610 607 imxmci_busy_wait_for_status(host, &stat, 611 608 STATUS_APPL_BUFF_FE, ··· 693 692 what, stat, MMC_INT_MASK); 694 693 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", 695 694 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); 696 - dev_err(mmc_dev(host->mmc), "CMD%d, bus %d-bit, dma_size = 0x%x\n", 697 - host->cmd?host->cmd->opcode:0, 1<<host->actual_bus_width, host->dma_size); 695 + dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", 696 + host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size); 698 697 } 699 698 700 699 if(!host->present || timeout)

+51 -4

drivers/mmc/mmc.c

··· 247 247 248 248 EXPORT_SYMBOL(mmc_wait_for_app_cmd); 249 249 250 + /** 251 + * mmc_set_data_timeout - set the timeout for a data command 252 + * @data: data phase for command 253 + * @card: the MMC card associated with the data transfer 254 + * @write: flag to differentiate reads from writes 255 + */ 256 + void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card, 257 + int write) 258 + { 259 + unsigned int mult; 260 + 261 + /* 262 + * SD cards use a 100 multiplier rather than 10 263 + */ 264 + mult = mmc_card_sd(card) ? 100 : 10; 265 + 266 + /* 267 + * Scale up the multiplier (and therefore the timeout) by 268 + * the r2w factor for writes. 269 + */ 270 + if (write) 271 + mult <<= card->csd.r2w_factor; 272 + 273 + data->timeout_ns = card->csd.tacc_ns * mult; 274 + data->timeout_clks = card->csd.tacc_clks * mult; 275 + 276 + /* 277 + * SD cards also have an upper limit on the timeout. 278 + */ 279 + if (mmc_card_sd(card)) { 280 + unsigned int timeout_us, limit_us; 281 + 282 + timeout_us = data->timeout_ns / 1000; 283 + timeout_us += data->timeout_clks * 1000 / 284 + (card->host->ios.clock / 1000); 285 + 286 + if (write) 287 + limit_us = 250000; 288 + else 289 + limit_us = 100000; 290 + 291 + if (timeout_us > limit_us) { 292 + data->timeout_ns = limit_us * 1000; 293 + data->timeout_clks = 0; 294 + } 295 + } 296 + } 297 + EXPORT_SYMBOL(mmc_set_data_timeout); 298 + 250 299 static int mmc_select_card(struct mmc_host *host, struct mmc_card *card); 251 300 252 301 /** ··· 957 908 { 958 909 int err; 959 910 struct mmc_card *card; 960 - 961 911 struct mmc_request mrq; 962 912 struct mmc_command cmd; 963 913 struct mmc_data data; 964 - 965 914 struct scatterlist sg; 966 915 967 916 list_for_each_entry(card, &host->cards, node) { ··· 994 947 995 948 memset(&data, 0, sizeof(struct mmc_data)); 996 949 997 - data.timeout_ns = card->csd.tacc_ns * 10; 998 - data.timeout_clks = card->csd.tacc_clks * 10; 950 + mmc_set_data_timeout(&data, card, 0); 951 + 999 952 data.blksz_bits = 3; 1000 953 data.blksz = 1 << 3; 1001 954 data.blocks = 1;

+7 -53

drivers/mmc/mmc_block.c

··· 30 30 #include <linux/mutex.h> 31 31 32 32 #include <linux/mmc/card.h> 33 + #include <linux/mmc/host.h> 33 34 #include <linux/mmc/protocol.h> 34 35 35 36 #include <asm/system.h> ··· 172 171 173 172 brq.cmd.arg = req->sector << 9; 174 173 brq.cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 175 - brq.data.timeout_ns = card->csd.tacc_ns * 10; 176 - brq.data.timeout_clks = card->csd.tacc_clks * 10; 177 174 brq.data.blksz_bits = md->block_bits; 178 175 brq.data.blksz = 1 << md->block_bits; 179 176 brq.data.blocks = req->nr_sectors >> (md->block_bits - 9); 180 177 brq.stop.opcode = MMC_STOP_TRANSMISSION; 181 178 brq.stop.arg = 0; 182 179 brq.stop.flags = MMC_RSP_R1B | MMC_CMD_AC; 180 + 181 + mmc_set_data_timeout(&brq.data, card, rq_data_dir(req) != READ); 183 182 184 183 if (rq_data_dir(req) == READ) { 185 184 brq.cmd.opcode = brq.data.blocks > 1 ? MMC_READ_MULTIPLE_BLOCK : MMC_READ_SINGLE_BLOCK; ··· 188 187 brq.cmd.opcode = MMC_WRITE_BLOCK; 189 188 brq.data.flags |= MMC_DATA_WRITE; 190 189 brq.data.blocks = 1; 191 - 192 - /* 193 - * Scale up the timeout by the r2w factor 194 - */ 195 - brq.data.timeout_ns <<= card->csd.r2w_factor; 196 - brq.data.timeout_clks <<= card->csd.r2w_factor; 197 190 } 198 191 199 192 if (brq.data.blocks > 1) { ··· 319 324 md->read_only = mmc_blk_readonly(card); 320 325 321 326 /* 322 - * Figure out a workable block size. MMC cards have: 323 - * - two block sizes, one for read and one for write. 324 - * - may support partial reads and/or writes 325 - * (allows block sizes smaller than specified) 327 + * Both SD and MMC specifications state (although a bit 328 + * unclearly in the MMC case) that a block size of 512 329 + * bytes must always be supported by the card. 326 330 */ 327 - md->block_bits = card->csd.read_blkbits; 328 - if (card->csd.write_blkbits != card->csd.read_blkbits) { 329 - if (card->csd.write_blkbits < card->csd.read_blkbits && 330 - card->csd.read_partial) { 331 - /* 332 - * write block size is smaller than read block 333 - * size, but we support partial reads, so choose 334 - * the smaller write block size. 335 - */ 336 - md->block_bits = card->csd.write_blkbits; 337 - } else if (card->csd.write_blkbits > card->csd.read_blkbits && 338 - card->csd.write_partial) { 339 - /* 340 - * read block size is smaller than write block 341 - * size, but we support partial writes. Use read 342 - * block size. 343 - */ 344 - } else { 345 - /* 346 - * We don't support this configuration for writes. 347 - */ 348 - printk(KERN_ERR "%s: unable to select block size for " 349 - "writing (rb%u wb%u rp%u wp%u)\n", 350 - mmc_card_id(card), 351 - 1 << card->csd.read_blkbits, 352 - 1 << card->csd.write_blkbits, 353 - card->csd.read_partial, 354 - card->csd.write_partial); 355 - md->read_only = 1; 356 - } 357 - } 358 - 359 - /* 360 - * Refuse to allow block sizes smaller than 512 bytes. 361 - */ 362 - if (md->block_bits < 9) { 363 - printk(KERN_ERR "%s: unable to support block size %u\n", 364 - mmc_card_id(card), 1 << md->block_bits); 365 - ret = -EINVAL; 366 - goto err_kfree; 367 - } 331 + md->block_bits = 9; 368 332 369 333 md->disk = alloc_disk(1 << MMC_SHIFT); 370 334 if (md->disk == NULL) {

+1 -1

include/linux/mmc/host.h

··· 77 77 struct device *dev; 78 78 struct class_device class_dev; 79 79 int index; 80 - struct mmc_host_ops *ops; 80 + const struct mmc_host_ops *ops; 81 81 unsigned int f_min; 82 82 unsigned int f_max; 83 83 u32 ocr_avail;

+2

include/linux/mmc/mmc.h

··· 105 105 extern int mmc_wait_for_app_cmd(struct mmc_host *, unsigned int, 106 106 struct mmc_command *, int); 107 107 108 + extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *, int); 109 + 108 110 extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card); 109 111 110 112 static inline void mmc_claim_host(struct mmc_host *host)

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