tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.17:

- Correct FlexCAN PHY settings on imx95-19x19-evk board (Haibo Chen)
- Add missing microSD slot supplies for DH electronics i.MX8M Plus
boards (Marek Vasut)
- Fix assigned clocks for JPEG encoder node on i.MX95 (Marek Vasut)
- A couple of regulator setting fixes for imx8mp-tqma8mpql
board (Markus Niebel)

* tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx95: Fix JPEG encoder node assigned clock
arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2
arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC
arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM
arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator
arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off

Link: https://lore.kernel.org/r/aK6BuzIYwUBRU1GW@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann e019bbd8 0aee6faf

+44 -27
+1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
··· 555 555 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 556 556 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 557 557 vmmc-supply = <&reg_usdhc2_vmmc>; 558 + vqmmc-supply = <&ldo5>; 558 559 bus-width = <4>; 559 560 status = "okay"; 560 561 };
+1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
··· 609 609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 610 610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 611 611 vmmc-supply = <&reg_usdhc2_vmmc>; 612 + vqmmc-supply = <&ldo5>; 612 613 bus-width = <4>; 613 614 status = "okay"; 614 615 };
+7 -6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
··· 467 467 status = "okay"; 468 468 }; 469 469 470 + &reg_usdhc2_vqmmc { 471 + status = "okay"; 472 + }; 473 + 470 474 &sai5 { 471 475 pinctrl-names = "default"; 472 476 pinctrl-0 = <&pinctrl_sai5>; ··· 880 876 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 881 877 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 882 878 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 883 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 884 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 879 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 885 880 }; 886 881 887 882 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 889 886 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 890 887 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 891 888 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 892 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 893 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 889 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 894 890 }; 895 891 896 892 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 898 896 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 899 897 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 900 898 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 901 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 902 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 899 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 903 900 }; 904 901 905 902 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+7 -6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
··· 604 604 status = "okay"; 605 605 }; 606 606 607 + &reg_usdhc2_vqmmc { 608 + status = "okay"; 609 + }; 610 + 607 611 &sai3 { 608 612 pinctrl-names = "default"; 609 613 pinctrl-0 = <&pinctrl_sai3>; ··· 987 983 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 988 984 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 989 985 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 990 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 991 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 986 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 992 987 }; 993 988 994 989 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 996 993 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 997 994 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 998 995 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 999 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1000 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 996 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1001 997 }; 1002 998 1003 999 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 1005 1003 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1006 1004 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1007 1005 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1008 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1009 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 1006 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1010 1007 }; 1011 1008 1012 1009 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+22 -9
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
··· 16 16 reg = <0x0 0x40000000 0 0x80000000>; 17 17 }; 18 18 19 - /* identical to buck4_reg, but should never change */ 20 - reg_vcc3v3: regulator-vcc3v3 { 21 - compatible = "regulator-fixed"; 22 - regulator-name = "VCC3V3"; 23 - regulator-min-microvolt = <3300000>; 19 + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 20 + compatible = "regulator-gpio"; 21 + pinctrl-names = "default"; 22 + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; 23 + regulator-name = "V_SD2"; 24 + regulator-min-microvolt = <1800000>; 24 25 regulator-max-microvolt = <3300000>; 25 - regulator-always-on; 26 + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 27 + states = <1800000 0x1>, 28 + <3300000 0x0>; 29 + vin-supply = <&ldo5_reg>; 30 + status = "disabled"; 26 31 }; 27 32 }; 28 33 ··· 178 173 read-only; 179 174 reg = <0x53>; 180 175 pagesize = <16>; 181 - vcc-supply = <&reg_vcc3v3>; 176 + vcc-supply = <&buck4_reg>; 182 177 }; 183 178 184 179 m24c64: eeprom@57 { 185 180 compatible = "atmel,24c64"; 186 181 reg = <0x57>; 187 182 pagesize = <32>; 188 - vcc-supply = <&reg_vcc3v3>; 183 + vcc-supply = <&buck4_reg>; 189 184 }; 185 + }; 186 + 187 + &usdhc2 { 188 + vqmmc-supply = <&reg_usdhc2_vqmmc>; 190 189 }; 191 190 192 191 &usdhc3 { ··· 202 193 non-removable; 203 194 no-sd; 204 195 no-sdio; 205 - vmmc-supply = <&reg_vcc3v3>; 196 + vmmc-supply = <&buck4_reg>; 206 197 vqmmc-supply = <&buck5_reg>; 207 198 status = "okay"; 208 199 }; ··· 240 231 241 232 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 242 233 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 234 + }; 235 + 236 + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { 237 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>; 243 238 }; 244 239 245 240 pinctrl_usdhc3: usdhc3grp {
+5 -5
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
··· 80 80 flexcan1_phy: can-phy0 { 81 81 compatible = "nxp,tjr1443"; 82 82 #phy-cells = <0>; 83 - max-bitrate = <1000000>; 83 + max-bitrate = <8000000>; 84 84 enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>; 85 - standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>; 85 + standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_LOW>; 86 86 }; 87 87 88 88 flexcan2_phy: can-phy1 { 89 89 compatible = "nxp,tjr1443"; 90 90 #phy-cells = <0>; 91 - max-bitrate = <1000000>; 92 - enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>; 93 - standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>; 91 + max-bitrate = <8000000>; 92 + enable-gpios = <&i2c4_gpio_expander_21 4 GPIO_ACTIVE_HIGH>; 93 + standby-gpios = <&i2c4_gpio_expander_21 3 GPIO_ACTIVE_LOW>; 94 94 }; 95 95 96 96 reg_vref_1v8: regulator-1p8v {
+1 -1
arch/arm64/boot/dts/freescale/imx95.dtsi
··· 1843 1843 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 1844 1844 clocks = <&scmi_clk IMX95_CLK_VPU>, 1845 1845 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 1846 - assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1846 + assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 1847 1847 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 1848 1848 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1849 1849 };