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iio: accel: bma400: Use index-based register addressing and lookup

Introduce formula-based macros to compute GEN INTR configuration register
addresses from the interrupt number and register index. This reduces the
need for 22 explicit register macros to three base definitions.

Add a centralized lookup table keyed by IIO event direction and replace
get_gen_config_reg() with a helper integrated with this table.

Apply these changes across the affected callbacks to ensure consistent
access to generic interrupt registers.

No functional changes are intended.

Signed-off-by: Akshay Jindal <akshayaj.lkd@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Akshay Jindal and committed by
Jonathan Cameron e03d2138 a2ef0af1

+88 -60
+11 -6
drivers/iio/accel/bma400.h
··· 98 98 #define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) 99 99 #define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) 100 100 101 + enum bma400_generic_intr { 102 + BMA400_GEN1_INTR = 0x1, 103 + BMA400_GEN2_INTR = 0x2, 104 + }; 105 + 101 106 #define BMA400_INT_CONFIG1_REG 0x20 102 107 #define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) 103 108 #define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) ··· 115 110 #define BMA400_TWO_BITS_MASK GENMASK(1, 0) 116 111 117 112 /* Generic interrupts register */ 118 - #define BMA400_GEN1INT_CONFIG0_REG 0x3f 119 - #define BMA400_GEN2INT_CONFIG0_REG 0x4A 113 + #define BMA400_GENINT_CONFIG_REG_BASE 0x3f 114 + #define BMA400_NUM_GENINT_CONFIG_REGS 11 115 + #define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \ 116 + (BMA400_GENINT_CONFIG_REG_BASE + \ 117 + (gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \ 118 + (config_idx)) 120 119 #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) 121 120 #define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) 122 121 #define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) ··· 153 144 BMA400_DETECT_INACTIVITY = 0x0, 154 145 BMA400_DETECT_ACTIVITY = 0x1, 155 146 }; 156 - 157 - #define BMA400_GEN_CONFIG2_OFF 0x02 158 - #define BMA400_GEN_CONFIG3_OFF 0x03 159 - #define BMA400_GEN_CONFIG31_OFF 0x04 160 147 161 148 /* TAP config registers */ 162 149 #define BMA400_TAP_CONFIG_REG 0x57
+77 -54
drivers/iio/accel/bma400_core.c
··· 121 121 __be16 duration; 122 122 }; 123 123 124 + struct bma400_genintr_info { 125 + enum bma400_generic_intr genintr; 126 + unsigned int intrmask; 127 + enum iio_event_direction dir; 128 + enum bma400_detect_criterion detect_mode; 129 + }; 130 + 131 + /* Lookup struct for determining GEN1/GEN2 based on dir */ 132 + static const struct bma400_genintr_info bma400_genintrs[] = { 133 + [IIO_EV_DIR_RISING] = { 134 + .genintr = BMA400_GEN1_INTR, 135 + .intrmask = BMA400_INT_CONFIG0_GEN1_MASK, 136 + .dir = IIO_EV_DIR_RISING, 137 + .detect_mode = BMA400_DETECT_ACTIVITY, 138 + }, 139 + [IIO_EV_DIR_FALLING] = { 140 + .genintr = BMA400_GEN2_INTR, 141 + .intrmask = BMA400_INT_CONFIG0_GEN2_MASK, 142 + .dir = IIO_EV_DIR_FALLING, 143 + .detect_mode = BMA400_DETECT_INACTIVITY, 144 + } 145 + }; 146 + 147 + static inline const struct bma400_genintr_info * 148 + get_bma400_genintr_info(enum iio_event_direction dir) 149 + { 150 + switch (dir) { 151 + case IIO_EV_DIR_RISING: 152 + case IIO_EV_DIR_FALLING: 153 + return &bma400_genintrs[dir]; 154 + default: 155 + return NULL; 156 + }; 157 + } 158 + 124 159 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) 125 160 { 126 161 switch (reg) { ··· 1194 1159 enum iio_event_direction dir, 1195 1160 int state) 1196 1161 { 1197 - int ret, reg, msk, value; 1198 - int field_value = 0; 1162 + int ret; 1163 + unsigned int intrmask, regval; 1164 + enum bma400_generic_intr genintr; 1165 + enum bma400_detect_criterion detect_criterion; 1166 + const struct bma400_genintr_info *bma400_genintr; 1199 1167 1200 - switch (dir) { 1201 - case IIO_EV_DIR_RISING: 1202 - reg = BMA400_GEN1INT_CONFIG0_REG; 1203 - msk = BMA400_INT_CONFIG0_GEN1_MASK; 1204 - value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | 1205 - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVITY); 1206 - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, 1207 - FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); 1208 - break; 1209 - case IIO_EV_DIR_FALLING: 1210 - reg = BMA400_GEN2INT_CONFIG0_REG; 1211 - msk = BMA400_INT_CONFIG0_GEN2_MASK; 1212 - value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | 1213 - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIVITY); 1214 - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, 1215 - FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); 1216 - break; 1217 - default: 1168 + bma400_genintr = get_bma400_genintr_info(dir); 1169 + if (!bma400_genintr) 1218 1170 return -EINVAL; 1219 - } 1171 + 1172 + genintr = bma400_genintr->genintr; 1173 + detect_criterion = bma400_genintr->detect_mode; 1174 + intrmask = bma400_genintr->intrmask; 1220 1175 1221 1176 /* Enabling all axis for interrupt evaluation */ 1222 - ret = regmap_write(data->regmap, reg, 1177 + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), 1223 1178 BMA400_GENINT_CONFIG0_X_EN_MASK | 1224 1179 BMA400_GENINT_CONFIG0_Y_EN_MASK | 1225 1180 BMA400_GENINT_CONFIG0_Z_EN_MASK| ··· 1220 1195 return ret; 1221 1196 1222 1197 /* OR combination of all axis for interrupt evaluation */ 1223 - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); 1198 + regval = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | 1199 + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion); 1200 + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), regval); 1224 1201 if (ret) 1225 1202 return ret; 1226 1203 1227 1204 /* Initial value to avoid interrupts while enabling*/ 1228 - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); 1205 + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), 0x0A); 1229 1206 if (ret) 1230 1207 return ret; 1231 1208 1232 1209 /* Initial duration value to avoid interrupts while enabling*/ 1233 - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); 1210 + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), 0x0F); 1234 1211 if (ret) 1235 1212 return ret; 1236 1213 1237 - ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, 1238 - field_value); 1214 + regval = state ? intrmask : 0; 1215 + ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, regval); 1239 1216 if (ret) 1240 1217 return ret; 1241 1218 1242 - ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, 1243 - field_value); 1219 + ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask, regval); 1244 1220 if (ret) 1245 1221 return ret; 1246 1222 1247 - set_mask_bits(&data->generic_event_en, msk, field_value); 1223 + set_mask_bits(&data->generic_event_en, intrmask, regval); 1248 1224 return 0; 1249 1225 } 1250 1226 ··· 1370 1344 } 1371 1345 } 1372 1346 1373 - static int get_gen_config_reg(enum iio_event_direction dir) 1374 - { 1375 - switch (dir) { 1376 - case IIO_EV_DIR_FALLING: 1377 - return BMA400_GEN2INT_CONFIG0_REG; 1378 - case IIO_EV_DIR_RISING: 1379 - return BMA400_GEN1INT_CONFIG0_REG; 1380 - default: 1381 - return -EINVAL; 1382 - } 1383 - } 1384 - 1385 1347 static int bma400_read_event_value(struct iio_dev *indio_dev, 1386 1348 const struct iio_chan_spec *chan, 1387 1349 enum iio_event_type type, ··· 1378 1364 int *val, int *val2) 1379 1365 { 1380 1366 struct bma400_data *data = iio_priv(indio_dev); 1381 - int ret, reg, reg_val, raw; 1367 + int ret, reg_val, raw; 1368 + enum bma400_generic_intr genintr; 1369 + const struct bma400_genintr_info *bma400_genintr; 1382 1370 1383 1371 if (chan->type != IIO_ACCEL) 1384 1372 return -EINVAL; 1385 1373 1386 1374 switch (type) { 1387 1375 case IIO_EV_TYPE_MAG: 1388 - reg = get_gen_config_reg(dir); 1389 - if (reg < 0) 1376 + bma400_genintr = get_bma400_genintr_info(dir); 1377 + if (!bma400_genintr) 1390 1378 return -EINVAL; 1379 + genintr = bma400_genintr->genintr; 1391 1380 1392 1381 *val2 = 0; 1393 1382 switch (info) { 1394 1383 case IIO_EV_INFO_VALUE: 1395 1384 ret = regmap_read(data->regmap, 1396 - reg + BMA400_GEN_CONFIG2_OFF, 1385 + BMA400_GENINT_CONFIG_REG(genintr, 2), 1397 1386 val); 1398 1387 if (ret) 1399 1388 return ret; ··· 1404 1387 case IIO_EV_INFO_PERIOD: 1405 1388 mutex_lock(&data->mutex); 1406 1389 ret = regmap_bulk_read(data->regmap, 1407 - reg + BMA400_GEN_CONFIG3_OFF, 1390 + BMA400_GENINT_CONFIG_REG(genintr, 3), 1408 1391 &data->duration, 1409 1392 sizeof(data->duration)); 1410 1393 if (ret) { ··· 1415 1398 mutex_unlock(&data->mutex); 1416 1399 return IIO_VAL_INT; 1417 1400 case IIO_EV_INFO_HYSTERESIS: 1418 - ret = regmap_read(data->regmap, reg, val); 1401 + ret = regmap_read(data->regmap, 1402 + BMA400_GENINT_CONFIG_REG(genintr, 0), 1403 + val); 1419 1404 if (ret) 1420 1405 return ret; 1421 1406 *val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); ··· 1471 1452 int val, int val2) 1472 1453 { 1473 1454 struct bma400_data *data = iio_priv(indio_dev); 1474 - int reg, ret, raw; 1455 + int ret, raw; 1456 + enum bma400_generic_intr genintr; 1457 + const struct bma400_genintr_info *bma400_genintr; 1475 1458 1476 1459 if (chan->type != IIO_ACCEL) 1477 1460 return -EINVAL; 1478 1461 1479 1462 switch (type) { 1480 1463 case IIO_EV_TYPE_MAG: 1481 - reg = get_gen_config_reg(dir); 1482 - if (reg < 0) 1464 + bma400_genintr = get_bma400_genintr_info(dir); 1465 + if (!bma400_genintr) 1483 1466 return -EINVAL; 1467 + genintr = bma400_genintr->genintr; 1484 1468 1485 1469 switch (info) { 1486 1470 case IIO_EV_INFO_VALUE: ··· 1491 1469 return -EINVAL; 1492 1470 1493 1471 return regmap_write(data->regmap, 1494 - reg + BMA400_GEN_CONFIG2_OFF, 1472 + BMA400_GENINT_CONFIG_REG(genintr, 2), 1495 1473 val); 1496 1474 case IIO_EV_INFO_PERIOD: 1497 1475 if (val < 1 || val > 65535) ··· 1500 1478 mutex_lock(&data->mutex); 1501 1479 put_unaligned_be16(val, &data->duration); 1502 1480 ret = regmap_bulk_write(data->regmap, 1503 - reg + BMA400_GEN_CONFIG3_OFF, 1481 + BMA400_GENINT_CONFIG_REG(genintr, 3), 1504 1482 &data->duration, 1505 1483 sizeof(data->duration)); 1506 1484 mutex_unlock(&data->mutex); ··· 1509 1487 if (val < 0 || val > 3) 1510 1488 return -EINVAL; 1511 1489 1512 - return regmap_update_bits(data->regmap, reg, 1490 + return regmap_update_bits(data->regmap, 1491 + BMA400_GENINT_CONFIG_REG(genintr, 0), 1513 1492 BMA400_GENINT_CONFIG0_HYST_MASK, 1514 1493 FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, 1515 1494 val));