Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-qcon-ethqos-rgmii-accessor-cleanups'
Russell King says:
====================
net: stmmac: qcon-ethqos: "rgmii" accessor cleanups
This series cleans up the "rgmii" accessors in qcom-ethqos.
readl() and writel() return and take a u32 for the value. Rather than
implicitly casting this to an int, keep it as a u32.
Add set/clear functions to reduce the code and make it easier to read.
Finally, convert the open-coded poll loops to use the iopoll helpers.
Note that patch 1 has a checkpatch warning concerning "volatile" -
I'm changing the type here, and the "volatile" is removed in patch 3.
I do not feel it is appropriate to remove it in patch 1.
====================
Link: https://patch.msgid.link/aR76i0HjXitfl7xk@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+110
-135
+110
-135
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+110
-135
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
···
116
116
bool needs_sgmii_loopback;
117
117
};
118
118
119
-
static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
119
+
static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
120
120
{
121
121
return readl(ethqos->rgmii_base + offset);
122
122
}
123
123
124
-
static void rgmii_writel(struct qcom_ethqos *ethqos,
125
-
int value, unsigned int offset)
124
+
static void rgmii_writel(struct qcom_ethqos *ethqos, u32 value,
125
+
unsigned int offset)
126
126
{
127
127
writel(value, ethqos->rgmii_base + offset);
128
128
}
129
129
130
-
static void rgmii_updatel(struct qcom_ethqos *ethqos,
131
-
int mask, int val, unsigned int offset)
130
+
static void rgmii_updatel(struct qcom_ethqos *ethqos, u32 mask, u32 val,
131
+
unsigned int offset)
132
132
{
133
-
unsigned int temp;
133
+
u32 temp;
134
134
135
135
temp = rgmii_readl(ethqos, offset);
136
136
temp = (temp & ~(mask)) | val;
137
137
rgmii_writel(ethqos, temp, offset);
138
+
}
139
+
140
+
static void rgmii_setmask(struct qcom_ethqos *ethqos, u32 mask,
141
+
unsigned int offset)
142
+
{
143
+
rgmii_updatel(ethqos, mask, mask, offset);
144
+
}
145
+
146
+
static void rgmii_clrmask(struct qcom_ethqos *ethqos, u32 mask,
147
+
unsigned int offset)
148
+
{
149
+
rgmii_updatel(ethqos, mask, 0, offset);
138
150
}
139
151
140
152
static void rgmii_dump(void *priv)
···
206
194
static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
207
195
{
208
196
qcom_ethqos_set_sgmii_loopback(ethqos, true);
209
-
rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
210
-
RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
197
+
rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
211
198
}
212
199
213
200
static const struct ethqos_emac_por emac_v2_3_0_por[] = {
···
311
300
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
312
301
{
313
302
struct device *dev = ðqos->pdev->dev;
314
-
unsigned int val;
315
-
int retry = 1000;
303
+
u32 val;
316
304
317
305
/* Set CDR_EN */
318
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
319
-
SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
306
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
320
307
321
308
/* Set CDR_EXT_EN */
322
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
323
-
SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
309
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
310
+
SDCC_HC_REG_DLL_CONFIG);
324
311
325
312
/* Clear CK_OUT_EN */
326
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
327
-
0, SDCC_HC_REG_DLL_CONFIG);
313
+
rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
314
+
SDCC_HC_REG_DLL_CONFIG);
328
315
329
316
/* Set DLL_EN */
330
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
331
-
SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
317
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
332
318
333
319
if (!ethqos->has_emac_ge_3) {
334
-
rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
335
-
0, SDCC_HC_REG_DLL_CONFIG);
320
+
rgmii_clrmask(ethqos, SDCC_DLL_MCLK_GATING_EN,
321
+
SDCC_HC_REG_DLL_CONFIG);
336
322
337
-
rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
338
-
0, SDCC_HC_REG_DLL_CONFIG);
323
+
rgmii_clrmask(ethqos, SDCC_DLL_CDR_FINE_PHASE,
324
+
SDCC_HC_REG_DLL_CONFIG);
339
325
}
340
326
341
327
/* Wait for CK_OUT_EN clear */
342
-
do {
343
-
val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
344
-
val &= SDCC_DLL_CONFIG_CK_OUT_EN;
345
-
if (!val)
346
-
break;
347
-
mdelay(1);
348
-
retry--;
349
-
} while (retry > 0);
350
-
if (!retry)
328
+
if (read_poll_timeout_atomic(rgmii_readl, val,
329
+
!(val & SDCC_DLL_CONFIG_CK_OUT_EN),
330
+
1000, 1000000, false,
331
+
ethqos, SDCC_HC_REG_DLL_CONFIG))
351
332
dev_err(dev, "Clear CK_OUT_EN timedout\n");
352
333
353
334
/* Set CK_OUT_EN */
354
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
355
-
SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
335
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
336
+
SDCC_HC_REG_DLL_CONFIG);
356
337
357
338
/* Wait for CK_OUT_EN set */
358
-
retry = 1000;
359
-
do {
360
-
val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
361
-
val &= SDCC_DLL_CONFIG_CK_OUT_EN;
362
-
if (val)
363
-
break;
364
-
mdelay(1);
365
-
retry--;
366
-
} while (retry > 0);
367
-
if (!retry)
339
+
if (read_poll_timeout_atomic(rgmii_readl, val,
340
+
val & SDCC_DLL_CONFIG_CK_OUT_EN,
341
+
1000, 1000000, false,
342
+
ethqos, SDCC_HC_REG_DLL_CONFIG))
368
343
dev_err(dev, "Set CK_OUT_EN timedout\n");
369
344
370
345
/* Set DDR_CAL_EN */
371
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
372
-
SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
346
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
347
+
SDCC_HC_REG_DLL_CONFIG2);
373
348
374
349
if (!ethqos->has_emac_ge_3) {
375
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
376
-
0, SDCC_HC_REG_DLL_CONFIG2);
350
+
rgmii_clrmask(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
351
+
SDCC_HC_REG_DLL_CONFIG2);
377
352
378
353
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
379
354
0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
···
367
370
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
368
371
BIT(2), SDCC_HC_REG_DLL_CONFIG2);
369
372
370
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
371
-
SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
373
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
372
374
SDCC_HC_REG_DLL_CONFIG2);
373
375
}
374
376
···
388
392
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
389
393
390
394
/* Disable loopback mode */
391
-
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
392
-
0, RGMII_IO_MACRO_CONFIG2);
395
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
396
+
RGMII_IO_MACRO_CONFIG2);
393
397
394
398
/* Determine if this platform wants loopback enabled after programming */
395
399
if (ethqos->rgmii_config_loopback_en)
···
398
402
loopback = 0;
399
403
400
404
/* Select RGMII, write 0 to interface select */
401
-
rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
402
-
0, RGMII_IO_MACRO_CONFIG);
405
+
rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG);
403
406
404
407
switch (speed) {
405
408
case SPEED_1000:
406
-
rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
407
-
RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
408
-
rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
409
-
0, RGMII_IO_MACRO_CONFIG);
410
-
rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
411
-
RGMII_CONFIG_POS_NEG_DATA_SEL,
409
+
rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
412
410
RGMII_IO_MACRO_CONFIG);
413
-
rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
414
-
RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
415
-
rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
416
-
0, RGMII_IO_MACRO_CONFIG2);
411
+
rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
412
+
RGMII_IO_MACRO_CONFIG);
413
+
rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
414
+
RGMII_IO_MACRO_CONFIG);
415
+
rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP,
416
+
RGMII_IO_MACRO_CONFIG);
417
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
418
+
RGMII_IO_MACRO_CONFIG2);
417
419
418
420
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
419
421
phase_shift, RGMII_IO_MACRO_CONFIG2);
420
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
421
-
0, RGMII_IO_MACRO_CONFIG2);
422
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
423
-
RGMII_CONFIG2_RX_PROG_SWAP,
422
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
423
+
RGMII_IO_MACRO_CONFIG2);
424
+
rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
424
425
RGMII_IO_MACRO_CONFIG2);
425
426
426
427
/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
···
432
439
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
433
440
57, SDCC_HC_REG_DDR_CONFIG);
434
441
}
435
-
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
436
-
SDCC_DDR_CONFIG_PRG_DLY_EN,
442
+
rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
437
443
SDCC_HC_REG_DDR_CONFIG);
438
444
rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
439
445
loopback, RGMII_IO_MACRO_CONFIG);
440
446
break;
441
447
442
448
case SPEED_100:
443
-
rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
444
-
RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
445
-
rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
446
-
RGMII_CONFIG_BYPASS_TX_ID_EN,
449
+
rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
447
450
RGMII_IO_MACRO_CONFIG);
448
-
rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
449
-
0, RGMII_IO_MACRO_CONFIG);
450
-
rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
451
-
0, RGMII_IO_MACRO_CONFIG);
452
-
rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
453
-
0, RGMII_IO_MACRO_CONFIG2);
451
+
rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
452
+
RGMII_IO_MACRO_CONFIG);
453
+
rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
454
+
RGMII_IO_MACRO_CONFIG);
455
+
rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
456
+
RGMII_IO_MACRO_CONFIG);
457
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
458
+
RGMII_IO_MACRO_CONFIG2);
454
459
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
455
460
phase_shift, RGMII_IO_MACRO_CONFIG2);
456
461
rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
457
462
BIT(6), RGMII_IO_MACRO_CONFIG);
458
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
459
-
0, RGMII_IO_MACRO_CONFIG2);
463
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
464
+
RGMII_IO_MACRO_CONFIG2);
460
465
461
466
if (ethqos->has_emac_ge_3)
462
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
463
-
RGMII_CONFIG2_RX_PROG_SWAP,
467
+
rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
464
468
RGMII_IO_MACRO_CONFIG2);
465
469
else
466
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
467
-
0, RGMII_IO_MACRO_CONFIG2);
470
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
471
+
RGMII_IO_MACRO_CONFIG2);
468
472
469
473
/* Write 0x5 to PRG_RCLK_DLY_CODE */
470
474
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
471
475
(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
472
-
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
473
-
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
476
+
rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
474
477
SDCC_HC_REG_DDR_CONFIG);
475
-
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
476
-
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
478
+
rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
477
479
SDCC_HC_REG_DDR_CONFIG);
478
480
rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
479
481
loopback, RGMII_IO_MACRO_CONFIG);
480
482
break;
481
483
482
484
case SPEED_10:
483
-
rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
484
-
RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
485
-
rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
486
-
RGMII_CONFIG_BYPASS_TX_ID_EN,
485
+
rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
487
486
RGMII_IO_MACRO_CONFIG);
488
-
rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
489
-
0, RGMII_IO_MACRO_CONFIG);
490
-
rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
491
-
0, RGMII_IO_MACRO_CONFIG);
492
-
rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
493
-
0, RGMII_IO_MACRO_CONFIG2);
487
+
rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
488
+
RGMII_IO_MACRO_CONFIG);
489
+
rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
490
+
RGMII_IO_MACRO_CONFIG);
491
+
rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
492
+
RGMII_IO_MACRO_CONFIG);
493
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
494
+
RGMII_IO_MACRO_CONFIG2);
494
495
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
495
496
phase_shift, RGMII_IO_MACRO_CONFIG2);
496
497
rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
497
498
BIT(12) | GENMASK(9, 8),
498
499
RGMII_IO_MACRO_CONFIG);
499
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
500
-
0, RGMII_IO_MACRO_CONFIG2);
500
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
501
+
RGMII_IO_MACRO_CONFIG2);
501
502
if (ethqos->has_emac_ge_3)
502
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
503
-
RGMII_CONFIG2_RX_PROG_SWAP,
503
+
rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
504
504
RGMII_IO_MACRO_CONFIG2);
505
505
else
506
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
507
-
0, RGMII_IO_MACRO_CONFIG2);
506
+
rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
507
+
RGMII_IO_MACRO_CONFIG2);
508
508
/* Write 0x5 to PRG_RCLK_DLY_CODE */
509
509
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
510
510
(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
511
-
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
512
-
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
511
+
rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
513
512
SDCC_HC_REG_DDR_CONFIG);
514
-
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
515
-
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
513
+
rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
516
514
SDCC_HC_REG_DDR_CONFIG);
517
515
rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
518
516
loopback, RGMII_IO_MACRO_CONFIG);
···
519
535
static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)
520
536
{
521
537
struct device *dev = ðqos->pdev->dev;
522
-
volatile unsigned int dll_lock;
523
-
unsigned int i, retry = 1000;
538
+
unsigned int i;
539
+
u32 val;
524
540
525
541
/* Reset to POR values and enable clk */
526
542
for (i = 0; i < ethqos->num_por; i++)
···
531
547
/* Initialize the DLL first */
532
548
533
549
/* Set DLL_RST */
534
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
535
-
SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
550
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_RST,
551
+
SDCC_HC_REG_DLL_CONFIG);
536
552
537
553
/* Set PDN */
538
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
539
-
SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
554
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_PDN,
555
+
SDCC_HC_REG_DLL_CONFIG);
540
556
541
557
if (ethqos->has_emac_ge_3) {
542
558
if (speed == SPEED_1000) {
···
550
566
}
551
567
552
568
/* Clear DLL_RST */
553
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
554
-
SDCC_HC_REG_DLL_CONFIG);
569
+
rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
555
570
556
571
/* Clear PDN */
557
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
558
-
SDCC_HC_REG_DLL_CONFIG);
572
+
rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
559
573
560
574
if (speed != SPEED_100 && speed != SPEED_10) {
561
575
/* Set DLL_EN */
562
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
563
-
SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
576
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN,
577
+
SDCC_HC_REG_DLL_CONFIG);
564
578
565
579
/* Set CK_OUT_EN */
566
-
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
567
-
SDCC_DLL_CONFIG_CK_OUT_EN,
580
+
rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
568
581
SDCC_HC_REG_DLL_CONFIG);
569
582
570
583
/* Set USR_CTL bit 26 with mask of 3 bits */
···
570
589
SDCC_USR_CTL);
571
590
572
591
/* wait for DLL LOCK */
573
-
do {
574
-
mdelay(1);
575
-
dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
576
-
if (dll_lock & SDC4_STATUS_DLL_LOCK)
577
-
break;
578
-
retry--;
579
-
} while (retry > 0);
580
-
if (!retry)
592
+
if (read_poll_timeout_atomic(rgmii_readl, val,
593
+
val & SDC4_STATUS_DLL_LOCK,
594
+
1000, 1000000, true,
595
+
ethqos, SDC4_STATUS))
581
596
dev_err(dev, "Timeout while waiting for DLL lock\n");
582
597
}
583
598
···
608
631
609
632
switch (speed) {
610
633
case SPEED_2500:
611
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
612
-
RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
634
+
rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
613
635
RGMII_IO_MACRO_CONFIG2);
614
636
ethqos_set_serdes_speed(ethqos, SPEED_2500);
615
637
ethqos_pcs_set_inband(priv, false);
616
638
break;
617
639
case SPEED_1000:
618
-
rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
619
-
RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
640
+
rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
620
641
RGMII_IO_MACRO_CONFIG2);
621
642
ethqos_set_serdes_speed(ethqos, SPEED_1000);
622
643
ethqos_pcs_set_inband(priv, true);