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Merge tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DTS updates for v5.20

This introduces initial support for Lenovo ThinkPad X13s, Qualcomm 8cx
Gen 3 Compute Reference Device, SA8295P Automotive Development Platform,
Xiaomi Mi 5s Plus, five new SC7180 Chrome OS boards, Inforce IFC6560, LG
G7 ThinQ and LG V35 ThinQ.

With IPQ8074 gaining GDSC support, this was expressed in the gcc node
and defined for the USB nodes. The SDHCI reset line was defined to get
the storage devices into a known state.

For MSM8996 interconnect providers, the second DSI interface, resets for
SDHCI are introduced. Support for the Xiaomi Mi 5s Plus is introduced
and the Dragonboard 820c gains definitions for its LEDs.

The MSM8998 platform changes consists of a various cleanup patches, the
FxTec Pro1 is split out from using the MTP dts and Sony Xperia devices
on the "Yoshino" platform gains ToF sensor.

On SC7180 five new Trogdor based boards are added and the description of
keyboard and detachables is improved.

On the SC7280-based Herobrine board DisplayPort is enabled, SPI flash
clock rate is changed, WiFi is enabled and the modem firmware path is
updated. The Villager boards gains touchscreen, and keyboard backlight.

This introduces initial support for the SC8280XP (aka 8cx Gen 3) and
related automotive platforms are introduced, with support for the
Qualcomm reference board, the Lenovo Thinkpad X13s and the SA8295P
Automotive Development Platform.

In addition to a wide range of smaller fixes on the SDM630 and SDM660
platforms, support for the secondary high speed USB controller is
introduced and the Sony Xperia "Nile" platform gains support for the RGB
status LED. Support for the Inforce IFC6560 board is introduced.

On SDM845 the bandwidth monitor for the CPU subsystem is introduced, to
scale LLCC clock rate based on profiling. CPU and cluster idle states
are switched to OSI hierarchical states. DB845c and SHIFT 6mq gains LED
support and new support for the LG G7 ThinQ and LG V35 ThinQ boards are
added.

DLL/DDR configuration for SDHCI nodes are defined for SM6125.

On SM8250 the GPU per-process page tables is enabled and for RB5 the
Light Pulse Generator-based LEDs are added.

The display clock controller is introduced for SM8350.

On SM8450 this introduces the camera clock controller and the UART
typically used for Bluetooth. The interconnect path for the crypto
engine is added to the SCM node, to ensure this is adequately clocked.

The assigned-clock-rate for the display processor is dropped from
several platforms, now that the driver derrives the min and max from the
clock.

In addition to this a wide range of fixes for stylistic issues and
issues discovered through Devicetree binding validation across many
platforms and boards are introduced.

* tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (193 commits)
arm64: dts: qcom: sc8280xp: fix DP PHY node unit addresses
arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clock
arm64: dts: qcom: sc7280: fix PCIe clock reference
docs: arm: index.rst: add google/chromebook-boot-flow
arm64: dts: qcom: msm8996: clean up PCIe PHY node
arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
arm64: dts: qcom: sm8450: drop UFS PHY clock-cells
arm64: dts: qcom: sm8250: drop UFS PHY clock-cells
arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells
arm64: dts: qcom: sm8450: drop USB PHY clock index
arm64: dts: qcom: sm8350: drop USB PHY clock index
arm64: dts: qcom: msm8998: drop USB PHY clock index
arm64: dts: qcom: ipq8074: drop USB PHY clock index
arm64: dts: qcom: ipq6018: drop USB PHY clock index
arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells
arm64: dts: qcom: sc7280: drop PCIe PHY clock index
Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"
arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHY
arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domains
arm64: dts: qcom: msm8996: add missing DSI clock assignments
...

Link: https://lore.kernel.org/r/20220713203939.1431054-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann e0a59250 8c1e9736

+11373 -1634
+69
Documentation/arm/google/chromebook-boot-flow.rst
··· 1 + .. SPDX-License-Identifier: GPL-2.0 2 + 3 + ====================================== 4 + Chromebook Boot Flow 5 + ====================================== 6 + 7 + Most recent Chromebooks that use device tree are using the opensource 8 + depthcharge_ bootloader. Depthcharge_ expects the OS to be packaged as a `FIT 9 + Image`_ which contains an OS image as well as a collection of device trees. It 10 + is up to depthcharge_ to pick the right device tree from the `FIT Image`_ and 11 + provide it to the OS. 12 + 13 + The scheme that depthcharge_ uses to pick the device tree takes into account 14 + three variables: 15 + 16 + - Board name, specified at depthcharge_ compile time. This is $(BOARD) below. 17 + - Board revision number, determined at runtime (perhaps by reading GPIO 18 + strappings, perhaps via some other method). This is $(REV) below. 19 + - SKU number, read from GPIO strappings at boot time. This is $(SKU) below. 20 + 21 + For recent Chromebooks, depthcharge_ creates a match list that looks like this: 22 + 23 + - google,$(BOARD)-rev$(REV)-sku$(SKU) 24 + - google,$(BOARD)-rev$(REV) 25 + - google,$(BOARD)-sku$(SKU) 26 + - google,$(BOARD) 27 + 28 + Note that some older Chromebooks use a slightly different list that may 29 + not include SKU matching or may prioritize SKU/rev differently. 30 + 31 + Note that for some boards there may be extra board-specific logic to inject 32 + extra compatibles into the list, but this is uncommon. 33 + 34 + Depthcharge_ will look through all device trees in the `FIT Image`_ trying to 35 + find one that matches the most specific compatible. It will then look 36 + through all device trees in the `FIT Image`_ trying to find the one that 37 + matches the *second most* specific compatible, etc. 38 + 39 + When searching for a device tree, depthcharge_ doesn't care where the 40 + compatible string falls within a device tree's root compatible string array. 41 + As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device 42 + trees: 43 + 44 + - "google,lazor-rev5-sku0", "google,lazor-rev4-sku0", "qcom,sc7180" 45 + - "google,lazor", "qcom,sc7180" 46 + 47 + Then depthcharge_ will pick the first device tree even though 48 + "google,lazor-rev4-sku0" was the second compatible listed in that device tree. 49 + This is because it is a more specific compatible than "google,lazor". 50 + 51 + It should be noted that depthcharge_ does not have any smarts to try to 52 + match board or SKU revisions that are "close by". That is to say that 53 + if depthcharge_ knows it's on "rev4" of a board but there is no "rev4" 54 + device tree then depthcharge_ *won't* look for a "rev3" device tree. 55 + 56 + In general when any significant changes are made to a board the board 57 + revision number is increased even if none of those changes need to 58 + be reflected in the device tree. Thus it's fairly common to see device 59 + trees with multiple revisions. 60 + 61 + It should be noted that, taking into account the above system that 62 + depthcharge_ has, the most flexibility is achieved if the device tree 63 + supporting the newest revision(s) of a board omits the "-rev{REV}" 64 + compatible strings. When this is done then if you get a new board 65 + revision and try to run old software on it then we'll at pick the 66 + newest device tree we know about. 67 + 68 + .. _depthcharge: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/depthcharge/ 69 + .. _`FIT Image`: https://doc.coreboot.org/lib/payloads/fit.html
+2
Documentation/arm/index.rst
··· 31 31 .. toctree:: 32 32 :maxdepth: 1 33 33 34 + google/chromebook-boot-flow 35 + 34 36 ixp4xx 35 37 36 38 marvell
+321 -9
Documentation/devicetree/bindings/arm/qcom.yaml
··· 44 44 sc7280 45 45 sc8180x 46 46 sc8280xp 47 + sda660 47 48 sdm630 48 49 sdm632 49 50 sdm660 ··· 90 89 91 90 A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in 92 91 foundry 2. 92 + 93 + There are many devices in the list below that run the standard ChromeOS 94 + bootloader setup and use the open source depthcharge bootloader to boot the 95 + OS. These devices do not use the scheme described above. For details, see: 96 + https://docs.kernel.org/arm/google/chromebook-boot-flow.html 93 97 94 98 properties: 95 99 $nodename: ··· 196 190 - sony,kagura-row 197 191 - sony,keyaki-row 198 192 - xiaomi,gemini 193 + - xiaomi,natrium 199 194 - xiaomi,scorpio 200 195 - const: qcom,msm8996 201 196 ··· 221 214 - qcom,ipq8074-hk10-c2 222 215 - const: qcom,ipq8074 223 216 224 - - items: 217 + - description: Qualcomm Technologies, Inc. SC7180 IDP 218 + items: 225 219 - enum: 226 220 - qcom,sc7180-idp 227 221 - const: qcom,sc7180 228 222 229 - - items: 230 - - enum: 231 - - qcom,sc7280-crd 232 - - qcom,sc7280-idp 233 - - qcom,sc7280-idp2 234 - - google,hoglin 235 - - google,piglin 236 - - google,senor 223 + - description: HP Chromebook x2 11c (rev1 - 2) 224 + items: 225 + - const: google,coachz-rev1 226 + - const: google,coachz-rev2 227 + - const: qcom,sc7180 228 + 229 + - description: HP Chromebook x2 11c (newest rev) 230 + items: 231 + - const: google,coachz 232 + - const: qcom,sc7180 233 + 234 + - description: HP Chromebook x2 11c with LTE (rev1 - 2) 235 + items: 236 + - const: google,coachz-rev1-sku0 237 + - const: google,coachz-rev2-sku0 238 + - const: qcom,sc7180 239 + 240 + - description: HP Chromebook x2 11c with LTE (newest rev) 241 + items: 242 + - const: google,coachz-sku0 243 + - const: qcom,sc7180 244 + 245 + - description: Lenovo Chromebook Duet 5 13 (rev2) 246 + items: 247 + - const: google,homestar-rev2 248 + - const: google,homestar-rev23 249 + - const: qcom,sc7180 250 + 251 + - description: Lenovo Chromebook Duet 5 13 (rev3) 252 + items: 253 + - const: google,homestar-rev3 254 + - const: qcom,sc7180 255 + 256 + - description: Lenovo Chromebook Duet 5 13 (newest rev) 257 + items: 258 + - const: google,homestar 259 + - const: qcom,sc7180 260 + 261 + - description: Google Kingoftown (rev0) 262 + items: 263 + - const: google,kingoftown-rev0 264 + - const: qcom,sc7180 265 + 266 + - description: Google Kingoftown (newest rev) 267 + items: 268 + - const: google,kingoftown 269 + - const: qcom,sc7180 270 + 271 + - description: Acer Chromebook Spin 513 (rev0) 272 + items: 273 + - const: google,lazor-rev0 274 + - const: qcom,sc7180 275 + 276 + - description: Acer Chromebook Spin 513 (rev1 - 2) 277 + items: 278 + - const: google,lazor-rev1 279 + - const: google,lazor-rev2 280 + - const: qcom,sc7180 281 + 282 + - description: Acer Chromebook Spin 513 (rev3 - 8) 283 + items: 284 + - const: google,lazor-rev3 285 + - const: google,lazor-rev4 286 + - const: google,lazor-rev5 287 + - const: google,lazor-rev6 288 + - const: google,lazor-rev7 289 + - const: google,lazor-rev8 290 + - const: qcom,sc7180 291 + 292 + - description: Acer Chromebook Spin 513 (newest rev) 293 + items: 294 + - const: google,lazor 295 + - const: qcom,sc7180 296 + 297 + - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2) 298 + items: 299 + - const: google,lazor-rev1-sku2 300 + - const: google,lazor-rev2-sku2 301 + - const: qcom,sc7180 302 + 303 + - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8) 304 + items: 305 + - const: google,lazor-rev3-sku2 306 + - const: google,lazor-rev4-sku2 307 + - const: google,lazor-rev5-sku2 308 + - const: google,lazor-rev6-sku2 309 + - const: google,lazor-rev7-sku2 310 + - const: google,lazor-rev8-sku2 311 + - const: qcom,sc7180 312 + 313 + - description: Acer Chromebook Spin 513 with KB Backlight (newest rev) 314 + items: 315 + - const: google,lazor-sku2 316 + - const: qcom,sc7180 317 + 318 + - description: Acer Chromebook Spin 513 with LTE (rev1 - 2) 319 + items: 320 + - const: google,lazor-rev1-sku0 321 + - const: google,lazor-rev2-sku0 322 + - const: qcom,sc7180 323 + 324 + - description: Acer Chromebook Spin 513 with LTE (rev3 - 8) 325 + items: 326 + - const: google,lazor-rev3-sku0 327 + - const: google,lazor-rev4-sku0 328 + - const: google,lazor-rev5-sku0 329 + - const: google,lazor-rev6-sku0 330 + - const: google,lazor-rev7-sku0 331 + - const: google,lazor-rev8-sku0 332 + - const: qcom,sc7180 333 + 334 + - description: Acer Chromebook Spin 513 with LTE (newest rev) 335 + items: 336 + - const: google,lazor-sku0 337 + - const: qcom,sc7180 338 + 339 + - description: Acer Chromebook 511 (rev4 - rev8) 340 + items: 341 + - const: google,lazor-rev4-sku4 342 + - const: google,lazor-rev5-sku4 343 + - const: google,lazor-rev6-sku4 344 + - const: google,lazor-rev7-sku4 345 + - const: google,lazor-rev8-sku4 346 + - const: qcom,sc7180 347 + 348 + - description: Acer Chromebook 511 (newest rev) 349 + items: 350 + - const: google,lazor-sku4 351 + - const: qcom,sc7180 352 + 353 + - description: Acer Chromebook 511 without Touchscreen (rev4) 354 + items: 355 + - const: google,lazor-rev4-sku5 356 + - const: qcom,sc7180 357 + 358 + - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8) 359 + items: 360 + - const: google,lazor-rev5-sku5 361 + - const: google,lazor-rev5-sku6 362 + - const: google,lazor-rev6-sku6 363 + - const: google,lazor-rev7-sku6 364 + - const: google,lazor-rev8-sku6 365 + - const: qcom,sc7180 366 + 367 + - description: Acer Chromebook 511 without Touchscreen (newest rev) 368 + items: 369 + - const: google,lazor-sku6 370 + - const: qcom,sc7180 371 + 372 + - description: Google Mrbland with AUO panel (rev0) 373 + items: 374 + - const: google,mrbland-rev0-sku0 375 + - const: qcom,sc7180 376 + 377 + - description: Google Mrbland with AUO panel (newest rev) 378 + items: 379 + - const: google,mrbland-sku1536 380 + - const: qcom,sc7180 381 + 382 + - description: Google Mrbland with BOE panel (rev0) 383 + items: 384 + - const: google,mrbland-rev0-sku16 385 + - const: qcom,sc7180 386 + 387 + - description: Google Mrbland with BOE panel (newest rev) 388 + items: 389 + - const: google,mrbland-sku1024 390 + - const: google,mrbland-sku768 391 + - const: qcom,sc7180 392 + 393 + - description: Google Pazquel with Parade (newest rev) 394 + items: 395 + - const: google,pazquel-sku5 396 + - const: qcom,sc7180 397 + 398 + - description: Google Pazquel with TI (newest rev) 399 + items: 400 + - const: google,pazquel-sku1 401 + - const: qcom,sc7180 402 + 403 + - description: Google Pazquel with LTE and Parade (newest rev) 404 + items: 405 + - const: google,pazquel-sku4 406 + - const: qcom,sc7180 407 + 408 + - description: Google Pazquel with LTE and TI (newest rev) 409 + items: 410 + - const: google,pazquel-sku0 411 + - const: google,pazquel-sku2 412 + - const: qcom,sc7180 413 + 414 + - description: Sharp Dynabook Chromebook C1 (rev1) 415 + items: 416 + - const: google,pompom-rev1 417 + - const: qcom,sc7180 418 + 419 + - description: Sharp Dynabook Chromebook C1 (rev2) 420 + items: 421 + - const: google,pompom-rev2 422 + - const: qcom,sc7180 423 + 424 + - description: Sharp Dynabook Chromebook C1 (newest rev) 425 + items: 426 + - const: google,pompom 427 + - const: qcom,sc7180 428 + 429 + - description: Sharp Dynabook Chromebook C1 with LTE (rev1) 430 + items: 431 + - const: google,pompom-rev1-sku0 432 + - const: qcom,sc7180 433 + 434 + - description: Sharp Dynabook Chromebook C1 with LTE (rev2) 435 + items: 436 + - const: google,pompom-rev2-sku0 437 + - const: qcom,sc7180 438 + 439 + - description: Sharp Dynabook Chromebook C1 with LTE (newest rev) 440 + items: 441 + - const: google,pompom-sku0 442 + - const: qcom,sc7180 443 + 444 + - description: Google Quackingstick (newest rev) 445 + items: 446 + - const: google,quackingstick-sku1537 447 + - const: qcom,sc7180 448 + 449 + - description: Google Quackingstick with LTE (newest rev) 450 + items: 451 + - const: google,quackingstick-sku1536 452 + - const: qcom,sc7180 453 + 454 + - description: Google Trogdor (newest rev) 455 + items: 456 + - const: google,trogdor 457 + - const: qcom,sc7180 458 + 459 + - description: Google Trogdor with LTE (newest rev) 460 + items: 461 + - const: google,trogdor-sku0 462 + - const: qcom,sc7180 463 + 464 + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0) 465 + items: 466 + - const: google,wormdingler-rev0-sku16 467 + - const: qcom,sc7180 468 + 469 + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev) 470 + items: 471 + - const: google,wormdingler-sku1024 472 + - const: qcom,sc7180 473 + 474 + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev) 475 + items: 476 + - const: google,wormdingler-sku1025 477 + - const: qcom,sc7180 478 + 479 + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0) 480 + items: 481 + - const: google,wormdingler-rev0-sku0 482 + - const: qcom,sc7180 483 + 484 + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev) 485 + items: 486 + - const: google,wormdingler-sku0 487 + - const: qcom,sc7180 488 + 489 + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev) 490 + items: 491 + - const: google,wormdingler-sku1 492 + - const: qcom,sc7180 493 + 494 + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4) 495 + items: 496 + - const: qcom,sc7280-crd 497 + - const: google,hoglin-rev3 498 + - const: google,hoglin-rev4 499 + - const: google,piglin-rev3 500 + - const: google,piglin-rev4 501 + - const: qcom,sc7280 502 + 503 + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) 504 + items: 505 + - const: google,hoglin 506 + - const: qcom,sc7280 507 + 508 + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform 509 + items: 510 + - const: qcom,sc7280-idp 511 + - const: google,senor 512 + - const: qcom,sc7280 513 + 514 + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform 515 + items: 516 + - const: qcom,sc7280-idp2 517 + - const: google,piglin 518 + - const: qcom,sc7280 519 + 520 + - description: Google Herobrine (newest rev) 521 + items: 522 + - const: google,herobrine 523 + - const: qcom,sc7280 524 + 525 + - description: Google Villager (newest rev) 526 + items: 527 + - const: google,villager 237 528 - const: qcom,sc7280 238 529 239 530 - items: ··· 543 238 544 239 - items: 545 240 - enum: 241 + - lenovo,thinkpad-x13s 242 + - qcom,sc8280xp-crd 546 243 - qcom,sc8280xp-qrd 547 244 - const: qcom,sc8280xp 245 + 246 + - items: 247 + - enum: 248 + - inforce,ifc6560 249 + - const: qcom,sda660 548 250 549 251 - items: 550 252 - enum:
+4 -2
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
··· 4 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 7 + title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 8 8 9 9 maintainers: 10 10 - Jonathan Marek <jonathan@marek.ca> 11 11 12 12 description: | 13 13 Qualcomm display clock control module which supports the clocks, resets and 14 - power domains on SM8150 and SM8250. 14 + power domains on SM8150/SM8250/SM8350. 15 15 16 16 See also: 17 17 dt-bindings/clock/qcom,dispcc-sm8150.h 18 18 dt-bindings/clock/qcom,dispcc-sm8250.h 19 + dt-bindings/clock/qcom,dispcc-sm8350.h 19 20 20 21 properties: 21 22 compatible: ··· 24 23 - qcom,sc8180x-dispcc 25 24 - qcom,sm8150-dispcc 26 25 - qcom,sm8250-dispcc 26 + - qcom,sm8350-dispcc 27 27 28 28 clocks: 29 29 items:
+72
Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Graphics Clock & Reset Controller Binding 8 + 9 + maintainers: 10 + - Robert Foss <robert.foss@linaro.org> 11 + 12 + description: | 13 + Qualcomm graphics clock control module which supports the clocks, resets and 14 + power domains on Qualcomm SoCs. 15 + 16 + See also: 17 + dt-bindings/clock/qcom,gpucc-sm8350.h 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - qcom,sm8350-gpucc 23 + 24 + clocks: 25 + items: 26 + - description: Board XO source 27 + - description: GPLL0 main branch source 28 + - description: GPLL0 div branch source 29 + 30 + '#clock-cells': 31 + const: 1 32 + 33 + '#reset-cells': 34 + const: 1 35 + 36 + '#power-domain-cells': 37 + const: 1 38 + 39 + reg: 40 + maxItems: 1 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - clocks 46 + - '#clock-cells' 47 + - '#reset-cells' 48 + - '#power-domain-cells' 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/clock/qcom,gcc-sm8350.h> 55 + #include <dt-bindings/clock/qcom,rpmh.h> 56 + 57 + soc { 58 + #address-cells = <2>; 59 + #size-cells = <2>; 60 + 61 + clock-controller@3d90000 { 62 + compatible = "qcom,sm8350-gpucc"; 63 + reg = <0 0x03d90000 0 0x9000>; 64 + clocks = <&rpmhcc RPMH_CXO_CLK>, 65 + <&gcc GCC_GPU_GPLL0_CLK_SRC>, 66 + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 67 + #clock-cells = <1>; 68 + #reset-cells = <1>; 69 + #power-domain-cells = <1>; 70 + }; 71 + }; 72 + ...
+80
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Camera Clock & Reset Controller Binding for SM8450 8 + 9 + maintainers: 10 + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> 11 + 12 + description: | 13 + Qualcomm camera clock control module which supports the clocks, resets and 14 + power domains on SM8450. 15 + 16 + See also include/dt-bindings/clock/qcom,sm8450-camcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,sm8450-camcc 21 + 22 + clocks: 23 + items: 24 + - description: Camera AHB clock from GCC 25 + - description: Board XO source 26 + - description: Board active XO source 27 + - description: Sleep clock source 28 + 29 + power-domains: 30 + maxItems: 1 31 + description: 32 + A phandle and PM domain specifier for the MMCX power domain. 33 + 34 + required-opps: 35 + description: 36 + A phandle to an OPP node describing required MMCX performance point. 37 + 38 + '#clock-cells': 39 + const: 1 40 + 41 + '#reset-cells': 42 + const: 1 43 + 44 + '#power-domain-cells': 45 + const: 1 46 + 47 + reg: 48 + maxItems: 1 49 + 50 + required: 51 + - compatible 52 + - reg 53 + - clocks 54 + - power-domains 55 + - required-opps 56 + - '#clock-cells' 57 + - '#reset-cells' 58 + - '#power-domain-cells' 59 + 60 + additionalProperties: false 61 + 62 + examples: 63 + - | 64 + #include <dt-bindings/clock/qcom,gcc-sm8450.h> 65 + #include <dt-bindings/clock/qcom,rpmh.h> 66 + #include <dt-bindings/power/qcom-rpmpd.h> 67 + clock-controller@ade0000 { 68 + compatible = "qcom,sm8450-camcc"; 69 + reg = <0xade0000 0x20000>; 70 + clocks = <&gcc GCC_CAMERA_AHB_CLK>, 71 + <&rpmhcc RPMH_CXO_CLK>, 72 + <&rpmhcc RPMH_CXO_CLK_A>, 73 + <&sleep_clk>; 74 + power-domains = <&rpmhpd SM8450_MMCX>; 75 + required-opps = <&rpmhpd_opp_low_svs>; 76 + #clock-cells = <1>; 77 + #reset-cells = <1>; 78 + #power-domain-cells = <1>; 79 + }; 80 + ...
+1
MAINTAINERS
··· 2540 2540 ARM/QUALCOMM SUPPORT 2541 2541 M: Andy Gross <agross@kernel.org> 2542 2542 M: Bjorn Andersson <bjorn.andersson@linaro.org> 2543 + R: Konrad Dybcio <konrad.dybcio@somainline.org> 2543 2544 L: linux-arm-msm@vger.kernel.org 2544 2545 S: Maintained 2545 2546 T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
+25 -3
arch/arm64/boot/dts/qcom/Makefile
··· 30 30 dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb 31 31 dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb 32 32 dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb 33 - dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-dora.dtb 34 - dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-kagura.dtb 35 - dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb 36 33 dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb 37 34 dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb 38 35 dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb 39 36 dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb 37 + dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-natrium.dtb 40 38 dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb 41 39 dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb 42 40 dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb ··· 50 52 dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb 51 53 dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb 52 54 dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb 55 + dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb 53 56 dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb 54 57 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb 55 58 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb ··· 59 60 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb 60 61 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb 61 62 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb 63 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb 64 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb 62 65 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb 63 66 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb 64 67 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb ··· 76 75 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb 77 76 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb 78 77 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb 78 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb 79 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb 80 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb 81 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb 82 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb 83 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb 84 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb 85 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb 79 86 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb 80 87 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb 81 88 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb 82 89 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb 83 90 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb 84 91 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb 92 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb 93 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb 94 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb 95 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb 96 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb 97 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb 98 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb 99 + dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb 85 100 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb 86 101 dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb 87 102 dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb ··· 106 89 dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb 107 90 dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb 108 91 dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb 92 + dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb 93 + dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb 94 + dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb 109 95 dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb 110 96 dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb 111 97 dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb ··· 120 100 dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb 121 101 dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb 122 102 dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb 103 + dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb 104 + dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb 123 105 dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb 124 106 dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb 125 107 dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb
+23 -13
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
··· 8 8 #include "msm8916-pm8916.dtsi" 9 9 #include <dt-bindings/gpio/gpio.h> 10 10 #include <dt-bindings/input/input.h> 11 + #include <dt-bindings/leds/common.h> 11 12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 12 13 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 13 14 #include <dt-bindings/sound/apq8016-lpass.h> ··· 21 20 serial0 = &blsp1_uart2; 22 21 serial1 = &blsp1_uart1; 23 22 usid0 = &pm8916_0; 24 - i2c0 = &blsp_i2c2; 25 - i2c1 = &blsp_i2c6; 26 - i2c3 = &blsp_i2c4; 27 - spi0 = &blsp_spi5; 28 - spi1 = &blsp_spi3; 23 + i2c0 = &blsp_i2c2; 24 + i2c1 = &blsp_i2c6; 25 + i2c3 = &blsp_i2c4; 26 + spi0 = &blsp_spi5; 27 + spi1 = &blsp_spi3; 29 28 }; 30 29 31 30 chosen { ··· 93 92 94 93 gpio-keys { 95 94 compatible = "gpio-keys"; 96 - #address-cells = <1>; 97 - #size-cells = <0>; 98 95 autorepeat; 99 96 100 97 pinctrl-names = "default"; 101 98 pinctrl-0 = <&msm_key_volp_n_default>; 102 99 103 - button@0 { 100 + button { 104 101 label = "Volume Up"; 105 102 linux,code = <KEY_VOLUMEUP>; 106 103 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; ··· 115 116 116 117 led@1 { 117 118 label = "apq8016-sbc:green:user1"; 119 + function = LED_FUNCTION_HEARTBEAT; 120 + color = <LED_COLOR_ID_GREEN>; 118 121 gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; 119 122 linux,default-trigger = "heartbeat"; 120 123 default-state = "off"; ··· 124 123 125 124 led@2 { 126 125 label = "apq8016-sbc:green:user2"; 126 + function = LED_FUNCTION_DISK_ACTIVITY; 127 + color = <LED_COLOR_ID_GREEN>; 127 128 gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; 128 129 linux,default-trigger = "mmc0"; 129 130 default-state = "off"; ··· 133 130 134 131 led@3 { 135 132 label = "apq8016-sbc:green:user3"; 133 + function = LED_FUNCTION_DISK_ACTIVITY; 134 + color = <LED_COLOR_ID_GREEN>; 136 135 gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; 137 136 linux,default-trigger = "mmc1"; 138 137 default-state = "off"; ··· 142 137 143 138 led@4 { 144 139 label = "apq8016-sbc:green:user4"; 140 + color = <LED_COLOR_ID_GREEN>; 145 141 gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; 146 142 linux,default-trigger = "none"; 147 143 panic-indicator; ··· 151 145 152 146 led@5 { 153 147 label = "apq8016-sbc:yellow:wlan"; 148 + function = LED_FUNCTION_WLAN; 149 + color = <LED_COLOR_ID_YELLOW>; 154 150 gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; 155 151 linux,default-trigger = "phy0tx"; 156 152 default-state = "off"; ··· 160 152 161 153 led@6 { 162 154 label = "apq8016-sbc:blue:bt"; 155 + function = LED_FUNCTION_BLUETOOTH; 156 + color = <LED_COLOR_ID_BLUE>; 163 157 gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; 164 158 linux,default-trigger = "bluetooth-power"; 165 159 default-state = "off"; ··· 783 773 "USB_HUB_RESET_N_PM", 784 774 "USB_SW_SEL_PM"; 785 775 786 - usb_hub_reset_pm: usb-hub-reset-pm { 776 + usb_hub_reset_pm: usb-hub-reset-pm-state { 787 777 pins = "gpio3"; 788 778 function = PMIC_GPIO_FUNC_NORMAL; 789 779 ··· 791 781 output-high; 792 782 }; 793 783 794 - usb_hub_reset_pm_device: usb-hub-reset-pm-device { 784 + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { 795 785 pins = "gpio3"; 796 786 function = PMIC_GPIO_FUNC_NORMAL; 797 787 798 788 output-low; 799 789 }; 800 790 801 - usb_sw_sel_pm: usb-sw-sel-pm { 791 + usb_sw_sel_pm: usb-sw-sel-pm-state { 802 792 pins = "gpio4"; 803 793 function = PMIC_GPIO_FUNC_NORMAL; 804 794 ··· 807 797 output-high; 808 798 }; 809 799 810 - usb_sw_sel_pm_device: usb-sw-sel-pm-device { 800 + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { 811 801 pins = "gpio4"; 812 802 function = PMIC_GPIO_FUNC_NORMAL; 813 803 ··· 816 806 output-low; 817 807 }; 818 808 819 - pm8916_gpios_leds: pm8916-gpios-leds { 809 + pm8916_gpios_leds: pm8916-gpios-leds-state { 820 810 pins = "gpio1", "gpio2"; 821 811 function = PMIC_GPIO_FUNC_NORMAL; 822 812
+73 -18
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
··· 10 10 #include "pmi8994.dtsi" 11 11 #include <dt-bindings/input/input.h> 12 12 #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/leds/common.h> 13 14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 14 15 #include <dt-bindings/sound/qcom,q6afe.h> 15 16 #include <dt-bindings/sound/qcom,q6asm.h> ··· 50 49 serial0 = &blsp2_uart2; 51 50 serial1 = &blsp2_uart3; 52 51 serial2 = &blsp1_uart2; 53 - i2c0 = &blsp1_i2c3; 54 - i2c1 = &blsp2_i2c1; 55 - i2c2 = &blsp2_i2c1; 56 - spi0 = &blsp1_spi1; 57 - spi1 = &blsp2_spi6; 52 + i2c0 = &blsp1_i2c3; 53 + i2c1 = &blsp2_i2c1; 54 + i2c2 = &blsp2_i2c1; 55 + spi0 = &blsp1_spi1; 56 + spi1 = &blsp2_spi6; 58 57 }; 59 58 60 59 chosen { ··· 83 82 }; 84 83 }; 85 84 86 - gpio_keys { 85 + gpio-keys { 87 86 compatible = "gpio-keys"; 88 - #address-cells = <1>; 89 - #size-cells = <0>; 90 87 autorepeat; 91 88 92 89 pinctrl-names = "default"; 93 90 pinctrl-0 = <&volume_up_gpio>; 94 91 95 - button@0 { 92 + button { 96 93 label = "Volume Up"; 97 94 linux,code = <KEY_VOLUMEUP>; 98 95 gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; ··· 554 555 pinctrl-names = "default"; 555 556 pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; 556 557 557 - ls_exp_gpio_f: pm8994_gpio5 { 558 + ls_exp_gpio_f: pm8994-gpio5-state { 558 559 pinconf { 559 560 pins = "gpio5"; 561 + function = PMIC_GPIO_FUNC_NORMAL; 560 562 output-low; 561 563 power-source = <2>; // PM8994_GPIO_S4, 1.8V 562 564 }; 563 565 }; 564 566 565 - bt_en_gpios: bt_en_gpios { 567 + bt_en_gpios: bt-en-pios-state { 566 568 pinconf { 567 569 pins = "gpio19"; 568 570 function = PMIC_GPIO_FUNC_NORMAL; ··· 574 574 }; 575 575 }; 576 576 577 - wlan_en_gpios: wlan_en_gpios { 577 + wlan_en_gpios: wlan-en-gpios-state { 578 578 pinconf { 579 579 pins = "gpio8"; 580 580 function = PMIC_GPIO_FUNC_NORMAL; ··· 585 585 }; 586 586 }; 587 587 588 - audio_mclk: clk_div1 { 588 + audio_mclk: clk-div1-state { 589 589 pinconf { 590 590 pins = "gpio15"; 591 591 function = "func1"; ··· 593 593 }; 594 594 }; 595 595 596 - volume_up_gpio: pm8996_gpio2 { 596 + volume_up_gpio: pm8996-gpio2-state { 597 597 pinconf { 598 598 pins = "gpio2"; 599 599 function = "normal"; ··· 605 605 }; 606 606 }; 607 607 608 - divclk4_pin_a: divclk4 { 608 + divclk4_pin_a: divclk4-state { 609 609 pinconf { 610 610 pins = "gpio18"; 611 611 function = PMIC_GPIO_FUNC_FUNC2; ··· 615 615 }; 616 616 }; 617 617 618 - usb3_vbus_det_gpio: pm8996_gpio22 { 618 + usb3_vbus_det_gpio: pm8996-gpio22-state { 619 619 pinconf { 620 620 pins = "gpio22"; 621 621 function = PMIC_GPIO_FUNC_NORMAL; ··· 671 671 "NC", 672 672 "NC"; 673 673 674 - usb2_vbus_det_gpio: pmi8996_gpio6 { 674 + usb2_vbus_det_gpio: pmi8996-gpio6-state { 675 675 pinconf { 676 676 pins = "gpio6"; 677 677 function = PMIC_GPIO_FUNC_NORMAL; ··· 680 680 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 681 681 power-source = <PM8994_GPIO_S4>; // 1.8V 682 682 }; 683 + }; 684 + }; 685 + 686 + &pmi8994_lpg { 687 + qcom,power-source = <1>; 688 + 689 + pinctrl-names = "default"; 690 + pinctrl-0 = <&pmi8994_mpp2_userled4>; 691 + 692 + qcom,dtest = <0 0>, 693 + <0 0>, 694 + <0 0>, 695 + <4 1>; 696 + 697 + status = "okay"; 698 + 699 + led@1 { 700 + reg = <1>; 701 + color = <LED_COLOR_ID_GREEN>; 702 + function = LED_FUNCTION_HEARTBEAT; 703 + function-enumerator = <1>; 704 + 705 + linux,default-trigger = "heartbeat"; 706 + default-state = "on"; 707 + }; 708 + 709 + led@2 { 710 + reg = <2>; 711 + color = <LED_COLOR_ID_GREEN>; 712 + function = LED_FUNCTION_HEARTBEAT; 713 + function-enumerator = <0>; 714 + }; 715 + 716 + led@3 { 717 + reg = <3>; 718 + color = <LED_COLOR_ID_GREEN>; 719 + function = LED_FUNCTION_HEARTBEAT; 720 + function-enumerator = <2>; 721 + }; 722 + 723 + led@4 { 724 + reg = <4>; 725 + color = <LED_COLOR_ID_GREEN>; 726 + function = LED_FUNCTION_HEARTBEAT; 727 + function-enumerator = <3>; 728 + }; 729 + }; 730 + 731 + &pmi8994_mpps { 732 + pmi8994_mpp2_userled4: mpp2-userled4-state { 733 + pins = "mpp2"; 734 + function = "sink"; 735 + 736 + output-low; 737 + qcom,dtest = <4>; 683 738 }; 684 739 }; 685 740 ··· 1012 957 &sound { 1013 958 compatible = "qcom,apq8096-sndcard"; 1014 959 model = "DB820c"; 1015 - audio-routing = "RX_BIAS", "MCLK", 960 + audio-routing = "RX_BIAS", "MCLK", 1016 961 "MM_DL1", "MultiMedia1 Playback", 1017 962 "MM_DL2", "MultiMedia2 Playback", 1018 963 "MultiMedia3 Capture", "MM_UL3";
+3 -3
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
··· 29 29 status = "okay"; 30 30 }; 31 31 32 - &i2c_1 { 32 + &blsp1_i2c3 { 33 33 pinctrl-0 = <&i2c_1_pins>; 34 34 pinctrl-names = "default"; 35 35 status = "okay"; 36 36 }; 37 37 38 - &spi_0 { 38 + &blsp1_spi1 { 39 39 cs-select = <0>; 40 40 status = "okay"; 41 41 ··· 43 43 #address-cells = <1>; 44 44 #size-cells = <1>; 45 45 reg = <0>; 46 - compatible = "n25q128a11"; 46 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 47 47 spi-max-frequency = <50000000>; 48 48 }; 49 49 };
+21 -20
arch/arm64/boot/dts/qcom/ipq6018.dtsi
··· 87 87 }; 88 88 }; 89 89 90 - cpu_opp_table: cpu_opp_table { 90 + cpu_opp_table: opp-table-cpu { 91 91 compatible = "operating-points-v2"; 92 92 opp-shared; 93 93 ··· 125 125 126 126 firmware { 127 127 scm { 128 - compatible = "qcom,scm"; 128 + compatible = "qcom,scm-ipq6018", "qcom,scm"; 129 129 }; 130 130 }; 131 131 ··· 282 282 status = "disabled"; 283 283 }; 284 284 285 - spi_0: spi@78b5000 { 285 + blsp1_spi1: spi@78b5000 { 286 286 compatible = "qcom,spi-qup-v2.2.1"; 287 287 #address-cells = <1>; 288 288 #size-cells = <0>; ··· 297 297 status = "disabled"; 298 298 }; 299 299 300 - spi_1: spi@78b6000 { 300 + blsp1_spi2: spi@78b6000 { 301 301 compatible = "qcom,spi-qup-v2.2.1"; 302 302 #address-cells = <1>; 303 303 #size-cells = <0>; ··· 312 312 status = "disabled"; 313 313 }; 314 314 315 - i2c_0: i2c@78b6000 { 315 + blsp1_i2c2: i2c@78b6000 { 316 316 compatible = "qcom,i2c-qup-v2.2.1"; 317 317 #address-cells = <1>; 318 318 #size-cells = <0>; ··· 321 321 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 322 322 <&gcc GCC_BLSP1_AHB_CLK>; 323 323 clock-names = "core", "iface"; 324 - clock-frequency = <400000>; 324 + clock-frequency = <400000>; 325 325 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 326 326 dma-names = "tx", "rx"; 327 327 status = "disabled"; 328 328 }; 329 329 330 - i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 330 + blsp1_i2c3: i2c@78b7000 { 331 331 compatible = "qcom,i2c-qup-v2.2.1"; 332 332 #address-cells = <1>; 333 333 #size-cells = <0>; ··· 336 336 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 337 337 <&gcc GCC_BLSP1_AHB_CLK>; 338 338 clock-names = "core", "iface"; 339 - clock-frequency = <400000>; 339 + clock-frequency = <400000>; 340 340 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 341 341 dma-names = "tx", "rx"; 342 342 status = "disabled"; ··· 525 525 }; 526 526 527 527 timer@b120000 { 528 - #address-cells = <2>; 529 - #size-cells = <2>; 530 - ranges; 528 + #address-cells = <1>; 529 + #size-cells = <1>; 530 + ranges = <0 0 0 0x10000000>; 531 531 compatible = "arm,armv7-timer-mem"; 532 532 reg = <0x0 0x0b120000 0x0 0x1000>; 533 533 ··· 535 535 frame-number = <0>; 536 536 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 537 537 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 538 - reg = <0x0 0x0b121000 0x0 0x1000>, 539 - <0x0 0x0b122000 0x0 0x1000>; 538 + reg = <0x0b121000 0x1000>, 539 + <0x0b122000 0x1000>; 540 540 }; 541 541 542 542 frame@b123000 { 543 543 frame-number = <1>; 544 544 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 545 - reg = <0x0 0xb123000 0x0 0x1000>; 545 + reg = <0x0b123000 0x1000>; 546 546 status = "disabled"; 547 547 }; 548 548 549 549 frame@b124000 { 550 550 frame-number = <2>; 551 551 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 552 - reg = <0x0 0x0b124000 0x0 0x1000>; 552 + reg = <0x0b124000 0x1000>; 553 553 status = "disabled"; 554 554 }; 555 555 556 556 frame@b125000 { 557 557 frame-number = <3>; 558 558 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 559 - reg = <0x0 0x0b125000 0x0 0x1000>; 559 + reg = <0x0b125000 0x1000>; 560 560 status = "disabled"; 561 561 }; 562 562 563 563 frame@b126000 { 564 564 frame-number = <4>; 565 565 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 566 - reg = <0x0 0x0b126000 0x0 0x1000>; 566 + reg = <0x0b126000 0x1000>; 567 567 status = "disabled"; 568 568 }; 569 569 570 570 frame@b127000 { 571 571 frame-number = <5>; 572 572 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 573 - reg = <0x0 0x0b127000 0x0 0x1000>; 573 + reg = <0x0b127000 0x1000>; 574 574 status = "disabled"; 575 575 }; 576 576 577 577 frame@b128000 { 578 578 frame-number = <6>; 579 579 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 580 - reg = <0x0 0x0b128000 0x0 0x1000>; 580 + reg = <0x0b128000 0x1000>; 581 581 status = "disabled"; 582 582 }; 583 583 }; ··· 621 621 622 622 glink-edge { 623 623 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 624 + label = "rtr"; 624 625 qcom,remote-pid = <1>; 625 626 mboxes = <&apcs_glb 8>; 626 627 ··· 711 710 <0x0 0x00078800 0x0 0x1F8>, /* PCS */ 712 711 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 713 712 #phy-cells = <0>; 714 - #clock-cells = <1>; 713 + #clock-cells = <0>; 715 714 clocks = <&gcc GCC_USB0_PIPE_CLK>; 716 715 clock-names = "pipe0"; 717 716 clock-output-names = "gcc_usb0_pipe_clk_src";
+24 -18
arch/arm64/boot/dts/qcom/ipq8074.dtsi
··· 119 119 <&xo>; 120 120 clock-names = "aux", "cfg_ahb", "ref"; 121 121 122 - resets = <&gcc GCC_USB1_PHY_BCR>, 122 + resets = <&gcc GCC_USB1_PHY_BCR>, 123 123 <&gcc GCC_USB3PHY_1_PHY_BCR>; 124 124 reset-names = "phy","common"; 125 125 status = "disabled"; ··· 130 130 <0x00058800 0x1f8>, /* PCS */ 131 131 <0x00058600 0x044>; /* PCS misc*/ 132 132 #phy-cells = <0>; 133 - #clock-cells = <1>; 133 + #clock-cells = <0>; 134 134 clocks = <&gcc GCC_USB1_PIPE_CLK>; 135 135 clock-names = "pipe0"; 136 136 clock-output-names = "gcc_usb1_pipe_clk_src"; ··· 162 162 <&xo>; 163 163 clock-names = "aux", "cfg_ahb", "ref"; 164 164 165 - resets = <&gcc GCC_USB0_PHY_BCR>, 165 + resets = <&gcc GCC_USB0_PHY_BCR>, 166 166 <&gcc GCC_USB3PHY_0_PHY_BCR>; 167 167 reset-names = "phy","common"; 168 168 status = "disabled"; ··· 173 173 <0x00078800 0x1f8>, /* PCS */ 174 174 <0x00078600 0x044>; /* PCS misc*/ 175 175 #phy-cells = <0>; 176 - #clock-cells = <1>; 176 + #clock-cells = <0>; 177 177 clocks = <&gcc GCC_USB0_PIPE_CLK>; 178 178 clock-names = "pipe0"; 179 179 clock-output-names = "gcc_usb0_pipe_clk_src"; ··· 347 347 compatible = "qcom,gcc-ipq8074"; 348 348 reg = <0x01800000 0x80000>; 349 349 #clock-cells = <0x1>; 350 + #power-domain-cells = <1>; 350 351 #reset-cells = <0x1>; 351 352 }; 352 353 ··· 376 375 cell-index = <0>; 377 376 }; 378 377 379 - sdhc_1: sdhci@7824900 { 378 + sdhc_1: mmc@7824900 { 380 379 compatible = "qcom,sdhci-msm-v4"; 381 380 reg = <0x7824900 0x500>, <0x7824000 0x800>; 382 381 reg-names = "hc_mem", "core_mem"; ··· 385 384 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 386 385 interrupt-names = "hc_irq", "pwr_irq"; 387 386 388 - clocks = <&xo>, 389 - <&gcc GCC_SDCC1_AHB_CLK>, 390 - <&gcc GCC_SDCC1_APPS_CLK>; 391 - clock-names = "xo", "iface", "core"; 387 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 388 + <&gcc GCC_SDCC1_APPS_CLK>, 389 + <&xo>; 390 + clock-names = "iface", "core", "xo"; 391 + resets = <&gcc GCC_SDCC1_BCR>; 392 392 max-frequency = <384000000>; 393 393 mmc-ddr-1_8v; 394 394 mmc-hs200-1_8v; ··· 536 534 status = "disabled"; 537 535 }; 538 536 539 - qpic_nand: nand@79b0000 { 537 + qpic_nand: nand-controller@79b0000 { 540 538 compatible = "qcom,ipq8074-nand"; 541 539 reg = <0x079b0000 0x10000>; 542 540 #address-cells = <1>; ··· 576 574 assigned-clock-rates = <133330000>, 577 575 <133330000>, 578 576 <19200000>; 577 + 578 + power-domains = <&gcc USB0_GDSC>; 579 579 580 580 resets = <&gcc GCC_USB0_BCR>; 581 581 status = "disabled"; ··· 619 615 <133330000>, 620 616 <19200000>; 621 617 618 + power-domains = <&gcc USB1_GDSC>; 619 + 622 620 resets = <&gcc GCC_USB1_BCR>; 623 621 status = "disabled"; 624 622 ··· 652 646 msi-controller; 653 647 reg = <0x0 0xffd>; 654 648 }; 655 - }; 656 - 657 - timer { 658 - compatible = "arm,armv8-timer"; 659 - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 660 - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 661 - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 662 - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 663 649 }; 664 650 665 651 watchdog: watchdog@b017000 { ··· 844 846 "axi_m_sticky"; 845 847 status = "disabled"; 846 848 }; 849 + }; 850 + 851 + timer { 852 + compatible = "arm,armv8-timer"; 853 + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 854 + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 855 + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 856 + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 847 857 }; 848 858 };
+1 -1
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
··· 27 27 28 28 label = "GPIO Buttons"; 29 29 30 - volume-up { 30 + button-volume-up { 31 31 label = "Volume Up"; 32 32 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 33 33 linux,code = <KEY_VOLUMEUP>;
+2 -2
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
··· 28 28 29 29 label = "GPIO Buttons"; 30 30 31 - volume-up { 31 + button-volume-up { 32 32 label = "Volume Up"; 33 33 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 34 34 linux,code = <KEY_VOLUMEUP>; 35 35 debounce-interval = <15>; 36 36 }; 37 37 38 - volume-down { 38 + button-volume-down { 39 39 label = "Volume Down"; 40 40 gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; 41 41 linux,code = <KEY_VOLUMEDOWN>;
+1 -1
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
··· 39 39 40 40 label = "GPIO Buttons"; 41 41 42 - volume-up { 42 + button-volume-up { 43 43 label = "Volume Up"; 44 44 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 45 45 linux,code = <KEY_VOLUMEUP>;
+1 -1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
··· 39 39 40 40 label = "GPIO Buttons"; 41 41 42 - volume-up { 42 + button-volume-up { 43 43 label = "Volume Up"; 44 44 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 45 45 linux,code = <KEY_VOLUMEUP>;
+1 -1
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
··· 28 28 29 29 label = "GPIO Buttons"; 30 30 31 - volume-up { 31 + button-volume-up { 32 32 label = "Volume Up"; 33 33 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 34 34 linux,code = <KEY_VOLUMEUP>;
+12 -4
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
··· 31 31 32 32 label = "GPIO Buttons"; 33 33 34 - volume-up { 34 + button-volume-up { 35 35 label = "Volume Up"; 36 36 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 37 37 linux,code = <KEY_VOLUMEUP>; 38 38 }; 39 39 40 - home { 40 + button-home { 41 41 label = "Home"; 42 42 gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; 43 43 linux,code = <KEY_HOMEPAGE>; ··· 52 52 53 53 label = "GPIO Hall Effect Sensor"; 54 54 55 - hall-sensor { 55 + event-hall-sensor { 56 56 label = "Hall Effect Sensor"; 57 57 gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; 58 58 linux,input-type = <EV_SW>; ··· 460 460 drive-strength = <2>; 461 461 bias-disable; 462 462 }; 463 + 464 + ts_int_default: ts-int-default { 465 + pins = "gpio13"; 466 + function = "gpio"; 467 + 468 + drive-strength = <2>; 469 + bias-disable; 470 + }; 463 471 }; 464 472 465 473 &pm8916_gpios { 466 - nfc_clk_req: nfc-clk-req { 474 + nfc_clk_req: nfc-clk-req-state { 467 475 pins = "gpio2"; 468 476 function = "func1"; 469 477
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
··· 128 128 drive-strength = <2>; 129 129 bias-disable; 130 130 }; 131 - 132 - ts_int_default: ts-int-default { 133 - pins = "gpio13"; 134 - function = "gpio"; 135 - 136 - drive-strength = <2>; 137 - bias-disable; 138 - }; 139 131 };
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
··· 69 69 drive-strength = <2>; 70 70 bias-disable; 71 71 }; 72 - 73 - ts_int_default: ts-int-default { 74 - pins = "gpio13"; 75 - function = "gpio"; 76 - 77 - drive-strength = <2>; 78 - bias-disable; 79 - }; 80 72 };
+2 -2
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
··· 34 34 35 35 label = "GPIO Buttons"; 36 36 37 - volume-up { 37 + button-volume-up { 38 38 label = "Volume Up"; 39 39 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 40 40 linux,code = <KEY_VOLUMEUP>; 41 41 }; 42 42 43 - home-key { 43 + button-home { 44 44 label = "Home Key"; 45 45 gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; 46 46 linux,code = <KEY_HOMEPAGE>;
+3 -3
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
··· 49 49 50 50 label = "GPIO Buttons"; 51 51 52 - volume-up { 52 + button-volume-up { 53 53 label = "Volume Up"; 54 54 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 55 55 linux,code = <KEY_VOLUMEUP>; 56 56 }; 57 57 58 - home { 58 + button-home { 59 59 label = "Home"; 60 60 gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; 61 61 linux,code = <KEY_HOMEPAGE>; ··· 70 70 71 71 label = "GPIO Hall Effect Sensor"; 72 72 73 - hall-sensor { 73 + event-hall-sensor { 74 74 label = "Hall Effect Sensor"; 75 75 gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; 76 76 linux,input-type = <EV_SW>;
+1 -1
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
··· 29 29 30 30 label = "GPIO Buttons"; 31 31 32 - volume-up { 32 + button-volume-up { 33 33 label = "Volume Up"; 34 34 gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; 35 35 linux,code = <KEY_VOLUMEUP>;
+16 -12
arch/arm64/boot/dts/qcom/msm8916.dtsi
··· 216 216 }; 217 217 }; 218 218 219 - cpu_opp_table: cpu-opp-table { 219 + cpu_opp_table: opp-table-cpu { 220 220 compatible = "operating-points-v2"; 221 221 opp-shared; 222 222 ··· 301 301 rpmcc: clock-controller { 302 302 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 303 303 #clock-cells = <1>; 304 + clocks = <&xo_board>; 305 + clock-names = "xo"; 304 306 }; 305 307 306 308 rpmpd: power-controller { ··· 438 436 }; 439 437 440 438 qfprom: qfprom@5c000 { 441 - compatible = "qcom,qfprom"; 439 + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 442 440 reg = <0x0005c000 0x1000>; 443 441 #address-cells = <1>; 444 442 #size-cells = <1>; ··· 1466 1464 #sound-dai-cells = <1>; 1467 1465 }; 1468 1466 1469 - sdhc_1: sdhci@7824000 { 1467 + sdhc_1: mmc@7824000 { 1470 1468 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1471 1469 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1472 1470 reg-names = "hc_mem", "core_mem"; ··· 1474 1472 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1475 1473 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1476 1474 interrupt-names = "hc_irq", "pwr_irq"; 1477 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1478 - <&gcc GCC_SDCC1_AHB_CLK>, 1475 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1476 + <&gcc GCC_SDCC1_APPS_CLK>, 1479 1477 <&xo_board>; 1480 - clock-names = "core", "iface", "xo"; 1478 + clock-names = "iface", "core", "xo"; 1481 1479 mmc-ddr-1_8v; 1482 1480 bus-width = <8>; 1483 1481 non-removable; 1484 1482 status = "disabled"; 1485 1483 }; 1486 1484 1487 - sdhc_2: sdhci@7864000 { 1485 + sdhc_2: mmc@7864000 { 1488 1486 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1489 1487 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1490 1488 reg-names = "hc_mem", "core_mem"; ··· 1492 1490 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1493 1491 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1494 1492 interrupt-names = "hc_irq", "pwr_irq"; 1495 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1496 - <&gcc GCC_SDCC2_AHB_CLK>, 1493 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1494 + <&gcc GCC_SDCC2_APPS_CLK>, 1497 1495 <&xo_board>; 1498 - clock-names = "core", "iface", "xo"; 1496 + clock-names = "iface", "core", "xo"; 1499 1497 bus-width = <4>; 1500 1498 status = "disabled"; 1501 1499 }; ··· 1790 1788 <&rpmpd MSM8916_VDDMX>; 1791 1789 power-domain-names = "cx", "mx"; 1792 1790 1793 - qcom,state = <&wcnss_smp2p_out 0>; 1794 - qcom,state-names = "stop"; 1791 + qcom,smem-states = <&wcnss_smp2p_out 0>; 1792 + qcom,smem-state-names = "stop"; 1795 1793 1796 1794 pinctrl-names = "default"; 1797 1795 pinctrl-0 = <&wcnss_pin_a>; ··· 1860 1858 compatible = "qcom,msm8916-a53pll"; 1861 1859 reg = <0x0b016000 0x40>; 1862 1860 #clock-cells = <0>; 1861 + clocks = <&xo_board>; 1862 + clock-names = "xo"; 1863 1863 }; 1864 1864 1865 1865 timer@b020000 {
+3 -3
arch/arm64/boot/dts/qcom/msm8953.dtsi
··· 215 215 216 216 firmware { 217 217 scm: scm { 218 - compatible = "qcom,scm-msm8953"; 218 + compatible = "qcom,scm-msm8953", "qcom,scm"; 219 219 clocks = <&gcc GCC_CRYPTO_CLK>, 220 220 <&gcc GCC_CRYPTO_AXI_CLK>, 221 221 <&gcc GCC_CRYPTO_AHB_CLK>; ··· 795 795 }; 796 796 }; 797 797 798 - sdhc_1: sdhci@7824900 { 798 + sdhc_1: mmc@7824900 { 799 799 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 800 800 801 801 reg = <0x7824900 0x500>, <0x7824000 0x800>; ··· 855 855 }; 856 856 }; 857 857 858 - sdhc_2: sdhci@7864900 { 858 + sdhc_2: mmc@7864900 { 859 859 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 860 860 861 861 reg = <0x7864900 0x500>, <0x7864000 0x800>;
+1 -1
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
··· 74 74 vdd_l17_29-supply = <&vph_pwr>; 75 75 vdd_l20_21-supply = <&vph_pwr>; 76 76 vdd_l25-supply = <&pm8994_s5>; 77 - vdd_lvs1_2 = <&pm8994_s4>; 77 + vdd_lvs1_2-supply = <&pm8994_s4>; 78 78 79 79 /* S1, S2, S6 and S12 are managed by RPMPD */ 80 80
+3 -5
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
··· 51 51 }; 52 52 }; 53 53 54 - gpio_keys { 54 + gpio-keys { 55 55 compatible = "gpio-keys"; 56 - #address-cells = <1>; 57 - #size-cells = <0>; 58 56 autorepeat; 59 57 60 - button@0 { 58 + button { 61 59 label = "Volume Up"; 62 60 gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; 63 61 linux,input-type = <1>; ··· 169 171 vdd_l17_29-supply = <&vph_pwr>; 170 172 vdd_l20_21-supply = <&vph_pwr>; 171 173 vdd_l25-supply = <&pm8994_s5>; 172 - vdd_lvs1_2 = <&pm8994_s4>; 174 + vdd_lvs1_2-supply = <&pm8994_s4>; 173 175 174 176 /* S1, S2, S6 and S12 are managed by RPMPD */ 175 177
+16 -13
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
··· 64 64 compatible = "gpio-keys"; 65 65 autorepeat; 66 66 67 - volupkey { 67 + volup-key { 68 68 label = "Volume Up"; 69 69 gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; 70 70 linux,input-type = <1>; ··· 73 73 debounce-interval = <15>; 74 74 }; 75 75 76 - camsnapkey { 76 + camsnap-key { 77 77 label = "Camera Snapshot"; 78 78 gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; 79 79 linux,input-type = <1>; ··· 82 82 debounce-interval = <15>; 83 83 }; 84 84 85 - camfocuskey { 85 + camfocus-key { 86 86 label = "Camera Focus"; 87 87 gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; 88 88 linux,input-type = <1>; ··· 100 100 101 101 label = "GPIO Hall Effect Sensor"; 102 102 103 - hall-front-sensor { 103 + event-hall-front-sensor { 104 104 label = "Hall Effect Front Sensor"; 105 105 gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; 106 106 linux,input-type = <EV_SW>; ··· 108 108 linux,can-disable; 109 109 }; 110 110 111 - hall-back-sensor { 111 + event-hall-back-sensor { 112 112 label = "Hall Effect Back Sensor"; 113 113 gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; 114 114 linux,input-type = <EV_SW>; ··· 470 470 }; 471 471 472 472 &pm8994_gpios { 473 - bt_en_gpios: bt_en_gpios { 473 + bt_en_gpios: bt-en-gpios-state { 474 474 pinconf { 475 475 pins = "gpio19"; 476 476 function = PMIC_GPIO_FUNC_NORMAL; ··· 481 481 }; 482 482 }; 483 483 484 - divclk4_pin_a: divclk4 { 484 + divclk4_pin_a: divclk4-state { 485 485 pinconf { 486 486 pins = "gpio18"; 487 487 function = PMIC_GPIO_FUNC_FUNC2; ··· 519 519 * TODO: remove once a driver is available 520 520 * TODO: add VBUS GPIO 5 521 521 */ 522 - hd3ss460_pol: pol_low { 522 + hd3ss460_pol: pol-low-state { 523 523 pins = "gpio8"; 524 - drive-strength = <3>; 524 + function = PMIC_GPIO_FUNC_NORMAL; 525 + qcom,drive-strength = <3>; 525 526 bias-pull-down; 526 527 }; 527 528 528 - hd3ss460_amsel: amsel_high { 529 + hd3ss460_amsel: amsel-high-state { 529 530 pins = "gpio9"; 530 - drive-strength = <1>; 531 + function = PMIC_GPIO_FUNC_NORMAL; 532 + qcom,drive-strength = <1>; 531 533 bias-pull-up; 532 534 }; 533 535 534 - hd3ss460_en: en_high { 536 + hd3ss460_en: en-high-state { 535 537 pins = "gpio10"; 536 - drive-strength = <1>; 538 + function = PMIC_GPIO_FUNC_NORMAL; 539 + qcom,drive-strength = <1>; 537 540 bias-pull-up; 538 541 }; 539 542 };
+5 -7
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
··· 27 27 /* Kitakami firmware doesn't support PSCI */ 28 28 /delete-node/ psci; 29 29 30 - gpio_keys { 30 + gpio-keys { 31 31 compatible = "gpio-keys"; 32 - #address-cells = <1>; 33 - #size-cells = <0>; 34 32 autorepeat; 35 33 36 - button@0 { 34 + button-0 { 37 35 label = "Volume Down"; 38 36 gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; 39 37 linux,input-type = <1>; ··· 40 42 debounce-interval = <15>; 41 43 }; 42 44 43 - button@1 { 45 + button-1 { 44 46 label = "Volume Up"; 45 47 gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; 46 48 linux,input-type = <1>; ··· 49 51 debounce-interval = <15>; 50 52 }; 51 53 52 - button@2 { 54 + button-2 { 53 55 label = "Camera Snapshot"; 54 56 gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; 55 57 linux,input-type = <1>; ··· 58 60 debounce-interval = <15>; 59 61 }; 60 62 61 - button@3 { 63 + button-3 { 62 64 label = "Camera Focus"; 63 65 gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; 64 66 linux,input-type = <1>;
+13 -12
arch/arm64/boot/dts/qcom/msm8994.dtsi
··· 100 100 CPU6: cpu@102 { 101 101 device_type = "cpu"; 102 102 compatible = "arm,cortex-a57"; 103 - reg = <0x0 0x101>; 103 + reg = <0x0 0x102>; 104 104 enable-method = "psci"; 105 105 next-level-cache = <&L2_1>; 106 106 }; ··· 108 108 CPU7: cpu@103 { 109 109 device_type = "cpu"; 110 110 compatible = "arm,cortex-a57"; 111 - reg = <0x0 0x101>; 111 + reg = <0x0 0x103>; 112 112 enable-method = "psci"; 113 113 next-level-cache = <&L2_1>; 114 114 }; ··· 461 461 }; 462 462 }; 463 463 464 - sdhc1: sdhci@f9824900 { 464 + sdhc1: mmc@f9824900 { 465 465 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 466 466 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 467 467 reg-names = "hc_mem", "core_mem"; ··· 470 470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 471 471 interrupt-names = "hc_irq", "pwr_irq"; 472 472 473 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 474 - <&gcc GCC_SDCC1_AHB_CLK>, 473 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 474 + <&gcc GCC_SDCC1_APPS_CLK>, 475 475 <&xo_board>; 476 - clock-names = "core", "iface", "xo"; 476 + clock-names = "iface", "core", "xo"; 477 477 478 478 pinctrl-names = "default", "sleep"; 479 479 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; ··· 484 484 status = "disabled"; 485 485 }; 486 486 487 - sdhc2: sdhci@f98a4900 { 487 + sdhc2: mmc@f98a4900 { 488 488 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 489 489 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 490 490 reg-names = "hc_mem", "core_mem"; ··· 493 493 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 494 494 interrupt-names = "hc_irq", "pwr_irq"; 495 495 496 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 497 - <&gcc GCC_SDCC2_AHB_CLK>, 498 - <&xo_board>; 499 - clock-names = "core", "iface", "xo"; 496 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 497 + <&gcc GCC_SDCC2_APPS_CLK>, 498 + <&xo_board>; 499 + clock-names = "iface", "core", "xo"; 500 500 501 501 pinctrl-names = "default", "sleep"; 502 502 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; ··· 1069 1069 <600000000>; 1070 1070 }; 1071 1071 1072 - ocmem: ocmem@fdd00000 { 1072 + ocmem: sram@fdd00000 { 1073 1073 compatible = "qcom,msm8974-ocmem"; 1074 1074 reg = <0xfdd00000 0x2000>, 1075 1075 <0xfec00000 0x200000>; 1076 1076 reg-names = "ctrl", "mem"; 1077 + ranges = <0 0xfec00000 0x200000>; 1077 1078 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1078 1079 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1079 1080 clock-names = "core", "iface";
-11
arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts
··· 1 - // SPDX-License-Identifier: BSD-3-Clause 2 - /* 3 - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 - */ 5 - 6 - #include "msm8996-sony-xperia-tone-dora.dts" 7 - #include "pmi8996.dtsi" 8 - 9 - / { 10 - model = "Sony Xperia X Performance (PMI8996)"; 11 - };
-11
arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts
··· 1 - // SPDX-License-Identifier: BSD-3-Clause 2 - /* 3 - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 - */ 5 - 6 - #include "msm8996-sony-xperia-tone-kagura.dts" 7 - #include "pmi8996.dtsi" 8 - 9 - / { 10 - model = "Sony Xperia XZ (PMI8996)"; 11 - };
-11
arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts
··· 1 - // SPDX-License-Identifier: BSD-3-Clause 2 - /* 3 - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 - */ 5 - 6 - #include "msm8996-sony-xperia-tone-keyaki.dts" 7 - #include "pmi8996.dtsi" 8 - 9 - / { 10 - model = "Sony Xperia XZs (PMI8996)"; 11 - };
+36 -41
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
··· 8 8 #include "msm8996.dtsi" 9 9 #include "pm8994.dtsi" 10 10 #include "pmi8994.dtsi" 11 + #include "pmi8996.dtsi" 11 12 #include <dt-bindings/input/input.h> 12 13 #include <dt-bindings/gpio/gpio.h> 13 14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> ··· 21 20 22 21 / { 23 22 qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ 24 - qcom,pmic-id = <0x20009 0x2000a 0 0>; /* PM8994 + PMI8994 */ 25 23 qcom,board-id = <8 0>; 26 24 27 25 chosen { ··· 40 40 ftrace-size = <0x20000>; 41 41 pmsg-size = <0x20000>; 42 42 ecc-size = <16>; 43 - }; 44 - 45 - cont_splash_mem: memory@83401000 { 46 - reg = <0 0x83401000 0 0x23ff000>; 47 - no-map; 48 43 }; 49 44 50 45 adsp_mem: adsp@8ea00000 { ··· 242 247 * probably a reason for it, and just to be on the safe side, we follow suit. 243 248 */ 244 249 pm8994_gpios_defaults: pm8994-gpios-default-state { 245 - pm8994-gpio1-nc { 250 + pm8994-gpio1-nc-pins { 246 251 pins = "gpio1"; 247 252 function = PMIC_GPIO_FUNC_NORMAL; 248 253 drive-push-pull; 249 254 bias-high-impedance; 250 255 }; 251 256 252 - vol-down-n { 257 + vol-down-n-pins { 253 258 pins = "gpio2"; 254 259 function = PMIC_GPIO_FUNC_NORMAL; 255 260 drive-push-pull; ··· 259 264 power-source = <PM8994_GPIO_S4>; 260 265 }; 261 266 262 - vol-up-n { 267 + vol-up-n-pins { 263 268 pins = "gpio3"; 264 269 function = PMIC_GPIO_FUNC_NORMAL; 265 270 drive-push-pull; ··· 268 273 power-source = <PM8994_GPIO_S4>; 269 274 }; 270 275 271 - camera-snapshot-n { 276 + camera-snapshot-n-pins { 272 277 pins = "gpio4"; 273 278 function = PMIC_GPIO_FUNC_NORMAL; 274 279 drive-push-pull; ··· 278 283 power-source = <PM8994_GPIO_S4>; 279 284 }; 280 285 281 - camera-focus-n { 286 + camera-focus-n-pins { 282 287 pins = "gpio5"; 283 288 function = PMIC_GPIO_FUNC_NORMAL; 284 289 drive-push-pull; ··· 288 293 power-source = <PM8994_GPIO_S4>; 289 294 }; 290 295 291 - pm8994-gpio6-nc { 296 + pm8994-gpio6-nc-pins { 292 297 pins = "gpio6"; 293 298 function = PMIC_GPIO_FUNC_NORMAL; 294 299 drive-push-pull; ··· 296 301 power-source = <PM8994_GPIO_VPH>; 297 302 }; 298 303 299 - nfc-download { 304 + nfc-download-pins { 300 305 pins = "gpio7"; 301 306 function = PMIC_GPIO_FUNC_NORMAL; 302 307 output-low; ··· 306 311 power-source = <PM8994_GPIO_S4>; 307 312 }; 308 313 309 - pm8994-gpio8-nc { 314 + pm8994-gpio8-nc-pins { 310 315 pins = "gpio8"; 311 316 function = PMIC_GPIO_FUNC_NORMAL; 312 317 output-low; ··· 316 321 power-source = <PM8994_GPIO_VPH>; 317 322 }; 318 323 319 - pm8994-gpio9-nc { 324 + pm8994-gpio9-nc-pins { 320 325 pins = "gpio9"; 321 326 function = PMIC_GPIO_FUNC_NORMAL; 322 327 output-high; ··· 326 331 power-source = <PM8994_GPIO_VPH>; 327 332 }; 328 333 329 - nfc-clock { 334 + nfc-clock-pins { 330 335 pins = "gpio10"; 331 336 function = PMIC_GPIO_FUNC_NORMAL; 332 337 input-enable; ··· 336 341 power-source = <PM8994_GPIO_S4>; 337 342 }; 338 343 339 - pm8994-gpio11-nc { 344 + pm8994-gpio11-nc-pins { 340 345 pins = "gpio11"; 341 346 function = PMIC_GPIO_FUNC_NORMAL; 342 347 drive-push-pull; ··· 344 349 power-source = <PM8994_GPIO_VPH>; 345 350 }; 346 351 347 - pm8994-gpio12-nc { 352 + pm8994-gpio12-nc-pins { 348 353 pins = "gpio12"; 349 354 function = PMIC_GPIO_FUNC_NORMAL; 350 355 drive-push-pull; ··· 352 357 power-source = <PM8994_GPIO_VPH>; 353 358 }; 354 359 355 - ear-enable { 360 + ear-enable-pins { 356 361 pins = "gpio13"; 357 362 function = PMIC_GPIO_FUNC_NORMAL; 358 363 output-high; ··· 362 367 power-source = <PM8994_GPIO_S4>; 363 368 }; 364 369 365 - pm8994-gpio14-nc { 370 + pm8994-gpio14-nc-pins { 366 371 pins = "gpio14"; 367 372 function = PMIC_GPIO_FUNC_NORMAL; 368 373 drive-push-pull; ··· 372 377 power-source = <PM8994_GPIO_VPH>; 373 378 }; 374 379 375 - pm-divclk1-gpio { 380 + pm-divclk1-gpio-pins { 376 381 pins = "gpio15"; 377 382 function = "func1"; 378 383 output-high; ··· 382 387 power-source = <PM8994_GPIO_VPH>; 383 388 }; 384 389 385 - pmi-clk-gpio { 390 + pmi-clk-gpio-pins { 386 391 pins = "gpio16"; 387 392 function = PMIC_GPIO_FUNC_NORMAL; 388 393 drive-push-pull; 389 394 }; 390 395 391 - pm8994-gpio17-nc { 396 + pm8994-gpio17-nc-pins { 392 397 pins = "gpio17"; 393 398 function = PMIC_GPIO_FUNC_NORMAL; 394 399 drive-push-pull; ··· 396 401 power-source = <PM8994_GPIO_VPH>; 397 402 }; 398 403 399 - rome-sleep { 404 + rome-sleep-pins { 400 405 pins = "gpio18"; 401 406 function = PMIC_GPIO_FUNC_FUNC2; 402 407 output-low; ··· 406 411 power-source = <PM8994_GPIO_S4>; 407 412 }; 408 413 409 - pm8994-gpio19-nc { 414 + pm8994-gpio19-nc-pins { 410 415 pins = "gpio19"; 411 416 function = PMIC_GPIO_FUNC_NORMAL; 412 417 output-low; ··· 416 421 power-source = <PM8994_GPIO_VPH>; 417 422 }; 418 423 419 - pm8994-gpio22-nc { 424 + pm8994-gpio22-nc-pins { 420 425 pins = "gpio22"; 421 426 function = PMIC_GPIO_FUNC_NORMAL; 422 427 drive-push-pull; ··· 441 446 "RF_ID"; 442 447 443 448 pm8994_mpps_defaults: pm8994-mpps-default-state { 444 - lcd-id_adc-mpp { 449 + lcd-id_adc-mpp-pins { 445 450 pins = "mpp2"; 446 451 function = "analog"; 447 452 input-enable; 448 453 qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH6>; 449 454 }; 450 455 451 - pm-mpp4-nc { 456 + pm-mpp4-nc-pins { 452 457 pins = "mpp4"; 453 458 function = "digital"; 454 459 bias-high-impedance; 455 460 power-source = <PM8994_GPIO_VPH>; 456 461 }; 457 462 458 - flash-therm-mpp { 463 + flash-therm-mpp-pins { 459 464 pins = "mpp5"; 460 465 function = "analog"; 461 466 input-enable; 462 467 qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>; 463 468 }; 464 469 465 - mpp6-nc { 470 + mpp6-nc-pins { 466 471 pins = "mpp6"; 467 472 function = "digital"; 468 473 bias-high-impedance; 469 474 }; 470 475 471 - rf-id-mpp { 476 + rf-id-mpp-pins { 472 477 pins = "mpp8"; 473 478 function = "analog"; 474 479 input-enable; ··· 499 504 "NC"; 500 505 501 506 pmi8994_gpios_defaults: pmi8994-gpios-default-state { 502 - vib-ldo-en-gpio { 507 + vib-ldo-en-gpio-pins { 503 508 pins = "gpio1"; 504 509 function = PMIC_GPIO_FUNC_NORMAL; 505 510 drive-push-pull; ··· 508 513 power-source = <PM8994_GPIO_S4>; 509 514 }; 510 515 511 - pmi-gpio2-nc { 516 + pmi-gpio2-nc-pins { 512 517 pins = "gpio2"; 513 518 function = PMIC_GPIO_FUNC_NORMAL; 514 519 drive-push-pull; ··· 518 523 power-source = <PM8994_GPIO_VPH>; 519 524 }; 520 525 521 - pmi-gpio3-nc { 526 + pmi-gpio3-nc-pins { 522 527 pins = "gpio3"; 523 528 function = PMIC_GPIO_FUNC_NORMAL; 524 529 drive-push-pull; ··· 528 533 power-source = <PM8994_GPIO_VPH>; 529 534 }; 530 535 531 - pmi-gpio4-nc { 536 + pmi-gpio4-nc-pins { 532 537 pins = "gpio4"; 533 538 function = PMIC_GPIO_FUNC_NORMAL; 534 539 drive-push-pull; ··· 537 542 power-source = <PM8994_GPIO_S4>; 538 543 }; 539 544 540 - pmi-gpio5-nc { 545 + pmi-gpio5-nc-pins { 541 546 pins = "gpio5"; 542 547 function = PMIC_GPIO_FUNC_NORMAL; 543 548 drive-push-pull; ··· 546 551 power-source = <PM8994_GPIO_S4>; 547 552 }; 548 553 549 - pmi-gpio6-nc { 554 + pmi-gpio6-nc-pins { 550 555 pins = "gpio6"; 551 556 function = PMIC_GPIO_FUNC_NORMAL; 552 557 drive-push-pull; ··· 555 560 power-source = <PM8994_GPIO_S4>; 556 561 }; 557 562 558 - pmi-gpio7-nc { 563 + pmi-gpio7-nc-pins { 559 564 pins = "gpio7"; 560 565 function = PMIC_GPIO_FUNC_NORMAL; 561 566 drive-push-pull; ··· 564 569 power-source = <PM8994_GPIO_S4>; 565 570 }; 566 571 567 - pmi-gpio8-nc { 572 + pmi-gpio8-nc-pins { 568 573 pins = "gpio8"; 569 574 function = PMIC_GPIO_FUNC_NORMAL; 570 575 drive-push-pull; ··· 573 578 power-source = <PM8994_GPIO_S4>; 574 579 }; 575 580 576 - usb-switch-sel { 581 + usb-switch-sel-pins { 577 582 pins = "gpio9"; 578 583 function = PMIC_GPIO_FUNC_NORMAL; 579 584 drive-push-pull; 580 585 }; 581 586 582 - pmi-gpio10-nc { 587 + pmi-gpio10-nc-pins { 583 588 pins = "gpio10"; 584 589 function = PMIC_GPIO_FUNC_NORMAL; 585 590 output-low;
+7 -7
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
··· 38 38 }; 39 39 }; 40 40 41 - gpio_keys { 41 + gpio-keys { 42 42 compatible = "gpio-keys"; 43 43 44 - vol_up { 44 + key-vol-up { 45 45 label = "Volume Up"; 46 46 gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; 47 47 linux,code = <KEY_VOLUMEUP>; ··· 49 49 debounce-interval = <15>; 50 50 }; 51 51 52 - dome { 52 + key-dome { 53 53 label = "Home"; 54 54 gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; 55 55 linux,code = <KEY_HOME>; ··· 608 608 }; 609 609 610 610 &pm8994_gpios { 611 - wlan_en_default: wlan-en-default { 611 + wlan_en_default: wlan-en-state { 612 612 pins = "gpio8"; 613 613 function = PMIC_GPIO_FUNC_NORMAL; 614 614 output-low; ··· 617 617 bias-disable; 618 618 }; 619 619 620 - rome_enable_default: rome-enable-default { 620 + rome_enable_default: rome-enable-state { 621 621 pins = "gpio9"; 622 622 function = PMIC_GPIO_FUNC_NORMAL; 623 623 output-high; ··· 625 625 power-source = <PM8994_GPIO_VPH>; 626 626 }; 627 627 628 - divclk1_default: divclk1_default { 628 + divclk1_default: divclk1-state { 629 629 pins = "gpio15"; 630 630 function = PMIC_GPIO_FUNC_FUNC1; 631 631 bias-disable; ··· 633 633 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 634 634 }; 635 635 636 - divclk4_pin_a: divclk4 { 636 + divclk4_pin_a: divclk4-state { 637 637 pins = "gpio18"; 638 638 function = PMIC_GPIO_FUNC_FUNC2; 639 639 bias-disable;
+2 -2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
··· 156 156 &sound { 157 157 compatible = "qcom,apq8096-sndcard"; 158 158 model = "gemini"; 159 - audio-routing = "RX_BIAS", "MCLK", 159 + audio-routing = "RX_BIAS", "MCLK", 160 160 "MM_DL1", "MultiMedia1 Playback", 161 161 "MM_DL2", "MultiMedia2 Playback", 162 162 "MultiMedia3 Capture", "MM_UL3"; ··· 257 257 "UIM_BATT_ALARM", /* GPIO_21 */ 258 258 "NC"; /* GPIO_22 */ 259 259 260 - divclk2_pin_a: divclk2 { 260 + divclk2_pin_a: divclk2-state { 261 261 pins = "gpio16"; 262 262 function = PMIC_GPIO_FUNC_FUNC2; 263 263 bias-disable;
+414
arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2022, Alec Su <ae40515@yahoo.com.tw> 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "msm8996-xiaomi-common.dtsi" 9 + #include "pmi8996.dtsi" 10 + #include <dt-bindings/sound/qcom,q6afe.h> 11 + #include <dt-bindings/sound/qcom,q6asm.h> 12 + 13 + / { 14 + model = "Xiaomi Mi 5s Plus"; 15 + compatible = "xiaomi,natrium", "qcom,msm8996"; 16 + chassis-type = "handset"; 17 + qcom,msm-id = <305 0x10000>; 18 + qcom,board-id = <47 0>; 19 + }; 20 + 21 + &adsp_pil { 22 + firmware-name = "qcom/msm8996/natrium/adsp.mbn"; 23 + }; 24 + 25 + &blsp2_i2c6 { 26 + touchscreen@20 { 27 + compatible = "syna,rmi4-i2c"; 28 + reg = <0x20>; 29 + interrupt-parent = <&tlmm>; 30 + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 31 + vdd-supply = <&vdd_3v2_tp>; 32 + syna,reset-delay-ms = <200>; 33 + syna,startup-delay-ms = <5>; 34 + 35 + pinctrl-names = "default", "sleep"; 36 + pinctrl-0 = <&touchscreen_default>; 37 + pinctrl-1 = <&touchscreen_sleep>; 38 + }; 39 + }; 40 + 41 + &dsi0 { 42 + status = "okay"; 43 + 44 + vdda-supply = <&vreg_l2a_1p25>; 45 + vcca-supply = <&vreg_l28a_0p925>; 46 + 47 + pinctrl-names = "default", "sleep"; 48 + pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; 49 + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; 50 + 51 + panel: panel@0 { 52 + compatible = "jdi,fhd-r63452"; 53 + reg = <0>; 54 + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; 55 + backlight = <&pmi8994_wled>; 56 + 57 + port { 58 + panel_in: endpoint { 59 + remote-endpoint = <&dsi0_out>; 60 + }; 61 + }; 62 + }; 63 + }; 64 + 65 + &dsi0_out { 66 + remote-endpoint = <&panel_in>; 67 + }; 68 + 69 + &gpu { 70 + zap-shader { 71 + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; 72 + }; 73 + }; 74 + 75 + &mss_pil { 76 + firmware-name = "qcom/msm8996/natrium/mba.mbn", 77 + "qcom/msm8996/natrium/modem.mbn"; 78 + }; 79 + 80 + &pmi8994_wled { 81 + status = "okay"; 82 + 83 + qcom,enabled-strings = <0 1>; 84 + qcom,switching-freq = <600>; 85 + }; 86 + 87 + &q6asmdai { 88 + dai@0 { 89 + reg = <0>; 90 + }; 91 + 92 + dai@1 { 93 + reg = <1>; 94 + }; 95 + 96 + dai@2 { 97 + reg = <2>; 98 + }; 99 + }; 100 + 101 + &slpi_pil { 102 + firmware-name = "qcom/msm8996/natrium/slpi.mbn"; 103 + }; 104 + 105 + &sound { 106 + compatible = "qcom,apq8096-sndcard"; 107 + model = "natrium"; 108 + audio-routing = "RX_BIAS", "MCLK"; 109 + 110 + mm1-dai-link { 111 + link-name = "MultiMedia1"; 112 + cpu { 113 + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; 114 + }; 115 + }; 116 + 117 + mm2-dai-link { 118 + link-name = "MultiMedia2"; 119 + cpu { 120 + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; 121 + }; 122 + }; 123 + 124 + mm3-dai-link { 125 + link-name = "MultiMedia3"; 126 + cpu { 127 + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; 128 + }; 129 + }; 130 + 131 + slim-dai-link { 132 + link-name = "SLIM Playback"; 133 + cpu { 134 + sound-dai = <&q6afedai SLIMBUS_6_RX>; 135 + }; 136 + 137 + platform { 138 + sound-dai = <&q6routing>; 139 + }; 140 + 141 + codec { 142 + sound-dai = <&wcd9335 6>; 143 + }; 144 + }; 145 + 146 + slimcap-dai-link { 147 + link-name = "SLIM Capture"; 148 + cpu { 149 + sound-dai = <&q6afedai SLIMBUS_0_TX>; 150 + }; 151 + 152 + platform { 153 + sound-dai = <&q6routing>; 154 + }; 155 + 156 + codec { 157 + sound-dai = <&wcd9335 1>; 158 + }; 159 + }; 160 + }; 161 + 162 + &venus { 163 + firmware-name = "qcom/msm8996/natrium/venus.mbn"; 164 + }; 165 + 166 + &rpm_requests { 167 + pm8994-regulators { 168 + vreg_l3a_0p875: l3 { 169 + regulator-name = "vreg_l3a_0p875"; 170 + regulator-min-microvolt = <850000>; 171 + regulator-max-microvolt = <1300000>; 172 + }; 173 + vreg_l11a_1p1: l11 { 174 + regulator-name = "vreg_l11a_1p1"; 175 + regulator-min-microvolt = <1100000>; 176 + regulator-max-microvolt = <1100000>; 177 + }; 178 + vreg_l17a_2p8: l17 { 179 + regulator-name = "vreg_l17a_2p8"; 180 + regulator-min-microvolt = <2800000>; 181 + regulator-max-microvolt = <2800000>; 182 + }; 183 + vreg_l18a_2p8: l18 { 184 + regulator-name = "vreg_l18a_2p8"; 185 + regulator-min-microvolt = <2800000>; 186 + regulator-max-microvolt = <2800000>; 187 + }; 188 + vreg_l29a_2p8: l29 { 189 + regulator-name = "vreg_l29a_2p8"; 190 + regulator-min-microvolt = <2800000>; 191 + regulator-max-microvolt = <2800000>; 192 + }; 193 + }; 194 + }; 195 + 196 + &pm8994_gpios { 197 + gpio-line-names = 198 + "NC", /* GPIO_1 */ 199 + "VOL_UP_N", /* GPIO_2 */ 200 + "SPKR_ID", /* GPIO_3 */ 201 + "PWM_HAPTICS", /* GPIO_4 */ 202 + "INFARED_DRV", /* GPIO_5 */ 203 + "NC", /* GPIO_6 */ 204 + "KEYPAD_LED_EN_A", /* GPIO_7 */ 205 + "WL_EN", /* GPIO_8 */ 206 + "3P3_ENABLE", /* GPIO_9 */ 207 + "NC", /* GPIO_10 */ 208 + "NC", /* GPIO_11 */ 209 + "NC", /* GPIO_12 */ 210 + "NC", /* GPIO_13 */ 211 + "NC", /* GPIO_14 */ 212 + "DIVCLK1_CDC", /* GPIO_15 */ 213 + "DIVCLK2_HAPTICS", /* GPIO_16 */ 214 + "NC", /* GPIO_17 */ 215 + "32KHz_CLK_IN", /* GPIO_18 */ 216 + "BT_EN", /* GPIO_19 */ 217 + "PMIC_SLB", /* GPIO_20 */ 218 + "UIM_BATT_ALARM", /* GPIO_21 */ 219 + "NC"; /* GPIO_22 */ 220 + }; 221 + 222 + &pm8994_mpps { 223 + gpio-line-names = 224 + "NC", /* MPP_1 */ 225 + "CCI_TIMER1", /* MPP_2 */ 226 + "PMIC_SLB", /* MPP_3 */ 227 + "EXT_FET_WLED_PWR_EN_N",/* MPP_4 */ 228 + "NC", /* MPP_5 */ 229 + "NC", /* MPP_6 */ 230 + "NC", /* MPP_7 */ 231 + "NC"; /* MPP_8 */ 232 + }; 233 + 234 + &pmi8994_gpios { 235 + gpio-line-names = 236 + "NC", /* GPIO_1 */ 237 + "SPKR_PA_EN", /* GPIO_2 */ 238 + "NC", /* GPIO_3 */ 239 + "NC", /* GPIO_4 */ 240 + "NC", /* GPIO_5 */ 241 + "NC", /* GPIO_6 */ 242 + "NC", /* GPIO_7 */ 243 + "NC", /* GPIO_8 */ 244 + "NC", /* GPIO_9 */ 245 + "NC"; /* GPIO_10 */ 246 + }; 247 + 248 + &tlmm { 249 + gpio-line-names = 250 + "ESE_SPI_MOSI", /* GPIO_0 */ 251 + "ESE_SPI_MISO", /* GPIO_1 */ 252 + "NC", /* GPIO_2 */ 253 + "ESE_SPI_CLK", /* GPIO_3 */ 254 + "MSM_UART_TX", /* GPIO_4 */ 255 + "MSM_UART_RX", /* GPIO_5 */ 256 + "NFC_I2C_SDA", /* GPIO_6 */ 257 + "NFC_I2C_SCL", /* GPIO_7 */ 258 + "LCD0_RESET_N", /* GPIO_8 */ 259 + "NFC_IRQ", /* GPIO_9 */ 260 + "LCD_TE", /* GPIO_10 */ 261 + "LCD_ID_DET1", /* GPIO_11 */ 262 + "NFC_DISABLE", /* GPIO_12 */ 263 + "CAM_MCLK0", /* GPIO_13 */ 264 + "CAM_MCLK1", /* GPIO_14 */ 265 + "CAM_MCLK2", /* GPIO_15 */ 266 + "ESE_PWR_REQ", /* GPIO_16 */ 267 + "CCI_I2C_SDA0", /* GPIO_17 */ 268 + "CCI_I2C_SCL0", /* GPIO_18 */ 269 + "CCI_I2C_SDA1", /* GPIO_19 */ 270 + "CCI_I2C_SCL1", /* GPIO_20 */ 271 + "NFC_DWL_REQ", /* GPIO_21 */ 272 + "CCI_TIMER1", /* GPIO_22 */ 273 + "WEBCAM1_RESET_N", /* GPIO_23 */ 274 + "ESE_IRQ", /* GPIO_24 */ 275 + "NC", /* GPIO_25 */ 276 + "WEBCAM1_STANDBY", /* GPIO_26 */ 277 + "NC", /* GPIO_27 */ 278 + "NC", /* GPIO_28 */ 279 + "NC", /* GPIO_29 */ 280 + "CAM_VDD_1P2_EN_2", /* GPIO_30 */ 281 + "CAM_RESET_0", /* GPIO_31 */ 282 + "CAM_RESET_1", /* GPIO_32 */ 283 + "NC", /* GPIO_33 */ 284 + "NC", /* GPIO_34 */ 285 + "PCI_E0_RST_N", /* GPIO_35 */ 286 + "PCI_E0_CLKREQ_N", /* GPIO_36 */ 287 + "PCI_E0_WAKE", /* GPIO_37 */ 288 + "CHARGER_INT", /* GPIO_38 */ 289 + "CHARGER_RESET", /* GPIO_39 */ 290 + "NC", /* GPIO_40 */ 291 + "QCA_UART_TXD", /* GPIO_41 */ 292 + "QCA_UART_RXD", /* GPIO_42 */ 293 + "QCA_UART_CTS", /* GPIO_43 */ 294 + "QCA_UART_RTS", /* GPIO_44 */ 295 + "MAWC_UART_TX", /* GPIO_45 */ 296 + "MAWC_UART_RX", /* GPIO_46 */ 297 + "NC", /* GPIO_47 */ 298 + "NC", /* GPIO_48 */ 299 + "NC", /* GPIO_49 */ 300 + "FP_SPI_RST", /* GPIO_50 */ 301 + "TYPEC_I2C_SDA", /* GPIO_51 */ 302 + "TYPEC_I2C_SCL", /* GPIO_52 */ 303 + "CODEC_INT2_N", /* GPIO_53 */ 304 + "CODEC_INT1_N", /* GPIO_54 */ 305 + "APPS_I2C7_SDA", /* GPIO_55 */ 306 + "APPS_I2C7_SCL", /* GPIO_56 */ 307 + "FORCE_USB_BOOT", /* GPIO_57 */ 308 + "NC", /* GPIO_58 */ 309 + "NC", /* GPIO_59 */ 310 + "NC", /* GPIO_60 */ 311 + "NC", /* GPIO_61 */ 312 + "ESE_RSTN", /* GPIO_62 */ 313 + "TYPEC_INT", /* GPIO_63 */ 314 + "CODEC_RESET_N", /* GPIO_64 */ 315 + "PCM_CLK", /* GPIO_65 */ 316 + "PCM_SYNC", /* GPIO_66 */ 317 + "PCM_DIN", /* GPIO_67 */ 318 + "PCM_DOUT", /* GPIO_68 */ 319 + "CDC_44K1_CLK", /* GPIO_69 */ 320 + "SLIMBUS_CLK", /* GPIO_70 */ 321 + "SLIMBUS_DATA0", /* GPIO_71 */ 322 + "SLIMBUS_DATA1", /* GPIO_72 */ 323 + "LDO_5V_IN_EN", /* GPIO_73 */ 324 + "TYPEC_EN_N", /* GPIO_74 */ 325 + "NC", /* GPIO_75 */ 326 + "NC", /* GPIO_76 */ 327 + "NC", /* GPIO_77 */ 328 + "NC", /* GPIO_78 */ 329 + "NC", /* GPIO_79 */ 330 + "SENSOR_RESET_N", /* GPIO_80 */ 331 + "FP_SPI_MOSI", /* GPIO_81 */ 332 + "FP_SPI_MISO", /* GPIO_82 */ 333 + "FP_SPI_CS_N", /* GPIO_83 */ 334 + "FP_SPI_CLK", /* GPIO_84 */ 335 + "NC", /* GPIO_85 */ 336 + "CAM_VDD_1P2_EN", /* GPIO_86 */ 337 + "MSM_TS_I2C_SDA", /* GPIO_87 */ 338 + "MSM_TS_I2C_SCL", /* GPIO_88 */ 339 + "TS_RESOUT_N", /* GPIO_89 */ 340 + "ESE_SPI_CS_N", /* GPIO_90 */ 341 + "NC", /* GPIO_91 */ 342 + "CAM2_AVDD_EN", /* GPIO_92 */ 343 + "CAM2_VCM_EN", /* GPIO_93 */ 344 + "NC", /* GPIO_94 */ 345 + "NC", /* GPIO_95 */ 346 + "NC", /* GPIO_96 */ 347 + "GRFC_0", /* GPIO_97 */ 348 + "GRFC_1", /* GPIO_98 */ 349 + "NC", /* GPIO_99 */ 350 + "GRFC_3", /* GPIO_100 */ 351 + "GRFC_4", /* GPIO_101 */ 352 + "GRFC_5", /* GPIO_102 */ 353 + "NC", /* GPIO_103 */ 354 + "GRFC_7", /* GPIO_104 */ 355 + "UIM2_DATA", /* GPIO_105 */ 356 + "UIM2_CLK", /* GPIO_106 */ 357 + "UIM2_RESET", /* GPIO_107 */ 358 + "UIM2_PRESENT", /* GPIO_108 */ 359 + "UIM1_DATA", /* GPIO_109 */ 360 + "UIM1_CLK", /* GPIO_110 */ 361 + "UIM1_RESET", /* GPIO_111 */ 362 + "UIM1_PRESENT", /* GPIO_112 */ 363 + "UIM_BATT_ALARM", /* GPIO_113 */ 364 + "GRFC_8", /* GPIO_114 */ 365 + "GRFC_9", /* GPIO_115 */ 366 + "TX_GTR_THRES", /* GPIO_116 */ 367 + "ACCEL_INT", /* GPIO_117 */ 368 + "GYRO_INT", /* GPIO_118 */ 369 + "COMPASS_INT", /* GPIO_119 */ 370 + "PROXIMITY_INT_N", /* GPIO_120 */ 371 + "FP_IRQ", /* GPIO_121 */ 372 + "P_SENSE", /* GPIO_122 */ 373 + "HALL_INTR2", /* GPIO_123 */ 374 + "HALL_INTR1", /* GPIO_124 */ 375 + "TS_INT_N", /* GPIO_125 */ 376 + "NC", /* GPIO_126 */ 377 + "GRFC_11", /* GPIO_127 */ 378 + "NC", /* GPIO_128 */ 379 + "EXT_GPS_LNA_EN", /* GPIO_129 */ 380 + "NC", /* GPIO_130 */ 381 + "LCD_ID_DET2", /* GPIO_131 */ 382 + "LCD_TE2", /* GPIO_132 */ 383 + "GRFC_14", /* GPIO_133 */ 384 + "GSM_TX2_PHASE_D", /* GPIO_134 */ 385 + "NC", /* GPIO_135 */ 386 + "GRFC_15", /* GPIO_136 */ 387 + "RFFE3_DATA", /* GPIO_137 */ 388 + "RFFE3_CLK", /* GPIO_138 */ 389 + "NC", /* GPIO_139 */ 390 + "NC", /* GPIO_140 */ 391 + "RFFE5_DATA", /* GPIO_141 */ 392 + "RFFE5_CLK", /* GPIO_142 */ 393 + "NC", /* GPIO_143 */ 394 + "COEX_UART_TX", /* GPIO_144 */ 395 + "COEX_UART_RX", /* GPIO_145 */ 396 + "RFFE2_DATA", /* GPIO_146 */ 397 + "RFFE2_CLK", /* GPIO_147 */ 398 + "RFFE1_DATA", /* GPIO_148 */ 399 + "RFFE1_CLK"; /* GPIO_149 */ 400 + 401 + touchscreen_default: touchscreen-default { 402 + pins = "gpio89", "gpio125"; 403 + function = "gpio"; 404 + drive-strength = <10>; 405 + bias-pull-up; 406 + }; 407 + 408 + touchscreen_sleep: touchscreen-sleep { 409 + pins = "gpio89", "gpio125"; 410 + function = "gpio"; 411 + drive-strength = <2>; 412 + bias-disable; 413 + }; 414 + };
+1 -1
arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts
··· 137 137 &sound { 138 138 compatible = "qcom,apq8096-sndcard"; 139 139 model = "scorpio"; 140 - audio-routing = "RX_BIAS", "MCLK"; 140 + audio-routing = "RX_BIAS", "MCLK"; 141 141 142 142 mm1-dai-link { 143 143 link-name = "MultiMedia1";
+255 -42
arch/arm64/boot/dts/qcom/msm8996.dtsi
··· 6 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 7 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 + #include <dt-bindings/interconnect/qcom,msm8996.h> 9 10 #include <dt-bindings/power/qcom-rpmpd.h> 10 11 #include <dt-bindings/soc/qcom,apr.h> 11 12 #include <dt-bindings/thermal/thermal.h> ··· 358 357 359 358 firmware { 360 359 scm { 361 - compatible = "qcom,scm-msm8996"; 360 + compatible = "qcom,scm-msm8996", "qcom,scm"; 362 361 qcom,dload-mode = <&tcsr 0x13000>; 363 362 }; 364 363 }; ··· 464 463 rpmcc: qcom,rpmcc { 465 464 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 466 465 #clock-cells = <1>; 466 + clocks = <&xo_board>; 467 + clock-names = "xo"; 467 468 }; 468 469 469 470 rpmpd: power-controller { ··· 588 585 ranges = <0 0 0 0xffffffff>; 589 586 compatible = "simple-bus"; 590 587 591 - pcie_phy: phy@34000 { 588 + pcie_phy: phy-wrapper@34000 { 592 589 compatible = "qcom,msm8996-qmp-pcie-phy"; 593 590 reg = <0x00034000 0x488>; 594 591 #address-cells = <1>; 595 592 #size-cells = <1>; 596 - ranges; 593 + ranges = <0x0 0x00034000 0x4000>; 597 594 598 595 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 599 596 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, ··· 604 601 <&gcc GCC_PCIE_PHY_COM_BCR>, 605 602 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 606 603 reset-names = "phy", "common", "cfg"; 604 + 607 605 status = "disabled"; 608 606 609 - pciephy_0: phy@35000 { 610 - reg = <0x00035000 0x130>, 611 - <0x00035200 0x200>, 612 - <0x00035400 0x1dc>; 613 - #phy-cells = <0>; 607 + pciephy_0: phy@1000 { 608 + reg = <0x1000 0x130>, 609 + <0x1200 0x200>, 610 + <0x1400 0x1dc>; 614 611 615 - #clock-cells = <1>; 616 - clock-output-names = "pcie_0_pipe_clk_src"; 617 612 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 618 613 clock-names = "pipe0"; 619 614 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 620 615 reset-names = "lane0"; 616 + 617 + #clock-cells = <0>; 618 + clock-output-names = "pcie_0_pipe_clk_src"; 619 + 620 + #phy-cells = <0>; 621 621 }; 622 622 623 - pciephy_1: phy@36000 { 624 - reg = <0x00036000 0x130>, 625 - <0x00036200 0x200>, 626 - <0x00036400 0x1dc>; 627 - #phy-cells = <0>; 623 + pciephy_1: phy@2000 { 624 + reg = <0x2000 0x130>, 625 + <0x2200 0x200>, 626 + <0x2400 0x1dc>; 628 627 629 - clock-output-names = "pcie_1_pipe_clk_src"; 630 628 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 631 629 clock-names = "pipe1"; 632 630 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 633 631 reset-names = "lane1"; 632 + 633 + #clock-cells = <0>; 634 + clock-output-names = "pcie_1_pipe_clk_src"; 635 + 636 + #phy-cells = <0>; 634 637 }; 635 638 636 - pciephy_2: phy@37000 { 637 - reg = <0x00037000 0x130>, 638 - <0x00037200 0x200>, 639 - <0x00037400 0x1dc>; 640 - #phy-cells = <0>; 639 + pciephy_2: phy@3000 { 640 + reg = <0x3000 0x130>, 641 + <0x3200 0x200>, 642 + <0x3400 0x1dc>; 641 643 642 - clock-output-names = "pcie_2_pipe_clk_src"; 643 644 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 644 645 clock-names = "pipe2"; 645 646 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 646 647 reset-names = "lane2"; 648 + 649 + #clock-cells = <0>; 650 + clock-output-names = "pcie_2_pipe_clk_src"; 651 + 652 + #phy-cells = <0>; 647 653 }; 648 654 }; 649 655 ··· 662 650 }; 663 651 664 652 qfprom@74000 { 665 - compatible = "qcom,qfprom"; 653 + compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 666 654 reg = <0x00074000 0x8ff>; 667 655 #address-cells = <1>; 668 656 #size-cells = <1>; ··· 699 687 700 688 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 701 689 <&rpmcc RPM_SMD_LN_BB_CLK>, 702 - <&sleep_clk>; 703 - clock-names = "cxo", "cxo2", "sleep_clk"; 690 + <&sleep_clk>, 691 + <&pciephy_0>, 692 + <&pciephy_1>, 693 + <&pciephy_2>, 694 + <&ssusb_phy_0>, 695 + <0>, <0>, <0>; 696 + clock-names = "cxo", 697 + "cxo2", 698 + "sleep_clk", 699 + "pcie_0_pipe_clk_src", 700 + "pcie_1_pipe_clk_src", 701 + "pcie_2_pipe_clk_src", 702 + "usb3_phy_pipe_clk_src", 703 + "ufs_rx_symbol_0_clk_src", 704 + "ufs_rx_symbol_1_clk_src", 705 + "ufs_tx_symbol_0_clk_src"; 706 + }; 707 + 708 + bimc: interconnect@408000 { 709 + compatible = "qcom,msm8996-bimc"; 710 + reg = <0x00408000 0x5a000>; 711 + #interconnect-cells = <1>; 712 + clock-names = "bus", "bus_a"; 713 + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 714 + <&rpmcc RPM_SMD_BIMC_A_CLK>; 704 715 }; 705 716 706 717 tsens0: thermal-sensor@4a9000 { ··· 770 735 dma-names = "rx", "tx"; 771 736 }; 772 737 738 + cnoc: interconnect@500000 { 739 + compatible = "qcom,msm8996-cnoc"; 740 + reg = <0x00500000 0x1000>; 741 + #interconnect-cells = <1>; 742 + clock-names = "bus", "bus_a"; 743 + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 744 + <&rpmcc RPM_SMD_CNOC_A_CLK>; 745 + }; 746 + 747 + snoc: interconnect@524000 { 748 + compatible = "qcom,msm8996-snoc"; 749 + reg = <0x00524000 0x1c000>; 750 + #interconnect-cells = <1>; 751 + clock-names = "bus", "bus_a"; 752 + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 753 + <&rpmcc RPM_SMD_SNOC_A_CLK>; 754 + }; 755 + 756 + a0noc: interconnect@543000 { 757 + compatible = "qcom,msm8996-a0noc"; 758 + reg = <0x00543000 0x6000>; 759 + #interconnect-cells = <1>; 760 + clock-names = "aggre0_snoc_axi", 761 + "aggre0_cnoc_ahb", 762 + "aggre0_noc_mpu_cfg"; 763 + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 764 + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 765 + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 766 + power-domains = <&gcc AGGRE0_NOC_GDSC>; 767 + }; 768 + 769 + a1noc: interconnect@562000 { 770 + compatible = "qcom,msm8996-a1noc"; 771 + reg = <0x00562000 0x5000>; 772 + #interconnect-cells = <1>; 773 + clock-names = "bus", "bus_a"; 774 + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 775 + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 776 + }; 777 + 778 + a2noc: interconnect@583000 { 779 + compatible = "qcom,msm8996-a2noc"; 780 + reg = <0x00583000 0x7000>; 781 + #interconnect-cells = <1>; 782 + clock-names = "bus", "bus_a"; 783 + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 784 + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 785 + }; 786 + 787 + mnoc: interconnect@5a4000 { 788 + compatible = "qcom,msm8996-mnoc"; 789 + reg = <0x005a4000 0x1c000>; 790 + #interconnect-cells = <1>; 791 + clock-names = "bus", "bus_a", "iface"; 792 + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 793 + <&rpmcc RPM_SMD_MMAXI_A_CLK>, 794 + <&mmcc AHB_CLK_SRC>; 795 + }; 796 + 797 + pnoc: interconnect@5c0000 { 798 + compatible = "qcom,msm8996-pnoc"; 799 + reg = <0x005c0000 0x3000>; 800 + #interconnect-cells = <1>; 801 + clock-names = "bus", "bus_a"; 802 + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 803 + <&rpmcc RPM_SMD_PCNOC_A_CLK>; 804 + }; 805 + 773 806 tcsr_mutex_regs: syscon@740000 { 774 807 compatible = "syscon"; 775 808 reg = <0x00740000 0x40000>; ··· 854 751 #reset-cells = <1>; 855 752 #power-domain-cells = <1>; 856 753 reg = <0x008c0000 0x40000>; 754 + clocks = <&xo_board>, 755 + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 756 + <&gcc GPLL0>, 757 + <&dsi0_phy 1>, 758 + <&dsi0_phy 0>, 759 + <0>, 760 + <0>, 761 + <0>; 762 + clock-names = "xo", 763 + "gcc_mmss_noc_cfg_ahb_clk", 764 + "gpll0", 765 + "dsi0pll", 766 + "dsi0pllbyte", 767 + "dsi1pll", 768 + "dsi1pllbyte", 769 + "hdmipll"; 857 770 assigned-clocks = <&mmcc MMPLL9_PLL>, 858 771 <&mmcc MMPLL1_PLL>, 859 772 <&mmcc MMPLL3_PLL>, ··· 898 779 interrupt-controller; 899 780 #interrupt-cells = <1>; 900 781 901 - clocks = <&mmcc MDSS_AHB_CLK>; 902 - clock-names = "iface"; 782 + clocks = <&mmcc MDSS_AHB_CLK>, 783 + <&mmcc MDSS_MDP_CLK>; 784 + clock-names = "iface", "core"; 903 785 904 786 #address-cells = <1>; 905 787 #size-cells = <1>; ··· 934 814 assigned-clock-rates = <300000000>, 935 815 <19200000>; 936 816 817 + interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 818 + <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 819 + <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 820 + interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 821 + 937 822 ports { 938 823 #address-cells = <1>; 939 824 #size-cells = <0>; ··· 954 829 reg = <1>; 955 830 mdp5_intf1_out: endpoint { 956 831 remote-endpoint = <&dsi0_in>; 832 + }; 833 + }; 834 + 835 + port@2 { 836 + reg = <2>; 837 + mdp5_intf2_out: endpoint { 838 + remote-endpoint = <&dsi1_in>; 957 839 }; 958 840 }; 959 841 }; ··· 988 856 "core_mmss", 989 857 "pixel", 990 858 "core"; 859 + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 860 + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 991 861 992 862 phys = <&dsi0_phy>; 993 863 phy-names = "dsi"; ··· 1034 900 status = "disabled"; 1035 901 }; 1036 902 903 + dsi1: dsi@996000 { 904 + compatible = "qcom,mdss-dsi-ctrl"; 905 + reg = <0x00996000 0x400>; 906 + reg-names = "dsi_ctrl"; 907 + 908 + interrupt-parent = <&mdss>; 909 + interrupts = <4>; 910 + 911 + clocks = <&mmcc MDSS_MDP_CLK>, 912 + <&mmcc MDSS_BYTE1_CLK>, 913 + <&mmcc MDSS_AHB_CLK>, 914 + <&mmcc MDSS_AXI_CLK>, 915 + <&mmcc MMSS_MISC_AHB_CLK>, 916 + <&mmcc MDSS_PCLK1_CLK>, 917 + <&mmcc MDSS_ESC1_CLK>; 918 + clock-names = "mdp_core", 919 + "byte", 920 + "iface", 921 + "bus", 922 + "core_mmss", 923 + "pixel", 924 + "core"; 925 + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 926 + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 927 + 928 + phys = <&dsi1_phy>; 929 + phy-names = "dsi"; 930 + status = "disabled"; 931 + 932 + #address-cells = <1>; 933 + #size-cells = <0>; 934 + 935 + ports { 936 + #address-cells = <1>; 937 + #size-cells = <0>; 938 + 939 + port@0 { 940 + reg = <0>; 941 + dsi1_in: endpoint { 942 + remote-endpoint = <&mdp5_intf2_out>; 943 + }; 944 + }; 945 + 946 + port@1 { 947 + reg = <1>; 948 + dsi1_out: endpoint { 949 + }; 950 + }; 951 + }; 952 + }; 953 + 954 + dsi1_phy: dsi-phy@996400 { 955 + compatible = "qcom,dsi-phy-14nm"; 956 + reg = <0x00996400 0x100>, 957 + <0x00996500 0x300>, 958 + <0x00996800 0x188>; 959 + reg-names = "dsi_phy", 960 + "dsi_phy_lane", 961 + "dsi_pll"; 962 + 963 + #clock-cells = <1>; 964 + #phy-cells = <0>; 965 + 966 + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 967 + clock-names = "iface", "ref"; 968 + status = "disabled"; 969 + }; 970 + 1037 971 hdmi: hdmi-tx@9a0000 { 1038 972 compatible = "qcom,hdmi-tx-8996"; 1039 973 reg = <0x009a0000 0x50c>, ··· 1127 925 "extp"; 1128 926 1129 927 phys = <&hdmi_phy>; 1130 - phy-names = "hdmi_phy"; 1131 928 #sound-dai-cells = <1>; 1132 929 1133 930 status = "disabled"; ··· 1189 988 "mem", 1190 989 "mem_iface"; 1191 990 991 + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 992 + interconnect-names = "gfx-mem"; 993 + 1192 994 power-domains = <&mmcc GPU_GX_GDSC>; 1193 995 iommus = <&adreno_smmu 0>; 1194 996 ··· 1205 1001 #cooling-cells = <2>; 1206 1002 1207 1003 gpu_opp_table: opp-table { 1208 - compatible ="operating-points-v2"; 1004 + compatible = "operating-points-v2"; 1209 1005 1210 1006 /* 1211 1007 * 624Mhz and 560Mhz are only available on speed ··· 1827 1623 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1828 1624 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1829 1625 1830 - clock-names = "pipe", 1626 + clock-names = "pipe", 1831 1627 "aux", 1832 1628 "cfg", 1833 1629 "bus_master", ··· 1841 1637 bus-range = <0x00 0xff>; 1842 1638 num-lanes = <1>; 1843 1639 1844 - status = "disabled"; 1640 + status = "disabled"; 1845 1641 1846 1642 reg = <0x00608000 0x2000>, 1847 1643 <0x0d000000 0xf1d>, ··· 1881 1677 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1882 1678 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1883 1679 1884 - clock-names = "pipe", 1680 + clock-names = "pipe", 1885 1681 "aux", 1886 1682 "cfg", 1887 1683 "bus_master", ··· 1931 1727 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1932 1728 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1933 1729 1934 - clock-names = "pipe", 1730 + clock-names = "pipe", 1935 1731 "aux", 1936 1732 "cfg", 1937 1733 "bus_master", ··· 2217 2013 <&mmcc VIDEO_AXI_CLK>, 2218 2014 <&mmcc VIDEO_MAXI_CLK>; 2219 2015 clock-names = "core", "iface", "bus", "mbus"; 2016 + interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2017 + <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2018 + interconnect-names = "video-mem", "cpu-cfg"; 2220 2019 iommus = <&venus_smmu 0x00>, 2221 2020 <&venus_smmu 0x01>, 2222 2021 <&venus_smmu 0x0a>, ··· 2939 2732 <&gcc GCC_USB30_MASTER_CLK>; 2940 2733 assigned-clock-rates = <19200000>, <120000000>; 2941 2734 2735 + interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2736 + <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2737 + interconnect-names = "usb-ddr", "apps-usb"; 2738 + 2942 2739 power-domains = <&gcc USB30_GDSC>; 2943 2740 status = "disabled"; 2944 2741 ··· 2980 2769 <0x07410600 0x1a8>; 2981 2770 #phy-cells = <0>; 2982 2771 2983 - #clock-cells = <1>; 2772 + #clock-cells = <0>; 2984 2773 clock-output-names = "usb3_phy_pipe_clk_src"; 2985 2774 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2986 2775 clock-names = "pipe0"; ··· 3015 2804 status = "disabled"; 3016 2805 }; 3017 2806 3018 - sdhc1: sdhci@7464900 { 2807 + sdhc1: mmc@7464900 { 3019 2808 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3020 2809 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3021 2810 reg-names = "hc_mem", "core_mem"; ··· 3028 2817 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3029 2818 <&gcc GCC_SDCC1_APPS_CLK>, 3030 2819 <&rpmcc RPM_SMD_BB_CLK1>; 2820 + resets = <&gcc GCC_SDCC1_BCR>; 3031 2821 3032 2822 pinctrl-names = "default", "sleep"; 3033 2823 pinctrl-0 = <&sdc1_state_on>; ··· 3039 2827 status = "disabled"; 3040 2828 }; 3041 2829 3042 - sdhc2: sdhci@74a4900 { 2830 + sdhc2: mmc@74a4900 { 3043 2831 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3044 2832 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3045 2833 reg-names = "hc_mem", "core_mem"; ··· 3052 2840 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3053 2841 <&gcc GCC_SDCC2_APPS_CLK>, 3054 2842 <&rpmcc RPM_SMD_BB_CLK1>; 2843 + resets = <&gcc GCC_SDCC2_BCR>; 3055 2844 3056 2845 pinctrl-names = "default", "sleep"; 3057 2846 pinctrl-0 = <&sdc2_state_on>; ··· 3297 3084 compatible = "qcom,bam-v1.7.0"; 3298 3085 qcom,controlled-remotely; 3299 3086 reg = <0x09184000 0x32000>; 3300 - num-channels = <31>; 3087 + num-channels = <31>; 3301 3088 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3302 3089 #dma-cells = <1>; 3303 3090 qcom,ee = <1>; ··· 3309 3096 reg = <0x091c0000 0x2C000>; 3310 3097 reg-names = "ctrl"; 3311 3098 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3312 - dmas = <&slimbam 3>, <&slimbam 4>, 3099 + dmas = <&slimbam 3>, <&slimbam 4>, 3313 3100 <&slimbam 5>, <&slimbam 6>; 3314 3101 dma-names = "rx", "tx", "tx2", "rx2"; 3315 3102 #address-cells = <1>; ··· 3321 3108 3322 3109 tasha_ifd: tas-ifd { 3323 3110 compatible = "slim217,1a0"; 3324 - reg = <0 0>; 3111 + reg = <0 0>; 3325 3112 }; 3326 3113 3327 3114 wcd9335: codec@1{ ··· 3329 3116 pinctrl-names = "default"; 3330 3117 3331 3118 compatible = "slim217,1a0"; 3332 - reg = <1 0>; 3119 + reg = <1 0>; 3333 3120 3334 3121 interrupt-parent = <&tlmm>; 3335 3122 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3336 3123 <53 IRQ_TYPE_LEVEL_HIGH>; 3337 - interrupt-names = "intr1", "intr2"; 3124 + interrupt-names = "intr1", "intr2"; 3338 3125 interrupt-controller; 3339 3126 #interrupt-cells = <1>; 3340 3127 reset-gpios = <&tlmm 64 0>; 3341 3128 3342 - slim-ifc-dev = <&tasha_ifd>; 3129 + slim-ifc-dev = <&tasha_ifd>; 3343 3130 3344 3131 #sound-dai-cells = <1>; 3345 3132 };
+8 -15
arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts
··· 16 16 17 17 touchpad@15 { 18 18 compatible = "hid-over-i2c"; 19 - interrupt-parent = <&tlmm>; 20 - interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; 21 19 reg = <0x15>; 22 - hid-descr-addr = <0x0001>; 23 - 24 20 pinctrl-names = "default"; 25 21 pinctrl-0 = <&touchpad>; 22 + 23 + interrupt-parent = <&tlmm>; 24 + interrupts = <123 IRQ_TYPE_LEVEL_LOW>; 25 + 26 + hid-descr-addr = <0x0001>; 26 27 }; 27 28 28 29 keyboard@3a { 29 30 compatible = "hid-over-i2c"; 30 - interrupt-parent = <&tlmm>; 31 - interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; 32 31 reg = <0x3a>; 32 + interrupt-parent = <&tlmm>; 33 + interrupts = <37 IRQ_TYPE_LEVEL_LOW>; 34 + 33 35 hid-descr-addr = <0x0001>; 34 36 }; 35 37 }; 36 38 37 39 &sdhc2 { 38 40 cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 39 - }; 40 - 41 - &tlmm { 42 - touchpad: touchpad { 43 - config { 44 - pins = "gpio123"; 45 - bias-pull-up; 46 - }; 47 - }; 48 41 };
+85 -53
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
··· 8 8 */ 9 9 10 10 #include "msm8998.dtsi" 11 - #include "pm8998.dtsi" 12 11 #include "pm8005.dtsi" 12 + #include "pm8998.dtsi" 13 13 14 14 / { 15 - chosen { 16 - }; 17 - 18 15 vph_pwr: vph-pwr-regulator { 19 16 compatible = "regulator-fixed"; 20 17 regulator-name = "vph_pwr"; ··· 31 34 vddrf-supply = <&vreg_l17a_1p3>; 32 35 vddch0-supply = <&vreg_l25a_3p3>; 33 36 max-speed = <3200000>; 37 + }; 38 + }; 39 + 40 + &blsp1_uart3_on { 41 + rx { 42 + /delete-property/ bias-disable; 43 + /* 44 + * Configure a pull-up on 45 (RX). This is needed to 45 + * avoid garbage data when the TX pin of the Bluetooth 46 + * module is in tri-state (module powered off or not 47 + * driving the signal yet). 48 + */ 49 + bias-pull-up; 50 + }; 51 + 52 + cts { 53 + /delete-property/ bias-disable; 54 + /* 55 + * Configure a pull-down on 47 (CTS) to match the pull 56 + * of the Bluetooth module. 57 + */ 58 + bias-pull-down; 34 59 }; 35 60 }; 36 61 ··· 93 74 cpu-idle-states = <&BIG_CPU_SLEEP_1>; 94 75 }; 95 76 77 + /* 78 + * If EFIFB is used, enabling MMCC will cause important MMSS clocks to be cleaned 79 + * up, because as far as Linux is concerned - they are unused. Disable it by default 80 + * on clamshell devices, as it will break them, unless either simplefb is configured to 81 + * hold a vote for these clocks, or panels are brought up properly, using drm/msm. 82 + */ 83 + &mmcc { 84 + status = "disabled"; 85 + }; 86 + 87 + &mmss_smmu { 88 + status = "disabled"; 89 + }; 90 + 96 91 &pcie0 { 97 92 status = "okay"; 98 93 }; ··· 115 82 status = "okay"; 116 83 }; 117 84 118 - &pm8005_lsid1 { 119 - pm8005-regulators { 120 - compatible = "qcom,pm8005-regulators"; 85 + &pm8005_regulators { 86 + vdd_s1-supply = <&vph_pwr>; 121 87 122 - vdd_s1-supply = <&vph_pwr>; 88 + pm8005_s1: s1 { /* VDD_GFX supply */ 89 + regulator-min-microvolt = <524000>; 90 + regulator-max-microvolt = <1100000>; 91 + regulator-enable-ramp-delay = <500>; 123 92 124 - pm8005_s1: s1 { /* VDD_GFX supply */ 125 - regulator-min-microvolt = <524000>; 126 - regulator-max-microvolt = <1100000>; 127 - regulator-enable-ramp-delay = <500>; 128 - 129 - /* hack until we rig up the gpu consumer */ 130 - regulator-always-on; 131 - }; 93 + /* hack until we rig up the gpu consumer */ 94 + regulator-always-on; 132 95 }; 133 96 }; 134 97 ··· 172 143 regulator-min-microvolt = <1352000>; 173 144 regulator-max-microvolt = <1352000>; 174 145 }; 146 + 175 147 vreg_s4a_1p8: s4 { 176 148 regulator-min-microvolt = <1800000>; 177 149 regulator-max-microvolt = <1800000>; 178 150 regulator-allow-set-load; 179 151 }; 152 + 180 153 vreg_s5a_2p04: s5 { 181 154 regulator-min-microvolt = <1904000>; 182 155 regulator-max-microvolt = <2040000>; 183 156 }; 157 + 184 158 vreg_s7a_1p025: s7 { 185 159 regulator-min-microvolt = <900000>; 186 160 regulator-max-microvolt = <1028000>; 187 161 }; 162 + 188 163 vreg_l1a_0p875: l1 { 189 164 regulator-min-microvolt = <880000>; 190 165 regulator-max-microvolt = <880000>; 191 166 regulator-allow-set-load; 192 167 }; 168 + 193 169 vreg_l2a_1p2: l2 { 194 170 regulator-min-microvolt = <1200000>; 195 171 regulator-max-microvolt = <1200000>; 196 172 regulator-allow-set-load; 197 173 }; 174 + 198 175 vreg_l3a_1p0: l3 { 199 176 regulator-min-microvolt = <1000000>; 200 177 regulator-max-microvolt = <1000000>; 201 178 }; 179 + 202 180 vreg_l5a_0p8: l5 { 203 181 regulator-min-microvolt = <800000>; 204 182 regulator-max-microvolt = <800000>; 205 183 }; 184 + 206 185 vreg_l6a_1p8: l6 { 207 186 regulator-min-microvolt = <1808000>; 208 187 regulator-max-microvolt = <1808000>; 209 188 }; 189 + 210 190 vreg_l7a_1p8: l7 { 211 191 regulator-min-microvolt = <1800000>; 212 192 regulator-max-microvolt = <1800000>; 213 193 regulator-allow-set-load; 214 194 }; 195 + 215 196 vreg_l8a_1p2: l8 { 216 197 regulator-min-microvolt = <1200000>; 217 198 regulator-max-microvolt = <1200000>; 218 199 }; 200 + 219 201 vreg_l9a_1p8: l9 { 220 202 regulator-min-microvolt = <1808000>; 221 203 regulator-max-microvolt = <2960000>; 222 204 }; 205 + 223 206 vreg_l10a_1p8: l10 { 224 207 regulator-min-microvolt = <1808000>; 225 208 regulator-max-microvolt = <2960000>; 226 209 }; 210 + 227 211 vreg_l11a_1p0: l11 { 228 212 regulator-min-microvolt = <1000000>; 229 213 regulator-max-microvolt = <1000000>; 230 214 }; 215 + 231 216 vreg_l12a_1p8: l12 { 232 217 regulator-min-microvolt = <1800000>; 233 218 regulator-max-microvolt = <1800000>; 234 219 }; 220 + 235 221 vreg_l13a_2p95: l13 { 236 222 regulator-min-microvolt = <1808000>; 237 223 regulator-max-microvolt = <2960000>; 238 224 }; 225 + 239 226 vreg_l14a_1p88: l14 { 240 227 regulator-min-microvolt = <1880000>; 241 228 regulator-max-microvolt = <1880000>; 242 229 }; 230 + 243 231 vreg_l15a_1p8: l15 { 244 232 regulator-min-microvolt = <1800000>; 245 233 regulator-max-microvolt = <1800000>; 246 234 }; 235 + 247 236 vreg_l16a_2p7: l16 { 248 237 regulator-min-microvolt = <2704000>; 249 238 regulator-max-microvolt = <2704000>; 250 239 }; 240 + 251 241 vreg_l17a_1p3: l17 { 252 242 regulator-min-microvolt = <1304000>; 253 243 regulator-max-microvolt = <1304000>; 254 244 regulator-allow-set-load; 255 245 }; 246 + 256 247 vreg_l18a_2p7: l18 { 257 248 regulator-min-microvolt = <2704000>; 258 249 regulator-max-microvolt = <2704000>; 259 250 }; 251 + 260 252 vreg_l19a_3p0: l19 { 261 253 regulator-min-microvolt = <3008000>; 262 254 regulator-max-microvolt = <3008000>; 263 255 }; 256 + 264 257 vreg_l20a_2p95: l20 { 265 258 regulator-min-microvolt = <2960000>; 266 259 regulator-max-microvolt = <2960000>; 267 260 regulator-allow-set-load; 268 261 }; 262 + 269 263 vreg_l21a_2p95: l21 { 270 264 regulator-min-microvolt = <2960000>; 271 265 regulator-max-microvolt = <2960000>; 272 266 regulator-allow-set-load; 273 267 regulator-system-load = <800000>; 274 268 }; 269 + 275 270 vreg_l22a_2p85: l22 { 276 271 regulator-min-microvolt = <2864000>; 277 272 regulator-max-microvolt = <2864000>; 278 273 }; 274 + 279 275 vreg_l23a_3p3: l23 { 280 276 regulator-min-microvolt = <3312000>; 281 277 regulator-max-microvolt = <3312000>; 282 278 }; 279 + 283 280 vreg_l24a_3p075: l24 { 284 281 regulator-min-microvolt = <3088000>; 285 282 regulator-max-microvolt = <3088000>; 286 283 }; 284 + 287 285 vreg_l25a_3p3: l25 { 288 286 regulator-min-microvolt = <3104000>; 289 287 regulator-max-microvolt = <3312000>; 290 288 regulator-allow-set-load; 291 289 }; 290 + 292 291 vreg_l26a_1p2: l26 { 293 292 regulator-min-microvolt = <1200000>; 294 293 regulator-max-microvolt = <1200000>; 295 294 }; 295 + 296 296 vreg_l28_3p0: l28 { 297 297 regulator-min-microvolt = <3008000>; 298 298 regulator-max-microvolt = <3008000>; ··· 336 278 regulator-min-microvolt = <1800000>; 337 279 regulator-max-microvolt = <1800000>; 338 280 }; 339 - 340 281 }; 341 282 }; 342 283 343 284 &remoteproc_mss { 344 285 status = "okay"; 345 - }; 346 - 347 - &tlmm { 348 - gpio-reserved-ranges = <0 4>, <81 4>; 349 - 350 - touchpad: touchpad { 351 - config { 352 - pins = "gpio123"; 353 - bias-pull-up; /* pull up */ 354 - }; 355 - }; 356 286 }; 357 287 358 288 &sdhc2 { ··· 350 304 vqmmc-supply = <&vreg_l13a_2p95>; 351 305 352 306 pinctrl-names = "default", "sleep"; 353 - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; 354 - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; 307 + pinctrl-0 = <&sdc2_on &sdc2_cd>; 308 + pinctrl-1 = <&sdc2_off &sdc2_cd>; 309 + }; 310 + 311 + &tlmm { 312 + gpio-reserved-ranges = <0 4>, <81 4>; 313 + 314 + touchpad: touchpad-pin { 315 + pins = "gpio123"; 316 + bias-pull-up; 317 + }; 355 318 }; 356 319 357 320 &ufshc { ··· 395 340 vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 396 341 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 397 342 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 398 - }; 399 - 400 - /* PINCTRL - board-specific pinctrl */ 401 - &blsp1_uart3_on { 402 - rx { 403 - /delete-property/ bias-disable; 404 - /* 405 - * Configure a pull-up on 45 (RX). This is needed to 406 - * avoid garbage data when the TX pin of the Bluetooth 407 - * module is in tri-state (module powered off or not 408 - * driving the signal yet). 409 - */ 410 - bias-pull-up; 411 - }; 412 - 413 - cts { 414 - /delete-property/ bias-disable; 415 - /* 416 - * Configure a pull-down on 47 (CTS) to match the pull 417 - * of the Bluetooth module. 418 - */ 419 - bias-pull-down; 420 - }; 421 343 };
+434 -26
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
··· 6 6 7 7 /dts-v1/; 8 8 9 - #include "msm8998-mtp.dtsi" 10 - 11 9 #include <dt-bindings/input/input.h> 12 10 #include <dt-bindings/leds/common.h> 13 11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 12 + #include "msm8998.dtsi" 13 + #include "pm8005.dtsi" 14 + #include "pm8998.dtsi" 15 + #include "pmi8998.dtsi" 14 16 15 17 / { 16 18 model = "F(x)tec Pro1 (QX1000)"; 17 19 compatible = "fxtec,pro1", "qcom,msm8998"; 18 20 chassis-type = "handset"; 19 21 qcom,board-id = <0x02000b 0x10>; 22 + 23 + aliases { 24 + serial0 = &blsp2_uart1; 25 + serial1 = &blsp1_uart3; 26 + }; 20 27 21 28 /* 22 29 * Until we hook up type-c detection, we ··· 40 33 pinctrl-names = "default"; 41 34 pinctrl-0 = <&hall_sensor1_default>; 42 35 43 - hall-sensor1 { 36 + event-hall-sensor1 { 44 37 label = "Keyboard Hall Sensor"; 45 38 gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; 46 39 debounce-interval = <15>; ··· 56 49 pinctrl-names = "default"; 57 50 pinctrl-0 = <&gpio_kb_pins_extra>; 58 51 59 - home { 52 + key-home { 60 53 label = "Home"; 61 54 gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; 62 55 linux,code = <KEY_HOMEPAGE>; ··· 64 57 linux,can-disable; 65 58 }; 66 59 67 - super-l { 60 + key-super-l { 68 61 label = "Super Left"; 69 62 gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; 70 63 linux,code = <KEY_FN>; ··· 72 65 linux,can-disable; 73 66 }; 74 67 75 - super-r { 68 + key-super-r { 76 69 label = "Super Right"; 77 70 gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; 78 71 linux,code = <KEY_FN>; ··· 80 73 linux,can-disable; 81 74 }; 82 75 83 - shift { 76 + key-shift { 84 77 label = "Shift"; 85 78 gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; 86 79 linux,code = <KEY_RIGHTSHIFT>; ··· 88 81 linux,can-disable; 89 82 }; 90 83 91 - ctrl { 84 + key-ctrl { 92 85 label = "Ctrl"; 93 86 gpios = <&tlmm 128 GPIO_ACTIVE_LOW>; 94 87 linux,code = <KEY_LEFTCTRL>; ··· 96 89 linux,can-disable; 97 90 }; 98 91 99 - alt { 92 + key-alt { 100 93 label = "Alt"; 101 94 gpios = <&tlmm 129 GPIO_ACTIVE_LOW>; 102 95 linux,code = <KEY_LEFTALT>; ··· 108 101 gpio-keys { 109 102 compatible = "gpio-keys"; 110 103 label = "Side buttons"; 111 - #address-cells = <1>; 112 - #size-cells = <0>; 113 104 pinctrl-names = "default"; 114 105 pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>, 115 106 <&cam_snapshot_pin_a>; 116 - vol-up { 107 + button-vol-up { 117 108 label = "Volume Up"; 118 109 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; 119 110 linux,input-type = <EV_KEY>; ··· 120 115 debounce-interval = <15>; 121 116 }; 122 117 123 - camera-snapshot { 118 + button-camera-snapshot { 124 119 label = "Camera Snapshot"; 125 120 gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; 126 121 linux,input-type = <EV_KEY>; ··· 128 123 debounce-interval = <15>; 129 124 }; 130 125 131 - camera-focus { 126 + button-camera-focus { 132 127 label = "Camera Focus"; 133 128 gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; 134 129 linux,input-type = <EV_KEY>; ··· 140 135 keyboard-leds { 141 136 compatible = "gpio-leds"; 142 137 143 - backlight { 138 + led-0 { 144 139 color = <LED_COLOR_ID_WHITE>; 145 140 default-state = "off"; 146 141 function = LED_FUNCTION_KBD_BACKLIGHT; ··· 149 144 retain-state-suspended; 150 145 }; 151 146 152 - caps-lock { 147 + led-1 { 153 148 color = <LED_COLOR_ID_YELLOW>; 154 149 default-state = "off"; 155 150 function = LED_FUNCTION_CAPSLOCK; ··· 192 187 pinctrl-0 = <&ts_vio_default>; 193 188 regulator-always-on; 194 189 }; 190 + 191 + vph_pwr: vph-pwr-regulator { 192 + compatible = "regulator-fixed"; 193 + regulator-name = "vph_pwr"; 194 + regulator-always-on; 195 + regulator-boot-on; 196 + }; 197 + }; 198 + 199 + &blsp1_uart3 { 200 + status = "okay"; 201 + 202 + bluetooth { 203 + compatible = "qcom,wcn3990-bt"; 204 + 205 + vddio-supply = <&vreg_s4a_1p8>; 206 + vddxo-supply = <&vreg_l7a_1p8>; 207 + vddrf-supply = <&vreg_l17a_1p3>; 208 + vddch0-supply = <&vreg_l25a_3p3>; 209 + max-speed = <3200000>; 210 + }; 211 + }; 212 + 213 + &blsp1_uart3_on { 214 + rx { 215 + /delete-property/ bias-disable; 216 + /* 217 + * Configure a pull-up on 45 (RX). This is needed to 218 + * avoid garbage data when the TX pin of the Bluetooth 219 + * module is in tri-state (module powered off or not 220 + * driving the signal yet). 221 + */ 222 + bias-pull-up; 223 + }; 224 + 225 + cts { 226 + /delete-property/ bias-disable; 227 + /* 228 + * Configure a pull-down on 47 (CTS) to match the pull 229 + * of the Bluetooth module. 230 + */ 231 + bias-pull-down; 232 + }; 233 + }; 234 + 235 + &blsp2_uart1 { 236 + status = "okay"; 195 237 }; 196 238 197 239 &blsp2_i2c1 { 198 - status = "ok"; 240 + status = "okay"; 199 241 200 242 touchscreen@14 { 201 243 compatible = "goodix,gt9286"; ··· 257 205 }; 258 206 }; 259 207 260 - &mmcc { 261 - status = "ok"; 208 + &etf { 209 + status = "okay"; 262 210 }; 263 211 264 - &mmss_smmu { 265 - status = "ok"; 212 + &etm1 { 213 + status = "okay"; 214 + }; 215 + 216 + &etm2 { 217 + status = "okay"; 218 + }; 219 + 220 + &etm3 { 221 + status = "okay"; 222 + }; 223 + 224 + &etm4 { 225 + status = "okay"; 226 + }; 227 + 228 + &etm5 { 229 + status = "okay"; 230 + }; 231 + 232 + &etm6 { 233 + status = "okay"; 234 + }; 235 + 236 + &etm7 { 237 + status = "okay"; 238 + }; 239 + 240 + &etm8 { 241 + status = "okay"; 242 + }; 243 + 244 + &etr { 245 + status = "okay"; 246 + }; 247 + 248 + &funnel1 { 249 + status = "okay"; 250 + }; 251 + 252 + &funnel2 { 253 + status = "okay"; 254 + }; 255 + 256 + &funnel3 { 257 + status = "okay"; 258 + }; 259 + 260 + &funnel4 { 261 + // FIXME: Figure out why clock late_initcall crashes the board with 262 + // this enabled. 263 + // status = "okay"; 264 + }; 265 + 266 + &funnel5 { 267 + // FIXME: Figure out why clock late_initcall crashes the board with 268 + // this enabled. 269 + // status = "okay"; 270 + }; 271 + 272 + &pcie0 { 273 + status = "okay"; 274 + }; 275 + 276 + &pcie_phy { 277 + status = "okay"; 278 + }; 279 + 280 + &pm8005_regulators { 281 + vdd_s1-supply = <&vph_pwr>; 282 + 283 + pm8005_s1: s1 { /* VDD_GFX supply */ 284 + regulator-min-microvolt = <524000>; 285 + regulator-max-microvolt = <1100000>; 286 + regulator-enable-ramp-delay = <500>; 287 + 288 + /* Hack until we rig up the gpu consumer */ 289 + regulator-always-on; 290 + }; 266 291 }; 267 292 268 293 &pm8998_gpio { 269 - vol_up_pin_a: vol-up-active { 294 + vol_up_pin_a: vol-up-active-state { 270 295 pins = "gpio6"; 271 296 function = "normal"; 272 297 bias-pull-up; ··· 351 222 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 352 223 }; 353 224 354 - cam_focus_pin_a: cam-focus-btn-active { 225 + cam_focus_pin_a: cam-focus-btn-active-state { 355 226 pins = "gpio7"; 356 227 function = "normal"; 357 228 bias-pull-up; ··· 359 230 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 360 231 }; 361 232 362 - cam_snapshot_pin_a: cam-snapshot-btn-active { 233 + cam_snapshot_pin_a: cam-snapshot-btn-active-state { 363 234 pins = "gpio8"; 364 235 function = "normal"; 365 236 bias-pull-up; ··· 376 247 debounce = <15625>; 377 248 linux,code = <KEY_VOLUMEDOWN>; 378 249 }; 250 + }; 251 + 252 + &qusb2phy { 253 + status = "okay"; 254 + 255 + vdda-pll-supply = <&vreg_l12a_1p8>; 256 + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 257 + }; 258 + 259 + &replicator1 { 260 + status = "okay"; 261 + }; 262 + 263 + &rpm_requests { 264 + pm8998-regulators { 265 + compatible = "qcom,rpm-pm8998-regulators"; 266 + 267 + vdd_s1-supply = <&vph_pwr>; 268 + vdd_s2-supply = <&vph_pwr>; 269 + vdd_s3-supply = <&vph_pwr>; 270 + vdd_s4-supply = <&vph_pwr>; 271 + vdd_s5-supply = <&vph_pwr>; 272 + vdd_s6-supply = <&vph_pwr>; 273 + vdd_s7-supply = <&vph_pwr>; 274 + vdd_s8-supply = <&vph_pwr>; 275 + vdd_s9-supply = <&vph_pwr>; 276 + vdd_s10-supply = <&vph_pwr>; 277 + vdd_s11-supply = <&vph_pwr>; 278 + vdd_s12-supply = <&vph_pwr>; 279 + vdd_s13-supply = <&vph_pwr>; 280 + vdd_l1_l27-supply = <&vreg_s7a_1p025>; 281 + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; 282 + vdd_l3_l11-supply = <&vreg_s7a_1p025>; 283 + vdd_l4_l5-supply = <&vreg_s7a_1p025>; 284 + vdd_l6-supply = <&vreg_s5a_2p04>; 285 + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; 286 + vdd_l9-supply = <&vreg_bob>; 287 + vdd_l10_l23_l25-supply = <&vreg_bob>; 288 + vdd_l13_l19_l21-supply = <&vreg_bob>; 289 + vdd_l16_l28-supply = <&vreg_bob>; 290 + vdd_l18_l22-supply = <&vreg_bob>; 291 + vdd_l20_l24-supply = <&vreg_bob>; 292 + vdd_l26-supply = <&vreg_s3a_1p35>; 293 + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; 294 + 295 + vreg_s3a_1p35: s3 { 296 + regulator-min-microvolt = <1352000>; 297 + regulator-max-microvolt = <1352000>; 298 + }; 299 + 300 + vreg_s4a_1p8: s4 { 301 + regulator-min-microvolt = <1800000>; 302 + regulator-max-microvolt = <1800000>; 303 + regulator-allow-set-load; 304 + }; 305 + 306 + vreg_s5a_2p04: s5 { 307 + regulator-min-microvolt = <1904000>; 308 + regulator-max-microvolt = <2040000>; 309 + }; 310 + 311 + vreg_s7a_1p025: s7 { 312 + regulator-min-microvolt = <900000>; 313 + regulator-max-microvolt = <1028000>; 314 + }; 315 + 316 + vreg_l1a_0p875: l1 { 317 + regulator-min-microvolt = <880000>; 318 + regulator-max-microvolt = <880000>; 319 + }; 320 + 321 + vreg_l2a_1p2: l2 { 322 + regulator-min-microvolt = <1200000>; 323 + regulator-max-microvolt = <1200000>; 324 + }; 325 + 326 + vreg_l3a_1p0: l3 { 327 + regulator-min-microvolt = <1000000>; 328 + regulator-max-microvolt = <1000000>; 329 + }; 330 + 331 + vreg_l5a_0p8: l5 { 332 + regulator-min-microvolt = <800000>; 333 + regulator-max-microvolt = <800000>; 334 + }; 335 + 336 + vreg_l6a_1p8: l6 { 337 + regulator-min-microvolt = <1808000>; 338 + regulator-max-microvolt = <1808000>; 339 + }; 340 + 341 + vreg_l7a_1p8: l7 { 342 + regulator-min-microvolt = <1800000>; 343 + regulator-max-microvolt = <1800000>; 344 + }; 345 + 346 + vreg_l8a_1p2: l8 { 347 + regulator-min-microvolt = <1200000>; 348 + regulator-max-microvolt = <1200000>; 349 + }; 350 + 351 + vreg_l9a_1p8: l9 { 352 + regulator-min-microvolt = <1808000>; 353 + regulator-max-microvolt = <2960000>; 354 + }; 355 + 356 + vreg_l10a_1p8: l10 { 357 + regulator-min-microvolt = <1808000>; 358 + regulator-max-microvolt = <2960000>; 359 + }; 360 + 361 + vreg_l11a_1p0: l11 { 362 + regulator-min-microvolt = <1000000>; 363 + regulator-max-microvolt = <1000000>; 364 + }; 365 + 366 + vreg_l12a_1p8: l12 { 367 + regulator-min-microvolt = <1800000>; 368 + regulator-max-microvolt = <1800000>; 369 + }; 370 + 371 + vreg_l13a_2p95: l13 { 372 + regulator-min-microvolt = <1808000>; 373 + regulator-max-microvolt = <2960000>; 374 + }; 375 + 376 + vreg_l14a_1p88: l14 { 377 + regulator-min-microvolt = <1880000>; 378 + regulator-max-microvolt = <1880000>; 379 + }; 380 + 381 + vreg_l15a_1p8: l15 { 382 + regulator-min-microvolt = <1800000>; 383 + regulator-max-microvolt = <1800000>; 384 + }; 385 + 386 + vreg_l16a_2p7: l16 { 387 + regulator-min-microvolt = <2704000>; 388 + regulator-max-microvolt = <2704000>; 389 + }; 390 + 391 + vreg_l17a_1p3: l17 { 392 + regulator-min-microvolt = <1304000>; 393 + regulator-max-microvolt = <1304000>; 394 + }; 395 + 396 + vreg_l18a_2p7: l18 { 397 + regulator-min-microvolt = <2704000>; 398 + regulator-max-microvolt = <2704000>; 399 + }; 400 + 401 + vreg_l19a_3p0: l19 { 402 + regulator-min-microvolt = <3008000>; 403 + regulator-max-microvolt = <3008000>; 404 + }; 405 + 406 + vreg_l20a_2p95: l20 { 407 + regulator-min-microvolt = <2960000>; 408 + regulator-max-microvolt = <2960000>; 409 + regulator-allow-set-load; 410 + }; 411 + 412 + vreg_l21a_2p95: l21 { 413 + regulator-min-microvolt = <2960000>; 414 + regulator-max-microvolt = <2960000>; 415 + regulator-system-load = <800000>; 416 + regulator-allow-set-load; 417 + }; 418 + 419 + vreg_l22a_2p85: l22 { 420 + regulator-min-microvolt = <2864000>; 421 + regulator-max-microvolt = <2864000>; 422 + }; 423 + 424 + vreg_l23a_3p3: l23 { 425 + regulator-min-microvolt = <3312000>; 426 + regulator-max-microvolt = <3312000>; 427 + }; 428 + 429 + vreg_l24a_3p075: l24 { 430 + regulator-min-microvolt = <3088000>; 431 + regulator-max-microvolt = <3088000>; 432 + }; 433 + 434 + vreg_l25a_3p3: l25 { 435 + regulator-min-microvolt = <3104000>; 436 + regulator-max-microvolt = <3312000>; 437 + }; 438 + 439 + vreg_l26a_1p2: l26 { 440 + regulator-min-microvolt = <1200000>; 441 + regulator-max-microvolt = <1200000>; 442 + regulator-allow-set-load; 443 + }; 444 + 445 + vreg_l28_3p0: l28 { 446 + regulator-min-microvolt = <3008000>; 447 + regulator-max-microvolt = <3008000>; 448 + }; 449 + 450 + vreg_lvs1a_1p8: lvs1 { 451 + regulator-min-microvolt = <1800000>; 452 + regulator-max-microvolt = <1800000>; 453 + }; 454 + 455 + vreg_lvs2a_1p8: lvs2 { 456 + regulator-min-microvolt = <1800000>; 457 + regulator-max-microvolt = <1800000>; 458 + }; 459 + 460 + }; 461 + 462 + pmi8998-regulators { 463 + compatible = "qcom,rpm-pmi8998-regulators"; 464 + 465 + vdd_bob-supply = <&vph_pwr>; 466 + 467 + vreg_bob: bob { 468 + regulator-min-microvolt = <3312000>; 469 + regulator-max-microvolt = <3600000>; 470 + }; 471 + }; 472 + }; 473 + 474 + &remoteproc_adsp { 475 + status = "okay"; 476 + }; 477 + 478 + &remoteproc_mss { 479 + status = "okay"; 480 + }; 481 + 482 + &remoteproc_slpi { 483 + status = "okay"; 379 484 }; 380 485 381 486 &tlmm { ··· 660 297 }; 661 298 }; 662 299 300 + &sdhc2 { 301 + status = "okay"; 302 + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; 303 + 304 + vmmc-supply = <&vreg_l21a_2p95>; 305 + vqmmc-supply = <&vreg_l13a_2p95>; 306 + 307 + pinctrl-names = "default", "sleep"; 308 + pinctrl-0 = <&sdc2_on &sdc2_cd>; 309 + pinctrl-1 = <&sdc2_off &sdc2_cd>; 310 + }; 311 + 312 + &stm { 313 + status = "okay"; 314 + }; 315 + 663 316 &ufshc { 664 - status = "ok"; 317 + status = "okay"; 318 + vcc-supply = <&vreg_l20a_2p95>; 319 + vccq-supply = <&vreg_l26a_1p2>; 320 + vccq2-supply = <&vreg_s4a_1p8>; 321 + vcc-max-microamp = <750000>; 322 + vccq-max-microamp = <560000>; 323 + vccq2-max-microamp = <750000>; 665 324 }; 666 325 667 326 &ufsphy { 668 - status = "ok"; 327 + status = "okay"; 328 + vdda-phy-supply = <&vreg_l1a_0p875>; 329 + vdda-pll-supply = <&vreg_l2a_1p2>; 330 + vddp-ref-clk-supply = <&vreg_l26a_1p2>; 331 + }; 332 + 333 + &usb3 { 334 + status = "okay"; 669 335 }; 670 336 671 337 &usb3_dwc3 { ··· 702 310 extcon = <&extcon_usb>; 703 311 }; 704 312 313 + &usb3phy { 314 + status = "okay"; 315 + 316 + vdda-phy-supply = <&vreg_l1a_0p875>; 317 + vdda-pll-supply = <&vreg_l2a_1p2>; 318 + }; 319 + 705 320 /* GT9286 analog supply */ 706 321 &vreg_l28_3p0 { 707 322 regulator-min-microvolt = <2800000>; 708 323 regulator-max-microvolt = <2800000>; 324 + }; 325 + 326 + &wifi { 327 + status = "okay"; 328 + 329 + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; 330 + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 331 + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 332 + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 709 333 };
+5 -4
arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts
··· 16 16 17 17 keyboard@3a { 18 18 compatible = "hid-over-i2c"; 19 - interrupt-parent = <&tlmm>; 20 - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; 21 19 reg = <0x3a>; 22 - hid-descr-addr = <0x0001>; 23 - 24 20 pinctrl-names = "default"; 25 21 pinctrl-0 = <&touchpad>; 22 + 23 + interrupt-parent = <&tlmm>; 24 + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; 25 + 26 + hid-descr-addr = <0x0001>; 26 27 }; 27 28 }; 28 29
+5 -4
arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
··· 16 16 17 17 keyboard@3a { 18 18 compatible = "hid-over-i2c"; 19 - interrupt-parent = <&tlmm>; 20 - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; 21 19 reg = <0x3a>; 22 - hid-descr-addr = <0x0001>; 23 - 24 20 pinctrl-names = "default"; 25 21 pinctrl-0 = <&touchpad>; 22 + 23 + interrupt-parent = <&tlmm>; 24 + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; 25 + 26 + hid-descr-addr = <0x0001>; 26 27 }; 27 28 }; 28 29
+441 -2
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
··· 3 3 4 4 /dts-v1/; 5 5 6 - #include "msm8998-mtp.dtsi" 6 + #include "msm8998.dtsi" 7 + #include "pm8005.dtsi" 8 + #include "pm8998.dtsi" 9 + #include "pmi8998.dtsi" 7 10 8 11 / { 9 12 model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; 10 - compatible = "qcom,msm8998-mtp"; 13 + compatible = "qcom,msm8998-mtp", "qcom,msm8998"; 11 14 12 15 qcom,board-id = <8 0>; 16 + 17 + aliases { 18 + serial0 = &blsp2_uart1; 19 + serial1 = &blsp1_uart3; 20 + }; 21 + 22 + chosen { 23 + stdout-path = "serial0:115200n8"; 24 + }; 25 + 26 + vph_pwr: vph-pwr-regulator { 27 + compatible = "regulator-fixed"; 28 + regulator-name = "vph_pwr"; 29 + regulator-always-on; 30 + regulator-boot-on; 31 + }; 32 + }; 33 + 34 + &blsp1_uart3 { 35 + status = "okay"; 36 + 37 + bluetooth { 38 + compatible = "qcom,wcn3990-bt"; 39 + 40 + vddio-supply = <&vreg_s4a_1p8>; 41 + vddxo-supply = <&vreg_l7a_1p8>; 42 + vddrf-supply = <&vreg_l17a_1p3>; 43 + vddch0-supply = <&vreg_l25a_3p3>; 44 + max-speed = <3200000>; 45 + }; 46 + }; 47 + 48 + &blsp1_uart3_on { 49 + rx { 50 + /delete-property/ bias-disable; 51 + /* 52 + * Configure a pull-up on 45 (RX). This is needed to 53 + * avoid garbage data when the TX pin of the Bluetooth 54 + * module is in tri-state (module powered off or not 55 + * driving the signal yet). 56 + */ 57 + bias-pull-up; 58 + }; 59 + 60 + cts { 61 + /delete-property/ bias-disable; 62 + /* 63 + * Configure a pull-down on 47 (CTS) to match the pull 64 + * of the Bluetooth module. 65 + */ 66 + bias-pull-down; 67 + }; 68 + }; 69 + 70 + &blsp2_uart1 { 71 + status = "okay"; 72 + }; 73 + 74 + &etf { 75 + status = "okay"; 76 + }; 77 + 78 + &etm1 { 79 + status = "okay"; 80 + }; 81 + 82 + &etm2 { 83 + status = "okay"; 84 + }; 85 + 86 + &etm3 { 87 + status = "okay"; 88 + }; 89 + 90 + &etm4 { 91 + status = "okay"; 92 + }; 93 + 94 + &etm5 { 95 + status = "okay"; 96 + }; 97 + 98 + &etm6 { 99 + status = "okay"; 100 + }; 101 + 102 + &etm7 { 103 + status = "okay"; 104 + }; 105 + 106 + &etm8 { 107 + status = "okay"; 108 + }; 109 + 110 + &etr { 111 + status = "okay"; 112 + }; 113 + 114 + &funnel1 { 115 + status = "okay"; 116 + }; 117 + 118 + &funnel2 { 119 + status = "okay"; 120 + }; 121 + 122 + &funnel3 { 123 + status = "okay"; 124 + }; 125 + 126 + &funnel4 { 127 + // FIXME: Figure out why clock late_initcall crashes the board with 128 + // this enabled. 129 + // status = "okay"; 130 + }; 131 + 132 + &funnel5 { 133 + // FIXME: Figure out why clock late_initcall crashes the board with 134 + // this enabled. 135 + // status = "okay"; 136 + }; 137 + 138 + &pcie0 { 139 + status = "okay"; 140 + }; 141 + 142 + &pcie_phy { 143 + status = "okay"; 144 + }; 145 + 146 + &pm8005_regulators { 147 + vdd_s1-supply = <&vph_pwr>; 148 + 149 + pm8005_s1: s1 { /* VDD_GFX supply */ 150 + regulator-min-microvolt = <524000>; 151 + regulator-max-microvolt = <1100000>; 152 + regulator-enable-ramp-delay = <500>; 153 + 154 + /* Hack until we rig up the gpu consumer */ 155 + regulator-always-on; 156 + }; 157 + }; 158 + 159 + &qusb2phy { 160 + status = "okay"; 161 + 162 + vdda-pll-supply = <&vreg_l12a_1p8>; 163 + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 164 + }; 165 + 166 + &replicator1 { 167 + status = "okay"; 168 + }; 169 + 170 + &rpm_requests { 171 + pm8998-regulators { 172 + compatible = "qcom,rpm-pm8998-regulators"; 173 + 174 + vdd_s1-supply = <&vph_pwr>; 175 + vdd_s2-supply = <&vph_pwr>; 176 + vdd_s3-supply = <&vph_pwr>; 177 + vdd_s4-supply = <&vph_pwr>; 178 + vdd_s5-supply = <&vph_pwr>; 179 + vdd_s6-supply = <&vph_pwr>; 180 + vdd_s7-supply = <&vph_pwr>; 181 + vdd_s8-supply = <&vph_pwr>; 182 + vdd_s9-supply = <&vph_pwr>; 183 + vdd_s10-supply = <&vph_pwr>; 184 + vdd_s11-supply = <&vph_pwr>; 185 + vdd_s12-supply = <&vph_pwr>; 186 + vdd_s13-supply = <&vph_pwr>; 187 + vdd_l1_l27-supply = <&vreg_s7a_1p025>; 188 + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; 189 + vdd_l3_l11-supply = <&vreg_s7a_1p025>; 190 + vdd_l4_l5-supply = <&vreg_s7a_1p025>; 191 + vdd_l6-supply = <&vreg_s5a_2p04>; 192 + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; 193 + vdd_l9-supply = <&vreg_bob>; 194 + vdd_l10_l23_l25-supply = <&vreg_bob>; 195 + vdd_l13_l19_l21-supply = <&vreg_bob>; 196 + vdd_l16_l28-supply = <&vreg_bob>; 197 + vdd_l18_l22-supply = <&vreg_bob>; 198 + vdd_l20_l24-supply = <&vreg_bob>; 199 + vdd_l26-supply = <&vreg_s3a_1p35>; 200 + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; 201 + 202 + vreg_s3a_1p35: s3 { 203 + regulator-min-microvolt = <1352000>; 204 + regulator-max-microvolt = <1352000>; 205 + }; 206 + 207 + vreg_s4a_1p8: s4 { 208 + regulator-min-microvolt = <1800000>; 209 + regulator-max-microvolt = <1800000>; 210 + regulator-allow-set-load; 211 + }; 212 + 213 + vreg_s5a_2p04: s5 { 214 + regulator-min-microvolt = <1904000>; 215 + regulator-max-microvolt = <2040000>; 216 + }; 217 + 218 + vreg_s7a_1p025: s7 { 219 + regulator-min-microvolt = <900000>; 220 + regulator-max-microvolt = <1028000>; 221 + }; 222 + 223 + vreg_l1a_0p875: l1 { 224 + regulator-min-microvolt = <880000>; 225 + regulator-max-microvolt = <880000>; 226 + }; 227 + 228 + vreg_l2a_1p2: l2 { 229 + regulator-min-microvolt = <1200000>; 230 + regulator-max-microvolt = <1200000>; 231 + }; 232 + 233 + vreg_l3a_1p0: l3 { 234 + regulator-min-microvolt = <1000000>; 235 + regulator-max-microvolt = <1000000>; 236 + }; 237 + 238 + vreg_l5a_0p8: l5 { 239 + regulator-min-microvolt = <800000>; 240 + regulator-max-microvolt = <800000>; 241 + }; 242 + 243 + vreg_l6a_1p8: l6 { 244 + regulator-min-microvolt = <1808000>; 245 + regulator-max-microvolt = <1808000>; 246 + }; 247 + 248 + vreg_l7a_1p8: l7 { 249 + regulator-min-microvolt = <1800000>; 250 + regulator-max-microvolt = <1800000>; 251 + }; 252 + 253 + vreg_l8a_1p2: l8 { 254 + regulator-min-microvolt = <1200000>; 255 + regulator-max-microvolt = <1200000>; 256 + }; 257 + 258 + vreg_l9a_1p8: l9 { 259 + regulator-min-microvolt = <1808000>; 260 + regulator-max-microvolt = <2960000>; 261 + }; 262 + 263 + vreg_l10a_1p8: l10 { 264 + regulator-min-microvolt = <1808000>; 265 + regulator-max-microvolt = <2960000>; 266 + }; 267 + 268 + vreg_l11a_1p0: l11 { 269 + regulator-min-microvolt = <1000000>; 270 + regulator-max-microvolt = <1000000>; 271 + }; 272 + 273 + vreg_l12a_1p8: l12 { 274 + regulator-min-microvolt = <1800000>; 275 + regulator-max-microvolt = <1800000>; 276 + }; 277 + 278 + vreg_l13a_2p95: l13 { 279 + regulator-min-microvolt = <1808000>; 280 + regulator-max-microvolt = <2960000>; 281 + }; 282 + 283 + vreg_l14a_1p88: l14 { 284 + regulator-min-microvolt = <1880000>; 285 + regulator-max-microvolt = <1880000>; 286 + }; 287 + 288 + vreg_l15a_1p8: l15 { 289 + regulator-min-microvolt = <1800000>; 290 + regulator-max-microvolt = <1800000>; 291 + }; 292 + 293 + vreg_l16a_2p7: l16 { 294 + regulator-min-microvolt = <2704000>; 295 + regulator-max-microvolt = <2704000>; 296 + }; 297 + 298 + vreg_l17a_1p3: l17 { 299 + regulator-min-microvolt = <1304000>; 300 + regulator-max-microvolt = <1304000>; 301 + }; 302 + 303 + vreg_l18a_2p7: l18 { 304 + regulator-min-microvolt = <2704000>; 305 + regulator-max-microvolt = <2704000>; 306 + }; 307 + 308 + vreg_l19a_3p0: l19 { 309 + regulator-min-microvolt = <3008000>; 310 + regulator-max-microvolt = <3008000>; 311 + }; 312 + 313 + vreg_l20a_2p95: l20 { 314 + regulator-min-microvolt = <2960000>; 315 + regulator-max-microvolt = <2960000>; 316 + regulator-allow-set-load; 317 + }; 318 + 319 + vreg_l21a_2p95: l21 { 320 + regulator-min-microvolt = <2960000>; 321 + regulator-max-microvolt = <2960000>; 322 + regulator-system-load = <800000>; 323 + regulator-allow-set-load; 324 + }; 325 + 326 + vreg_l22a_2p85: l22 { 327 + regulator-min-microvolt = <2864000>; 328 + regulator-max-microvolt = <2864000>; 329 + }; 330 + 331 + vreg_l23a_3p3: l23 { 332 + regulator-min-microvolt = <3312000>; 333 + regulator-max-microvolt = <3312000>; 334 + }; 335 + 336 + vreg_l24a_3p075: l24 { 337 + regulator-min-microvolt = <3088000>; 338 + regulator-max-microvolt = <3088000>; 339 + }; 340 + 341 + vreg_l25a_3p3: l25 { 342 + regulator-min-microvolt = <3104000>; 343 + regulator-max-microvolt = <3312000>; 344 + }; 345 + 346 + vreg_l26a_1p2: l26 { 347 + regulator-min-microvolt = <1200000>; 348 + regulator-max-microvolt = <1200000>; 349 + regulator-allow-set-load; 350 + }; 351 + 352 + vreg_l28_3p0: l28 { 353 + regulator-min-microvolt = <3008000>; 354 + regulator-max-microvolt = <3008000>; 355 + }; 356 + 357 + vreg_lvs1a_1p8: lvs1 { 358 + regulator-min-microvolt = <1800000>; 359 + regulator-max-microvolt = <1800000>; 360 + }; 361 + 362 + vreg_lvs2a_1p8: lvs2 { 363 + regulator-min-microvolt = <1800000>; 364 + regulator-max-microvolt = <1800000>; 365 + }; 366 + 367 + }; 368 + 369 + pmi8998-regulators { 370 + compatible = "qcom,rpm-pmi8998-regulators"; 371 + 372 + vdd_bob-supply = <&vph_pwr>; 373 + 374 + vreg_bob: bob { 375 + regulator-min-microvolt = <3312000>; 376 + regulator-max-microvolt = <3600000>; 377 + }; 378 + }; 379 + }; 380 + 381 + &remoteproc_adsp { 382 + status = "okay"; 383 + }; 384 + 385 + &remoteproc_mss { 386 + status = "okay"; 387 + }; 388 + 389 + &remoteproc_slpi { 390 + status = "okay"; 391 + }; 392 + 393 + &tlmm { 394 + gpio-reserved-ranges = <0 4>, <81 4>; 395 + }; 396 + 397 + &sdhc2 { 398 + status = "okay"; 399 + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; 400 + 401 + vmmc-supply = <&vreg_l21a_2p95>; 402 + vqmmc-supply = <&vreg_l13a_2p95>; 403 + 404 + pinctrl-names = "default", "sleep"; 405 + pinctrl-0 = <&sdc2_on &sdc2_cd>; 406 + pinctrl-1 = <&sdc2_off &sdc2_cd>; 407 + }; 408 + 409 + &stm { 410 + status = "okay"; 411 + }; 412 + 413 + &ufshc { 414 + status = "okay"; 415 + vcc-supply = <&vreg_l20a_2p95>; 416 + vccq-supply = <&vreg_l26a_1p2>; 417 + vccq2-supply = <&vreg_s4a_1p8>; 418 + vcc-max-microamp = <750000>; 419 + vccq-max-microamp = <560000>; 420 + vccq2-max-microamp = <750000>; 421 + }; 422 + 423 + &ufsphy { 424 + status = "okay"; 425 + vdda-phy-supply = <&vreg_l1a_0p875>; 426 + vdda-pll-supply = <&vreg_l2a_1p2>; 427 + vddp-ref-clk-supply = <&vreg_l26a_1p2>; 428 + }; 429 + 430 + &usb3 { 431 + status = "okay"; 432 + }; 433 + 434 + &usb3_dwc3 { 435 + dr_mode = "host"; /* Force to host until we have Type-C hooked up */ 436 + }; 437 + 438 + &usb3phy { 439 + status = "okay"; 440 + 441 + vdda-phy-supply = <&vreg_l1a_0p875>; 442 + vdda-pll-supply = <&vreg_l2a_1p2>; 443 + }; 444 + 445 + &wifi { 446 + status = "okay"; 447 + 448 + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; 449 + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 450 + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 451 + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 13 452 };
-421
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 - 4 - #include "msm8998.dtsi" 5 - #include "pm8998.dtsi" 6 - #include "pmi8998.dtsi" 7 - #include "pm8005.dtsi" 8 - 9 - / { 10 - aliases { 11 - serial0 = &blsp2_uart1; 12 - serial1 = &blsp1_uart3; 13 - }; 14 - 15 - chosen { 16 - stdout-path = "serial0:115200n8"; 17 - }; 18 - 19 - vph_pwr: vph-pwr-regulator { 20 - compatible = "regulator-fixed"; 21 - regulator-name = "vph_pwr"; 22 - regulator-always-on; 23 - regulator-boot-on; 24 - }; 25 - }; 26 - 27 - &blsp1_uart3 { 28 - status = "okay"; 29 - 30 - bluetooth { 31 - compatible = "qcom,wcn3990-bt"; 32 - 33 - vddio-supply = <&vreg_s4a_1p8>; 34 - vddxo-supply = <&vreg_l7a_1p8>; 35 - vddrf-supply = <&vreg_l17a_1p3>; 36 - vddch0-supply = <&vreg_l25a_3p3>; 37 - max-speed = <3200000>; 38 - }; 39 - }; 40 - 41 - &blsp2_uart1 { 42 - status = "okay"; 43 - }; 44 - 45 - &etf { 46 - status = "okay"; 47 - }; 48 - 49 - &etm1 { 50 - status = "okay"; 51 - }; 52 - 53 - &etm2 { 54 - status = "okay"; 55 - }; 56 - 57 - &etm3 { 58 - status = "okay"; 59 - }; 60 - 61 - &etm4 { 62 - status = "okay"; 63 - }; 64 - 65 - &etm5 { 66 - status = "okay"; 67 - }; 68 - 69 - &etm6 { 70 - status = "okay"; 71 - }; 72 - 73 - &etm7 { 74 - status = "okay"; 75 - }; 76 - 77 - &etm8 { 78 - status = "okay"; 79 - }; 80 - 81 - &etr { 82 - status = "okay"; 83 - }; 84 - 85 - &funnel1 { 86 - status = "okay"; 87 - }; 88 - 89 - &funnel2 { 90 - status = "okay"; 91 - }; 92 - 93 - &funnel3 { 94 - status = "okay"; 95 - }; 96 - 97 - &funnel4 { 98 - // FIXME: Figure out why clock late_initcall crashes the board with 99 - // this enabled. 100 - // status = "okay"; 101 - }; 102 - 103 - &funnel5 { 104 - // FIXME: Figure out why clock late_initcall crashes the board with 105 - // this enabled. 106 - // status = "okay"; 107 - }; 108 - 109 - &pcie0 { 110 - status = "okay"; 111 - }; 112 - 113 - &pcie_phy { 114 - status = "okay"; 115 - }; 116 - 117 - &pm8005_lsid1 { 118 - pm8005-regulators { 119 - compatible = "qcom,pm8005-regulators"; 120 - 121 - vdd_s1-supply = <&vph_pwr>; 122 - 123 - pm8005_s1: s1 { /* VDD_GFX supply */ 124 - regulator-min-microvolt = <524000>; 125 - regulator-max-microvolt = <1100000>; 126 - regulator-enable-ramp-delay = <500>; 127 - 128 - /* hack until we rig up the gpu consumer */ 129 - regulator-always-on; 130 - }; 131 - }; 132 - }; 133 - 134 - &qusb2phy { 135 - status = "okay"; 136 - 137 - vdda-pll-supply = <&vreg_l12a_1p8>; 138 - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 139 - }; 140 - 141 - &replicator1 { 142 - status = "okay"; 143 - }; 144 - 145 - &rpm_requests { 146 - pm8998-regulators { 147 - compatible = "qcom,rpm-pm8998-regulators"; 148 - 149 - vdd_s1-supply = <&vph_pwr>; 150 - vdd_s2-supply = <&vph_pwr>; 151 - vdd_s3-supply = <&vph_pwr>; 152 - vdd_s4-supply = <&vph_pwr>; 153 - vdd_s5-supply = <&vph_pwr>; 154 - vdd_s6-supply = <&vph_pwr>; 155 - vdd_s7-supply = <&vph_pwr>; 156 - vdd_s8-supply = <&vph_pwr>; 157 - vdd_s9-supply = <&vph_pwr>; 158 - vdd_s10-supply = <&vph_pwr>; 159 - vdd_s11-supply = <&vph_pwr>; 160 - vdd_s12-supply = <&vph_pwr>; 161 - vdd_s13-supply = <&vph_pwr>; 162 - vdd_l1_l27-supply = <&vreg_s7a_1p025>; 163 - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; 164 - vdd_l3_l11-supply = <&vreg_s7a_1p025>; 165 - vdd_l4_l5-supply = <&vreg_s7a_1p025>; 166 - vdd_l6-supply = <&vreg_s5a_2p04>; 167 - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; 168 - vdd_l9-supply = <&vreg_bob>; 169 - vdd_l10_l23_l25-supply = <&vreg_bob>; 170 - vdd_l13_l19_l21-supply = <&vreg_bob>; 171 - vdd_l16_l28-supply = <&vreg_bob>; 172 - vdd_l18_l22-supply = <&vreg_bob>; 173 - vdd_l20_l24-supply = <&vreg_bob>; 174 - vdd_l26-supply = <&vreg_s3a_1p35>; 175 - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; 176 - 177 - vreg_s3a_1p35: s3 { 178 - regulator-min-microvolt = <1352000>; 179 - regulator-max-microvolt = <1352000>; 180 - }; 181 - vreg_s4a_1p8: s4 { 182 - regulator-min-microvolt = <1800000>; 183 - regulator-max-microvolt = <1800000>; 184 - regulator-allow-set-load; 185 - }; 186 - vreg_s5a_2p04: s5 { 187 - regulator-min-microvolt = <1904000>; 188 - regulator-max-microvolt = <2040000>; 189 - }; 190 - vreg_s7a_1p025: s7 { 191 - regulator-min-microvolt = <900000>; 192 - regulator-max-microvolt = <1028000>; 193 - }; 194 - vreg_l1a_0p875: l1 { 195 - regulator-min-microvolt = <880000>; 196 - regulator-max-microvolt = <880000>; 197 - }; 198 - vreg_l2a_1p2: l2 { 199 - regulator-min-microvolt = <1200000>; 200 - regulator-max-microvolt = <1200000>; 201 - }; 202 - vreg_l3a_1p0: l3 { 203 - regulator-min-microvolt = <1000000>; 204 - regulator-max-microvolt = <1000000>; 205 - }; 206 - vreg_l5a_0p8: l5 { 207 - regulator-min-microvolt = <800000>; 208 - regulator-max-microvolt = <800000>; 209 - }; 210 - vreg_l6a_1p8: l6 { 211 - regulator-min-microvolt = <1808000>; 212 - regulator-max-microvolt = <1808000>; 213 - }; 214 - vreg_l7a_1p8: l7 { 215 - regulator-min-microvolt = <1800000>; 216 - regulator-max-microvolt = <1800000>; 217 - }; 218 - vreg_l8a_1p2: l8 { 219 - regulator-min-microvolt = <1200000>; 220 - regulator-max-microvolt = <1200000>; 221 - }; 222 - vreg_l9a_1p8: l9 { 223 - regulator-min-microvolt = <1808000>; 224 - regulator-max-microvolt = <2960000>; 225 - }; 226 - vreg_l10a_1p8: l10 { 227 - regulator-min-microvolt = <1808000>; 228 - regulator-max-microvolt = <2960000>; 229 - }; 230 - vreg_l11a_1p0: l11 { 231 - regulator-min-microvolt = <1000000>; 232 - regulator-max-microvolt = <1000000>; 233 - }; 234 - vreg_l12a_1p8: l12 { 235 - regulator-min-microvolt = <1800000>; 236 - regulator-max-microvolt = <1800000>; 237 - }; 238 - vreg_l13a_2p95: l13 { 239 - regulator-min-microvolt = <1808000>; 240 - regulator-max-microvolt = <2960000>; 241 - }; 242 - vreg_l14a_1p88: l14 { 243 - regulator-min-microvolt = <1880000>; 244 - regulator-max-microvolt = <1880000>; 245 - }; 246 - vreg_l15a_1p8: l15 { 247 - regulator-min-microvolt = <1800000>; 248 - regulator-max-microvolt = <1800000>; 249 - }; 250 - vreg_l16a_2p7: l16 { 251 - regulator-min-microvolt = <2704000>; 252 - regulator-max-microvolt = <2704000>; 253 - }; 254 - vreg_l17a_1p3: l17 { 255 - regulator-min-microvolt = <1304000>; 256 - regulator-max-microvolt = <1304000>; 257 - }; 258 - vreg_l18a_2p7: l18 { 259 - regulator-min-microvolt = <2704000>; 260 - regulator-max-microvolt = <2704000>; 261 - }; 262 - vreg_l19a_3p0: l19 { 263 - regulator-min-microvolt = <3008000>; 264 - regulator-max-microvolt = <3008000>; 265 - }; 266 - vreg_l20a_2p95: l20 { 267 - regulator-min-microvolt = <2960000>; 268 - regulator-max-microvolt = <2960000>; 269 - regulator-allow-set-load; 270 - }; 271 - vreg_l21a_2p95: l21 { 272 - regulator-min-microvolt = <2960000>; 273 - regulator-max-microvolt = <2960000>; 274 - regulator-allow-set-load; 275 - regulator-system-load = <800000>; 276 - }; 277 - vreg_l22a_2p85: l22 { 278 - regulator-min-microvolt = <2864000>; 279 - regulator-max-microvolt = <2864000>; 280 - }; 281 - vreg_l23a_3p3: l23 { 282 - regulator-min-microvolt = <3312000>; 283 - regulator-max-microvolt = <3312000>; 284 - }; 285 - vreg_l24a_3p075: l24 { 286 - regulator-min-microvolt = <3088000>; 287 - regulator-max-microvolt = <3088000>; 288 - }; 289 - vreg_l25a_3p3: l25 { 290 - regulator-min-microvolt = <3104000>; 291 - regulator-max-microvolt = <3312000>; 292 - }; 293 - vreg_l26a_1p2: l26 { 294 - regulator-min-microvolt = <1200000>; 295 - regulator-max-microvolt = <1200000>; 296 - regulator-allow-set-load; 297 - }; 298 - vreg_l28_3p0: l28 { 299 - regulator-min-microvolt = <3008000>; 300 - regulator-max-microvolt = <3008000>; 301 - }; 302 - 303 - vreg_lvs1a_1p8: lvs1 { 304 - regulator-min-microvolt = <1800000>; 305 - regulator-max-microvolt = <1800000>; 306 - }; 307 - 308 - vreg_lvs2a_1p8: lvs2 { 309 - regulator-min-microvolt = <1800000>; 310 - regulator-max-microvolt = <1800000>; 311 - }; 312 - 313 - }; 314 - 315 - pmi8998-regulators { 316 - compatible = "qcom,rpm-pmi8998-regulators"; 317 - 318 - vdd_bob-supply = <&vph_pwr>; 319 - 320 - vreg_bob: bob { 321 - regulator-min-microvolt = <3312000>; 322 - regulator-max-microvolt = <3600000>; 323 - }; 324 - }; 325 - }; 326 - 327 - &remoteproc_adsp { 328 - status = "okay"; 329 - }; 330 - 331 - &remoteproc_mss { 332 - status = "okay"; 333 - }; 334 - 335 - &remoteproc_slpi { 336 - status = "okay"; 337 - }; 338 - 339 - &tlmm { 340 - gpio-reserved-ranges = <0 4>, <81 4>; 341 - }; 342 - 343 - &sdhc2 { 344 - status = "okay"; 345 - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; 346 - 347 - vmmc-supply = <&vreg_l21a_2p95>; 348 - vqmmc-supply = <&vreg_l13a_2p95>; 349 - 350 - pinctrl-names = "default", "sleep"; 351 - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; 352 - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; 353 - }; 354 - 355 - &stm { 356 - status = "okay"; 357 - }; 358 - 359 - &ufshc { 360 - status = "okay"; 361 - vcc-supply = <&vreg_l20a_2p95>; 362 - vccq-supply = <&vreg_l26a_1p2>; 363 - vccq2-supply = <&vreg_s4a_1p8>; 364 - vcc-max-microamp = <750000>; 365 - vccq-max-microamp = <560000>; 366 - vccq2-max-microamp = <750000>; 367 - }; 368 - 369 - &ufsphy { 370 - status = "okay"; 371 - vdda-phy-supply = <&vreg_l1a_0p875>; 372 - vdda-pll-supply = <&vreg_l2a_1p2>; 373 - vddp-ref-clk-supply = <&vreg_l26a_1p2>; 374 - }; 375 - 376 - &usb3 { 377 - status = "okay"; 378 - }; 379 - 380 - &usb3_dwc3 { 381 - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ 382 - }; 383 - 384 - &usb3phy { 385 - status = "okay"; 386 - 387 - vdda-phy-supply = <&vreg_l1a_0p875>; 388 - vdda-pll-supply = <&vreg_l2a_1p2>; 389 - }; 390 - 391 - &wifi { 392 - status = "okay"; 393 - 394 - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; 395 - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 396 - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 397 - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 398 - }; 399 - 400 - /* PINCTRL - board-specific pinctrl */ 401 - &blsp1_uart3_on { 402 - rx { 403 - /delete-property/ bias-disable; 404 - /* 405 - * Configure a pull-up on 45 (RX). This is needed to 406 - * avoid garbage data when the TX pin of the Bluetooth 407 - * module is in tri-state (module powered off or not 408 - * driving the signal yet). 409 - */ 410 - bias-pull-up; 411 - }; 412 - 413 - cts { 414 - /delete-property/ bias-disable; 415 - /* 416 - * Configure a pull-down on 47 (CTS) to match the pull 417 - * of the Bluetooth module. 418 - */ 419 - bias-pull-down; 420 - }; 421 - };
+1 -1
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
··· 32 32 }; 33 33 34 34 &pmi8998_gpio { 35 - button_backlight_default: button-backlight-default { 35 + button_backlight_default: button-backlight-state { 36 36 pinconf { 37 37 pins = "gpio5"; 38 38 function = "normal";
+61 -27
arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
··· 11 11 #include <dt-bindings/gpio/gpio.h> 12 12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 13 13 #include "msm8998.dtsi" 14 + #include "pm8005.dtsi" 14 15 #include "pm8998.dtsi" 15 16 #include "pmi8998.dtsi" 16 - #include "pm8005.dtsi" 17 17 18 18 / { 19 19 /* Required for bootloader to select correct board */ ··· 32 32 height = <1920>; 33 33 stride = <(1080 * 4)>; 34 34 format = "a8r8g8b8"; 35 + /* 36 + * That's a lot of clocks, but it's necessary due 37 + * to unused clk cleanup & no panel driver yet.. 38 + */ 39 + clocks = <&mmcc MDSS_AHB_CLK>, 40 + <&mmcc MDSS_AXI_CLK>, 41 + <&mmcc MDSS_VSYNC_CLK>, 42 + <&mmcc MDSS_MDP_CLK>, 43 + <&mmcc MDSS_BYTE0_CLK>, 44 + <&mmcc MDSS_BYTE0_INTF_CLK>, 45 + <&mmcc MDSS_PCLK0_CLK>, 46 + <&mmcc MDSS_ESC0_CLK>; 47 + power-domains = <&mmcc MDSS_GDSC>; 35 48 }; 36 49 }; 37 50 ··· 90 77 pinctrl-names = "default"; 91 78 pinctrl-0 = <&vol_keys_default>; 92 79 93 - vol-down { 80 + button-vol-down { 94 81 label = "Volume down"; 95 82 gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; 96 83 linux,code = <KEY_VOLUMEDOWN>; ··· 98 85 wakeup-source; 99 86 }; 100 87 101 - vol-up { 88 + button-vol-up { 102 89 label = "Volume up"; 103 90 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; 104 91 linux,code = <KEY_VOLUMEUP>; ··· 114 101 pinctrl-names = "default"; 115 102 pinctrl-0 = <&hall_sensor_default>; 116 103 117 - hall-sensor { 104 + event-hall-sensor { 118 105 label = "Hall Effect Sensor"; 119 106 gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; 120 107 linux,input-type = <EV_SW>; ··· 258 245 status = "okay"; 259 246 }; 260 247 261 - &pm8005_lsid1 { 262 - pm8005-regulators { 263 - compatible = "qcom,pm8005-regulators"; 264 - 265 - vdd_s1-supply = <&vph_pwr>; 266 - 267 - pm8005_s1: s1 { /* VDD_GFX supply */ 268 - regulator-min-microvolt = <524000>; 269 - regulator-max-microvolt = <1100000>; 270 - regulator-enable-ramp-delay = <500>; 271 - 272 - /* hack until we rig up the gpu consumer */ 273 - regulator-always-on; 274 - }; 248 + &pm8005_regulators { 249 + /* VDD_GFX supply */ 250 + pm8005_s1: s1 { 251 + regulator-min-microvolt = <524000>; 252 + regulator-max-microvolt = <1100000>; 253 + regulator-enable-ramp-delay = <500>; 254 + /* Hack until we rig up the gpu consumer */ 255 + regulator-always-on; 275 256 }; 276 257 }; 277 258 278 259 &pm8998_gpio { 279 - vol_keys_default: vol-keys-default { 280 - pinconf { 281 - pins = "gpio5", "gpio6"; 282 - function = "normal"; 283 - bias-pull-up; 284 - input-enable; 285 - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 286 - }; 260 + vol_keys_default: vol-keys-state { 261 + pins = "gpio5", "gpio6"; 262 + function = "normal"; 263 + bias-pull-up; 264 + input-enable; 265 + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 287 266 }; 288 267 }; 289 268 ··· 323 318 regulator-min-microvolt = <1352000>; 324 319 regulator-max-microvolt = <1352000>; 325 320 }; 321 + 326 322 vreg_s4a_1p8: s4 { 327 323 regulator-min-microvolt = <1800000>; 328 324 regulator-max-microvolt = <1800000>; 329 325 regulator-allow-set-load; 330 326 }; 327 + 331 328 vreg_s5a_2p04: s5 { 332 329 regulator-min-microvolt = <1904000>; 333 330 regulator-max-microvolt = <2040000>; 334 331 }; 332 + 335 333 vreg_s7a_1p025: s7 { 336 334 regulator-min-microvolt = <900000>; 337 335 regulator-max-microvolt = <1028000>; 338 336 }; 337 + 339 338 vreg_l1a_0p875: l1 { 340 339 regulator-min-microvolt = <880000>; 341 340 regulator-max-microvolt = <880000>; 342 341 }; 342 + 343 343 vreg_l2a_1p2: l2 { 344 344 regulator-min-microvolt = <1200000>; 345 345 regulator-max-microvolt = <1200000>; 346 346 }; 347 + 347 348 vreg_l3a_1p0: l3 { 348 349 regulator-min-microvolt = <1000000>; 349 350 regulator-max-microvolt = <1000000>; 350 351 }; 352 + 351 353 vreg_l5a_0p8: l5 { 352 354 regulator-min-microvolt = <800000>; 353 355 regulator-max-microvolt = <800000>; 354 356 }; 357 + 355 358 vreg_l6a_1p8: l6 { 356 359 regulator-min-microvolt = <1808000>; 357 360 regulator-max-microvolt = <1808000>; 358 361 }; 362 + 359 363 vreg_l7a_1p8: l7 { 360 364 regulator-min-microvolt = <1800000>; 361 365 regulator-max-microvolt = <1800000>; 362 366 }; 367 + 363 368 vreg_l8a_1p2: l8 { 364 369 regulator-min-microvolt = <1200000>; 365 370 regulator-max-microvolt = <1200000>; 366 371 }; 372 + 367 373 vreg_l9a_1p8: l9 { 368 374 regulator-min-microvolt = <1808000>; 369 375 regulator-max-microvolt = <2960000>; 370 376 }; 377 + 371 378 vreg_l10a_1p8: l10 { 372 379 regulator-min-microvolt = <1808000>; 373 380 regulator-max-microvolt = <2960000>; 374 381 }; 382 + 375 383 vreg_l11a_1p0: l11 { 376 384 regulator-min-microvolt = <1000000>; 377 385 regulator-max-microvolt = <1000000>; 378 386 }; 387 + 379 388 vreg_l12a_1p8: l12 { 380 389 regulator-min-microvolt = <1800000>; 381 390 regulator-max-microvolt = <1800000>; 382 391 }; 392 + 383 393 vreg_l13a_2p95: l13 { 384 394 regulator-min-microvolt = <1808000>; 385 395 regulator-max-microvolt = <2960000>; 386 396 }; 397 + 387 398 vreg_l14a_1p88: l14 { 388 399 regulator-min-microvolt = <1880000>; 389 400 regulator-max-microvolt = <1880000>; 390 401 }; 402 + 391 403 vreg_l15a_1p8: l15 { 392 404 regulator-min-microvolt = <1800000>; 393 405 regulator-max-microvolt = <1800000>; 394 406 }; 407 + 395 408 vreg_l16a_2p7: l16 { 396 409 regulator-min-microvolt = <2704000>; 397 410 regulator-max-microvolt = <2704000>; 398 411 }; 412 + 399 413 vreg_l17a_1p3: l17 { 400 414 regulator-min-microvolt = <1304000>; 401 415 regulator-max-microvolt = <1304000>; 402 416 }; 417 + 403 418 vreg_l18a_2p7: l18 { 404 419 regulator-min-microvolt = <2704000>; 405 420 regulator-max-microvolt = <2704000>; 406 421 }; 422 + 407 423 vreg_l19a_3p0: l19 { 408 424 regulator-min-microvolt = <3008000>; 409 425 regulator-max-microvolt = <3008000>; 410 426 }; 427 + 411 428 vreg_l20a_2p95: l20 { 412 429 regulator-min-microvolt = <2960000>; 413 430 regulator-max-microvolt = <2960000>; ··· 438 411 vreg_l21a_2p95: l21 { 439 412 regulator-min-microvolt = <2960000>; 440 413 regulator-max-microvolt = <2960000>; 441 - regulator-allow-set-load; 442 414 regulator-system-load = <800000>; 415 + regulator-allow-set-load; 443 416 }; 417 + 444 418 vreg_l22a_2p85: l22 { 445 419 regulator-min-microvolt = <2864000>; 446 420 regulator-max-microvolt = <2864000>; 447 421 }; 422 + 448 423 vreg_l23a_3p3: l23 { 449 424 regulator-min-microvolt = <3312000>; 450 425 regulator-max-microvolt = <3312000>; 451 426 }; 427 + 452 428 vreg_l24a_3p075: l24 { 453 429 regulator-min-microvolt = <3088000>; 454 430 regulator-max-microvolt = <3088000>; 455 431 }; 432 + 456 433 vreg_l25a_3p3: l25 { 457 434 regulator-min-microvolt = <3104000>; 458 435 regulator-max-microvolt = <3312000>; 459 436 }; 437 + 460 438 vreg_l26a_1p2: l26 { 461 439 regulator-min-microvolt = <1200000>; 462 440 regulator-max-microvolt = <1200000>; 463 441 regulator-allow-set-load; 464 442 }; 443 + 465 444 vreg_l28_3p0: l28 { 466 445 regulator-min-microvolt = <3008000>; 467 446 regulator-max-microvolt = <3008000>; 468 447 }; 448 + 469 449 vreg_lvs1a_1p8: lvs1 { }; 470 450 vreg_lvs2a_1p8: lvs2 { }; 471 451 };
+4
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts
··· 29 29 regulator-min-microvolt = <2800000>; 30 30 regulator-max-microvolt = <2800000>; 31 31 }; 32 + 33 + &vreg_lvs1a_1p8 { 34 + status = "disabled"; 35 + };
+1 -1
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts
··· 38 38 }; 39 39 40 40 &pmi8998_gpio { 41 - disp_dvdd_en: disp-dvdd-en-active { 41 + disp_dvdd_en: disp-dvdd-en-active-state { 42 42 pins = "gpio10"; 43 43 function = "normal"; 44 44 bias-disable;
+80 -40
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
··· 5 5 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 6 6 */ 7 7 8 + #include <dt-bindings/input/input.h> 9 + #include <dt-bindings/leds/common.h> 10 + #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 8 11 #include "msm8998.dtsi" 9 12 #include "pm8005.dtsi" 10 13 #include "pm8998.dtsi" 11 14 #include "pmi8998.dtsi" 12 - #include <dt-bindings/input/input.h> 13 - #include <dt-bindings/leds/common.h> 14 - #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 15 - #include <dt-bindings/sound/qcom,q6afe.h> 16 - #include <dt-bindings/sound/qcom,q6asm.h> 17 15 18 16 / { 19 17 /* required for bootloader to select correct board */ ··· 19 21 qcom,board-id = <8 0>; 20 22 21 23 clocks { 22 - compatible = "simple-bus"; 23 - 24 24 div1_mclk: divclk1 { 25 25 compatible = "gpio-gate-clock"; 26 26 pinctrl-0 = <&audio_mclk_pin>; ··· 87 91 regulator-boot-on; 88 92 }; 89 93 94 + extcon_usb: extcon-usb { 95 + compatible = "linux,extcon-usb-gpio"; 96 + id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; 97 + vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; 98 + pinctrl-names = "default"; 99 + pinctrl-0 = <&usb_extcon_active &usb_vbus_active>; 100 + }; 101 + 90 102 gpio-keys { 91 103 compatible = "gpio-keys"; 92 104 label = "Side buttons"; 93 105 pinctrl-names = "default"; 94 106 pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, 95 107 <&cam_snapshot_pin_a>; 96 - vol-down { 108 + button-vol-down { 97 109 label = "Volume Down"; 98 110 gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; 99 111 linux,input-type = <EV_KEY>; ··· 110 106 debounce-interval = <15>; 111 107 }; 112 108 113 - camera-snapshot { 109 + button-camera-snapshot { 114 110 label = "Camera Snapshot"; 115 111 gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; 116 112 linux,input-type = <EV_KEY>; ··· 118 114 debounce-interval = <15>; 119 115 }; 120 116 121 - camera-focus { 117 + button-camera-focus { 122 118 label = "Camera Focus"; 123 119 gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; 124 120 linux,input-type = <EV_KEY>; ··· 133 129 pinctrl-names = "default"; 134 130 pinctrl-0 = <&hall_sensor0_default>; 135 131 136 - hall-sensor0 { 132 + event-hall-sensor0 { 137 133 label = "Cover Hall Sensor"; 138 134 gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; 139 135 linux,input-type = <EV_SW>; ··· 249 245 status = "okay"; 250 246 }; 251 247 248 + &blsp2_i2c2 { 249 + status = "okay"; 250 + 251 + proximity@29 { 252 + compatible = "st,vl53l0x"; 253 + reg = <0x29>; 254 + 255 + interrupt-parent = <&tlmm>; 256 + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; 257 + 258 + reset-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; 259 + vdd-supply = <&cam_vio_vreg>; 260 + 261 + pinctrl-names = "default"; 262 + pinctrl-0 = <&tof_int &tof_reset>; 263 + }; 264 + }; 265 + 252 266 &ibb { 253 267 regulator-min-microamp = <800000>; 254 268 regulator-max-microamp = <800000>; ··· 292 270 regulator-soft-start; 293 271 }; 294 272 295 - &mmcc { 296 - status = "ok"; 297 - }; 298 - 299 - &mmss_smmu { 300 - status = "ok"; 301 - }; 302 - 303 - &pm8005_lsid1 { 304 - pm8005-regulators { 305 - compatible = "qcom,pm8005-regulators"; 306 - 307 - vdd_s1-supply = <&vph_pwr>; 308 - 309 - /* VDD_GFX supply */ 310 - pm8005_s1: s1 { 311 - regulator-min-microvolt = <524000>; 312 - regulator-max-microvolt = <1088000>; 313 - regulator-enable-ramp-delay = <500>; 314 - regulator-always-on; 315 - }; 273 + &pm8005_regulators { 274 + /* VDD_GFX supply */ 275 + pm8005_s1: s1 { 276 + regulator-min-microvolt = <524000>; 277 + regulator-max-microvolt = <1088000>; 278 + regulator-enable-ramp-delay = <500>; 279 + /* Hack until we rig up the gpu consumer */ 280 + regulator-always-on; 316 281 }; 317 282 }; 318 283 319 284 &pm8998_gpio { 320 - vol_down_pin_a: vol-down-active { 285 + vol_down_pin_a: vol-down-active-state { 321 286 pins = "gpio5"; 322 287 function = PMIC_GPIO_FUNC_NORMAL; 323 288 bias-pull-up; ··· 312 303 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 313 304 }; 314 305 315 - cam_focus_pin_a: cam-focus-btn-active { 306 + cam_focus_pin_a: cam-focus-btn-active-state { 316 307 pins = "gpio7"; 317 308 function = PMIC_GPIO_FUNC_NORMAL; 318 309 bias-pull-up; ··· 320 311 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 321 312 }; 322 313 323 - cam_snapshot_pin_a: cam-snapshot-btn-active { 314 + cam_snapshot_pin_a: cam-snapshot-btn-active-state { 324 315 pins = "gpio8"; 325 316 function = PMIC_GPIO_FUNC_NORMAL; 326 317 bias-pull-up; ··· 328 319 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 329 320 }; 330 321 331 - audio_mclk_pin: audio-mclk-pin-active { 322 + audio_mclk_pin: audio-mclk-pin-active-state { 332 323 pins = "gpio13"; 333 324 function = "func2"; 334 325 power-source = <0>; ··· 336 327 }; 337 328 338 329 &pmi8998_gpio { 339 - cam_vio_default: cam-vio-active { 330 + cam_vio_default: cam-vio-active-state { 340 331 pins = "gpio1"; 341 332 function = PMIC_GPIO_FUNC_NORMAL; 342 333 bias-disable; ··· 346 337 power-source = <1>; 347 338 }; 348 339 349 - vib_default: vib-en { 340 + vib_default: vib-en-state { 350 341 pins = "gpio5"; 351 342 function = PMIC_GPIO_FUNC_NORMAL; 352 343 bias-disable; ··· 558 549 vqmmc-supply = <&vreg_l13a_2p95>; 559 550 560 551 pinctrl-names = "default", "sleep"; 561 - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; 562 - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; 552 + pinctrl-0 = <&sdc2_on &sdc2_cd>; 553 + pinctrl-1 = <&sdc2_off &sdc2_cd>; 563 554 }; 564 555 565 556 &tlmm { ··· 615 606 drive-strength = <2>; 616 607 }; 617 608 609 + tof_int: tof-int { 610 + pins = "gpio22"; 611 + function = "gpio"; 612 + bias-pull-up; 613 + drive-strength = <2>; 614 + input-enable; 615 + }; 616 + 618 617 cam1_vdig_default: cam1-vdig-default { 619 618 pins = "gpio25"; 619 + function = "gpio"; 620 + bias-disable; 621 + drive-strength = <2>; 622 + }; 623 + 624 + usb_extcon_active: usb-extcon-active { 625 + pins = "gpio38"; 626 + function = "gpio"; 627 + bias-disable; 628 + drive-strength = <16>; 629 + }; 630 + 631 + tof_reset: tof-reset { 632 + pins = "gpio27"; 620 633 function = "gpio"; 621 634 bias-disable; 622 635 drive-strength = <2>; ··· 657 626 function = "gpio"; 658 627 drive-strength = <8>; 659 628 bias-pull-up; 629 + }; 630 + 631 + usb_vbus_active: usb-vbus-active { 632 + pins = "gpio128"; 633 + function = "gpio"; 634 + bias-disable; 635 + drive-strength = <2>; 636 + output-low; 660 637 }; 661 638 662 639 ts_vddio_en: ts-vddio-en-default { ··· 697 658 &usb3_dwc3 { 698 659 /* Force to peripheral until we have Type-C hooked up */ 699 660 dr_mode = "peripheral"; 661 + extcon = <&extcon_usb>; 700 662 }; 701 663 702 664 &usb3phy {
+33 -62
arch/arm64/boot/dts/qcom/msm8998.dtsi
··· 838 838 }; 839 839 840 840 qfprom: qfprom@784000 { 841 - compatible = "qcom,qfprom"; 841 + compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 842 842 reg = <0x00784000 0x621c>; 843 843 #address-cells = <1>; 844 844 #size-cells = <1>; ··· 929 929 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 930 930 interrupt-names = "msi"; 931 931 interrupt-map-mask = <0 0 0 0x7>; 932 - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 932 + interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 933 933 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 934 934 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 935 935 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; ··· 1057 1057 reg = <0x03400000 0xc00000>; 1058 1058 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1059 1059 gpio-controller; 1060 - #gpio-cells = <0x2>; 1060 + #gpio-cells = <2>; 1061 1061 interrupt-controller; 1062 - #interrupt-cells = <0x2>; 1062 + #interrupt-cells = <2>; 1063 1063 1064 - sdc2_clk_on: sdc2_clk_on { 1065 - config { 1064 + sdc2_on: sdc2-on { 1065 + clk { 1066 1066 pins = "sdc2_clk"; 1067 - bias-disable; 1068 1067 drive-strength = <16>; 1069 - }; 1070 - }; 1071 - 1072 - sdc2_clk_off: sdc2_clk_off { 1073 - config { 1074 - pins = "sdc2_clk"; 1075 1068 bias-disable; 1076 - drive-strength = <2>; 1077 1069 }; 1078 - }; 1079 1070 1080 - sdc2_cmd_on: sdc2_cmd_on { 1081 - config { 1071 + cmd { 1082 1072 pins = "sdc2_cmd"; 1083 - bias-pull-up; 1084 1073 drive-strength = <10>; 1074 + bias-pull-up; 1075 + }; 1076 + 1077 + data { 1078 + pins = "sdc2_data"; 1079 + drive-strength = <10>; 1080 + bias-pull-up; 1085 1081 }; 1086 1082 }; 1087 1083 1088 - sdc2_cmd_off: sdc2_cmd_off { 1089 - config { 1084 + sdc2_off: sdc2-off { 1085 + clk { 1086 + pins = "sdc2_clk"; 1087 + drive-strength = <2>; 1088 + bias-disable; 1089 + }; 1090 + 1091 + cmd { 1090 1092 pins = "sdc2_cmd"; 1091 - bias-pull-up; 1092 1093 drive-strength = <2>; 1094 + bias-pull-up; 1093 1095 }; 1094 - }; 1095 1096 1096 - sdc2_data_on: sdc2_data_on { 1097 - config { 1097 + data { 1098 1098 pins = "sdc2_data"; 1099 - bias-pull-up; 1100 - drive-strength = <10>; 1101 - }; 1102 - }; 1103 - 1104 - sdc2_data_off: sdc2_data_off { 1105 - config { 1106 - pins = "sdc2_data"; 1107 - bias-pull-up; 1108 1099 drive-strength = <2>; 1109 - }; 1110 - }; 1111 - 1112 - sdc2_cd_on: sdc2_cd_on { 1113 - mux { 1114 - pins = "gpio95"; 1115 - function = "gpio"; 1116 - }; 1117 - 1118 - config { 1119 - pins = "gpio95"; 1120 1100 bias-pull-up; 1121 - drive-strength = <2>; 1122 1101 }; 1123 1102 }; 1124 1103 1125 - sdc2_cd_off: sdc2_cd_off { 1126 - mux { 1127 - pins = "gpio95"; 1128 - function = "gpio"; 1129 - }; 1130 - 1131 - config { 1132 - pins = "gpio95"; 1133 - bias-pull-up; 1134 - drive-strength = <2>; 1135 - }; 1104 + sdc2_cd: sdc2-cd { 1105 + pins = "gpio95"; 1106 + function = "gpio"; 1107 + bias-pull-up; 1108 + drive-strength = <2>; 1136 1109 }; 1137 1110 1138 - blsp1_uart3_on: blsp1_uart3_on { 1111 + blsp1_uart3_on: blsp1-uart3-on { 1139 1112 tx { 1140 1113 pins = "gpio45"; 1141 1114 function = "blsp_uart3_a"; ··· 1389 1416 status = "disabled"; 1390 1417 1391 1418 gpu_opp_table: opp-table { 1392 - compatible = "operating-points-v2"; 1419 + compatible = "operating-points-v2"; 1393 1420 opp-710000097 { 1394 1421 opp-hz = /bits/ 64 <710000097>; 1395 1422 opp-level = <RPM_SMD_LEVEL_TURBO>; ··· 2053 2080 <0xc010600 0x128>, 2054 2081 <0xc010800 0x200>; 2055 2082 #phy-cells = <0>; 2056 - #clock-cells = <1>; 2083 + #clock-cells = <0>; 2057 2084 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2058 2085 clock-names = "pipe0"; 2059 2086 clock-output-names = "usb3_phy_pipe_clk_src"; ··· 2075 2102 nvmem-cells = <&qusb2_hstx_trim>; 2076 2103 }; 2077 2104 2078 - sdhc2: sdhci@c0a4900 { 2105 + sdhc2: mmc@c0a4900 { 2079 2106 compatible = "qcom,sdhci-msm-v4"; 2080 2107 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2081 2108 reg-names = "hc_mem", "core_mem"; ··· 2388 2415 #reset-cells = <1>; 2389 2416 #power-domain-cells = <1>; 2390 2417 reg = <0xc8c0000 0x40000>; 2391 - status = "disabled"; 2392 2418 2393 2419 clock-names = "xo", 2394 2420 "gpll0", ··· 2422 2450 <&mmcc BIMC_SMMU_AXI_CLK>; 2423 2451 clock-names = "iface-mm", "iface-smmu", 2424 2452 "bus-mm", "bus-smmu"; 2425 - status = "disabled"; 2426 2453 2427 2454 #global-interrupts = <0>; 2428 2455 interrupts =
+2 -1
arch/arm64/boot/dts/qcom/pm6350.dtsi
··· 36 36 }; 37 37 38 38 pm6350_gpios: gpios@c000 { 39 - compatible = "qcom,pm6350-gpio"; 39 + compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; 40 40 reg = <0xc000>; 41 41 gpio-controller; 42 + gpio-ranges = <&pm6350_gpios 0 0 9>; 42 43 #gpio-cells = <2>; 43 44 interrupt-controller; 44 45 #interrupt-cells = <2>;
+1 -1
arch/arm64/boot/dts/qcom/pm660.dtsi
··· 171 171 }; 172 172 173 173 pm660_gpios: gpios@c000 { 174 - compatible = "qcom,pm660-gpio"; 174 + compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; 175 175 reg = <0xc000>; 176 176 gpio-controller; 177 177 gpio-ranges = <&pm660_gpios 0 0 13>;
+7 -1
arch/arm64/boot/dts/qcom/pm660l.dtsi
··· 65 65 #address-cells = <1>; 66 66 #size-cells = <0>; 67 67 68 + pm660l_lpg: lpg@b100 { 69 + compatible = "qcom,pm660l-lpg"; 70 + 71 + status = "disabled"; 72 + }; 73 + 68 74 pm660l_wled: leds@d800 { 69 75 compatible = "qcom,pm660l-wled"; 70 - reg = <0xd800 0xd900>; 76 + reg = <0xd800>, <0xd900>; 71 77 interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; 72 78 interrupt-names = "ovp"; 73 79 label = "backlight";
+4
arch/arm64/boot/dts/qcom/pm8005.dtsi
··· 28 28 reg = <0x5 SPMI_USID>; 29 29 #address-cells = <1>; 30 30 #size-cells = <0>; 31 + 32 + pm8005_regulators: regulators { 33 + compatible = "qcom,pm8005-regulators"; 34 + }; 31 35 }; 32 36 };
+2 -1
arch/arm64/boot/dts/qcom/pm8009.dtsi
··· 19 19 }; 20 20 21 21 pm8009_gpios: gpio@c000 { 22 - compatible = "qcom,pm8005-gpio"; 22 + compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; 23 23 reg = <0xc000>; 24 24 gpio-controller; 25 + gpio-ranges = <&pm8009_gpios 0 0 4>; 25 26 #gpio-cells = <2>; 26 27 interrupt-controller; 27 28 #interrupt-cells = <2>;
+2 -1
arch/arm64/boot/dts/qcom/pm8150.dtsi
··· 127 127 }; 128 128 129 129 pm8150_gpios: gpio@c000 { 130 - compatible = "qcom,pm8150-gpio"; 130 + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; 131 131 reg = <0xc000>; 132 132 gpio-controller; 133 + gpio-ranges = <&pm8150_gpios 0 0 10>; 133 134 #gpio-cells = <2>; 134 135 interrupt-controller; 135 136 #interrupt-cells = <2>;
+12 -1
arch/arm64/boot/dts/qcom/pm8150b.dtsi
··· 112 112 }; 113 113 114 114 pm8150b_gpios: gpio@c000 { 115 - compatible = "qcom,pm8150b-gpio"; 115 + compatible = "qcom,pm8150b-gpio", "qcom,spmi-gpio"; 116 116 reg = <0xc000>; 117 117 gpio-controller; 118 + gpio-ranges = <&pm8150b_gpios 0 0 12>; 118 119 #gpio-cells = <2>; 119 120 interrupt-controller; 120 121 #interrupt-cells = <2>; ··· 127 126 reg = <0x3 SPMI_USID>; 128 127 #address-cells = <1>; 129 128 #size-cells = <0>; 129 + 130 + pm8150b_lpg: lpg { 131 + compatible = "qcom,pm8150b-lpg"; 132 + 133 + #address-cells = <1>; 134 + #size-cells = <0>; 135 + #pwm-cells = <2>; 136 + 137 + status = "disabled"; 138 + }; 130 139 }; 131 140 };
+13 -1
arch/arm64/boot/dts/qcom/pm8150l.dtsi
··· 100 100 }; 101 101 102 102 pm8150l_gpios: gpio@c000 { 103 - compatible = "qcom,pm8150l-gpio"; 103 + compatible = "qcom,pm8150l-gpio", "qcom,spmi-gpio"; 104 104 reg = <0xc000>; 105 105 gpio-controller; 106 + gpio-ranges = <&pm8150l_gpios 0 0 12>; 106 107 #gpio-cells = <2>; 107 108 interrupt-controller; 108 109 #interrupt-cells = <2>; ··· 115 114 reg = <0x5 SPMI_USID>; 116 115 #address-cells = <1>; 117 116 #size-cells = <0>; 117 + 118 + pm8150l_lpg: lpg { 119 + compatible = "qcom,pm8150l-lpg"; 120 + 121 + #address-cells = <1>; 122 + #size-cells = <0>; 123 + #pwm-cells = <2>; 124 + 125 + status = "disabled"; 126 + }; 127 + 118 128 }; 119 129 };
+2 -1
arch/arm64/boot/dts/qcom/pm8350.dtsi
··· 45 45 }; 46 46 47 47 pm8350_gpios: gpio@8800 { 48 - compatible = "qcom,pm8350-gpio"; 48 + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; 49 49 reg = <0x8800>; 50 50 gpio-controller; 51 + gpio-ranges = <&pm8350_gpios 0 0 10>; 51 52 #gpio-cells = <2>; 52 53 interrupt-controller; 53 54 #interrupt-cells = <2>;
+2 -1
arch/arm64/boot/dts/qcom/pm8350b.dtsi
··· 45 45 }; 46 46 47 47 pm8350b_gpios: gpio@8800 { 48 - compatible = "qcom,pm8350b-gpio"; 48 + compatible = "qcom,pm8350b-gpio", "qcom,spmi-gpio"; 49 49 reg = <0x8800>; 50 50 gpio-controller; 51 + gpio-ranges = <&pm8350b_gpios 0 0 8>; 51 52 #gpio-cells = <2>; 52 53 interrupt-controller; 53 54 #interrupt-cells = <2>;
+12 -5
arch/arm64/boot/dts/qcom/pm8916.dtsi
··· 108 108 }; 109 109 110 110 pm8916_gpios: gpios@c000 { 111 - compatible = "qcom,pm8916-gpio"; 111 + compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; 112 112 reg = <0xc000>; 113 113 gpio-controller; 114 + gpio-ranges = <&pm8916_gpios 0 0 4>; 114 115 #gpio-cells = <2>; 115 - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, 116 - <0 0xc1 0 IRQ_TYPE_NONE>, 117 - <0 0xc2 0 IRQ_TYPE_NONE>, 118 - <0 0xc3 0 IRQ_TYPE_NONE>; 116 + interrupt-controller; 117 + #interrupt-cells = <2>; 119 118 }; 120 119 }; 121 120 ··· 123 124 reg = <0x1 SPMI_USID>; 124 125 #address-cells = <1>; 125 126 #size-cells = <0>; 127 + 128 + pm8916_pwm: pwm { 129 + compatible = "qcom,pm8916-pwm"; 130 + 131 + #pwm-cells = <2>; 132 + 133 + status = "disabled"; 134 + }; 126 135 127 136 pm8916_vib: vibrator@c000 { 128 137 compatible = "qcom,pm8916-vib";
+10
arch/arm64/boot/dts/qcom/pm8994.dtsi
··· 135 135 #address-cells = <1>; 136 136 #size-cells = <0>; 137 137 138 + pm8994_lpg: lpg { 139 + compatible = "qcom,pm8994-lpg"; 140 + 141 + #address-cells = <1>; 142 + #size-cells = <0>; 143 + #pwm-cells = <2>; 144 + 145 + status = "disabled"; 146 + }; 147 + 138 148 pm8994_spmi_regulators: regulators { 139 149 compatible = "qcom,pm8994-regulators"; 140 150 };
+21 -1
arch/arm64/boot/dts/qcom/pmi8994.dtsi
··· 19 19 interrupt-controller; 20 20 #interrupt-cells = <2>; 21 21 }; 22 + 23 + pmi8994_mpps: mpps@a000 { 24 + compatible = "qcom,pmi8994-mpp"; 25 + reg = <0xa000>; 26 + gpio-controller; 27 + gpio-ranges = <&pmi8994_mpps 0 0 4>; 28 + #gpio-cells = <2>; 29 + interrupt-controller; 30 + #interrupt-cells = <2>; 31 + }; 22 32 }; 23 33 24 34 pmic@3 { ··· 36 26 reg = <0x3 SPMI_USID>; 37 27 #address-cells = <1>; 38 28 #size-cells = <0>; 29 + 30 + pmi8994_lpg: lpg { 31 + compatible = "qcom,pmi8994-lpg"; 32 + 33 + #address-cells = <1>; 34 + #size-cells = <0>; 35 + #pwm-cells = <2>; 36 + 37 + status = "disabled"; 38 + }; 39 39 40 40 pmi8994_spmi_regulators: regulators { 41 41 compatible = "qcom,pmi8994-regulators"; ··· 55 35 56 36 pmi8994_wled: wled@d800 { 57 37 compatible = "qcom,pmi8994-wled"; 58 - reg = <0xd800 0xd900>; 38 + reg = <0xd800>, <0xd900>; 59 39 interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; 60 40 interrupt-names = "short"; 61 41 qcom,cabc;
+11 -2
arch/arm64/boot/dts/qcom/pmi8998.dtsi
··· 42 42 }; 43 43 }; 44 44 45 + pmi8998_lpg: lpg { 46 + compatible = "qcom,pmi8998-lpg"; 47 + 48 + #address-cells = <1>; 49 + #size-cells = <0>; 50 + #pwm-cells = <2>; 51 + 52 + status = "disabled"; 53 + }; 54 + 45 55 pmi8998_wled: leds@d800 { 46 56 compatible = "qcom,pmi8998-wled"; 47 - reg = <0xd800 0xd900>; 57 + reg = <0xd800>, <0xd900>; 48 58 interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, 49 59 <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; 50 60 interrupt-names = "ovp", "short"; ··· 62 52 63 53 status = "disabled"; 64 54 }; 65 - 66 55 }; 67 56 };
+1 -1
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
··· 116 116 }; 117 117 118 118 pmm8155au_1_gpios: gpio@c000 { 119 - compatible = "qcom,pmm8155au-gpio"; 119 + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; 120 120 reg = <0xc000>; 121 121 gpio-controller; 122 122 #gpio-cells = <2>;
+1 -1
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
··· 89 89 }; 90 90 91 91 pmm8155au_2_gpios: gpio@c000 { 92 - compatible = "qcom,pmm8155au-gpio"; 92 + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; 93 93 reg = <0xc000>; 94 94 gpio-controller; 95 95 #gpio-cells = <2>;
+2 -1
arch/arm64/boot/dts/qcom/pmr735b.dtsi
··· 45 45 }; 46 46 47 47 pmr735b_gpios: gpio@8800 { 48 - compatible = "qcom,pmr735b-gpio"; 48 + compatible = "qcom,pmr735b-gpio", "qcom,spmi-gpio"; 49 49 reg = <0x8800>; 50 50 gpio-controller; 51 + gpio-ranges = <&pmr735b_gpios 0 0 4>; 51 52 #gpio-cells = <2>; 52 53 interrupt-controller; 53 54 #interrupt-cells = <2>;
+4 -13
arch/arm64/boot/dts/qcom/pms405.dtsi
··· 38 38 #size-cells = <0>; 39 39 40 40 pms405_gpios: gpio@c000 { 41 - compatible = "qcom,pms405-gpio"; 41 + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; 42 42 reg = <0xc000>; 43 43 gpio-controller; 44 + gpio-ranges = <&pms405_gpios 0 0 12>; 44 45 #gpio-cells = <2>; 45 - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, 46 - <0 0xc1 0 IRQ_TYPE_NONE>, 47 - <0 0xc2 0 IRQ_TYPE_NONE>, 48 - <0 0xc3 0 IRQ_TYPE_NONE>, 49 - <0 0xc4 0 IRQ_TYPE_NONE>, 50 - <0 0xc5 0 IRQ_TYPE_NONE>, 51 - <0 0xc6 0 IRQ_TYPE_NONE>, 52 - <0 0xc7 0 IRQ_TYPE_NONE>, 53 - <0 0xc8 0 IRQ_TYPE_NONE>, 54 - <0 0xc9 0 IRQ_TYPE_NONE>, 55 - <0 0xca 0 IRQ_TYPE_NONE>, 56 - <0 0xcb 0 IRQ_TYPE_NONE>; 46 + interrupt-controller; 47 + #interrupt-cells = <2>; 57 48 }; 58 49 59 50 pon@800 {
+2 -2
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
··· 304 304 }; 305 305 306 306 &pms405_gpios { 307 - usb_vbus_boost_pin: usb-vbus-boost-pin { 307 + usb_vbus_boost_pin: usb-vbus-boost-state { 308 308 pinconf { 309 309 pins = "gpio3"; 310 310 function = PMIC_GPIO_FUNC_NORMAL; ··· 312 312 power-source = <1>; 313 313 }; 314 314 }; 315 - usb3_vbus_pin: usb3-vbus-pin { 315 + usb3_vbus_pin: usb3-vbus-state { 316 316 pinconf { 317 317 pins = "gpio12"; 318 318 function = PMIC_GPIO_FUNC_NORMAL;
+26 -9
arch/arm64/boot/dts/qcom/qcs404.dtsi
··· 366 366 }; 367 367 368 368 qfprom: qfprom@a4000 { 369 - compatible = "qcom,qfprom"; 369 + compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 370 370 reg = <0x000a4000 0x1000>; 371 371 #address-cells = <1>; 372 372 #size-cells = <1>; ··· 669 669 }; 670 670 671 671 blsp1_spi1_default: blsp1-spi1-default { 672 - pins = "gpio22", "gpio23", "gpio24", "gpio25"; 673 - function = "blsp_spi1"; 672 + mosi { 673 + pins = "gpio22"; 674 + function = "blsp_spi_mosi_a1"; 675 + }; 676 + 677 + miso { 678 + pins = "gpio23"; 679 + function = "blsp_spi_miso_a1"; 680 + }; 681 + 682 + cs_n { 683 + pins = "gpio24"; 684 + function = "blsp_spi_cs_n_a1"; 685 + }; 686 + 687 + clk { 688 + pins = "gpio25"; 689 + function = "blsp_spi_clk_a1"; 690 + }; 674 691 }; 675 692 676 693 blsp1_spi2_default: blsp1-spi2-default { ··· 806 789 status = "disabled"; 807 790 }; 808 791 809 - sdcc1: sdcc@7804000 { 792 + sdcc1: mmc@7804000 { 810 793 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 811 794 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 812 795 reg-names = "hc", "cqhci"; ··· 815 798 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 816 799 interrupt-names = "hc_irq", "pwr_irq"; 817 800 818 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 819 - <&gcc GCC_SDCC1_AHB_CLK>, 801 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 802 + <&gcc GCC_SDCC1_APPS_CLK>, 820 803 <&xo_board>; 821 - clock-names = "core", "iface", "xo"; 804 + clock-names = "iface", "core", "xo"; 822 805 823 806 status = "disabled"; 824 807 }; ··· 1119 1102 status = "disabled"; 1120 1103 }; 1121 1104 1122 - imem@8600000 { 1123 - compatible = "simple-mfd"; 1105 + sram@8600000 { 1106 + compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1124 1107 reg = <0x08600000 0x1000>; 1125 1108 1126 1109 #address-cells = <1>;
+40 -4
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
··· 5 5 6 6 /dts-v1/; 7 7 8 + #include <dt-bindings/leds/common.h> 8 9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 9 10 #include <dt-bindings/sound/qcom,q6afe.h> 10 11 #include <dt-bindings/sound/qcom,q6asm.h> ··· 60 59 61 60 user4 { 62 61 label = "green:user4"; 62 + function = LED_FUNCTION_INDICATOR; 63 + color = <LED_COLOR_ID_GREEN>; 63 64 gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; 64 65 linux,default-trigger = "panic-indicator"; 65 66 default-state = "off"; ··· 69 66 70 67 wlan { 71 68 label = "yellow:wlan"; 69 + function = LED_FUNCTION_WLAN; 70 + color = <LED_COLOR_ID_YELLOW>; 72 71 gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; 73 72 linux,default-trigger = "phy0tx"; 74 73 default-state = "off"; ··· 78 73 79 74 bt { 80 75 label = "blue:bt"; 76 + function = LED_FUNCTION_BLUETOOTH; 77 + color = <LED_COLOR_ID_BLUE>; 81 78 gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; 82 79 linux,default-trigger = "bluetooth-power"; 83 80 default-state = "off"; ··· 803 796 "NC", 804 797 "PM3003A_MODE"; 805 798 806 - lt9611_rst_pin: lt9611-rst-pin { 799 + lt9611_rst_pin: lt9611-rst-state { 807 800 pins = "gpio5"; 808 801 function = "normal"; 809 802 810 803 output-high; 811 804 input-disable; 812 805 power-source = <0>; 806 + }; 807 + }; 808 + 809 + &pm8150l_lpg { 810 + status = "okay"; 811 + 812 + led@1 { 813 + reg = <1>; 814 + color = <LED_COLOR_ID_GREEN>; 815 + function = LED_FUNCTION_HEARTBEAT; 816 + function-enumerator = <3>; 817 + 818 + linux,default-trigger = "heartbeat"; 819 + default-state = "on"; 820 + }; 821 + 822 + led@2 { 823 + reg = <2>; 824 + color = <LED_COLOR_ID_GREEN>; 825 + function = LED_FUNCTION_INDICATOR; 826 + function-enumerator = <2>; 827 + default-state = "on"; 828 + }; 829 + 830 + led@3 { 831 + reg = <3>; 832 + color = <LED_COLOR_ID_GREEN>; 833 + function = LED_FUNCTION_INDICATOR; 834 + function-enumerator = <1>; 813 835 }; 814 836 }; 815 837 ··· 866 830 867 831 &q6afedai { 868 832 qi2s@16 { 869 - reg = <16>; 833 + reg = <PRIMARY_MI2S_RX>; 870 834 qcom,sd-lines = <0 1 2 3>; 871 835 }; 872 836 }; ··· 874 838 /* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ 875 839 &q6afedai { 876 840 qi2s@20 { 877 - reg = <20>; 841 + reg = <TERTIARY_MI2S_RX>; 878 842 qcom,sd-lines = <0>; 879 843 }; 880 844 }; ··· 951 915 }; 952 916 953 917 codec { 954 - sound-dai = <&lt9611_codec 0>; 918 + sound-dai = <&lt9611_codec 0>; 955 919 }; 956 920 }; 957 921
+389
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2022, Linaro Limited 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 + #include <dt-bindings/spmi/spmi.h> 12 + 13 + #include "sa8540p.dtsi" 14 + 15 + / { 16 + model = "Qualcomm SA8295P ADP"; 17 + compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; 18 + 19 + aliases { 20 + serial0 = &qup2_uart17; 21 + }; 22 + 23 + chosen { 24 + stdout-path = "serial0:115200n8"; 25 + }; 26 + }; 27 + 28 + &apps_rsc { 29 + pmm8540-a-regulators { 30 + compatible = "qcom,pm8150-rpmh-regulators"; 31 + qcom,pmic-id = "a"; 32 + 33 + vreg_l3a: ldo3 { 34 + regulator-name = "vreg_l3a"; 35 + regulator-min-microvolt = <1200000>; 36 + regulator-max-microvolt = <1208000>; 37 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 38 + regulator-allow-set-load; 39 + }; 40 + 41 + vreg_l5a: ldo5 { 42 + regulator-name = "vreg_l5a"; 43 + regulator-min-microvolt = <912000>; 44 + regulator-max-microvolt = <912000>; 45 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 46 + regulator-allow-set-load; 47 + }; 48 + 49 + vreg_l7a: ldo7 { 50 + regulator-name = "vreg_l7a"; 51 + regulator-min-microvolt = <1800000>; 52 + regulator-max-microvolt = <1800000>; 53 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 54 + regulator-allow-set-load; 55 + }; 56 + 57 + vreg_l13a: ldo13 { 58 + regulator-name = "vreg_l13a"; 59 + regulator-min-microvolt = <3072000>; 60 + regulator-max-microvolt = <3072000>; 61 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 62 + regulator-allow-set-load; 63 + }; 64 + }; 65 + 66 + pmm8540-c-regulators { 67 + compatible = "qcom,pm8150-rpmh-regulators"; 68 + qcom,pmic-id = "c"; 69 + 70 + vreg_l1c: ldo1 { 71 + regulator-name = "vreg_l1c"; 72 + regulator-min-microvolt = <912000>; 73 + regulator-max-microvolt = <912000>; 74 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 75 + regulator-allow-set-load; 76 + }; 77 + 78 + vreg_l2c: ldo2 { 79 + regulator-name = "vreg_l2c"; 80 + regulator-min-microvolt = <3072000>; 81 + regulator-max-microvolt = <3072000>; 82 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 83 + regulator-allow-set-load; 84 + }; 85 + 86 + vreg_l3c: ldo3 { 87 + regulator-name = "vreg_l3c"; 88 + regulator-min-microvolt = <1200000>; 89 + regulator-max-microvolt = <1200000>; 90 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 91 + regulator-allow-set-load; 92 + }; 93 + 94 + vreg_l4c: ldo4 { 95 + regulator-name = "vreg_l4c"; 96 + regulator-min-microvolt = <1200000>; 97 + regulator-max-microvolt = <1208000>; 98 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 99 + regulator-allow-set-load; 100 + }; 101 + 102 + vreg_l6c: ldo6 { 103 + regulator-name = "vreg_l6c"; 104 + regulator-min-microvolt = <1200000>; 105 + regulator-max-microvolt = <1200000>; 106 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 107 + regulator-allow-set-load; 108 + }; 109 + 110 + vreg_l7c: ldo7 { 111 + regulator-name = "vreg_l7c"; 112 + regulator-min-microvolt = <1800000>; 113 + regulator-max-microvolt = <1800000>; 114 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 115 + regulator-allow-set-load; 116 + }; 117 + 118 + vreg_l10c: ldo10 { 119 + regulator-name = "vreg_l10c"; 120 + regulator-min-microvolt = <2504000>; 121 + regulator-max-microvolt = <2504000>; 122 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 123 + regulator-allow-set-load; 124 + }; 125 + 126 + vreg_l17c: ldo17 { 127 + regulator-name = "vreg_l17c"; 128 + regulator-min-microvolt = <2504000>; 129 + regulator-max-microvolt = <2504000>; 130 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 131 + regulator-allow-set-load; 132 + }; 133 + }; 134 + 135 + pmm8540-g-regulators { 136 + compatible = "qcom,pm8150-rpmh-regulators"; 137 + qcom,pmic-id = "g"; 138 + 139 + vreg_l3g: ldo3 { 140 + regulator-name = "vreg_l3g"; 141 + regulator-min-microvolt = <1200000>; 142 + regulator-max-microvolt = <1200000>; 143 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 144 + regulator-allow-set-load; 145 + }; 146 + 147 + vreg_l7g: ldo7 { 148 + regulator-name = "vreg_l7g"; 149 + regulator-min-microvolt = <1800000>; 150 + regulator-max-microvolt = <1800000>; 151 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 152 + regulator-allow-set-load; 153 + }; 154 + 155 + vreg_l8g: ldo8 { 156 + regulator-name = "vreg_l8g"; 157 + regulator-min-microvolt = <880000>; 158 + regulator-max-microvolt = <880000>; 159 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 160 + regulator-allow-set-load; 161 + }; 162 + }; 163 + }; 164 + 165 + &qup2 { 166 + status = "okay"; 167 + }; 168 + 169 + &qup2_uart17 { 170 + compatible = "qcom,geni-debug-uart"; 171 + status = "okay"; 172 + }; 173 + 174 + &remoteproc_adsp { 175 + firmware-name = "qcom/sa8540p/adsp.mbn"; 176 + status = "okay"; 177 + }; 178 + 179 + &remoteproc_nsp0 { 180 + firmware-name = "qcom/sa8540p/cdsp.mbn"; 181 + status = "okay"; 182 + }; 183 + 184 + &remoteproc_nsp1 { 185 + firmware-name = "qcom/sa8540p/cdsp1.mbn"; 186 + status = "okay"; 187 + }; 188 + 189 + &spmi_bus { 190 + pm8450a: pmic@0 { 191 + compatible = "qcom,pm8150", "qcom,spmi-pmic"; 192 + reg = <0x0 SPMI_USID>; 193 + #address-cells = <1>; 194 + #size-cells = <0>; 195 + 196 + pm8450a_gpios: gpio@c000 { 197 + compatible = "qcom,pm8150-gpio"; 198 + reg = <0xc000>; 199 + gpio-controller; 200 + #gpio-cells = <2>; 201 + interrupt-controller; 202 + #interrupt-cells = <2>; 203 + }; 204 + }; 205 + 206 + pm8450c: pmic@4 { 207 + compatible = "qcom,pm8150", "qcom,spmi-pmic"; 208 + reg = <0x4 SPMI_USID>; 209 + #address-cells = <1>; 210 + #size-cells = <0>; 211 + 212 + pm8450c_gpios: gpio@c000 { 213 + compatible = "qcom,pm8150-gpio"; 214 + reg = <0xc000>; 215 + gpio-controller; 216 + #gpio-cells = <2>; 217 + interrupt-controller; 218 + #interrupt-cells = <2>; 219 + }; 220 + }; 221 + 222 + pm8450e: pmic@8 { 223 + compatible = "qcom,pm8150", "qcom,spmi-pmic"; 224 + reg = <0x8 SPMI_USID>; 225 + #address-cells = <1>; 226 + #size-cells = <0>; 227 + 228 + pm8450e_gpios: gpio@c000 { 229 + compatible = "qcom,pm8150-gpio"; 230 + reg = <0xc000>; 231 + gpio-controller; 232 + #gpio-cells = <2>; 233 + interrupt-controller; 234 + #interrupt-cells = <2>; 235 + }; 236 + }; 237 + 238 + pm8450g: pmic@c { 239 + compatible = "qcom,pm8150", "qcom,spmi-pmic"; 240 + reg = <0xc SPMI_USID>; 241 + #address-cells = <1>; 242 + #size-cells = <0>; 243 + 244 + pm8450g_gpios: gpio@c000 { 245 + compatible = "qcom,pm8150-gpio"; 246 + reg = <0xc000>; 247 + gpio-controller; 248 + #gpio-cells = <2>; 249 + interrupt-controller; 250 + #interrupt-cells = <2>; 251 + }; 252 + }; 253 + }; 254 + 255 + &ufs_mem_hc { 256 + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; 257 + 258 + vcc-supply = <&vreg_l17c>; 259 + vcc-max-microamp = <800000>; 260 + vccq-supply = <&vreg_l6c>; 261 + vccq-max-microamp = <900000>; 262 + 263 + status = "okay"; 264 + }; 265 + 266 + &ufs_mem_phy { 267 + vdda-phy-supply = <&vreg_l8g>; 268 + vdda-pll-supply = <&vreg_l3g>; 269 + 270 + status = "okay"; 271 + }; 272 + 273 + &ufs_card_hc { 274 + reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>; 275 + 276 + vcc-supply = <&vreg_l10c>; 277 + vcc-max-microamp = <800000>; 278 + vccq-supply = <&vreg_l3c>; 279 + vccq-max-microamp = <900000>; 280 + 281 + status = "okay"; 282 + }; 283 + 284 + &ufs_card_phy { 285 + vdda-phy-supply = <&vreg_l8g>; 286 + vdda-pll-supply = <&vreg_l3g>; 287 + 288 + status = "okay"; 289 + }; 290 + 291 + &usb_0 { 292 + status = "okay"; 293 + }; 294 + 295 + &usb_0_dwc3 { 296 + /* TODO: Define USB-C connector properly */ 297 + dr_mode = "peripheral"; 298 + }; 299 + 300 + &usb_0_hsphy { 301 + vdda-pll-supply = <&vreg_l5a>; 302 + vdda18-supply = <&vreg_l7a>; 303 + vdda33-supply = <&vreg_l13a>; 304 + 305 + status = "okay"; 306 + }; 307 + 308 + &usb_0_qmpphy { 309 + vdda-phy-supply = <&vreg_l3a>; 310 + vdda-pll-supply = <&vreg_l5a>; 311 + 312 + status = "okay"; 313 + }; 314 + 315 + &usb_1 { 316 + status = "okay"; 317 + }; 318 + 319 + &usb_1_dwc3 { 320 + /* TODO: Define USB-C connector properly */ 321 + dr_mode = "host"; 322 + }; 323 + 324 + &usb_1_hsphy { 325 + vdda-pll-supply = <&vreg_l1c>; 326 + vdda18-supply = <&vreg_l7c>; 327 + vdda33-supply = <&vreg_l2c>; 328 + 329 + status = "okay"; 330 + }; 331 + 332 + &usb_1_qmpphy { 333 + vdda-phy-supply = <&vreg_l4c>; 334 + vdda-pll-supply = <&vreg_l1c>; 335 + 336 + status = "okay"; 337 + }; 338 + 339 + &usb_2_hsphy0 { 340 + vdda-pll-supply = <&vreg_l5a>; 341 + vdda18-supply = <&vreg_l7g>; 342 + vdda33-supply = <&vreg_l13a>; 343 + 344 + status = "okay"; 345 + }; 346 + 347 + &usb_2_hsphy1 { 348 + vdda-pll-supply = <&vreg_l5a>; 349 + vdda18-supply = <&vreg_l7g>; 350 + vdda33-supply = <&vreg_l13a>; 351 + 352 + status = "okay"; 353 + }; 354 + 355 + &usb_2_hsphy2 { 356 + vdda-pll-supply = <&vreg_l5a>; 357 + vdda18-supply = <&vreg_l7g>; 358 + vdda33-supply = <&vreg_l13a>; 359 + 360 + status = "okay"; 361 + }; 362 + 363 + &usb_2_hsphy3 { 364 + vdda-pll-supply = <&vreg_l5a>; 365 + vdda18-supply = <&vreg_l7g>; 366 + vdda33-supply = <&vreg_l13a>; 367 + 368 + status = "okay"; 369 + }; 370 + 371 + &usb_2_qmpphy0 { 372 + vdda-phy-supply = <&vreg_l3a>; 373 + vdda-pll-supply = <&vreg_l5a>; 374 + 375 + status = "okay"; 376 + }; 377 + 378 + &usb_2_qmpphy1 { 379 + vdda-phy-supply = <&vreg_l3a>; 380 + vdda-pll-supply = <&vreg_l5a>; 381 + 382 + status = "okay"; 383 + }; 384 + 385 + &xo_board_clk { 386 + clock-frequency = <38400000>; 387 + }; 388 + 389 + /* PINCTRL */
+133
arch/arm64/boot/dts/qcom/sa8540p.dtsi
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2022, Linaro Limited 5 + */ 6 + 7 + #include "sc8280xp.dtsi" 8 + 9 + /delete-node/ &cpu0_opp_table; 10 + /delete-node/ &cpu4_opp_table; 11 + 12 + / { 13 + cpu0_opp_table: cpu0-opp-table { 14 + compatible = "operating-points-v2"; 15 + opp-shared; 16 + 17 + opp-403200000 { 18 + opp-hz = /bits/ 64 <403200000>; 19 + }; 20 + opp-499200000 { 21 + opp-hz = /bits/ 64 <499200000>; 22 + }; 23 + opp-595200000 { 24 + opp-hz = /bits/ 64 <595200000>; 25 + }; 26 + opp-710400000 { 27 + opp-hz = /bits/ 64 <710400000>; 28 + }; 29 + opp-806400000 { 30 + opp-hz = /bits/ 64 <806400000>; 31 + }; 32 + opp-902400000 { 33 + opp-hz = /bits/ 64 <902400000>; 34 + }; 35 + opp-1017600000 { 36 + opp-hz = /bits/ 64 <1017600000>; 37 + }; 38 + opp-1113600000 { 39 + opp-hz = /bits/ 64 <1113600000>; 40 + }; 41 + opp-1209600000 { 42 + opp-hz = /bits/ 64 <1209600000>; 43 + }; 44 + opp-1324800000 { 45 + opp-hz = /bits/ 64 <1324800000>; 46 + }; 47 + opp-1440000000 { 48 + opp-hz = /bits/ 64 <1440000000>; 49 + }; 50 + opp-1555200000 { 51 + opp-hz = /bits/ 64 <1555200000>; 52 + }; 53 + opp-1670400000 { 54 + opp-hz = /bits/ 64 <1670400000>; 55 + }; 56 + opp-1785600000 { 57 + opp-hz = /bits/ 64 <1785600000>; 58 + }; 59 + opp-1881600000 { 60 + opp-hz = /bits/ 64 <1881600000>; 61 + }; 62 + opp-2016000000 { 63 + opp-hz = /bits/ 64 <2016000000>; 64 + }; 65 + opp-2131200000 { 66 + opp-hz = /bits/ 64 <2131200000>; 67 + }; 68 + opp-2246400000 { 69 + opp-hz = /bits/ 64 <2246400000>; 70 + }; 71 + }; 72 + 73 + cpu4_opp_table: cpu4-opp-table { 74 + compatible = "operating-points-v2"; 75 + opp-shared; 76 + 77 + opp-825600000 { 78 + opp-hz = /bits/ 64 <825600000>; 79 + }; 80 + opp-940800000 { 81 + opp-hz = /bits/ 64 <940800000>; 82 + }; 83 + opp-1056000000 { 84 + opp-hz = /bits/ 64 <1056000000>; 85 + }; 86 + opp-1171200000 { 87 + opp-hz = /bits/ 64 <1171200000>; 88 + }; 89 + opp-1286400000 { 90 + opp-hz = /bits/ 64 <1286400000>; 91 + }; 92 + opp-1401600000 { 93 + opp-hz = /bits/ 64 <1401600000>; 94 + }; 95 + opp-1516800000 { 96 + opp-hz = /bits/ 64 <1516800000>; 97 + }; 98 + opp-1632000000 { 99 + opp-hz = /bits/ 64 <1632000000>; 100 + }; 101 + opp-1747200000 { 102 + opp-hz = /bits/ 64 <1747200000>; 103 + }; 104 + opp-1862400000 { 105 + opp-hz = /bits/ 64 <1862400000>; 106 + }; 107 + opp-1977600000 { 108 + opp-hz = /bits/ 64 <1977600000>; 109 + }; 110 + opp-2073600000 { 111 + opp-hz = /bits/ 64 <2073600000>; 112 + }; 113 + opp-2169600000 { 114 + opp-hz = /bits/ 64 <2169600000>; 115 + }; 116 + opp-2284800000 { 117 + opp-hz = /bits/ 64 <2284800000>; 118 + }; 119 + opp-2380800000 { 120 + opp-hz = /bits/ 64 <2380800000>; 121 + }; 122 + opp-2496000000 { 123 + opp-hz = /bits/ 64 <2496000000>; 124 + }; 125 + opp-2592000000 { 126 + opp-hz = /bits/ 64 <2592000000>; 127 + }; 128 + }; 129 + }; 130 + 131 + &rpmhpd { 132 + compatible = "qcom,sa8540p-rpmhpd"; 133 + };
+3 -2
arch/arm64/boot/dts/qcom/sc7180-idp.dts
··· 330 330 331 331 &dsi_phy { 332 332 status = "okay"; 333 + vdds-supply = <&vreg_l4a_0p8>; 333 334 }; 334 335 335 336 &mdp { ··· 390 389 pinctrl-names = "default","sleep"; 391 390 pinctrl-0 = <&sdc2_on>; 392 391 pinctrl-1 = <&sdc2_off>; 393 - vmmc-supply = <&vreg_l9c_2p9>; 392 + vmmc-supply = <&vreg_l9c_2p9>; 394 393 vqmmc-supply = <&vreg_l6c_2p9>; 395 394 396 395 cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; ··· 468 467 /* PINCTRL - additions to nodes defined in sc7180.dtsi */ 469 468 470 469 &pm6150l_gpio { 471 - disp_pins: disp-pins { 470 + disp_pins: disp-state { 472 471 pinconf { 473 472 pins = "gpio3"; 474 473 function = PMIC_GPIO_FUNC_FUNC1;
+4
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
··· 81 81 }; 82 82 83 83 &cros_ec { 84 + keyboard-controller { 85 + compatible = "google,cros-ec-keyb-switches"; 86 + }; 87 + 84 88 cros_ec_proximity: proximity { 85 89 compatible = "google,cros-ec-mkbp-proximity"; 86 90 label = "proximity-wifi";
+7 -1
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
··· 5 5 * Copyright 2021 Google LLC. 6 6 */ 7 7 8 - #include "sc7180-trogdor.dtsi" 8 + /* This file must be included after sc7180-trogdor.dtsi */ 9 9 10 10 / { 11 11 /* BOARD-SPECIFIC TOP LEVEL NODES */ ··· 112 112 113 113 &camcc { 114 114 status = "okay"; 115 + }; 116 + 117 + &cros_ec { 118 + keyboard-controller { 119 + compatible = "google,cros-ec-keyb-switches"; 120 + }; 115 121 }; 116 122 117 123 &panel {
+44
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Kingoftown board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-ti-sn65dsi86.dtsi" 12 + #include "sc7180-trogdor-kingoftown.dtsi" 13 + 14 + / { 15 + model = "Google Kingoftown (rev0)"; 16 + compatible = "google,kingoftown-rev0", "qcom,sc7180"; 17 + }; 18 + 19 + /* 20 + * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a 21 + * power rail instead, since kingoftown does not have FP. 22 + */ 23 + &pp3300_fp_tp { 24 + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; 25 + enable-active-high; 26 + 27 + pinctrl-names = "default"; 28 + pinctrl-0 = <&en_fp_rails>; 29 + }; 30 + 31 + &tlmm { 32 + en_fp_rails: en-fp-rails { 33 + pinmux { 34 + pins = "gpio74"; 35 + function = "gpio"; 36 + }; 37 + 38 + pinconf { 39 + pins = "gpio74"; 40 + drive-strength = <2>; 41 + bias-disable; 42 + }; 43 + }; 44 + };
+17
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Kingoftown board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-parade-ps8640.dtsi" 12 + #include "sc7180-trogdor-kingoftown.dtsi" 13 + 14 + / { 15 + model = "Google Kingoftown (rev1+)"; 16 + compatible = "google,kingoftown", "qcom,sc7180"; 17 + };
+225
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Kingoftown board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /* This file must be included after sc7180-trogdor.dtsi */ 9 + #include <arm/cros-ec-keyboard.dtsi> 10 + #include "sc7180-trogdor-lte-sku.dtsi" 11 + 12 + &alc5682 { 13 + compatible = "realtek,rt5682s"; 14 + realtek,dmic1-clk-pin = <2>; 15 + realtek,dmic-clk-rate-hz = <2048000>; 16 + }; 17 + 18 + &ap_tp_i2c { 19 + status = "okay"; 20 + }; 21 + 22 + ap_ts_pen_1v8: &i2c4 { 23 + status = "okay"; 24 + clock-frequency = <400000>; 25 + 26 + ap_ts: touchscreen@10 { 27 + compatible = "elan,ekth3500"; 28 + reg = <0x10>; 29 + pinctrl-names = "default"; 30 + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; 31 + 32 + interrupt-parent = <&tlmm>; 33 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 34 + 35 + vcc33-supply = <&pp3300_ts>; 36 + 37 + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; 38 + }; 39 + }; 40 + 41 + &keyboard_controller { 42 + function-row-physmap = < 43 + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 44 + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 45 + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 46 + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 47 + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 48 + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 49 + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 50 + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 51 + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 52 + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 53 + >; 54 + linux,keymap = < 55 + MATRIX_KEY(0x00, 0x02, KEY_BACK) 56 + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 57 + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 58 + MATRIX_KEY(0x01, 0x02, KEY_SCALE) 59 + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 60 + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 61 + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 62 + MATRIX_KEY(0x02, 0x09, KEY_MUTE) 63 + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 64 + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 65 + 66 + CROS_STD_MAIN_KEYMAP 67 + >; 68 + }; 69 + 70 + &panel { 71 + compatible = "edp-panel"; 72 + }; 73 + 74 + &pp3300_dx_edp { 75 + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; 76 + }; 77 + 78 + &sound { 79 + compatible = "google,sc7180-trogdor"; 80 + model = "sc7180-rt5682s-max98357a-1mic"; 81 + }; 82 + 83 + &wifi { 84 + qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; 85 + }; 86 + 87 + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ 88 + 89 + &en_pp3300_dx_edp { 90 + pinmux { 91 + pins = "gpio67"; 92 + }; 93 + 94 + pinconf { 95 + pins = "gpio67"; 96 + }; 97 + }; 98 + 99 + /* PINCTRL - board-specific pinctrl */ 100 + 101 + &tlmm { 102 + gpio-line-names = "TP_INT_L", /* 0 */ 103 + "AP_RAM_ID0", 104 + "AP_SKU_ID2", 105 + "AP_RAM_ID1", 106 + "", 107 + "AP_RAM_ID2", 108 + "AP_TP_I2C_SDA", 109 + "AP_TP_I2C_SCL", 110 + "TS_RESET_L", 111 + "TS_INT_L", 112 + "", /* 10 */ 113 + "EDP_BRIJ_IRQ", 114 + "AP_EDP_BKLTEN", 115 + "", 116 + "", 117 + "EDP_BRIJ_I2C_SDA", 118 + "EDP_BRIJ_I2C_SCL", 119 + "HUB_RST_L", 120 + "", 121 + "", 122 + "", /* 20 */ 123 + "", 124 + "", 125 + "AMP_EN", 126 + "", 127 + "", 128 + "", 129 + "", 130 + "HP_IRQ", 131 + "", 132 + "", /* 30 */ 133 + "AP_BRD_ID2", 134 + "BRIJ_SUSPEND", 135 + "AP_BRD_ID0", 136 + "AP_H1_SPI_MISO", 137 + "AP_H1_SPI_MOSI", 138 + "AP_H1_SPI_CLK", 139 + "AP_H1_SPI_CS_L", 140 + "BT_UART_CTS", 141 + "BT_UART_RTS", 142 + "BT_UART_TXD", /* 40 */ 143 + "BT_UART_RXD", 144 + "H1_AP_INT_ODL", 145 + "", 146 + "UART_AP_TX_DBG_RX", 147 + "UART_DBG_TX_AP_RX", 148 + "HP_I2C_SDA", 149 + "HP_I2C_SCL", 150 + "FORCED_USB_BOOT", 151 + "AMP_BCLK", 152 + "AMP_LRCLK", /* 50 */ 153 + "AMP_DIN", 154 + "", 155 + "HP_BCLK", 156 + "HP_LRCLK", 157 + "HP_DOUT", 158 + "HP_DIN", 159 + "HP_MCLK", 160 + "AP_SKU_ID0", 161 + "AP_EC_SPI_MISO", 162 + "AP_EC_SPI_MOSI", /* 60 */ 163 + "AP_EC_SPI_CLK", 164 + "AP_EC_SPI_CS_L", 165 + "AP_SPI_CLK", 166 + "AP_SPI_MOSI", 167 + "AP_SPI_MISO", 168 + /* 169 + * AP_FLASH_WP_L is crossystem ABI. Schematics 170 + * call it BIOS_FLASH_WP_L. 171 + */ 172 + "AP_FLASH_WP_L", 173 + "EN_PP3300_DX_EDP", 174 + "AP_SPI_CS0_L", 175 + "", 176 + "", /* 70 */ 177 + "", 178 + "", 179 + "", 180 + "EN_FP_RAILS", 181 + "UIM2_DATA", 182 + "UIM2_CLK", 183 + "UIM2_RST", 184 + "UIM2_PRESENT_L", 185 + "UIM1_DATA", 186 + "UIM1_CLK", /* 80 */ 187 + "UIM1_RST", 188 + "", 189 + "CODEC_PWR_EN", 190 + "HUB_EN", 191 + "", 192 + "", 193 + "", 194 + "", 195 + "", 196 + "AP_SKU_ID1", /* 90 */ 197 + "AP_RST_REQ", 198 + "", 199 + "AP_BRD_ID1", 200 + "AP_EC_INT_L", 201 + "", 202 + "", 203 + "", 204 + "", 205 + "", 206 + "", /* 100 */ 207 + "", 208 + "", 209 + "", 210 + "EDP_BRIJ_EN", 211 + "", 212 + "", 213 + "", 214 + "", 215 + "", 216 + "", /* 110 */ 217 + "", 218 + "", 219 + "", 220 + "", 221 + "AP_TS_PEN_I2C_SDA", 222 + "AP_TS_PEN_I2C_SCL", 223 + "DP_HOT_PLUG_DET", 224 + "EC_IN_RW_ODL"; 225 + };
+2 -1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
··· 5 5 * Copyright 2020 Google LLC. 6 6 */ 7 7 8 - #include "sc7180-trogdor.dtsi" 8 + /* This file must be included after sc7180-trogdor.dtsi */ 9 + #include <arm/cros-ec-keyboard.dtsi> 9 10 10 11 &ap_sar_sensor { 11 12 semtech,cs0-ground;
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x0 => 0 8 + * - bits 7..4: Panel ID: 0x0 (AUO) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-mrbland-rev0.dtsi" 14 + 15 + / { 16 + model = "Google Mrbland rev0 AUO panel board"; 17 + compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "auo,b101uan08.3"; 22 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x10 => 16 8 + * - bits 7..4: Panel ID: 0x1 (BOE) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-mrbland-rev0.dtsi" 14 + 15 + / { 16 + model = "Google Mrbland rev0 BOE panel board"; 17 + compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "boe,tv101wum-n53"; 22 + };
+53
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "sc7180-trogdor-mrbland.dtsi" 12 + 13 + &avdd_lcd { 14 + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; 15 + }; 16 + 17 + &panel { 18 + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; 19 + }; 20 + 21 + &v1p8_mipi { 22 + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 23 + }; 24 + 25 + /* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ 26 + &avdd_lcd_en { 27 + pinmux { 28 + pins = "gpio80"; 29 + }; 30 + 31 + pinconf { 32 + pins = "gpio80"; 33 + }; 34 + }; 35 + 36 + &mipi_1800_en { 37 + pinmux { 38 + pins = "gpio81"; 39 + }; 40 + 41 + pinconf { 42 + pins = "gpio81"; 43 + }; 44 + }; 45 + &vdd_reset_1800 { 46 + pinmux { 47 + pins = "gpio76"; 48 + }; 49 + 50 + pinconf { 51 + pins = "gpio76"; 52 + }; 53 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x600 => 1536 8 + * - bits 11..8: Panel ID: 0x6 (AUO) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-mrbland.dtsi" 14 + 15 + / { 16 + model = "Google Mrbland rev1+ AUO panel board"; 17 + compatible = "google,mrbland-sku1536", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "auo,b101uan08.3"; 22 + };
+24
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x300 => 768 8 + * - bits 11..8: Panel ID: 0x3 (BOE) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-mrbland.dtsi" 14 + 15 + / { 16 + model = "Google Mrbland (rev1 - 2) BOE panel board"; 17 + /* Uses ID 768 on rev1 and 1024 on rev2+ */ 18 + compatible = "google,mrbland-sku1024", "google,mrbland-sku768", 19 + "qcom,sc7180"; 20 + }; 21 + 22 + &panel { 23 + compatible = "boe,tv101wum-n53"; 24 + };
+350
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Mrbland board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + 12 + /* This board only has 1 USB Type-C port. */ 13 + /delete-node/ &usb_c1; 14 + 15 + / { 16 + avdd_lcd: avdd-lcd { 17 + compatible = "regulator-fixed"; 18 + regulator-name = "avdd_lcd"; 19 + 20 + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; 21 + enable-active-high; 22 + pinctrl-names = "default"; 23 + pinctrl-0 = <&avdd_lcd_en>; 24 + 25 + vin-supply = <&pp5000_a>; 26 + }; 27 + 28 + avee_lcd: avee-lcd { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "avee_lcd"; 31 + 32 + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; 33 + enable-active-high; 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&avee_lcd_en>; 36 + 37 + vin-supply = <&pp5000_a>; 38 + }; 39 + 40 + v1p8_mipi: v1p8-mipi { 41 + compatible = "regulator-fixed"; 42 + regulator-name = "v1p8_mipi"; 43 + 44 + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; 45 + enable-active-high; 46 + pinctrl-names = "default"; 47 + pinctrl-0 = <&mipi_1800_en>; 48 + 49 + vin-supply = <&pp3300_a>; 50 + }; 51 + }; 52 + 53 + &backlight { 54 + pwms = <&cros_ec_pwm 0>; 55 + }; 56 + 57 + &camcc { 58 + status = "okay"; 59 + }; 60 + 61 + &cros_ec { 62 + keyboard-controller { 63 + compatible = "google,cros-ec-keyb-switches"; 64 + }; 65 + }; 66 + 67 + &dsi0 { 68 + 69 + panel: panel@0 { 70 + /* Compatible will be filled in per-board */ 71 + reg = <0>; 72 + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 73 + pinctrl-names = "default"; 74 + pinctrl-0 = <&vdd_reset_1800>; 75 + avdd-supply = <&avdd_lcd>; 76 + avee-supply = <&avee_lcd>; 77 + pp1800-supply = <&v1p8_mipi>; 78 + pp3300-supply = <&pp3300_dx_edp>; 79 + backlight = <&backlight>; 80 + rotation = <270>; 81 + 82 + ports { 83 + #address-cells = <1>; 84 + #size-cells = <0>; 85 + port@0 { 86 + reg = <0>; 87 + panel_in: endpoint { 88 + remote-endpoint = <&dsi0_out>; 89 + }; 90 + }; 91 + }; 92 + }; 93 + 94 + ports { 95 + port@1 { 96 + endpoint { 97 + remote-endpoint = <&panel_in>; 98 + data-lanes = <0 1 2 3>; 99 + }; 100 + }; 101 + }; 102 + }; 103 + 104 + &gpio_keys { 105 + status = "okay"; 106 + }; 107 + 108 + &i2c4 { 109 + status = "okay"; 110 + clock-frequency = <400000>; 111 + 112 + ap_ts: touchscreen@5d { 113 + compatible = "goodix,gt7375p"; 114 + reg = <0x5d>; 115 + pinctrl-names = "default"; 116 + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; 117 + 118 + interrupt-parent = <&tlmm>; 119 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 120 + 121 + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; 122 + 123 + vdd-supply = <&pp3300_ts>; 124 + }; 125 + }; 126 + 127 + &pp1800_uf_cam { 128 + status = "okay"; 129 + }; 130 + 131 + &pp1800_wf_cam { 132 + status = "okay"; 133 + }; 134 + 135 + &pp2800_uf_cam { 136 + status = "okay"; 137 + }; 138 + 139 + &pp2800_wf_cam { 140 + status = "okay"; 141 + }; 142 + 143 + &wifi { 144 + qcom,ath10k-calibration-variant = "GO_MRBLAND"; 145 + }; 146 + 147 + /* 148 + * No eDP on this board but it's logically the same signal so just give it 149 + * a new name and assign the proper GPIO. 150 + */ 151 + pp3300_disp_on: &pp3300_dx_edp { 152 + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; 153 + }; 154 + 155 + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ 156 + 157 + /* 158 + * No eDP on this board but it's logically the same signal so just give it 159 + * a new name and assign the proper GPIO. 160 + */ 161 + 162 + tp_en: &en_pp3300_dx_edp { 163 + pinmux { 164 + pins = "gpio85"; 165 + }; 166 + 167 + pinconf { 168 + pins = "gpio85"; 169 + }; 170 + }; 171 + 172 + /* PINCTRL - board-specific pinctrl */ 173 + 174 + &tlmm { 175 + gpio-line-names = "HUB_RST_L", 176 + "AP_RAM_ID0", 177 + "AP_SKU_ID2", 178 + "AP_RAM_ID1", 179 + "", 180 + "AP_RAM_ID2", 181 + "UF_CAM_EN", 182 + "WF_CAM_EN", 183 + "TS_RESET_L", 184 + "TS_INT_L", 185 + "", 186 + "", 187 + "AP_EDP_BKLTEN", 188 + "UF_CAM_MCLK", 189 + "WF_CAM_CLK", 190 + "", 191 + "", 192 + "UF_CAM_SDA", 193 + "UF_CAM_SCL", 194 + "WF_CAM_SDA", 195 + "WF_CAM_SCL", 196 + "AVEE_LCD_EN", 197 + "", 198 + "AMP_EN", 199 + "", 200 + "", 201 + "", 202 + "", 203 + "HP_IRQ", 204 + "WF_CAM_RST_L", 205 + "UF_CAM_RST_L", 206 + "AP_BRD_ID2", 207 + "", 208 + "AP_BRD_ID0", 209 + "AP_H1_SPI_MISO", 210 + "AP_H1_SPI_MOSI", 211 + "AP_H1_SPI_CLK", 212 + "AP_H1_SPI_CS_L", 213 + "BT_UART_CTS", 214 + "BT_UART_RTS", 215 + "BT_UART_TXD", 216 + "BT_UART_RXD", 217 + "H1_AP_INT_ODL", 218 + "", 219 + "UART_AP_TX_DBG_RX", 220 + "UART_DBG_TX_AP_RX", 221 + "HP_I2C_SDA", 222 + "HP_I2C_SCL", 223 + "FORCED_USB_BOOT", 224 + "AMP_BCLK", 225 + "AMP_LRCLK", 226 + "AMP_DIN", 227 + "PEN_DET_ODL", 228 + "HP_BCLK", 229 + "HP_LRCLK", 230 + "HP_DOUT", 231 + "HP_DIN", 232 + "HP_MCLK", 233 + "AP_SKU_ID0", 234 + "AP_EC_SPI_MISO", 235 + "AP_EC_SPI_MOSI", 236 + "AP_EC_SPI_CLK", 237 + "AP_EC_SPI_CS_L", 238 + "AP_SPI_CLK", 239 + "AP_SPI_MOSI", 240 + "AP_SPI_MISO", 241 + /* 242 + * AP_FLASH_WP_L is crossystem ABI. Schematics 243 + * call it BIOS_FLASH_WP_L. 244 + */ 245 + "AP_FLASH_WP_L", 246 + "", 247 + "AP_SPI_CS0_L", 248 + "", 249 + "", 250 + "", 251 + "", 252 + "WLAN_SW_CTRL", 253 + "", 254 + "REPORT_E", 255 + "", 256 + "ID0", 257 + "", 258 + "ID1", 259 + "", 260 + "", 261 + "", 262 + "CODEC_PWR_EN", 263 + "HUB_EN", 264 + "TP_EN", 265 + "MIPI_1.8V_EN", 266 + "VDD_RESET_1.8V", 267 + "AVDD_LCD_EN", 268 + "", 269 + "AP_SKU_ID1", 270 + "AP_RST_REQ", 271 + "", 272 + "AP_BRD_ID1", 273 + "AP_EC_INT_L", 274 + "SDM_GRFC_3", 275 + "", 276 + "", 277 + "BOOT_CONFIG_4", 278 + "BOOT_CONFIG_2", 279 + "", 280 + "", 281 + "", 282 + "", 283 + "", 284 + "", 285 + "", 286 + "BOOT_CONFIG_3", 287 + "WCI2_LTE_COEX_TXD", 288 + "WCI2_LTE_COEX_RXD", 289 + "", 290 + "", 291 + "", 292 + "", 293 + "FORCED_USB_BOOT_POL", 294 + "AP_TS_PEN_I2C_SDA", 295 + "AP_TS_PEN_I2C_SCL", 296 + "DP_HOT_PLUG_DET", 297 + "EC_IN_RW_ODL"; 298 + 299 + avdd_lcd_en: avdd-lcd-en { 300 + pinmux { 301 + pins = "gpio88"; 302 + function = "gpio"; 303 + }; 304 + 305 + pinconf { 306 + pins = "gpio88"; 307 + drive-strength = <2>; 308 + bias-disable; 309 + }; 310 + }; 311 + 312 + avee_lcd_en: avee-lcd-en { 313 + pinmux { 314 + pins = "gpio21"; 315 + function = "gpio"; 316 + }; 317 + 318 + pinconf { 319 + pins = "gpio21"; 320 + drive-strength = <2>; 321 + bias-disable; 322 + }; 323 + }; 324 + 325 + mipi_1800_en: mipi-1800-en { 326 + pinmux { 327 + pins = "gpio86"; 328 + function = "gpio"; 329 + }; 330 + 331 + pinconf { 332 + pins = "gpio86"; 333 + drive-strength = <2>; 334 + bias-disable; 335 + }; 336 + }; 337 + 338 + vdd_reset_1800: vdd-reset-1800 { 339 + pinmux { 340 + pins = "gpio87"; 341 + function = "gpio"; 342 + }; 343 + 344 + pinconf { 345 + pins = "gpio87"; 346 + drive-strength = <2>; 347 + bias-disable; 348 + }; 349 + }; 350 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Pazquel board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-parade-ps8640.dtsi" 12 + #include "sc7180-trogdor-pazquel.dtsi" 13 + #include "sc7180-trogdor-lte-sku.dtsi" 14 + 15 + / { 16 + model = "Google Pazquel (Parade,LTE)"; 17 + compatible = "google,pazquel-sku4", "qcom,sc7180"; 18 + }; 19 + 20 + &ap_sar_sensor_i2c { 21 + status = "okay"; 22 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Pazquel board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-ti-sn65dsi86.dtsi" 12 + #include "sc7180-trogdor-pazquel.dtsi" 13 + #include "sc7180-trogdor-lte-sku.dtsi" 14 + 15 + / { 16 + model = "Google Pazquel (TI,LTE)"; 17 + compatible = "google,pazquel-sku0", "google,pazquel-sku2", "qcom,sc7180"; 18 + }; 19 + 20 + &ap_sar_sensor_i2c { 21 + status = "okay"; 22 + };
+17
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Pazquel board device tree source 4 + * 5 + * Copyright 2022 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-parade-ps8640.dtsi" 12 + #include "sc7180-trogdor-pazquel.dtsi" 13 + 14 + / { 15 + model = "Google Pazquel (Parade)"; 16 + compatible = "google,pazquel-sku5", "qcom,sc7180"; 17 + };
+17
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Pazquel board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + #include "sc7180-trogdor-ti-sn65dsi86.dtsi" 12 + #include "sc7180-trogdor-pazquel.dtsi" 13 + 14 + / { 15 + model = "Google Pazquel (TI)"; 16 + compatible = "google,pazquel-sku1", "qcom,sc7180"; 17 + };
+222
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Pazquel board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /* This file must be included after sc7180-trogdor.dtsi */ 9 + #include <arm/cros-ec-keyboard.dtsi> 10 + 11 + &ap_sar_sensor { 12 + compatible = "semtech,sx9324"; 13 + semtech,ph0-pin = <1 3 3>; 14 + semtech,ph1-pin = <3 1 3>; 15 + semtech,ph2-pin = <1 3 3>; 16 + semtech,ph3-pin = <0 0 0>; 17 + semtech,ph01-resolution = <1024>; 18 + semtech,ph23-resolution = <1024>; 19 + semtech,startup-sensor = <1>; 20 + semtech,ph01-proxraw-strength = <3>; 21 + semtech,ph23-proxraw-strength = <1>; 22 + semtech,avg-pos-strength = <128>; 23 + semtech,input-analog-gain = <0>; 24 + semtech,cs-idle-sleep = "gnd"; 25 + 26 + /delete-property/ svdd-supply; 27 + vdd-supply = <&pp1800_prox>; 28 + }; 29 + 30 + /delete-node/&trackpad; 31 + &ap_tp_i2c { 32 + status = "okay"; 33 + trackpad: trackpad@15 { 34 + compatible = "hid-over-i2c"; 35 + reg = <0x15>; 36 + pinctrl-names = "default"; 37 + pinctrl-0 = <&tp_int_odl>; 38 + 39 + interrupt-parent = <&tlmm>; 40 + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 41 + 42 + vcc-supply = <&pp3300_fp_tp>; 43 + post-power-on-delay-ms = <100>; 44 + hid-descr-addr = <0x0001>; 45 + 46 + wakeup-source; 47 + }; 48 + }; 49 + 50 + &keyboard_controller { 51 + function-row-physmap = < 52 + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 53 + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 54 + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 55 + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 56 + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 57 + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 58 + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 59 + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 60 + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 61 + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 62 + >; 63 + linux,keymap = < 64 + MATRIX_KEY(0x00, 0x02, KEY_BACK) 65 + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 66 + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 67 + MATRIX_KEY(0x01, 0x02, KEY_SCALE) 68 + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 69 + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 70 + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 71 + MATRIX_KEY(0x02, 0x09, KEY_MUTE) 72 + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 73 + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 74 + CROS_STD_MAIN_KEYMAP 75 + >; 76 + }; 77 + 78 + &panel { 79 + compatible = "edp-panel"; 80 + }; 81 + 82 + &pp3300_dx_edp { 83 + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; 84 + }; 85 + 86 + &en_pp3300_dx_edp { 87 + pinmux { 88 + pins = "gpio67"; 89 + }; 90 + 91 + pinconf { 92 + pins = "gpio67"; 93 + }; 94 + }; 95 + 96 + /* PINCTRL - board-specific pinctrl */ 97 + 98 + &tlmm { 99 + gpio-line-names = "TP_INT_ODL", 100 + "AP_RAM_ID0", 101 + "AP_SKU_ID2", 102 + "AP_RAM_ID1", 103 + "", 104 + "AP_RAM_ID2", 105 + "AP_TP_I2C_SDA", 106 + "AP_TP_I2C_SCL", 107 + "TS_RESET_L", 108 + "TS_INT_L", 109 + "", 110 + "EDP_BRIJ_IRQ", 111 + "AP_EDP_BKLTEN", 112 + "", 113 + "", 114 + "EDP_BRIJ_I2C_SDA", 115 + "EDP_BRIJ_I2C_SCL", 116 + "HUB_RST_L", 117 + "", 118 + "", 119 + "", 120 + "", 121 + "", 122 + "AMP_EN", 123 + "P_SENSOR_INT_L", 124 + "AP_SAR_SENSOR_SDA", 125 + "AP_SAR_SENSOR_SCL", 126 + "", 127 + "HP_IRQ", 128 + "", 129 + "", 130 + "AP_BRD_ID2", 131 + "BRIJ_SUSPEND", 132 + "AP_BRD_ID0", 133 + "AP_H1_SPI_MISO", 134 + "AP_H1_SPI_MOSI", 135 + "AP_H1_SPI_CLK", 136 + "AP_H1_SPI_CS_L", 137 + "", 138 + "", 139 + "", 140 + "", 141 + "H1_AP_INT_ODL", 142 + "", 143 + "UART_AP_TX_DBG_RX", 144 + "UART_DBG_TX_AP_RX", 145 + "HP_I2C_SDA", 146 + "HP_I2C_SCL", 147 + "FORCED_USB_BOOT", 148 + "AMP_BCLK", 149 + "AMP_LRCLK", 150 + "AMP_DIN", 151 + "", 152 + "HP_BCLK", 153 + "HP_LRCLK", 154 + "HP_DOUT", 155 + "HP_DIN", 156 + "HP_MCLK", 157 + "AP_SKU_ID0", 158 + "AP_EC_SPI_MISO", 159 + "AP_EC_SPI_MOSI", 160 + "AP_EC_SPI_CLK", 161 + "AP_EC_SPI_CS_L", 162 + "AP_SPI_CLK", 163 + "AP_SPI_MOSI", 164 + "AP_SPI_MISO", 165 + /* 166 + * AP_FLASH_WP_L is crossystem ABI. Schematics 167 + * call it BIOS_FLASH_WP_L. 168 + */ 169 + "AP_FLASH_WP_L", 170 + "EN_PP3300_DX_EDP", 171 + "AP_SPI_CS0_L", 172 + "", 173 + "", 174 + "", 175 + "", 176 + "", 177 + "", 178 + "UIM2_DATA", 179 + "UIM2_CLK", 180 + "UIM2_RST", 181 + "UIM2_PRESENT", 182 + "UIM1_DATA", 183 + "UIM1_CLK", 184 + "UIM1_RST", 185 + "", 186 + "CODEC_PWR_EN", 187 + "HUB_EN", 188 + "", 189 + "", 190 + "", 191 + "", 192 + "", 193 + "AP_SKU_ID1", 194 + "AP_RST_REQ", 195 + "", 196 + "AP_BRD_ID1", 197 + "AP_EC_INT_L", 198 + "", 199 + "", 200 + "", 201 + "", 202 + "", 203 + "", 204 + "", 205 + "", 206 + "", 207 + "EDP_BRIJ_EN", 208 + "", 209 + "", 210 + "", 211 + "", 212 + "", 213 + "", 214 + "", 215 + "", 216 + "", 217 + "", 218 + "AP_TS_PEN_I2C_SDA", 219 + "AP_TS_PEN_I2C_SCL", 220 + "DP_HOT_PLUG_DET", 221 + "EC_IN_RW_ODL"; 222 + };
+2
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
··· 6 6 */ 7 7 8 8 #include "sc7180-trogdor.dtsi" 9 + /* Must come after sc7180-trogdor.dtsi to modify cros_ec */ 10 + #include <arm/cros-ec-keyboard.dtsi> 9 11 #include "sc7180-trogdor-ti-sn65dsi86.dtsi" 10 12 11 13 / {
+38
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Quackingstick board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x600 => 1536 8 + * - bits 11..8: Panel ID: 0x6 (AUO) 9 + */ 10 + 11 + #include "sc7180-trogdor-quackingstick-r0.dts" 12 + #include "sc7180-trogdor-lte-sku.dtsi" 13 + 14 + / { 15 + model = "Google Quackingstick (rev0+) with LTE"; 16 + compatible = "google,quackingstick-sku1536", "qcom,sc7180"; 17 + }; 18 + 19 + &ap_sar_sensor { 20 + compatible = "semtech,sx9324"; 21 + semtech,ph0-pin = <3 1 3>; 22 + semtech,ph1-pin = <2 1 2>; 23 + semtech,ph2-pin = <3 3 1>; 24 + semtech,ph3-pin = <1 3 3>; 25 + semtech,ph01-resolution = <1024>; 26 + semtech,ph23-resolution = <1024>; 27 + semtech,startup-sensor = <1>; 28 + semtech,ph01-proxraw-strength = <3>; 29 + semtech,ph23-proxraw-strength = <3>; 30 + semtech,avg-pos-strength = <256>; 31 + 32 + /delete-property/ svdd-supply; 33 + vdd-supply = <&pp1800_prox>; 34 + }; 35 + 36 + &ap_sar_sensor_i2c { 37 + status = "okay"; 38 + };
+26
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Quackingstick board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x601 => 1537 8 + * - bits 11..8: Panel ID: 0x6 (AUO) 9 + */ 10 + 11 + #include "sc7180-trogdor-quackingstick.dtsi" 12 + 13 + / { 14 + model = "Google Quackingstick (rev0+)"; 15 + compatible = "google,quackingstick-sku1537", "qcom,sc7180"; 16 + }; 17 + 18 + &dsi_phy { 19 + qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; 20 + qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; 21 + qcom,phy-drive-ldo-level = <375>; 22 + }; 23 + 24 + &panel { 25 + compatible = "auo,b101uan08.3"; 26 + };
+324
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Quackingstick board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + 12 + /* This board only has 1 USB Type-C port. */ 13 + /delete-node/ &usb_c1; 14 + 15 + / { 16 + ppvar_lcd: ppvar-lcd { 17 + compatible = "regulator-fixed"; 18 + regulator-name = "ppvar_lcd"; 19 + 20 + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; 21 + enable-active-high; 22 + pinctrl-names = "default"; 23 + pinctrl-0 = <&ppvar_lcd_en>; 24 + 25 + vin-supply = <&pp5000_a>; 26 + }; 27 + 28 + v1p8_disp: v1p8-disp { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "v1p8_disp"; 31 + 32 + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; 33 + enable-active-high; 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&pp1800_disp_on>; 36 + 37 + vin-supply = <&pp3300_a>; 38 + }; 39 + }; 40 + 41 + &backlight { 42 + pwms = <&cros_ec_pwm 0>; 43 + }; 44 + 45 + &camcc { 46 + status = "okay"; 47 + }; 48 + 49 + &cros_ec { 50 + keyboard-controller { 51 + compatible = "google,cros-ec-keyb-switches"; 52 + }; 53 + }; 54 + 55 + &dsi0 { 56 + panel: panel@0 { 57 + /* Compatible will be filled in per-board */ 58 + reg = <0>; 59 + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 60 + pinctrl-names = "default"; 61 + pinctrl-0 = <&lcd_rst>; 62 + avdd-supply = <&ppvar_lcd>; 63 + pp1800-supply = <&v1p8_disp>; 64 + pp3300-supply = <&pp3300_dx_edp>; 65 + backlight = <&backlight>; 66 + rotation = <270>; 67 + 68 + ports { 69 + #address-cells = <1>; 70 + #size-cells = <0>; 71 + port@0 { 72 + reg = <0>; 73 + panel_in: endpoint { 74 + remote-endpoint = <&dsi0_out>; 75 + }; 76 + }; 77 + }; 78 + }; 79 + 80 + ports { 81 + port@1 { 82 + endpoint { 83 + remote-endpoint = <&panel_in>; 84 + data-lanes = <0 1 2 3>; 85 + }; 86 + }; 87 + }; 88 + }; 89 + 90 + &gpio_keys { 91 + status = "okay"; 92 + }; 93 + 94 + &i2c4 { 95 + status = "okay"; 96 + clock-frequency = <400000>; 97 + 98 + ap_ts: touchscreen@10 { 99 + compatible = "hid-over-i2c"; 100 + reg = <0x10>; 101 + pinctrl-names = "default"; 102 + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; 103 + 104 + interrupt-parent = <&tlmm>; 105 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 106 + 107 + post-power-on-delay-ms = <20>; 108 + hid-descr-addr = <0x0001>; 109 + 110 + vdd-supply = <&pp3300_ts>; 111 + }; 112 + }; 113 + 114 + &sdhc_2 { 115 + status = "okay"; 116 + }; 117 + 118 + &pp1800_uf_cam { 119 + status = "okay"; 120 + }; 121 + 122 + &pp1800_wf_cam { 123 + status = "okay"; 124 + }; 125 + 126 + &pp2800_uf_cam { 127 + status = "okay"; 128 + }; 129 + 130 + &pp2800_wf_cam { 131 + status = "okay"; 132 + }; 133 + 134 + /* 135 + * No eDP on this board but it's logically the same signal so just give it 136 + * a new name and assign the proper GPIO. 137 + */ 138 + pp3300_disp_on: &pp3300_dx_edp { 139 + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; 140 + }; 141 + 142 + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ 143 + 144 + /* 145 + * No eDP on this board but it's logically the same signal so just give it 146 + * a new name and assign the proper GPIO. 147 + */ 148 + 149 + tp_en: &en_pp3300_dx_edp { 150 + pinmux { 151 + pins = "gpio67"; 152 + }; 153 + 154 + pinconf { 155 + pins = "gpio67"; 156 + }; 157 + }; 158 + 159 + /* PINCTRL - board-specific pinctrl */ 160 + 161 + &tlmm { 162 + gpio-line-names = "HUB_RST_L", 163 + "AP_RAM_ID0", 164 + "AP_SKU_ID2", 165 + "AP_RAM_ID1", 166 + "", 167 + "AP_RAM_ID2", 168 + "UF_CAM_EN", 169 + "WF_CAM_EN", 170 + "TS_RESET_L", 171 + "TS_INT_L", 172 + "", 173 + "", 174 + "AP_EDP_BKLTEN", 175 + "UF_CAM_MCLK", 176 + "WF_CAM_CLK", 177 + "EDP_BRIJ_I2C_SDA", 178 + "EDP_BRIJ_I2C_SCL", 179 + "UF_CAM_SDA", 180 + "UF_CAM_SCL", 181 + "WF_CAM_SDA", 182 + "WF_CAM_SCL", 183 + "", 184 + "", 185 + "AMP_EN", 186 + "P_SENSOR_INT_L", 187 + "AP_SAR_SENSOR_SDA", 188 + "AP_SAR_SENSOR_SCL", 189 + "", 190 + "HP_IRQ", 191 + "WF_CAM_RST_L", 192 + "UF_CAM_RST_L", 193 + "AP_BRD_ID2", 194 + "", 195 + "AP_BRD_ID0", 196 + "AP_H1_SPI_MISO", 197 + "AP_H1_SPI_MOSI", 198 + "AP_H1_SPI_CLK", 199 + "AP_H1_SPI_CS_L", 200 + "", 201 + "", 202 + "", 203 + "", 204 + "H1_AP_INT_ODL", 205 + "", 206 + "UART_AP_TX_DBG_RX", 207 + "UART_DBG_TX_AP_RX", 208 + "HP_I2C_SDA", 209 + "HP_I2C_SCL", 210 + "FORCED_USB_BOOT", 211 + "", 212 + "", 213 + "AMP_DIN", 214 + "PEN_DET_ODL", 215 + "HP_BCLK", 216 + "HP_LRCLK", 217 + "HP_DOUT", 218 + "HP_DIN", 219 + "HP_MCLK", 220 + "AP_SKU_ID0", 221 + "AP_EC_SPI_MISO", 222 + "AP_EC_SPI_MOSI", 223 + "AP_EC_SPI_CLK", 224 + "AP_EC_SPI_CS_L", 225 + "AP_SPI_CLK", 226 + "AP_SPI_MOSI", 227 + "AP_SPI_MISO", 228 + /* 229 + * AP_FLASH_WP_L is crossystem ABI. Schematics 230 + * call it BIOS_FLASH_WP_L. 231 + */ 232 + "AP_FLASH_WP_L", 233 + "EN_PP3300_DX_EDP", 234 + "AP_SPI_CS0_L", 235 + "SD_CD_ODL", 236 + "", 237 + "", 238 + "", 239 + "", 240 + "", 241 + "UIM2_DATA", 242 + "UIM2_CLK", 243 + "UIM2_RST", 244 + "UIM2_PRESENT_L", 245 + "UIM1_DATA", 246 + "UIM1_CLK", 247 + "UIM1_RST", 248 + "", 249 + "CODEC_PWR_EN", 250 + "HUB_EN", 251 + "", 252 + "PP1800_DISP_ON", 253 + "LCD_RST", 254 + "PPVAR_LCD_EN", 255 + "", 256 + "AP_SKU_ID1", 257 + "AP_RST_REQ", 258 + "", 259 + "AP_BRD_ID1", 260 + "AP_EC_INT_L", 261 + "", 262 + "", 263 + "", 264 + "", 265 + "", 266 + "", 267 + "", 268 + "", 269 + "", 270 + "", 271 + "", 272 + "", 273 + "", 274 + "", 275 + "", 276 + "", 277 + "", 278 + "", 279 + "", 280 + "", 281 + "AP_TS_I2C_SDA", 282 + "AP_TS_I2C_SCL", 283 + "DP_HOT_PLUG_DET", 284 + "EC_IN_RW_ODL"; 285 + 286 + lcd_rst: lcd-rst { 287 + pinmux { 288 + pins = "gpio87"; 289 + function = "gpio"; 290 + }; 291 + 292 + pinconf { 293 + pins = "gpio87"; 294 + drive-strength = <2>; 295 + bias-disable; 296 + }; 297 + }; 298 + 299 + ppvar_lcd_en: ppvar-lcd-en { 300 + pinmux { 301 + pins = "gpio88"; 302 + function = "gpio"; 303 + }; 304 + 305 + pinconf { 306 + pins = "gpio88"; 307 + drive-strength = <2>; 308 + bias-disable; 309 + }; 310 + }; 311 + 312 + pp1800_disp_on: pp1800-disp-on { 313 + pinmux { 314 + pins = "gpio86"; 315 + function = "gpio"; 316 + }; 317 + 318 + pinconf { 319 + pins = "gpio86"; 320 + drive-strength = <2>; 321 + bias-disable; 322 + }; 323 + }; 324 + };
+2
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
··· 8 8 /dts-v1/; 9 9 10 10 #include "sc7180-trogdor.dtsi" 11 + /* Must come after sc7180-trogdor.dtsi to modify cros_ec */ 12 + #include <arm/cros-ec-keyboard.dtsi> 11 13 #include "sc7180-trogdor-ti-sn65dsi86.dtsi" 12 14 13 15 / {
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x10 => 16 8 + * - bits 7..4: Panel ID: 0x1 (BOE) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler-rev0.dtsi" 14 + 15 + / { 16 + model = "Google Wormdingler rev0 BOE panel board"; 17 + compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "boe,tv110c9m-ll3"; 22 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x0 => 0 8 + * - bits 7..4: Panel ID: 0x0 (INX) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler-rev0.dtsi" 14 + 15 + / { 16 + model = "Google Wormdingler rev0 INX panel board"; 17 + compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "innolux,hj110iz-01a"; 22 + };
+53
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "sc7180-trogdor-wormdingler.dtsi" 12 + 13 + &avdd_lcd { 14 + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; 15 + }; 16 + 17 + &panel { 18 + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; 19 + }; 20 + 21 + &v1p8_mipi { 22 + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 23 + }; 24 + 25 + /* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ 26 + &avdd_lcd_en { 27 + pinmux { 28 + pins = "gpio80"; 29 + }; 30 + 31 + pinconf { 32 + pins = "gpio80"; 33 + }; 34 + }; 35 + 36 + &mipi_1800_en { 37 + pinmux { 38 + pins = "gpio81"; 39 + }; 40 + 41 + pinconf { 42 + pins = "gpio81"; 43 + }; 44 + }; 45 + &vdd_reset_1800 { 46 + pinmux { 47 + pins = "gpio76"; 48 + }; 49 + 50 + pinconf { 51 + pins = "gpio76"; 52 + }; 53 + };
+29
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x401 => 1025 8 + * - bits 11..8: Panel ID: 0x4 (BOE) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler-rev1-boe.dts" 14 + 15 + / { 16 + model = "Google Wormdingler rev1+ (BOE, rt5682s)"; 17 + compatible = "google,wormdingler-sku1025", "qcom,sc7180"; 18 + }; 19 + 20 + &alc5682 { 21 + compatible = "realtek,rt5682s"; 22 + realtek,dmic1-clk-pin = <2>; 23 + realtek,dmic-clk-rate-hz = <2048000>; 24 + }; 25 + 26 + &sound { 27 + compatible = "google,sc7180-trogdor"; 28 + model = "sc7180-rt5682s-max98357a-1mic"; 29 + };
+28
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x400 => 1024 8 + * - bits 11..8: Panel ID: 0x4 (BOE) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler.dtsi" 14 + 15 + / { 16 + model = "Google Wormdingler rev1+ BOE panel board"; 17 + compatible = "google,wormdingler-sku1024", "qcom,sc7180"; 18 + }; 19 + 20 + &dsi_phy { 21 + qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; 22 + qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; 23 + qcom,phy-drive-ldo-level = <450>; 24 + }; 25 + 26 + &panel { 27 + compatible = "boe,tv110c9m-ll3"; 28 + };
+29
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x0001 => 1 8 + * - bits 11..8: Panel ID: 0x0 (INX) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler-rev1-inx.dts" 14 + 15 + / { 16 + model = "Google Wormdingler rev1+ (INX, rt5682s)"; 17 + compatible = "google,wormdingler-sku1", "qcom,sc7180"; 18 + }; 19 + 20 + &alc5682 { 21 + compatible = "realtek,rt5682s"; 22 + realtek,dmic1-clk-pin = <2>; 23 + realtek,dmic-clk-rate-hz = <2048000>; 24 + }; 25 + 26 + &sound { 27 + compatible = "google,sc7180-trogdor"; 28 + model = "sc7180-rt5682s-max98357a-1mic"; 29 + };
+22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + * 7 + * SKU: 0x0000 => 0 8 + * - bits 11..8: Panel ID: 0x0 (INX) 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include "sc7180-trogdor-wormdingler.dtsi" 14 + 15 + / { 16 + model = "Google Wormdingler rev1+ INX panel board"; 17 + compatible = "google,wormdingler-sku0", "qcom,sc7180"; 18 + }; 19 + 20 + &panel { 21 + compatible = "innolux,hj110iz-01a"; 22 + };
+412
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Google Wormdingler board device tree source 4 + * 5 + * Copyright 2021 Google LLC. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sc7180-trogdor.dtsi" 11 + 12 + / { 13 + avdd_lcd: avdd-lcd { 14 + compatible = "regulator-fixed"; 15 + regulator-name = "avdd_lcd"; 16 + 17 + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; 18 + enable-active-high; 19 + pinctrl-names = "default"; 20 + pinctrl-0 = <&avdd_lcd_en>; 21 + 22 + vin-supply = <&pp5000_a>; 23 + }; 24 + 25 + avee_lcd: avee-lcd { 26 + compatible = "regulator-fixed"; 27 + regulator-name = "avee_lcd"; 28 + 29 + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; 30 + enable-active-high; 31 + pinctrl-names = "default"; 32 + pinctrl-0 = <&avee_lcd_en>; 33 + 34 + vin-supply = <&pp5000_a>; 35 + }; 36 + 37 + pp1800_ts: 38 + v1p8_mipi: v1p8-mipi { 39 + compatible = "regulator-fixed"; 40 + regulator-name = "v1p8_mipi"; 41 + 42 + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; 43 + enable-active-high; 44 + pinctrl-names = "default"; 45 + pinctrl-0 = <&mipi_1800_en>; 46 + 47 + vin-supply = <&pp3300_a>; 48 + }; 49 + 50 + thermal-zones { 51 + skin_temp_thermal: skin-temp-thermal { 52 + polling-delay-passive = <250>; 53 + polling-delay = <0>; 54 + 55 + thermal-sensors = <&pm6150_adc_tm 1>; 56 + sustainable-power = <574>; 57 + 58 + trips { 59 + skin_temp_alert0: trip-point0 { 60 + temperature = <58000>; 61 + hysteresis = <1000>; 62 + type = "passive"; 63 + }; 64 + 65 + skin_temp_alert1: trip-point1 { 66 + temperature = <62500>; 67 + hysteresis = <1000>; 68 + type = "passive"; 69 + }; 70 + 71 + skin-temp-crit { 72 + temperature = <68000>; 73 + hysteresis = <1000>; 74 + type = "critical"; 75 + }; 76 + }; 77 + 78 + cooling-maps { 79 + map0 { 80 + trip = <&skin_temp_alert0>; 81 + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 82 + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 83 + }; 84 + 85 + map1 { 86 + trip = <&skin_temp_alert1>; 87 + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 88 + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 89 + }; 90 + }; 91 + }; 92 + }; 93 + }; 94 + 95 + &backlight { 96 + pwms = <&cros_ec_pwm 0>; 97 + }; 98 + 99 + &camcc { 100 + status = "okay"; 101 + }; 102 + 103 + &cros_ec { 104 + base_detection: cbas { 105 + compatible = "google,cros-cbas"; 106 + }; 107 + 108 + keyboard-controller { 109 + compatible = "google,cros-ec-keyb-switches"; 110 + }; 111 + }; 112 + 113 + &dsi0 { 114 + 115 + panel: panel@0 { 116 + reg = <0>; 117 + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 118 + pinctrl-names = "default"; 119 + pinctrl-0 = <&vdd_reset_1800>; 120 + avdd-supply = <&avdd_lcd>; 121 + avee-supply = <&avee_lcd>; 122 + pp1800-supply = <&v1p8_mipi>; 123 + pp3300-supply = <&pp3300_dx_edp>; 124 + backlight = <&backlight>; 125 + rotation = <270>; 126 + 127 + ports { 128 + #address-cells = <1>; 129 + #size-cells = <0>; 130 + port@0 { 131 + reg = <0>; 132 + panel_in: endpoint { 133 + remote-endpoint = <&dsi0_out>; 134 + }; 135 + }; 136 + }; 137 + }; 138 + 139 + ports { 140 + port@1 { 141 + endpoint { 142 + remote-endpoint = <&panel_in>; 143 + data-lanes = <0 1 2 3>; 144 + }; 145 + }; 146 + }; 147 + }; 148 + 149 + &i2c4 { 150 + status = "okay"; 151 + clock-frequency = <400000>; 152 + 153 + ap_ts: touchscreen@1 { 154 + compatible = "hid-over-i2c"; 155 + reg = <0x01>; 156 + pinctrl-names = "default"; 157 + pinctrl-0 = <&ts_int_l>; 158 + 159 + interrupt-parent = <&tlmm>; 160 + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 161 + 162 + post-power-on-delay-ms = <70>; 163 + hid-descr-addr = <0x0001>; 164 + 165 + vdd-supply = <&pp3300_ts>; 166 + vddl-supply = <&pp1800_ts>; 167 + }; 168 + }; 169 + 170 + &pm6150_adc { 171 + skin-temp-thermistor@4d { 172 + reg = <ADC5_AMUX_THM1_100K_PU>; 173 + qcom,ratiometric; 174 + qcom,hw-settle-time = <200>; 175 + }; 176 + }; 177 + 178 + &pm6150_adc_tm { 179 + status = "okay"; 180 + 181 + skin-temp-thermistor@1 { 182 + reg = <1>; 183 + io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; 184 + qcom,ratiometric; 185 + qcom,hw-settle-time-us = <200>; 186 + }; 187 + }; 188 + 189 + &pp1800_uf_cam { 190 + status = "okay"; 191 + }; 192 + 193 + &pp1800_wf_cam { 194 + status = "okay"; 195 + }; 196 + 197 + &pp2800_uf_cam { 198 + status = "okay"; 199 + }; 200 + 201 + &pp2800_wf_cam { 202 + status = "okay"; 203 + }; 204 + 205 + &wifi { 206 + qcom,ath10k-calibration-variant = "GO_WORMDINGLER"; 207 + }; 208 + 209 + /* 210 + * No eDP on this board but it's logically the same signal so just give it 211 + * a new name and assign the proper GPIO. 212 + */ 213 + pp3300_disp_on: &pp3300_dx_edp { 214 + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; 215 + }; 216 + 217 + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ 218 + 219 + /* 220 + * No eDP on this board but it's logically the same signal so just give it 221 + * a new name and assign the proper GPIO. 222 + */ 223 + 224 + tp_en: &en_pp3300_dx_edp { 225 + pinmux { 226 + pins = "gpio85"; 227 + }; 228 + 229 + pinconf { 230 + pins = "gpio85"; 231 + }; 232 + }; 233 + 234 + /* PINCTRL - board-specific pinctrl */ 235 + 236 + &tlmm { 237 + gpio-line-names = "HUB_RST_L", 238 + "AP_RAM_ID0", 239 + "AP_SKU_ID2", 240 + "AP_RAM_ID1", 241 + "", 242 + "AP_RAM_ID2", 243 + "UF_CAM_EN", 244 + "WF_CAM_EN", 245 + "TS_RESET_L", 246 + "TS_INT_L", 247 + "", 248 + "", 249 + "AP_EDP_BKLTEN", 250 + "UF_CAM_MCLK", 251 + "WF_CAM_CLK", 252 + "", 253 + "", 254 + "UF_CAM_SDA", 255 + "UF_CAM_SCL", 256 + "WF_CAM_SDA", 257 + "WF_CAM_SCL", 258 + "AVEE_LCD_EN", 259 + "", 260 + "AMP_EN", 261 + "", 262 + "", 263 + "", 264 + "", 265 + "HP_IRQ", 266 + "WF_CAM_RST_L", 267 + "UF_CAM_RST_L", 268 + "AP_BRD_ID2", 269 + "", 270 + "AP_BRD_ID0", 271 + "AP_H1_SPI_MISO", 272 + "AP_H1_SPI_MOSI", 273 + "AP_H1_SPI_CLK", 274 + "AP_H1_SPI_CS_L", 275 + "BT_UART_CTS", 276 + "BT_UART_RTS", 277 + "BT_UART_TXD", 278 + "BT_UART_RXD", 279 + "H1_AP_INT_ODL", 280 + "", 281 + "UART_AP_TX_DBG_RX", 282 + "UART_DBG_TX_AP_RX", 283 + "HP_I2C_SDA", 284 + "HP_I2C_SCL", 285 + "FORCED_USB_BOOT", 286 + "AMP_BCLK", 287 + "AMP_LRCLK", 288 + "AMP_DIN", 289 + "", 290 + "HP_BCLK", 291 + "HP_LRCLK", 292 + "HP_DOUT", 293 + "HP_DIN", 294 + "HP_MCLK", 295 + "AP_SKU_ID0", 296 + "AP_EC_SPI_MISO", 297 + "AP_EC_SPI_MOSI", 298 + "AP_EC_SPI_CLK", 299 + "AP_EC_SPI_CS_L", 300 + "AP_SPI_CLK", 301 + "AP_SPI_MOSI", 302 + "AP_SPI_MISO", 303 + /* 304 + * AP_FLASH_WP_L is crossystem ABI. Schematics 305 + * call it BIOS_FLASH_WP_L. 306 + */ 307 + "AP_FLASH_WP_L", 308 + "", 309 + "AP_SPI_CS0_L", 310 + "", 311 + "", 312 + "", 313 + "", 314 + "WLAN_SW_CTRL", 315 + "", 316 + "REPORT_E", 317 + "", 318 + "ID0", 319 + "", 320 + "ID1", 321 + "", 322 + "", 323 + "", 324 + "CODEC_PWR_EN", 325 + "HUB_EN", 326 + "TP_EN", 327 + "MIPI_1.8V_EN", 328 + "VDD_RESET_1.8V", 329 + "AVDD_LCD_EN", 330 + "", 331 + "AP_SKU_ID1", 332 + "AP_RST_REQ", 333 + "", 334 + "AP_BRD_ID1", 335 + "AP_EC_INT_L", 336 + "SDM_GRFC_3", 337 + "", 338 + "", 339 + "BOOT_CONFIG_4", 340 + "BOOT_CONFIG_2", 341 + "", 342 + "", 343 + "", 344 + "", 345 + "", 346 + "", 347 + "", 348 + "BOOT_CONFIG_3", 349 + "WCI2_LTE_COEX_TXD", 350 + "WCI2_LTE_COEX_RXD", 351 + "", 352 + "", 353 + "", 354 + "", 355 + "FORCED_USB_BOOT_POL", 356 + "AP_TS_PEN_I2C_SDA", 357 + "AP_TS_PEN_I2C_SCL", 358 + "DP_HOT_PLUG_DET", 359 + "EC_IN_RW_ODL"; 360 + 361 + avdd_lcd_en: avdd-lcd-en { 362 + pinmux { 363 + pins = "gpio88"; 364 + function = "gpio"; 365 + }; 366 + 367 + pinconf { 368 + pins = "gpio88"; 369 + drive-strength = <2>; 370 + bias-disable; 371 + }; 372 + }; 373 + 374 + avee_lcd_en: avee-lcd-en { 375 + pinmux { 376 + pins = "gpio21"; 377 + function = "gpio"; 378 + }; 379 + 380 + pinconf { 381 + pins = "gpio21"; 382 + drive-strength = <2>; 383 + bias-disable; 384 + }; 385 + }; 386 + 387 + mipi_1800_en: mipi-1800-en { 388 + pinmux { 389 + pins = "gpio86"; 390 + function = "gpio"; 391 + }; 392 + 393 + pinconf { 394 + pins = "gpio86"; 395 + drive-strength = <2>; 396 + bias-disable; 397 + }; 398 + }; 399 + 400 + vdd_reset_1800: vdd-reset-1800 { 401 + pinmux { 402 + pins = "gpio87"; 403 + function = "gpio"; 404 + }; 405 + 406 + pinconf { 407 + pins = "gpio87"; 408 + drive-strength = <2>; 409 + bias-disable; 410 + }; 411 + }; 412 + };
+4 -4
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/input/gpio-keys.h> 10 10 #include <dt-bindings/input/input.h> 11 + #include <dt-bindings/leds/common.h> 11 12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 12 13 #include <dt-bindings/sound/sc7180-lpass.h> 13 14 ··· 44 43 */ 45 44 46 45 /delete-node/ &hyp_mem; 46 + /delete-node/ &ipa_fw_mem; 47 47 /delete-node/ &xbl_mem; 48 48 /delete-node/ &aop_mem; 49 49 /delete-node/ &sec_apps_mem; ··· 332 330 pinctrl-names = "default"; 333 331 pinctrl-0 = <&pen_pdct_l>; 334 332 335 - pen_insert: pen-insert { 333 + pen_insert: switch-pen-insert { 336 334 label = "Pen Insert"; 337 335 338 336 /* Insert = low, eject = high */ ··· 357 355 keyboard_backlight: keyboard-backlight { 358 356 status = "disabled"; 359 357 label = "cros_ec::kbd_backlight"; 358 + function = LED_FUNCTION_KBD_BACKLIGHT; 360 359 pwms = <&cros_ec_pwm 0>; 361 360 max-brightness = <1023>; 362 361 }; ··· 815 812 pinctrl-names = "default"; 816 813 pinctrl-0 = <&dp_hot_plug_det>; 817 814 data-lanes = <0 1>; 818 - vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; 819 - vdda-0p9-supply = <&vdda_usb_ss_dp_core>; 820 815 }; 821 816 822 817 &pm6150_adc { ··· 904 903 }; 905 904 }; 906 905 907 - #include <arm/cros-ec-keyboard.dtsi> 908 906 #include <arm/cros-ec-sbs.dtsi> 909 907 910 908 &uart3 {
+35 -40
arch/arm64/boot/dts/qcom/sc7180.dtsi
··· 398 398 }; 399 399 }; 400 400 401 - cpu0_opp_table: cpu0_opp_table { 401 + cpu0_opp_table: opp-table-cpu0 { 402 402 compatible = "operating-points-v2"; 403 403 opp-shared; 404 404 ··· 453 453 }; 454 454 }; 455 455 456 - cpu6_opp_table: cpu6_opp_table { 456 + cpu6_opp_table: opp-table-cpu6 { 457 457 compatible = "operating-points-v2"; 458 458 opp-shared; 459 459 ··· 693 693 }; 694 694 }; 695 695 696 - sdhc_1: sdhci@7c4000 { 696 + sdhc_1: mmc@7c4000 { 697 697 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 698 698 reg = <0 0x7c4000 0 0x1000>, 699 699 <0 0x07c5000 0 0x1000>; ··· 704 704 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 705 705 interrupt-names = "hc_irq", "pwr_irq"; 706 706 707 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 708 - <&gcc GCC_SDCC1_AHB_CLK>, 707 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 708 + <&gcc GCC_SDCC1_APPS_CLK>, 709 709 <&rpmhcc RPMH_CXO_CLK>; 710 - clock-names = "core", "iface", "xo"; 710 + clock-names = "iface", "core", "xo"; 711 711 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 712 712 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 713 713 interconnect-names = "sdhc-ddr","cpu-sdhc"; ··· 725 725 726 726 status = "disabled"; 727 727 728 - sdhc1_opp_table: sdhc1-opp-table { 728 + sdhc1_opp_table: opp-table { 729 729 compatible = "operating-points-v2"; 730 730 731 731 opp-100000000 { ··· 744 744 }; 745 745 }; 746 746 747 - qup_opp_table: qup-opp-table { 747 + qup_opp_table: opp-table-qup { 748 748 compatible = "operating-points-v2"; 749 749 750 750 opp-75000000 { ··· 2048 2048 }; 2049 2049 2050 2050 gmu: gmu@506a000 { 2051 - compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2051 + compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2052 2052 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2053 2053 <0 0x0b490000 0 0x10000>; 2054 2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; ··· 2578 2578 }; 2579 2579 }; 2580 2580 2581 - sdhc_2: sdhci@8804000 { 2581 + sdhc_2: mmc@8804000 { 2582 2582 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2583 2583 reg = <0 0x08804000 0 0x1000>; 2584 2584 ··· 2587 2587 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2588 2588 interrupt-names = "hc_irq", "pwr_irq"; 2589 2589 2590 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2591 - <&gcc GCC_SDCC2_AHB_CLK>, 2590 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2591 + <&gcc GCC_SDCC2_APPS_CLK>, 2592 2592 <&rpmhcc RPMH_CXO_CLK>; 2593 - clock-names = "core", "iface", "xo"; 2593 + clock-names = "iface", "core", "xo"; 2594 2594 2595 2595 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2596 2596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; ··· 2602 2602 2603 2603 status = "disabled"; 2604 2604 2605 - sdhc2_opp_table: sdhc2-opp-table { 2605 + sdhc2_opp_table: opp-table { 2606 2606 compatible = "operating-points-v2"; 2607 2607 2608 2608 opp-100000000 { ··· 2621 2621 }; 2622 2622 }; 2623 2623 2624 - qspi_opp_table: qspi-opp-table { 2624 + qspi_opp_table: opp-table-qspi { 2625 2625 compatible = "operating-points-v2"; 2626 2626 2627 2627 opp-75000000 { ··· 2825 2825 compatible = "venus-encoder"; 2826 2826 }; 2827 2827 2828 - venus_opp_table: venus-opp-table { 2828 + venus_opp_table: opp-table { 2829 2829 compatible = "operating-points-v2"; 2830 2830 2831 2831 opp-150000000 { ··· 2896 2896 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2897 2897 clock-names = "iface", "ahb", "core"; 2898 2898 2899 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2900 - assigned-clock-rates = <300000000>; 2901 - 2902 2899 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2903 2900 interrupt-controller; 2904 2901 #interrupt-cells = <1>; ··· 2925 2928 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2926 2929 clock-names = "bus", "iface", "rot", "lut", "core", 2927 2930 "vsync"; 2928 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2929 - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2931 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2930 2932 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2931 2933 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2932 - assigned-clock-rates = <300000000>, 2933 - <19200000>, 2934 + assigned-clock-rates = <19200000>, 2934 2935 <19200000>, 2935 2936 <19200000>; 2936 2937 operating-points-v2 = <&mdp_opp_table>; ··· 2958 2963 }; 2959 2964 }; 2960 2965 2961 - mdp_opp_table: mdp-opp-table { 2966 + mdp_opp_table: opp-table { 2962 2967 compatible = "operating-points-v2"; 2963 2968 2964 2969 opp-200000000 { ··· 3037 3042 }; 3038 3043 }; 3039 3044 3040 - dsi_opp_table: dsi-opp-table { 3045 + dsi_opp_table: opp-table { 3041 3046 compatible = "operating-points-v2"; 3042 3047 3043 3048 opp-187500000 { ··· 3210 3215 }; 3211 3216 3212 3217 aoss_qmp: power-controller@c300000 { 3213 - compatible = "qcom,sc7180-aoss-qmp"; 3218 + compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3214 3219 reg = <0 0x0c300000 0 0x400>; 3215 3220 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3216 3221 mboxes = <&apss_shared 0>; ··· 3242 3247 cell-index = <0>; 3243 3248 }; 3244 3249 3245 - imem@146aa000 { 3246 - compatible = "simple-mfd"; 3250 + sram@146aa000 { 3251 + compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3247 3252 reg = <0 0x146aa000 0 0x2000>; 3248 3253 3249 3254 #address-cells = <1>; ··· 3379 3384 }; 3380 3385 3381 3386 timer@17c20000{ 3382 - #address-cells = <2>; 3383 - #size-cells = <2>; 3384 - ranges; 3387 + #address-cells = <1>; 3388 + #size-cells = <1>; 3389 + ranges = <0 0 0 0x20000000>; 3385 3390 compatible = "arm,armv7-timer-mem"; 3386 3391 reg = <0 0x17c20000 0 0x1000>; 3387 3392 ··· 3389 3394 frame-number = <0>; 3390 3395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3391 3396 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3392 - reg = <0 0x17c21000 0 0x1000>, 3393 - <0 0x17c22000 0 0x1000>; 3397 + reg = <0x17c21000 0x1000>, 3398 + <0x17c22000 0x1000>; 3394 3399 }; 3395 3400 3396 3401 frame@17c23000 { 3397 3402 frame-number = <1>; 3398 3403 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3399 - reg = <0 0x17c23000 0 0x1000>; 3404 + reg = <0x17c23000 0x1000>; 3400 3405 status = "disabled"; 3401 3406 }; 3402 3407 3403 3408 frame@17c25000 { 3404 3409 frame-number = <2>; 3405 3410 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3406 - reg = <0 0x17c25000 0 0x1000>; 3411 + reg = <0x17c25000 0x1000>; 3407 3412 status = "disabled"; 3408 3413 }; 3409 3414 3410 3415 frame@17c27000 { 3411 3416 frame-number = <3>; 3412 3417 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3413 - reg = <0 0x17c27000 0 0x1000>; 3418 + reg = <0x17c27000 0x1000>; 3414 3419 status = "disabled"; 3415 3420 }; 3416 3421 3417 3422 frame@17c29000 { 3418 3423 frame-number = <4>; 3419 3424 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3420 - reg = <0 0x17c29000 0 0x1000>; 3425 + reg = <0x17c29000 0x1000>; 3421 3426 status = "disabled"; 3422 3427 }; 3423 3428 3424 3429 frame@17c2b000 { 3425 3430 frame-number = <5>; 3426 3431 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3427 - reg = <0 0x17c2b000 0 0x1000>; 3432 + reg = <0x17c2b000 0x1000>; 3428 3433 status = "disabled"; 3429 3434 }; 3430 3435 3431 3436 frame@17c2d000 { 3432 3437 frame-number = <6>; 3433 3438 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3434 - reg = <0 0x17c2d000 0 0x1000>; 3439 + reg = <0x17c2d000 0x1000>; 3435 3440 status = "disabled"; 3436 3441 }; 3437 3442 }; ··· 3579 3584 compatible = "qcom,sc7180-lpass-cpu"; 3580 3585 3581 3586 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3582 - reg-names = "lpass-hdmiif", "lpass-lpaif"; 3587 + reg-names = "lpass-hdmiif", "lpass-lpaif"; 3583 3588 3584 3589 iommus = <&apps_smmu 0x1020 0>, 3585 3590 <&apps_smmu 0x1021 0>,
+16
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
··· 88 88 status = "okay"; 89 89 compatible = "qcom,sc7280-mss-pil"; 90 90 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; 91 + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 91 92 memory-region = <&mba_mem>, <&mpss_mem>; 93 + firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", 94 + "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; 95 + }; 96 + 97 + &remoteproc_wpss { 98 + status = "okay"; 99 + firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 92 100 }; 93 101 94 102 /* Increase the size from 2.5MB to 8MB */ 95 103 &rmtfs_mem { 96 104 reg = <0x0 0x9c900000 0x0 0x800000>; 105 + }; 106 + 107 + &wifi { 108 + status = "okay"; 109 + 110 + wifi-firmware { 111 + iommus = <&apps_smmu 0x1c02 0x1>; 112 + }; 97 113 };
+20
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * sc7280 device tree source for boards using Max98360 and wcd9385 codec 4 + * 5 + * Copyright (c) 2022, The Linux Foundation. All rights reserved. 6 + */ 7 + 8 + &mi2s1_data0 { 9 + drive-strength = <6>; 10 + bias-disable; 11 + }; 12 + 13 + &mi2s1_sclk { 14 + drive-strength = <6>; 15 + bias-disable; 16 + }; 17 + 18 + &mi2s1_ws { 19 + drive-strength = <6>; 20 + };
+73
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
··· 8 8 /dts-v1/; 9 9 10 10 #include "sc7280-herobrine.dtsi" 11 + #include "sc7280-herobrine-audio-wcd9385.dtsi" 11 12 12 13 / { 13 14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; ··· 135 134 status = "okay"; 136 135 }; 137 136 137 + /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 138 + 139 + /* 140 + * This pin goes to the display panel but then doesn't actually do anything 141 + * on the panel itself (it doesn't connect to the touchscreen controller). 142 + * We'll set a pullup here just to park the line. 143 + */ 144 + &ts_rst_conn { 145 + bias-pull-up; 146 + }; 147 + 138 148 /* PINCTRL - BOARD-SPECIFIC */ 139 149 140 150 /* ··· 155 143 * - If a pin is totally internal to Qcard then it gets Qcard name. 156 144 * - If a pin is not hooked up on Qcard, it gets no name. 157 145 */ 146 + &lpass_dmic01_clk { 147 + drive-strength = <8>; 148 + bias-disable; 149 + }; 150 + 151 + &lpass_dmic01_clk_sleep { 152 + drive-strength = <2>; 153 + }; 154 + 155 + &lpass_dmic01_data { 156 + bias-pull-down; 157 + }; 158 + 159 + &lpass_dmic23_clk { 160 + drive-strength = <8>; 161 + bias-disable; 162 + }; 163 + 164 + &lpass_dmic23_clk_sleep { 165 + drive-strength = <2>; 166 + }; 167 + 168 + &lpass_dmic23_data { 169 + bias-pull-down; 170 + }; 171 + 172 + &lpass_rx_swr_clk { 173 + drive-strength = <2>; 174 + slew-rate = <1>; 175 + bias-disable; 176 + }; 177 + 178 + &lpass_rx_swr_clk_sleep { 179 + bias-pull-down; 180 + }; 181 + 182 + &lpass_rx_swr_data { 183 + drive-strength = <2>; 184 + slew-rate = <1>; 185 + bias-bus-hold; 186 + }; 187 + 188 + &lpass_rx_swr_data_sleep { 189 + bias-pull-down; 190 + }; 191 + 192 + &lpass_tx_swr_clk { 193 + drive-strength = <2>; 194 + slew-rate = <1>; 195 + bias-disable; 196 + }; 197 + 198 + &lpass_tx_swr_clk_sleep { 199 + bias-pull-down; 200 + }; 201 + 202 + &lpass_tx_swr_data { 203 + drive-strength = <2>; 204 + slew-rate = <1>; 205 + bias-bus-hold; 206 + }; 158 207 159 208 &pm8350c_gpios { 160 209 gpio-line-names = "FLASH_STROBE_1", /* 1 */
+11
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
··· 128 128 status = "okay"; 129 129 }; 130 130 131 + /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 132 + 133 + /* 134 + * This pin goes to the display panel but then doesn't actually do anything 135 + * on the panel itself (it doesn't connect to the touchscreen controller). 136 + * We'll set a pullup here just to park the line. 137 + */ 138 + &ts_rst_conn { 139 + bias-pull-up; 140 + }; 141 + 131 142 /* PINCTRL - BOARD-SPECIFIC */ 132 143 133 144 /*
+29
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts
··· 46 46 }; 47 47 }; 48 48 49 + ts_i2c: &i2c13 { 50 + status = "okay"; 51 + clock-frequency = <400000>; 52 + 53 + ap_ts: touchscreen@10 { 54 + compatible = "elan,ekth6915"; 55 + reg = <0x10>; 56 + pinctrl-names = "default"; 57 + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; 58 + 59 + interrupt-parent = <&tlmm>; 60 + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; 61 + 62 + reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; 63 + 64 + vcc33-supply = <&ts_avdd>; 65 + }; 66 + }; 67 + 49 68 &ap_sar_sensor_i2c { 50 69 status = "okay"; 51 70 }; ··· 95 76 status = "okay"; 96 77 }; 97 78 79 + &pwmleds { 80 + status = "okay"; 81 + }; 82 + 98 83 /* For eMMC */ 99 84 &sdhc_1 { 100 85 status = "okay"; 86 + }; 87 + 88 + /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 89 + 90 + &ts_rst_conn { 91 + bias-disable; 101 92 }; 102 93 103 94 /* PINCTRL - BOARD-SPECIFIC */
+18 -4
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
··· 15 15 16 16 #include <dt-bindings/input/gpio-keys.h> 17 17 #include <dt-bindings/input/input.h> 18 + #include <dt-bindings/leds/common.h> 18 19 19 20 #include "sc7280-qcard.dtsi" 20 21 #include "sc7280-chrome-common.dtsi" ··· 296 295 297 296 /* BOARD-SPECIFIC TOP LEVEL NODES */ 298 297 299 - pwmleds { 298 + pwmleds: pwmleds { 300 299 compatible = "pwm-leds"; 301 300 status = "disabled"; 302 301 keyboard_backlight: keyboard-backlight { 303 - status = "disabled"; 304 302 label = "cros_ec::kbd_backlight"; 303 + function = LED_FUNCTION_KBD_BACKLIGHT; 305 304 pwms = <&cros_ec_pwm 0>; 306 305 max-brightness = <1023>; 307 306 }; ··· 389 388 390 389 vdd-supply = <&pp1800_prox>; 391 390 392 - label = "proximity-wifi-lte0"; 391 + label = "proximity-wifi_cellular-0"; 393 392 status = "disabled"; 394 393 }; 395 394 ··· 405 404 406 405 vdd-supply = <&pp1800_prox>; 407 406 408 - label = "proximity-wifi-lte1"; 407 + label = "proximity-wifi_cellular-1"; 409 408 status = "disabled"; 410 409 }; 411 410 }; ··· 428 427 429 428 &mdss { 430 429 status = "okay"; 430 + }; 431 + 432 + &mdss_dp { 433 + status = "okay"; 434 + pinctrl-names = "default"; 435 + pinctrl-0 = <&dp_hot_plug_det>; 436 + data-lanes = <0 1>; 437 + vdda-1p2-supply = <&vdd_a_usbssdp_0_1p2>; 438 + vdda-0p9-supply = <&vdd_a_usbssdp_0_core>; 431 439 }; 432 440 433 441 &mdss_mdp { ··· 484 474 vqmmc-supply = <&ppvar_l6c>; 485 475 486 476 cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; 477 + }; 478 + 479 + &spi_flash { 480 + spi-max-frequency = <50000000>; 487 481 }; 488 482 489 483 /* Fingerprint, enabled on a per-board basis */
+78 -13
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
··· 27 27 pinctrl-names = "default"; 28 28 pinctrl-0 = <&key_vol_up_default>; 29 29 30 - volume-up { 30 + key-volume-up { 31 31 label = "volume_up"; 32 32 gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; 33 33 linux,input-type = <1>; ··· 367 367 bias-disable; 368 368 }; 369 369 370 + &lpass_dmic01_clk { 371 + drive-strength = <8>; 372 + bias-disable; 373 + }; 374 + 375 + &lpass_dmic01_clk_sleep { 376 + drive-strength = <2>; 377 + }; 378 + 379 + &lpass_dmic01_data { 380 + bias-pull-down; 381 + }; 382 + 383 + &lpass_dmic23_clk { 384 + drive-strength = <8>; 385 + bias-disable; 386 + }; 387 + 388 + &lpass_dmic23_clk_sleep { 389 + drive-strength = <2>; 390 + }; 391 + 392 + &lpass_dmic23_data { 393 + bias-pull-down; 394 + }; 395 + 396 + &lpass_rx_swr_clk { 397 + drive-strength = <2>; 398 + slew-rate = <1>; 399 + bias-disable; 400 + }; 401 + 402 + &lpass_rx_swr_clk_sleep { 403 + bias-pull-down; 404 + }; 405 + 406 + &lpass_rx_swr_data { 407 + drive-strength = <2>; 408 + slew-rate = <1>; 409 + bias-bus-hold; 410 + }; 411 + 412 + &lpass_rx_swr_data_sleep { 413 + bias-pull-down; 414 + }; 415 + 416 + &lpass_tx_swr_clk { 417 + drive-strength = <2>; 418 + slew-rate = <1>; 419 + bias-disable; 420 + }; 421 + 422 + &lpass_tx_swr_clk_sleep { 423 + bias-pull-down; 424 + }; 425 + 426 + &lpass_tx_swr_data { 427 + drive-strength = <2>; 428 + slew-rate = <1>; 429 + bias-bus-hold; 430 + }; 431 + 432 + &mi2s1_data0 { 433 + drive-strength = <6>; 434 + bias-disable; 435 + }; 436 + 437 + &mi2s1_sclk { 438 + drive-strength = <6>; 439 + bias-disable; 440 + }; 441 + 442 + &mi2s1_ws { 443 + drive-strength = <6>; 444 + }; 445 + 370 446 &pm7325_gpios { 371 - key_vol_up_default: key-vol-up-default { 447 + key_vol_up_default: key-vol-up-state { 372 448 pins = "gpio6"; 373 449 function = "normal"; 374 450 input-enable; ··· 634 558 pins = "gpio86"; 635 559 function = "gpio"; 636 560 bias-pull-down; 637 - }; 638 - }; 639 - 640 - &remoteproc_wpss { 641 - status = "okay"; 642 - }; 643 - 644 - &wifi { 645 - status = "okay"; 646 - wifi-firmware { 647 - iommus = <&apps_smmu 0x1c02 0x1>; 648 561 }; 649 562 };
+8 -3
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
··· 123 123 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 124 124 }; 125 125 126 + vreg_l17b_1p8: ldo17 { 127 + regulator-min-microvolt = <1700000>; 128 + regulator-max-microvolt = <1900000>; 129 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 130 + }; 131 + 126 132 vdd_px_wcd9385: 127 133 vdd_txrx: 128 134 vddpx_0: ··· 523 517 */ 524 518 525 519 &pm8350c_gpios { 526 - pmic_edp_bl_en: pmic-edp-bl-en { 520 + pmic_edp_bl_en: pmic-edp-bl-en-state { 527 521 pins = "gpio7"; 528 522 function = "normal"; 529 523 bias-disable; ··· 533 527 output-low; 534 528 }; 535 529 536 - pmic_edp_bl_pwm: pmic-edp-bl-pwm { 530 + pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { 537 531 pins = "gpio8"; 538 532 function = "func1"; 539 533 bias-disable; ··· 610 604 ts_rst_conn: ts-rst-conn { 611 605 pins = "gpio54"; 612 606 function = "gpio"; 613 - bias-pull-up; 614 607 drive-strength = <2>; 615 608 }; 616 609 };
+184 -57
arch/arm64/boot/dts/qcom/sc7280.dtsi
··· 417 417 }; 418 418 }; 419 419 420 - cpu0_opp_table: cpu0-opp-table { 420 + cpu0_opp_table: opp-table-cpu0 { 421 421 compatible = "operating-points-v2"; 422 422 opp-shared; 423 423 ··· 477 477 }; 478 478 }; 479 479 480 - cpu4_opp_table: cpu4-opp-table { 480 + cpu4_opp_table: opp-table-cpu4 { 481 481 compatible = "operating-points-v2"; 482 482 opp-shared; 483 483 ··· 547 547 }; 548 548 }; 549 549 550 - cpu7_opp_table: cpu7-opp-table { 550 + cpu7_opp_table: opp-table-cpu7 { 551 551 compatible = "operating-points-v2"; 552 552 opp-shared; 553 553 ··· 763 763 method = "smc"; 764 764 }; 765 765 766 - qspi_opp_table: qspi-opp-table { 766 + qspi_opp_table: opp-table-qspi { 767 767 compatible = "operating-points-v2"; 768 768 769 769 opp-75000000 { ··· 787 787 }; 788 788 }; 789 789 790 - qup_opp_table: qup-opp-table { 790 + qup_opp_table: opp-table-qup { 791 791 compatible = "operating-points-v2"; 792 792 793 793 opp-75000000 { ··· 818 818 reg = <0 0x00100000 0 0x1f0000>; 819 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 820 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 821 - <0>, <&pcie1_lane 0>, 821 + <0>, <&pcie1_lane>, 822 822 <0>, <0>, <0>, <0>; 823 823 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 824 824 "pcie_0_pipe_clk", "pcie_1_pipe_clk", ··· 857 857 }; 858 858 }; 859 859 860 - sdhc_1: sdhci@7c4000 { 860 + sdhc_1: mmc@7c4000 { 861 861 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 862 862 pinctrl-names = "default", "sleep"; 863 863 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; ··· 873 873 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 874 874 interrupt-names = "hc_irq", "pwr_irq"; 875 875 876 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 877 - <&gcc GCC_SDCC1_AHB_CLK>, 876 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 877 + <&gcc GCC_SDCC1_APPS_CLK>, 878 878 <&rpmhcc RPMH_CXO_CLK>; 879 - clock-names = "core", "iface", "xo"; 879 + clock-names = "iface", "core", "xo"; 880 880 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 881 881 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 882 882 interconnect-names = "sdhc-ddr","cpu-sdhc"; ··· 2035 2035 2036 2036 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2037 2037 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2038 - <&pcie1_lane 0>, 2038 + <&pcie1_lane>, 2039 2039 <&rpmhcc RPMH_CXO_CLK>, 2040 2040 <&gcc GCC_PCIE_1_AUX_CLK>, 2041 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, ··· 2110 2110 clock-names = "pipe0"; 2111 2111 2112 2112 #phy-cells = <0>; 2113 - #clock-cells = <1>; 2113 + #clock-cells = <0>; 2114 2114 clock-output-names = "pcie_1_pipe_clk"; 2115 2115 }; 2116 2116 }; ··· 2201 2201 lpasscore: clock-controller@3900000 { 2202 2202 compatible = "qcom,sc7280-lpasscorecc"; 2203 2203 reg = <0 0x03900000 0 0x50000>; 2204 - clocks = <&rpmhcc RPMH_CXO_CLK>; 2204 + clocks = <&rpmhcc RPMH_CXO_CLK>; 2205 2205 clock-names = "bi_tcxo"; 2206 2206 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2207 2207 #clock-cells = <1>; ··· 2222 2222 compatible = "qcom,sc7280-lpass-ag-noc"; 2223 2223 #interconnect-cells = <2>; 2224 2224 qcom,bcm-voters = <&apps_bcm_voter>; 2225 + }; 2226 + 2227 + lpass_tlmm: pinctrl@33c0000 { 2228 + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2229 + reg = <0 0x033c0000 0x0 0x20000>, 2230 + <0 0x03550000 0x0 0x10000>; 2231 + qcom,adsp-bypass-mode; 2232 + gpio-controller; 2233 + #gpio-cells = <2>; 2234 + gpio-ranges = <&lpass_tlmm 0 0 15>; 2235 + 2236 + #clock-cells = <1>; 2237 + 2238 + lpass_dmic01_clk: dmic01-clk { 2239 + pins = "gpio6"; 2240 + function = "dmic1_clk"; 2241 + }; 2242 + 2243 + lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2244 + pins = "gpio6"; 2245 + function = "dmic1_clk"; 2246 + }; 2247 + 2248 + lpass_dmic01_data: dmic01-data { 2249 + pins = "gpio7"; 2250 + function = "dmic1_data"; 2251 + }; 2252 + 2253 + lpass_dmic01_data_sleep: dmic01-data-sleep { 2254 + pins = "gpio7"; 2255 + function = "dmic1_data"; 2256 + }; 2257 + 2258 + lpass_dmic23_clk: dmic23-clk { 2259 + pins = "gpio8"; 2260 + function = "dmic2_clk"; 2261 + }; 2262 + 2263 + lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2264 + pins = "gpio8"; 2265 + function = "dmic2_clk"; 2266 + }; 2267 + 2268 + lpass_dmic23_data: dmic23-data { 2269 + pins = "gpio9"; 2270 + function = "dmic2_data"; 2271 + }; 2272 + 2273 + lpass_dmic23_data_sleep: dmic23-data-sleep { 2274 + pins = "gpio9"; 2275 + function = "dmic2_data"; 2276 + }; 2277 + 2278 + lpass_rx_swr_clk: rx-swr-clk { 2279 + pins = "gpio3"; 2280 + function = "swr_rx_clk"; 2281 + }; 2282 + 2283 + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2284 + pins = "gpio3"; 2285 + function = "swr_rx_clk"; 2286 + }; 2287 + 2288 + lpass_rx_swr_data: rx-swr-data { 2289 + pins = "gpio4", "gpio5"; 2290 + function = "swr_rx_data"; 2291 + }; 2292 + 2293 + lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2294 + pins = "gpio4", "gpio5"; 2295 + function = "swr_rx_data"; 2296 + }; 2297 + 2298 + lpass_tx_swr_clk: tx-swr-clk { 2299 + pins = "gpio0"; 2300 + function = "swr_tx_clk"; 2301 + }; 2302 + 2303 + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2304 + pins = "gpio0"; 2305 + function = "swr_tx_clk"; 2306 + }; 2307 + 2308 + lpass_tx_swr_data: tx-swr-data { 2309 + pins = "gpio1", "gpio2", "gpio14"; 2310 + function = "swr_tx_data"; 2311 + }; 2312 + 2313 + lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2314 + pins = "gpio1", "gpio2", "gpio14"; 2315 + function = "swr_tx_data"; 2316 + }; 2225 2317 }; 2226 2318 2227 2319 gpu: gpu@3d00000 { ··· 2397 2305 }; 2398 2306 2399 2307 gmu: gmu@3d6a000 { 2400 - compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2308 + compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2401 2309 reg = <0 0x03d6a000 0 0x34000>, 2402 2310 <0 0x3de0000 0 0x10000>, 2403 2311 <0 0x0b290000 0 0x10000>; ··· 2405 2313 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2406 2314 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2407 2315 interrupt-names = "hfi", "gmu"; 2408 - clocks = <&gpucc 5>, 2409 - <&gpucc 8>, 2410 - <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2411 - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2412 - <&gpucc 2>, 2413 - <&gpucc 15>, 2414 - <&gpucc 11>; 2316 + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2317 + <&gpucc GPU_CC_CXO_CLK>, 2318 + <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2319 + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2320 + <&gpucc GPU_CC_AHB_CLK>, 2321 + <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2322 + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2415 2323 clock-names = "gmu", 2416 2324 "cxo", 2417 2325 "axi", ··· 2419 2327 "ahb", 2420 2328 "hub", 2421 2329 "smmu_vote"; 2422 - power-domains = <&gpucc 0>, 2423 - <&gpucc 1>; 2330 + power-domains = <&gpucc GPU_CC_CX_GDSC>, 2331 + <&gpucc GPU_CC_GX_GDSC>; 2424 2332 power-domain-names = "cx", 2425 2333 "gx"; 2426 2334 iommus = <&adreno_smmu 5 0x400>; ··· 2469 2377 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2470 2378 2471 2379 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2472 - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2473 - <&gpucc 2>, 2474 - <&gpucc 11>, 2475 - <&gpucc 5>, 2476 - <&gpucc 15>, 2477 - <&gpucc 13>; 2380 + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2381 + <&gpucc GPU_CC_AHB_CLK>, 2382 + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2383 + <&gpucc GPU_CC_CX_GMU_CLK>, 2384 + <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2385 + <&gpucc GPU_CC_HUB_AON_CLK>; 2478 2386 clock-names = "gcc_gpu_memnoc_gfx_clk", 2479 2387 "gcc_gpu_snoc_dvm_gfx_clk", 2480 2388 "gpu_cc_ahb_clk", ··· 2483 2391 "gpu_cc_hub_cx_int_clk", 2484 2392 "gpu_cc_hub_aon_clk"; 2485 2393 2486 - power-domains = <&gpucc 0>; 2394 + power-domains = <&gpucc GPU_CC_CX_GDSC>; 2487 2395 }; 2488 2396 2489 2397 remoteproc_mpss: remoteproc@4080000 { ··· 3028 2936 }; 3029 2937 }; 3030 2938 3031 - sdhc_2: sdhci@8804000 { 2939 + sdhc_2: mmc@8804000 { 3032 2940 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3033 2941 pinctrl-names = "default", "sleep"; 3034 2942 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; ··· 3042 2950 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3043 2951 interrupt-names = "hc_irq", "pwr_irq"; 3044 2952 3045 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 3046 - <&gcc GCC_SDCC2_AHB_CLK>, 2953 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2954 + <&gcc GCC_SDCC2_APPS_CLK>, 3047 2955 <&rpmhcc RPMH_CXO_CLK>; 3048 - clock-names = "core", "iface", "xo"; 2956 + clock-names = "iface", "core", "xo"; 3049 2957 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3050 2958 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3051 2959 interconnect-names = "sdhc-ddr","cpu-sdhc"; ··· 3426 3334 iommus = <&apps_smmu 0x21a2 0x0>; 3427 3335 }; 3428 3336 3429 - venus_opp_table: venus-opp-table { 3337 + venus_opp_table: opp-table { 3430 3338 compatible = "operating-points-v2"; 3431 3339 3432 3340 opp-133330000 { ··· 3518 3426 "ahb", 3519 3427 "core"; 3520 3428 3521 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3522 - assigned-clock-rates = <300000000>; 3523 - 3524 3429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3525 3430 interrupt-controller; 3526 3431 #interrupt-cells = <1>; ··· 3551 3462 "lut", 3552 3463 "core", 3553 3464 "vsync"; 3554 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3555 - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3465 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3556 3466 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3557 - assigned-clock-rates = <300000000>, 3558 - <19200000>, 3467 + assigned-clock-rates = <19200000>, 3559 3468 <19200000>; 3560 3469 operating-points-v2 = <&mdp_opp_table>; 3561 3470 power-domains = <&rpmhpd SC7280_CX>; ··· 3820 3733 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3821 3734 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3822 3735 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3823 - clock-names = "core_iface", 3736 + clock-names = "core_iface", 3824 3737 "core_aux", 3825 3738 "ctrl_link", 3826 3739 "ctrl_link_iface", ··· 3930 3843 }; 3931 3844 3932 3845 aoss_qmp: power-controller@c300000 { 3933 - compatible = "qcom,sc7280-aoss-qmp"; 3846 + compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 3934 3847 reg = <0 0x0c300000 0 0x400>; 3935 3848 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3936 3849 IPCC_MPROC_SIGNAL_GLINK_QMP ··· 3983 3896 edp_hot_plug_det: edp-hot-plug-det { 3984 3897 pins = "gpio60"; 3985 3898 function = "edp_hot"; 3899 + }; 3900 + 3901 + mi2s0_data0: mi2s0-data0 { 3902 + pins = "gpio98"; 3903 + function = "mi2s0_data0"; 3904 + }; 3905 + 3906 + mi2s0_data1: mi2s0-data1 { 3907 + pins = "gpio99"; 3908 + function = "mi2s0_data1"; 3909 + }; 3910 + 3911 + mi2s0_mclk: mi2s0-mclk { 3912 + pins = "gpio96"; 3913 + function = "pri_mi2s"; 3914 + }; 3915 + 3916 + mi2s0_sclk: mi2s0-sclk { 3917 + pins = "gpio97"; 3918 + function = "mi2s0_sck"; 3919 + }; 3920 + 3921 + mi2s0_ws: mi2s0-ws { 3922 + pins = "gpio100"; 3923 + function = "mi2s0_ws"; 3924 + }; 3925 + 3926 + mi2s1_data0: mi2s1-data0 { 3927 + pins = "gpio107"; 3928 + function = "mi2s1_data0"; 3929 + }; 3930 + 3931 + mi2s1_sclk: mi2s1-sclk { 3932 + pins = "gpio106"; 3933 + function = "mi2s1_sck"; 3934 + }; 3935 + 3936 + mi2s1_ws: mi2s1-ws { 3937 + pins = "gpio108"; 3938 + function = "mi2s1_ws"; 3986 3939 }; 3987 3940 3988 3941 pcie1_clkreq_n: pcie1-clkreq-n { ··· 4766 4639 }; 4767 4640 }; 4768 4641 4769 - imem@146a5000 { 4770 - compatible = "qcom,sc7280-imem", "syscon"; 4642 + sram@146a5000 { 4643 + compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 4771 4644 reg = <0 0x146a5000 0 0x6000>; 4772 4645 4773 4646 #address-cells = <1>; ··· 4898 4771 }; 4899 4772 4900 4773 timer@17c20000 { 4901 - #address-cells = <2>; 4902 - #size-cells = <2>; 4903 - ranges; 4774 + #address-cells = <1>; 4775 + #size-cells = <1>; 4776 + ranges = <0 0 0 0x20000000>; 4904 4777 compatible = "arm,armv7-timer-mem"; 4905 4778 reg = <0 0x17c20000 0 0x1000>; 4906 4779 ··· 4908 4781 frame-number = <0>; 4909 4782 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4910 4783 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4911 - reg = <0 0x17c21000 0 0x1000>, 4912 - <0 0x17c22000 0 0x1000>; 4784 + reg = <0x17c21000 0x1000>, 4785 + <0x17c22000 0x1000>; 4913 4786 }; 4914 4787 4915 4788 frame@17c23000 { 4916 4789 frame-number = <1>; 4917 4790 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4918 - reg = <0 0x17c23000 0 0x1000>; 4791 + reg = <0x17c23000 0x1000>; 4919 4792 status = "disabled"; 4920 4793 }; 4921 4794 4922 4795 frame@17c25000 { 4923 4796 frame-number = <2>; 4924 4797 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4925 - reg = <0 0x17c25000 0 0x1000>; 4798 + reg = <0x17c25000 0x1000>; 4926 4799 status = "disabled"; 4927 4800 }; 4928 4801 4929 4802 frame@17c27000 { 4930 4803 frame-number = <3>; 4931 4804 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4932 - reg = <0 0x17c27000 0 0x1000>; 4805 + reg = <0x17c27000 0x1000>; 4933 4806 status = "disabled"; 4934 4807 }; 4935 4808 4936 4809 frame@17c29000 { 4937 4810 frame-number = <4>; 4938 4811 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4939 - reg = <0 0x17c29000 0 0x1000>; 4812 + reg = <0x17c29000 0x1000>; 4940 4813 status = "disabled"; 4941 4814 }; 4942 4815 4943 4816 frame@17c2b000 { 4944 4817 frame-number = <5>; 4945 4818 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4946 - reg = <0 0x17c2b000 0 0x1000>; 4819 + reg = <0x17c2b000 0x1000>; 4947 4820 status = "disabled"; 4948 4821 }; 4949 4822 4950 4823 frame@17c2d000 { 4951 4824 frame-number = <6>; 4952 4825 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4953 - reg = <0 0x17c2d000 0 0x1000>; 4826 + reg = <0x17c2d000 0x1000>; 4954 4827 status = "disabled"; 4955 4828 }; 4956 4829 };
+427
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2022, Linaro Limited 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 + 12 + #include "sc8280xp.dtsi" 13 + #include "sc8280xp-pmics.dtsi" 14 + 15 + / { 16 + model = "Qualcomm SC8280XP CRD"; 17 + compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; 18 + 19 + aliases { 20 + serial0 = &qup2_uart17; 21 + }; 22 + 23 + backlight { 24 + compatible = "pwm-backlight"; 25 + pwms = <&pmc8280c_lpg 3 1000000>; 26 + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; 27 + power-supply = <&vreg_edp_bl>; 28 + 29 + pinctrl-names = "default"; 30 + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; 31 + }; 32 + 33 + chosen { 34 + stdout-path = "serial0:115200n8"; 35 + }; 36 + 37 + vreg_edp_bl: regulator-edp-bl { 38 + compatible = "regulator-fixed"; 39 + 40 + regulator-name = "VREG_EDP_BL"; 41 + regulator-min-microvolt = <3600000>; 42 + regulator-max-microvolt = <3600000>; 43 + 44 + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; 45 + enable-active-high; 46 + 47 + pinctrl-names = "default"; 48 + pinctrl-0 = <&edp_bl_reg_en>; 49 + 50 + regulator-boot-on; 51 + }; 52 + 53 + vreg_misc_3p3: regulator-misc-3p3 { 54 + compatible = "regulator-fixed"; 55 + 56 + regulator-name = "VREG_MISC_3P3"; 57 + regulator-min-microvolt = <3300000>; 58 + regulator-max-microvolt = <3300000>; 59 + 60 + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; 61 + enable-active-high; 62 + 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&misc_3p3_reg_en>; 65 + 66 + regulator-boot-on; 67 + regulator-always-on; 68 + }; 69 + }; 70 + 71 + &apps_rsc { 72 + pmc8280-1-rpmh-regulators { 73 + compatible = "qcom,pm8350-rpmh-regulators"; 74 + qcom,pmic-id = "b"; 75 + 76 + vdd-l3-l5-supply = <&vreg_s11b>; 77 + 78 + vreg_s11b: smps11 { 79 + regulator-name = "vreg_s11b"; 80 + regulator-min-microvolt = <1272000>; 81 + regulator-max-microvolt = <1272000>; 82 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 83 + }; 84 + 85 + vreg_l3b: ldo3 { 86 + regulator-name = "vreg_l3b"; 87 + regulator-min-microvolt = <1200000>; 88 + regulator-max-microvolt = <1200000>; 89 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 90 + regulator-allow-set-load; 91 + regulator-boot-on; 92 + regulator-always-on; 93 + }; 94 + 95 + vreg_l4b: ldo4 { 96 + regulator-name = "vreg_l4b"; 97 + regulator-min-microvolt = <912000>; 98 + regulator-max-microvolt = <912000>; 99 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 100 + regulator-allow-set-load; 101 + }; 102 + 103 + vreg_l6b: ldo6 { 104 + regulator-name = "vreg_l6b"; 105 + regulator-min-microvolt = <880000>; 106 + regulator-max-microvolt = <880000>; 107 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 108 + regulator-allow-set-load; 109 + regulator-boot-on; 110 + }; 111 + }; 112 + 113 + pmc8280c-rpmh-regulators { 114 + compatible = "qcom,pm8350c-rpmh-regulators"; 115 + qcom,pmic-id = "c"; 116 + 117 + vreg_l1c: ldo1 { 118 + regulator-name = "vreg_l1c"; 119 + regulator-min-microvolt = <1800000>; 120 + regulator-max-microvolt = <1800000>; 121 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 122 + regulator-allow-set-load; 123 + }; 124 + 125 + vreg_l7c: ldo7 { 126 + regulator-name = "vreg_l7c"; 127 + regulator-min-microvolt = <2504000>; 128 + regulator-max-microvolt = <2504000>; 129 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 130 + regulator-allow-set-load; 131 + }; 132 + 133 + vreg_l13c: ldo13 { 134 + regulator-name = "vreg_l13c"; 135 + regulator-min-microvolt = <3072000>; 136 + regulator-max-microvolt = <3072000>; 137 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 138 + regulator-allow-set-load; 139 + }; 140 + }; 141 + 142 + pmc8280-2-rpmh-regulators { 143 + compatible = "qcom,pm8350-rpmh-regulators"; 144 + qcom,pmic-id = "d"; 145 + 146 + vdd-l1-l4-supply = <&vreg_s11b>; 147 + 148 + vreg_l3d: ldo3 { 149 + regulator-name = "vreg_l3d"; 150 + regulator-min-microvolt = <1200000>; 151 + regulator-max-microvolt = <1200000>; 152 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 153 + regulator-allow-set-load; 154 + }; 155 + 156 + vreg_l4d: ldo4 { 157 + regulator-name = "vreg_l4d"; 158 + regulator-min-microvolt = <1200000>; 159 + regulator-max-microvolt = <1200000>; 160 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 161 + regulator-allow-set-load; 162 + }; 163 + 164 + vreg_l6d: ldo6 { 165 + regulator-name = "vreg_l6d"; 166 + regulator-min-microvolt = <880000>; 167 + regulator-max-microvolt = <880000>; 168 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 169 + regulator-allow-set-load; 170 + }; 171 + 172 + vreg_l7d: ldo7 { 173 + regulator-name = "vreg_l7d"; 174 + regulator-min-microvolt = <3072000>; 175 + regulator-max-microvolt = <3072000>; 176 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 177 + regulator-allow-set-load; 178 + }; 179 + 180 + vreg_l9d: ldo9 { 181 + regulator-name = "vreg_l9d"; 182 + regulator-min-microvolt = <912000>; 183 + regulator-max-microvolt = <912000>; 184 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 185 + regulator-allow-set-load; 186 + }; 187 + }; 188 + }; 189 + 190 + &pmc8280c_lpg { 191 + status = "okay"; 192 + }; 193 + 194 + &pmk8280_pon_pwrkey { 195 + status = "okay"; 196 + }; 197 + 198 + &qup0 { 199 + status = "okay"; 200 + }; 201 + 202 + &qup0_i2c4 { 203 + clock-frequency = <400000>; 204 + 205 + pinctrl-names = "default"; 206 + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; 207 + 208 + status = "okay"; 209 + 210 + touchscreen@10 { 211 + compatible = "hid-over-i2c"; 212 + reg = <0x10>; 213 + hid-descr-addr = <0x1>; 214 + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; 215 + vdd-supply = <&vreg_misc_3p3>; 216 + }; 217 + }; 218 + 219 + &qup1 { 220 + status = "okay"; 221 + }; 222 + 223 + &qup2 { 224 + status = "okay"; 225 + }; 226 + 227 + &qup2_i2c5 { 228 + clock-frequency = <400000>; 229 + 230 + pinctrl-names = "default"; 231 + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; 232 + 233 + status = "okay"; 234 + 235 + touchpad@15 { 236 + compatible = "hid-over-i2c"; 237 + reg = <0x15>; 238 + hid-descr-addr = <0x1>; 239 + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; 240 + vdd-supply = <&vreg_misc_3p3>; 241 + }; 242 + 243 + keyboard@68 { 244 + compatible = "hid-over-i2c"; 245 + reg = <0x68>; 246 + hid-descr-addr = <0x1>; 247 + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; 248 + vdd-supply = <&vreg_misc_3p3>; 249 + }; 250 + }; 251 + 252 + &qup2_uart17 { 253 + compatible = "qcom,geni-debug-uart"; 254 + 255 + status = "okay"; 256 + }; 257 + 258 + &remoteproc_adsp { 259 + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; 260 + 261 + status = "okay"; 262 + }; 263 + 264 + &remoteproc_nsp0 { 265 + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; 266 + 267 + status = "okay"; 268 + }; 269 + 270 + &ufs_mem_hc { 271 + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; 272 + 273 + vcc-supply = <&vreg_l7c>; 274 + vcc-max-microamp = <800000>; 275 + vccq-supply = <&vreg_l3d>; 276 + vccq-max-microamp = <900000>; 277 + 278 + status = "okay"; 279 + }; 280 + 281 + &ufs_mem_phy { 282 + vdda-phy-supply = <&vreg_l6b>; 283 + vdda-pll-supply = <&vreg_l3b>; 284 + 285 + status = "okay"; 286 + }; 287 + 288 + &usb_0 { 289 + status = "okay"; 290 + }; 291 + 292 + &usb_0_dwc3 { 293 + /* TODO: Define USB-C connector properly */ 294 + dr_mode = "host"; 295 + }; 296 + 297 + &usb_0_hsphy { 298 + vdda-pll-supply = <&vreg_l9d>; 299 + vdda18-supply = <&vreg_l1c>; 300 + vdda33-supply = <&vreg_l7d>; 301 + 302 + status = "okay"; 303 + }; 304 + 305 + &usb_0_qmpphy { 306 + vdda-phy-supply = <&vreg_l9d>; 307 + vdda-pll-supply = <&vreg_l4d>; 308 + 309 + status = "okay"; 310 + }; 311 + 312 + &usb_1 { 313 + status = "okay"; 314 + }; 315 + 316 + &usb_1_dwc3 { 317 + /* TODO: Define USB-C connector properly */ 318 + dr_mode = "host"; 319 + }; 320 + 321 + &usb_1_hsphy { 322 + vdda-pll-supply = <&vreg_l4b>; 323 + vdda18-supply = <&vreg_l1c>; 324 + vdda33-supply = <&vreg_l13c>; 325 + 326 + status = "okay"; 327 + }; 328 + 329 + &usb_1_qmpphy { 330 + vdda-phy-supply = <&vreg_l4b>; 331 + vdda-pll-supply = <&vreg_l3b>; 332 + 333 + status = "okay"; 334 + }; 335 + 336 + &xo_board_clk { 337 + clock-frequency = <38400000>; 338 + }; 339 + 340 + /* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ 341 + 342 + &pmc8280_1_gpios { 343 + edp_bl_en: edp-bl-en-state { 344 + pins = "gpio8"; 345 + function = "normal"; 346 + }; 347 + 348 + edp_bl_reg_en: edp-bl-reg-en-state { 349 + pins = "gpio9"; 350 + function = "normal"; 351 + }; 352 + 353 + misc_3p3_reg_en: misc-3p3-reg-en-state { 354 + pins = "gpio1"; 355 + function = "normal"; 356 + }; 357 + }; 358 + 359 + &pmc8280c_gpios { 360 + edp_bl_pwm: edp-bl-pwm-state { 361 + pins = "gpio8"; 362 + function = "func1"; 363 + }; 364 + }; 365 + 366 + &tlmm { 367 + gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; 368 + 369 + kybd_default: kybd-default-state { 370 + disable { 371 + pins = "gpio102"; 372 + function = "gpio"; 373 + output-low; 374 + }; 375 + 376 + int-n { 377 + pins = "gpio104"; 378 + function = "gpio"; 379 + bias-disable; 380 + }; 381 + 382 + reset { 383 + pins = "gpio105"; 384 + function = "gpio"; 385 + bias-disable; 386 + }; 387 + }; 388 + 389 + qup0_i2c4_default: qup0-i2c4-default-state { 390 + pins = "gpio171", "gpio172"; 391 + function = "qup4"; 392 + 393 + bias-disable; 394 + drive-strength = <16>; 395 + }; 396 + 397 + qup2_i2c5_default: qup2-i2c5-default-state { 398 + pins = "gpio81", "gpio82"; 399 + function = "qup21"; 400 + 401 + bias-disable; 402 + drive-strength = <16>; 403 + }; 404 + 405 + tpad_default: tpad-default-state { 406 + int-n { 407 + pins = "gpio182"; 408 + function = "gpio"; 409 + bias-disable; 410 + }; 411 + }; 412 + 413 + ts0_default: ts0-default-state { 414 + int-n { 415 + pins = "gpio175"; 416 + function = "gpio"; 417 + bias-pull-up; 418 + }; 419 + 420 + reset-n { 421 + pins = "gpio99"; 422 + function = "gpio"; 423 + output-high; 424 + drive-strength = <16>; 425 + }; 426 + }; 427 + };
+386
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2022, Linaro Limited 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 + 12 + #include "sc8280xp.dtsi" 13 + #include "sc8280xp-pmics.dtsi" 14 + 15 + / { 16 + model = "Lenovo ThinkPad X13s"; 17 + compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp"; 18 + 19 + backlight { 20 + compatible = "pwm-backlight"; 21 + pwms = <&pmc8280c_lpg 3 1000000>; 22 + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; 23 + power-supply = <&vreg_edp_bl>; 24 + 25 + pinctrl-names = "default"; 26 + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; 27 + }; 28 + 29 + vreg_edp_bl: regulator-edp-bl { 30 + compatible = "regulator-fixed"; 31 + 32 + regulator-name = "VBL9"; 33 + regulator-min-microvolt = <3600000>; 34 + regulator-max-microvolt = <3600000>; 35 + 36 + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; 37 + enable-active-high; 38 + 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&edp_bl_reg_en>; 41 + 42 + regulator-boot-on; 43 + }; 44 + 45 + vreg_misc_3p3: regulator-misc-3p3 { 46 + compatible = "regulator-fixed"; 47 + 48 + regulator-name = "VCC3B"; 49 + regulator-min-microvolt = <3300000>; 50 + regulator-max-microvolt = <3300000>; 51 + 52 + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; 53 + enable-active-high; 54 + 55 + pinctrl-names = "default"; 56 + pinctrl-0 = <&misc_3p3_reg_en>; 57 + 58 + regulator-boot-on; 59 + regulator-always-on; 60 + }; 61 + }; 62 + 63 + &apps_rsc { 64 + pmc8280-1-rpmh-regulators { 65 + compatible = "qcom,pm8350-rpmh-regulators"; 66 + qcom,pmic-id = "b"; 67 + 68 + vdd-l3-l5-supply = <&vreg_s11b>; 69 + 70 + vreg_s11b: smps11 { 71 + regulator-name = "vreg_s11b"; 72 + regulator-min-microvolt = <1272000>; 73 + regulator-max-microvolt = <1272000>; 74 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 75 + }; 76 + 77 + vreg_l3b: ldo3 { 78 + regulator-name = "vreg_l3b"; 79 + regulator-min-microvolt = <1200000>; 80 + regulator-max-microvolt = <1200000>; 81 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 82 + regulator-allow-set-load; 83 + regulator-boot-on; 84 + }; 85 + 86 + vreg_l4b: ldo4 { 87 + regulator-name = "vreg_l4b"; 88 + regulator-min-microvolt = <912000>; 89 + regulator-max-microvolt = <912000>; 90 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 91 + regulator-allow-set-load; 92 + }; 93 + 94 + vreg_l6b: ldo6 { 95 + regulator-name = "vreg_l6b"; 96 + regulator-min-microvolt = <880000>; 97 + regulator-max-microvolt = <880000>; 98 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 99 + regulator-allow-set-load; 100 + regulator-boot-on; 101 + regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 102 + }; 103 + }; 104 + 105 + pmc8280c-rpmh-regulators { 106 + compatible = "qcom,pm8350c-rpmh-regulators"; 107 + qcom,pmic-id = "c"; 108 + 109 + vreg_l1c: ldo1 { 110 + regulator-name = "vreg_l1c"; 111 + regulator-min-microvolt = <1800000>; 112 + regulator-max-microvolt = <1800000>; 113 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 114 + regulator-allow-set-load; 115 + }; 116 + 117 + vreg_l12c: ldo12 { 118 + regulator-name = "vreg_l12c"; 119 + regulator-min-microvolt = <1800000>; 120 + regulator-max-microvolt = <1800000>; 121 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 122 + regulator-allow-set-load; 123 + }; 124 + 125 + vreg_l13c: ldo13 { 126 + regulator-name = "vreg_l13c"; 127 + regulator-min-microvolt = <3072000>; 128 + regulator-max-microvolt = <3072000>; 129 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 130 + regulator-allow-set-load; 131 + }; 132 + }; 133 + 134 + pmc8280-2-rpmh-regulators { 135 + compatible = "qcom,pm8350-rpmh-regulators"; 136 + qcom,pmic-id = "d"; 137 + 138 + vdd-l1-l4-supply = <&vreg_s11b>; 139 + 140 + vreg_l3d: ldo3 { 141 + regulator-name = "vreg_l3d"; 142 + regulator-min-microvolt = <1200000>; 143 + regulator-max-microvolt = <1200000>; 144 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 145 + regulator-allow-set-load; 146 + }; 147 + 148 + vreg_l4d: ldo4 { 149 + regulator-name = "vreg_l4d"; 150 + regulator-min-microvolt = <1200000>; 151 + regulator-max-microvolt = <1200000>; 152 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 153 + regulator-allow-set-load; 154 + }; 155 + 156 + vreg_l7d: ldo7 { 157 + regulator-name = "vreg_l7d"; 158 + regulator-min-microvolt = <3072000>; 159 + regulator-max-microvolt = <3072000>; 160 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 161 + regulator-allow-set-load; 162 + }; 163 + 164 + vreg_l9d: ldo9 { 165 + regulator-name = "vreg_l9d"; 166 + regulator-min-microvolt = <912000>; 167 + regulator-max-microvolt = <912000>; 168 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 169 + regulator-allow-set-load; 170 + }; 171 + }; 172 + }; 173 + 174 + &pmc8280c_lpg { 175 + status = "okay"; 176 + }; 177 + 178 + &pmk8280_pon_pwrkey { 179 + status = "okay"; 180 + }; 181 + 182 + &qup0 { 183 + status = "okay"; 184 + }; 185 + 186 + &qup0_i2c4 { 187 + clock-frequency = <400000>; 188 + 189 + pinctrl-names = "default"; 190 + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; 191 + 192 + status = "okay"; 193 + 194 + /* FIXME: verify */ 195 + touchscreen@10 { 196 + compatible = "hid-over-i2c"; 197 + reg = <0x10>; 198 + hid-descr-addr = <0x1>; 199 + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; 200 + vdd-supply = <&vreg_misc_3p3>; 201 + }; 202 + }; 203 + 204 + &qup1 { 205 + status = "okay"; 206 + }; 207 + 208 + &qup2 { 209 + status = "okay"; 210 + }; 211 + 212 + &qup2_i2c5 { 213 + clock-frequency = <400000>; 214 + 215 + pinctrl-names = "default"; 216 + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; 217 + 218 + status = "okay"; 219 + 220 + touchpad@2c { 221 + compatible = "hid-over-i2c"; 222 + reg = <0x2c>; 223 + hid-descr-addr = <0x20>; 224 + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; 225 + vdd-supply = <&vreg_misc_3p3>; 226 + }; 227 + 228 + keyboard@68 { 229 + compatible = "hid-over-i2c"; 230 + reg = <0x68>; 231 + hid-descr-addr = <0x1>; 232 + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; 233 + vdd-supply = <&vreg_misc_3p3>; 234 + }; 235 + }; 236 + 237 + &remoteproc_adsp { 238 + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; 239 + 240 + status = "okay"; 241 + }; 242 + 243 + &remoteproc_nsp0 { 244 + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; 245 + 246 + status = "okay"; 247 + }; 248 + 249 + &usb_0 { 250 + status = "okay"; 251 + }; 252 + 253 + &usb_0_dwc3 { 254 + /* TODO: Define USB-C connector properly */ 255 + dr_mode = "host"; 256 + }; 257 + 258 + &usb_0_hsphy { 259 + vdda-pll-supply = <&vreg_l9d>; 260 + vdda18-supply = <&vreg_l1c>; 261 + vdda33-supply = <&vreg_l7d>; 262 + 263 + status = "okay"; 264 + }; 265 + 266 + &usb_0_qmpphy { 267 + vdda-phy-supply = <&vreg_l9d>; 268 + vdda-pll-supply = <&vreg_l4d>; 269 + 270 + status = "okay"; 271 + }; 272 + 273 + &usb_1 { 274 + status = "okay"; 275 + }; 276 + 277 + &usb_1_dwc3 { 278 + /* TODO: Define USB-C connector properly */ 279 + dr_mode = "host"; 280 + }; 281 + 282 + &usb_1_hsphy { 283 + vdda-pll-supply = <&vreg_l4b>; 284 + vdda18-supply = <&vreg_l1c>; 285 + vdda33-supply = <&vreg_l13c>; 286 + 287 + status = "okay"; 288 + }; 289 + 290 + &usb_1_qmpphy { 291 + vdda-phy-supply = <&vreg_l4b>; 292 + vdda-pll-supply = <&vreg_l3b>; 293 + 294 + status = "okay"; 295 + }; 296 + 297 + &xo_board_clk { 298 + clock-frequency = <38400000>; 299 + }; 300 + 301 + /* PINCTRL */ 302 + 303 + &pmc8280_1_gpios { 304 + edp_bl_en: edp-bl-en-state { 305 + pins = "gpio8"; 306 + function = "normal"; 307 + }; 308 + 309 + edp_bl_reg_en: edp-bl-reg-en-state { 310 + pins = "gpio9"; 311 + function = "normal"; 312 + }; 313 + 314 + misc_3p3_reg_en: misc-3p3-reg-en-state { 315 + pins = "gpio1"; 316 + function = "normal"; 317 + }; 318 + }; 319 + 320 + &pmc8280c_gpios { 321 + edp_bl_pwm: edp-bl-pwm-state { 322 + pins = "gpio8"; 323 + function = "func1"; 324 + }; 325 + }; 326 + 327 + &tlmm { 328 + gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; 329 + 330 + kybd_default: kybd-default-state { 331 + disable { 332 + pins = "gpio102"; 333 + function = "gpio"; 334 + output-low; 335 + }; 336 + 337 + int-n { 338 + pins = "gpio104"; 339 + function = "gpio"; 340 + bias-disable; 341 + }; 342 + 343 + reset { 344 + pins = "gpio105"; 345 + function = "gpio"; 346 + bias-disable; 347 + }; 348 + }; 349 + 350 + qup0_i2c4_default: qup0-i2c4-default-state { 351 + pins = "gpio171", "gpio172"; 352 + function = "qup4"; 353 + bias-disable; 354 + drive-strength = <16>; 355 + }; 356 + 357 + qup2_i2c5_default: qup2-i2c5-default-state { 358 + pins = "gpio81", "gpio82"; 359 + function = "qup21"; 360 + bias-disable; 361 + drive-strength = <16>; 362 + }; 363 + 364 + tpad_default: tpad-default-state { 365 + int-n { 366 + pins = "gpio182"; 367 + function = "gpio"; 368 + bias-disable; 369 + }; 370 + }; 371 + 372 + ts0_default: ts0-default-state { 373 + int-n { 374 + pins = "gpio175"; 375 + function = "gpio"; 376 + bias-pull-up; 377 + }; 378 + 379 + reset-n { 380 + pins = "gpio99"; 381 + function = "gpio"; 382 + output-high; 383 + drive-strength = <16>; 384 + }; 385 + }; 386 + };
+109
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2022, Linaro Limited 4 + */ 5 + 6 + #include <dt-bindings/input/input.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + #include <dt-bindings/spmi/spmi.h> 9 + 10 + &spmi_bus { 11 + pmk8280: pmic@0 { 12 + compatible = "qcom,pmk8350", "qcom,spmi-pmic"; 13 + reg = <0x0 SPMI_USID>; 14 + #address-cells = <1>; 15 + #size-cells = <0>; 16 + 17 + pmk8280_pon: pon@1300 { 18 + compatible = "qcom,pm8998-pon"; 19 + reg = <0x1300>; 20 + 21 + pmk8280_pon_pwrkey: pwrkey { 22 + compatible = "qcom,pmk8350-pwrkey"; 23 + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; 24 + linux,code = <KEY_POWER>; 25 + status = "disabled"; 26 + }; 27 + }; 28 + }; 29 + 30 + pmc8280_1: pmic@1 { 31 + compatible = "qcom,pm8350", "qcom,spmi-pmic"; 32 + reg = <0x1 SPMI_USID>; 33 + #address-cells = <1>; 34 + #size-cells = <0>; 35 + 36 + pmc8280_1_gpios: gpio@8800 { 37 + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; 38 + reg = <0x8800>; 39 + gpio-controller; 40 + gpio-ranges = <&pmc8280_1_gpios 0 0 10>; 41 + #gpio-cells = <2>; 42 + interrupt-controller; 43 + #interrupt-cells = <2>; 44 + }; 45 + }; 46 + 47 + pmc8280c: pmic@2 { 48 + compatible = "qcom,pm8350c", "qcom,spmi-pmic"; 49 + reg = <0x2 SPMI_USID>; 50 + #address-cells = <1>; 51 + #size-cells = <0>; 52 + 53 + pmc8280c_gpios: gpio@8800 { 54 + compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; 55 + reg = <0x8800>; 56 + gpio-controller; 57 + gpio-ranges = <&pmc8280c_gpios 0 0 9>; 58 + #gpio-cells = <2>; 59 + interrupt-controller; 60 + #interrupt-cells = <2>; 61 + }; 62 + 63 + pmc8280c_lpg: lpg@e800 { 64 + compatible = "qcom,pm8350c-pwm"; 65 + reg = <0xe800>; 66 + 67 + #address-cells = <1>; 68 + #size-cells = <0>; 69 + 70 + #pwm-cells = <2>; 71 + 72 + status = "disabled"; 73 + }; 74 + }; 75 + 76 + pmc8280_2: pmic@3 { 77 + compatible = "qcom,pm8350", "qcom,spmi-pmic"; 78 + reg = <0x3 SPMI_USID>; 79 + #address-cells = <1>; 80 + #size-cells = <0>; 81 + 82 + pmc8280_2_gpios: gpio@8800 { 83 + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; 84 + reg = <0x8800>; 85 + gpio-controller; 86 + gpio-ranges = <&pmc8280_2_gpios 0 0 10>; 87 + #gpio-cells = <2>; 88 + interrupt-controller; 89 + #interrupt-cells = <2>; 90 + }; 91 + }; 92 + 93 + pmr735a: pmic@4 { 94 + compatible = "qcom,pmr735a", "qcom,spmi-pmic"; 95 + reg = <0x4 SPMI_USID>; 96 + #address-cells = <1>; 97 + #size-cells = <0>; 98 + 99 + pmr735a_gpios: gpio@8800 { 100 + compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; 101 + reg = <0x8800>; 102 + gpio-controller; 103 + gpio-ranges = <&pmr735a_gpios 0 0 4>; 104 + #gpio-cells = <2>; 105 + interrupt-controller; 106 + #interrupt-cells = <2>; 107 + }; 108 + }; 109 + };
+2139
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2022, Linaro Limited 5 + */ 6 + 7 + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 8 + #include <dt-bindings/clock/qcom,rpmh.h> 9 + #include <dt-bindings/interconnect/qcom,sc8280xp.h> 10 + #include <dt-bindings/interrupt-controller/arm-gic.h> 11 + #include <dt-bindings/mailbox/qcom-ipcc.h> 12 + #include <dt-bindings/power/qcom-rpmpd.h> 13 + #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 + #include <dt-bindings/thermal/thermal.h> 15 + 16 + / { 17 + interrupt-parent = <&intc>; 18 + 19 + #address-cells = <2>; 20 + #size-cells = <2>; 21 + 22 + clocks { 23 + xo_board_clk: xo-board-clk { 24 + compatible = "fixed-clock"; 25 + #clock-cells = <0>; 26 + }; 27 + 28 + sleep_clk: sleep-clk { 29 + compatible = "fixed-clock"; 30 + #clock-cells = <0>; 31 + clock-frequency = <32764>; 32 + }; 33 + }; 34 + 35 + cpu0_opp_table: cpu0-opp-table { 36 + compatible = "operating-points-v2"; 37 + opp-shared; 38 + 39 + opp-403200000 { 40 + opp-hz = /bits/ 64 <403200000>; 41 + }; 42 + opp-499200000 { 43 + opp-hz = /bits/ 64 <499200000>; 44 + }; 45 + opp-595200000 { 46 + opp-hz = /bits/ 64 <595200000>; 47 + }; 48 + opp-691200000 { 49 + opp-hz = /bits/ 64 <691200000>; 50 + }; 51 + opp-806400000 { 52 + opp-hz = /bits/ 64 <806400000>; 53 + }; 54 + opp-902400000 { 55 + opp-hz = /bits/ 64 <902400000>; 56 + }; 57 + opp-1017600000 { 58 + opp-hz = /bits/ 64 <1017600000>; 59 + }; 60 + opp-1113600000 { 61 + opp-hz = /bits/ 64 <1113600000>; 62 + }; 63 + opp-1209600000 { 64 + opp-hz = /bits/ 64 <1209600000>; 65 + }; 66 + opp-1324800000 { 67 + opp-hz = /bits/ 64 <1324800000>; 68 + }; 69 + opp-1440000000 { 70 + opp-hz = /bits/ 64 <1440000000>; 71 + }; 72 + opp-1555200000 { 73 + opp-hz = /bits/ 64 <1555200000>; 74 + }; 75 + opp-1670400000 { 76 + opp-hz = /bits/ 64 <1670400000>; 77 + }; 78 + opp-1785600000 { 79 + opp-hz = /bits/ 64 <1785600000>; 80 + }; 81 + opp-1881600000 { 82 + opp-hz = /bits/ 64 <1881600000>; 83 + }; 84 + opp-1996800000 { 85 + opp-hz = /bits/ 64 <1996800000>; 86 + }; 87 + opp-2112000000 { 88 + opp-hz = /bits/ 64 <2112000000>; 89 + }; 90 + opp-2227200000 { 91 + opp-hz = /bits/ 64 <2227200000>; 92 + }; 93 + opp-2342400000 { 94 + opp-hz = /bits/ 64 <2342400000>; 95 + }; 96 + opp-2438400000 { 97 + opp-hz = /bits/ 64 <2438400000>; 98 + }; 99 + }; 100 + 101 + cpu4_opp_table: cpu4-opp-table { 102 + compatible = "operating-points-v2"; 103 + opp-shared; 104 + 105 + opp-825600000 { 106 + opp-hz = /bits/ 64 <825600000>; 107 + }; 108 + opp-940800000 { 109 + opp-hz = /bits/ 64 <940800000>; 110 + }; 111 + opp-1056000000 { 112 + opp-hz = /bits/ 64 <1056000000>; 113 + }; 114 + opp-1171200000 { 115 + opp-hz = /bits/ 64 <1171200000>; 116 + }; 117 + opp-1286400000 { 118 + opp-hz = /bits/ 64 <1286400000>; 119 + }; 120 + opp-1401600000 { 121 + opp-hz = /bits/ 64 <1401600000>; 122 + }; 123 + opp-1516800000 { 124 + opp-hz = /bits/ 64 <1516800000>; 125 + }; 126 + opp-1632000000 { 127 + opp-hz = /bits/ 64 <1632000000>; 128 + }; 129 + opp-1747200000 { 130 + opp-hz = /bits/ 64 <1747200000>; 131 + }; 132 + opp-1862400000 { 133 + opp-hz = /bits/ 64 <1862400000>; 134 + }; 135 + opp-1977600000 { 136 + opp-hz = /bits/ 64 <1977600000>; 137 + }; 138 + opp-2073600000 { 139 + opp-hz = /bits/ 64 <2073600000>; 140 + }; 141 + opp-2169600000 { 142 + opp-hz = /bits/ 64 <2169600000>; 143 + }; 144 + opp-2284800000 { 145 + opp-hz = /bits/ 64 <2284800000>; 146 + }; 147 + opp-2400000000 { 148 + opp-hz = /bits/ 64 <2400000000>; 149 + }; 150 + opp-2496000000 { 151 + opp-hz = /bits/ 64 <2496000000>; 152 + }; 153 + opp-2592000000 { 154 + opp-hz = /bits/ 64 <2592000000>; 155 + }; 156 + opp-2688000000 { 157 + opp-hz = /bits/ 64 <2688000000>; 158 + }; 159 + opp-2803200000 { 160 + opp-hz = /bits/ 64 <2803200000>; 161 + }; 162 + opp-2899200000 { 163 + opp-hz = /bits/ 64 <2899200000>; 164 + }; 165 + opp-2995200000 { 166 + opp-hz = /bits/ 64 <2995200000>; 167 + }; 168 + }; 169 + 170 + cpus { 171 + #address-cells = <2>; 172 + #size-cells = <0>; 173 + 174 + CPU0: cpu@0 { 175 + device_type = "cpu"; 176 + compatible = "qcom,kryo"; 177 + reg = <0x0 0x0>; 178 + enable-method = "psci"; 179 + capacity-dmips-mhz = <602>; 180 + next-level-cache = <&L2_0>; 181 + power-domains = <&CPU_PD0>; 182 + power-domain-names = "psci"; 183 + qcom,freq-domain = <&cpufreq_hw 0>; 184 + operating-points-v2 = <&cpu0_opp_table>; 185 + #cooling-cells = <2>; 186 + L2_0: l2-cache { 187 + compatible = "cache"; 188 + next-level-cache = <&L3_0>; 189 + L3_0: l3-cache { 190 + compatible = "cache"; 191 + }; 192 + }; 193 + }; 194 + 195 + CPU1: cpu@100 { 196 + device_type = "cpu"; 197 + compatible = "qcom,kryo"; 198 + reg = <0x0 0x100>; 199 + enable-method = "psci"; 200 + capacity-dmips-mhz = <602>; 201 + next-level-cache = <&L2_100>; 202 + power-domains = <&CPU_PD1>; 203 + power-domain-names = "psci"; 204 + qcom,freq-domain = <&cpufreq_hw 0>; 205 + operating-points-v2 = <&cpu0_opp_table>; 206 + #cooling-cells = <2>; 207 + L2_100: l2-cache { 208 + compatible = "cache"; 209 + next-level-cache = <&L3_0>; 210 + }; 211 + }; 212 + 213 + CPU2: cpu@200 { 214 + device_type = "cpu"; 215 + compatible = "qcom,kryo"; 216 + reg = <0x0 0x200>; 217 + enable-method = "psci"; 218 + capacity-dmips-mhz = <602>; 219 + next-level-cache = <&L2_200>; 220 + power-domains = <&CPU_PD2>; 221 + power-domain-names = "psci"; 222 + qcom,freq-domain = <&cpufreq_hw 0>; 223 + operating-points-v2 = <&cpu0_opp_table>; 224 + #cooling-cells = <2>; 225 + L2_200: l2-cache { 226 + compatible = "cache"; 227 + next-level-cache = <&L3_0>; 228 + }; 229 + }; 230 + 231 + CPU3: cpu@300 { 232 + device_type = "cpu"; 233 + compatible = "qcom,kryo"; 234 + reg = <0x0 0x300>; 235 + enable-method = "psci"; 236 + capacity-dmips-mhz = <602>; 237 + next-level-cache = <&L2_300>; 238 + power-domains = <&CPU_PD3>; 239 + power-domain-names = "psci"; 240 + qcom,freq-domain = <&cpufreq_hw 0>; 241 + operating-points-v2 = <&cpu0_opp_table>; 242 + #cooling-cells = <2>; 243 + L2_300: l2-cache { 244 + compatible = "cache"; 245 + next-level-cache = <&L3_0>; 246 + }; 247 + }; 248 + 249 + CPU4: cpu@400 { 250 + device_type = "cpu"; 251 + compatible = "qcom,kryo"; 252 + reg = <0x0 0x400>; 253 + enable-method = "psci"; 254 + capacity-dmips-mhz = <1024>; 255 + next-level-cache = <&L2_400>; 256 + power-domains = <&CPU_PD4>; 257 + power-domain-names = "psci"; 258 + qcom,freq-domain = <&cpufreq_hw 1>; 259 + operating-points-v2 = <&cpu4_opp_table>; 260 + #cooling-cells = <2>; 261 + L2_400: l2-cache { 262 + compatible = "cache"; 263 + next-level-cache = <&L3_0>; 264 + }; 265 + }; 266 + 267 + CPU5: cpu@500 { 268 + device_type = "cpu"; 269 + compatible = "qcom,kryo"; 270 + reg = <0x0 0x500>; 271 + enable-method = "psci"; 272 + capacity-dmips-mhz = <1024>; 273 + next-level-cache = <&L2_500>; 274 + power-domains = <&CPU_PD5>; 275 + power-domain-names = "psci"; 276 + qcom,freq-domain = <&cpufreq_hw 1>; 277 + operating-points-v2 = <&cpu4_opp_table>; 278 + #cooling-cells = <2>; 279 + L2_500: l2-cache { 280 + compatible = "cache"; 281 + next-level-cache = <&L3_0>; 282 + }; 283 + }; 284 + 285 + CPU6: cpu@600 { 286 + device_type = "cpu"; 287 + compatible = "qcom,kryo"; 288 + reg = <0x0 0x600>; 289 + enable-method = "psci"; 290 + capacity-dmips-mhz = <1024>; 291 + next-level-cache = <&L2_600>; 292 + power-domains = <&CPU_PD6>; 293 + power-domain-names = "psci"; 294 + qcom,freq-domain = <&cpufreq_hw 1>; 295 + operating-points-v2 = <&cpu4_opp_table>; 296 + #cooling-cells = <2>; 297 + L2_600: l2-cache { 298 + compatible = "cache"; 299 + next-level-cache = <&L3_0>; 300 + }; 301 + }; 302 + 303 + CPU7: cpu@700 { 304 + device_type = "cpu"; 305 + compatible = "qcom,kryo"; 306 + reg = <0x0 0x700>; 307 + enable-method = "psci"; 308 + capacity-dmips-mhz = <1024>; 309 + next-level-cache = <&L2_700>; 310 + power-domains = <&CPU_PD7>; 311 + power-domain-names = "psci"; 312 + qcom,freq-domain = <&cpufreq_hw 1>; 313 + operating-points-v2 = <&cpu4_opp_table>; 314 + #cooling-cells = <2>; 315 + L2_700: l2-cache { 316 + compatible = "cache"; 317 + next-level-cache = <&L3_0>; 318 + }; 319 + }; 320 + 321 + cpu-map { 322 + cluster0 { 323 + core0 { 324 + cpu = <&CPU0>; 325 + }; 326 + 327 + core1 { 328 + cpu = <&CPU1>; 329 + }; 330 + 331 + core2 { 332 + cpu = <&CPU2>; 333 + }; 334 + 335 + core3 { 336 + cpu = <&CPU3>; 337 + }; 338 + 339 + core4 { 340 + cpu = <&CPU4>; 341 + }; 342 + 343 + core5 { 344 + cpu = <&CPU5>; 345 + }; 346 + 347 + core6 { 348 + cpu = <&CPU6>; 349 + }; 350 + 351 + core7 { 352 + cpu = <&CPU7>; 353 + }; 354 + }; 355 + }; 356 + 357 + idle-states { 358 + entry-method = "psci"; 359 + 360 + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 361 + compatible = "arm,idle-state"; 362 + idle-state-name = "little-rail-power-collapse"; 363 + arm,psci-suspend-param = <0x40000004>; 364 + entry-latency-us = <355>; 365 + exit-latency-us = <909>; 366 + min-residency-us = <3934>; 367 + local-timer-stop; 368 + }; 369 + 370 + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 371 + compatible = "arm,idle-state"; 372 + idle-state-name = "big-rail-power-collapse"; 373 + arm,psci-suspend-param = <0x40000004>; 374 + entry-latency-us = <241>; 375 + exit-latency-us = <1461>; 376 + min-residency-us = <4488>; 377 + local-timer-stop; 378 + }; 379 + }; 380 + 381 + domain-idle-states { 382 + CLUSTER_SLEEP_0: cluster-sleep-0 { 383 + compatible = "domain-idle-state"; 384 + idle-state-name = "cluster-power-collapse"; 385 + arm,psci-suspend-param = <0x4100c344>; 386 + entry-latency-us = <3263>; 387 + exit-latency-us = <6562>; 388 + min-residency-us = <9987>; 389 + }; 390 + }; 391 + }; 392 + 393 + firmware { 394 + scm: scm { 395 + compatible = "qcom,scm-sc8280xp", "qcom,scm"; 396 + }; 397 + }; 398 + 399 + aggre1_noc: interconnect-aggre1-noc { 400 + compatible = "qcom,sc8280xp-aggre1-noc"; 401 + #interconnect-cells = <2>; 402 + qcom,bcm-voters = <&apps_bcm_voter>; 403 + }; 404 + 405 + aggre2_noc: interconnect-aggre2-noc { 406 + compatible = "qcom,sc8280xp-aggre2-noc"; 407 + #interconnect-cells = <2>; 408 + qcom,bcm-voters = <&apps_bcm_voter>; 409 + }; 410 + 411 + clk_virt: interconnect-clk-virt { 412 + compatible = "qcom,sc8280xp-clk-virt"; 413 + #interconnect-cells = <2>; 414 + qcom,bcm-voters = <&apps_bcm_voter>; 415 + }; 416 + 417 + config_noc: interconnect-config-noc { 418 + compatible = "qcom,sc8280xp-config-noc"; 419 + #interconnect-cells = <2>; 420 + qcom,bcm-voters = <&apps_bcm_voter>; 421 + }; 422 + 423 + dc_noc: interconnect-dc-noc { 424 + compatible = "qcom,sc8280xp-dc-noc"; 425 + #interconnect-cells = <2>; 426 + qcom,bcm-voters = <&apps_bcm_voter>; 427 + }; 428 + 429 + gem_noc: interconnect-gem-noc { 430 + compatible = "qcom,sc8280xp-gem-noc"; 431 + #interconnect-cells = <2>; 432 + qcom,bcm-voters = <&apps_bcm_voter>; 433 + }; 434 + 435 + lpass_noc: interconnect-lpass-ag-noc { 436 + compatible = "qcom,sc8280xp-lpass-ag-noc"; 437 + #interconnect-cells = <2>; 438 + qcom,bcm-voters = <&apps_bcm_voter>; 439 + }; 440 + 441 + mc_virt: interconnect-mc-virt { 442 + compatible = "qcom,sc8280xp-mc-virt"; 443 + #interconnect-cells = <2>; 444 + qcom,bcm-voters = <&apps_bcm_voter>; 445 + }; 446 + 447 + mmss_noc: interconnect-mmss-noc { 448 + compatible = "qcom,sc8280xp-mmss-noc"; 449 + #interconnect-cells = <2>; 450 + qcom,bcm-voters = <&apps_bcm_voter>; 451 + }; 452 + 453 + nspa_noc: interconnect-nspa-noc { 454 + compatible = "qcom,sc8280xp-nspa-noc"; 455 + #interconnect-cells = <2>; 456 + qcom,bcm-voters = <&apps_bcm_voter>; 457 + }; 458 + 459 + nspb_noc: interconnect-nspb-noc { 460 + compatible = "qcom,sc8280xp-nspb-noc"; 461 + #interconnect-cells = <2>; 462 + qcom,bcm-voters = <&apps_bcm_voter>; 463 + }; 464 + 465 + system_noc: interconnect-system-noc { 466 + compatible = "qcom,sc8280xp-system-noc"; 467 + #interconnect-cells = <2>; 468 + qcom,bcm-voters = <&apps_bcm_voter>; 469 + }; 470 + 471 + memory@80000000 { 472 + device_type = "memory"; 473 + /* We expect the bootloader to fill in the size */ 474 + reg = <0x0 0x80000000 0x0 0x0>; 475 + }; 476 + 477 + pmu { 478 + compatible = "arm,armv8-pmuv3"; 479 + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 480 + }; 481 + 482 + psci { 483 + compatible = "arm,psci-1.0"; 484 + method = "smc"; 485 + 486 + CPU_PD0: cpu0 { 487 + #power-domain-cells = <0>; 488 + power-domains = <&CLUSTER_PD>; 489 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 490 + }; 491 + 492 + CPU_PD1: cpu1 { 493 + #power-domain-cells = <0>; 494 + power-domains = <&CLUSTER_PD>; 495 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 496 + }; 497 + 498 + CPU_PD2: cpu2 { 499 + #power-domain-cells = <0>; 500 + power-domains = <&CLUSTER_PD>; 501 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 502 + }; 503 + 504 + CPU_PD3: cpu3 { 505 + #power-domain-cells = <0>; 506 + power-domains = <&CLUSTER_PD>; 507 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 508 + }; 509 + 510 + CPU_PD4: cpu4 { 511 + #power-domain-cells = <0>; 512 + power-domains = <&CLUSTER_PD>; 513 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 514 + }; 515 + 516 + CPU_PD5: cpu5 { 517 + #power-domain-cells = <0>; 518 + power-domains = <&CLUSTER_PD>; 519 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 520 + }; 521 + 522 + CPU_PD6: cpu6 { 523 + #power-domain-cells = <0>; 524 + power-domains = <&CLUSTER_PD>; 525 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 526 + }; 527 + 528 + CPU_PD7: cpu7 { 529 + #power-domain-cells = <0>; 530 + power-domains = <&CLUSTER_PD>; 531 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 532 + }; 533 + 534 + CLUSTER_PD: cpu-cluster0 { 535 + #power-domain-cells = <0>; 536 + domain-idle-states = <&CLUSTER_SLEEP_0>; 537 + }; 538 + }; 539 + 540 + qup_opp_table_100mhz: qup-100mhz-opp-table { 541 + compatible = "operating-points-v2"; 542 + 543 + opp-75000000 { 544 + opp-hz = /bits/ 64 <75000000>; 545 + required-opps = <&rpmhpd_opp_low_svs>; 546 + }; 547 + 548 + opp-100000000 { 549 + opp-hz = /bits/ 64 <100000000>; 550 + required-opps = <&rpmhpd_opp_svs>; 551 + }; 552 + }; 553 + 554 + reserved-memory { 555 + #address-cells = <2>; 556 + #size-cells = <2>; 557 + ranges; 558 + 559 + reserved-region@80000000 { 560 + reg = <0 0x80000000 0 0x860000>; 561 + no-map; 562 + }; 563 + 564 + cmd_db: cmd-db-region@80860000 { 565 + compatible = "qcom,cmd-db"; 566 + reg = <0 0x80860000 0 0x20000>; 567 + no-map; 568 + }; 569 + 570 + reserved-region@80880000 { 571 + reg = <0 0x80880000 0 0x80000>; 572 + no-map; 573 + }; 574 + 575 + smem_mem: smem-region@80900000 { 576 + compatible = "qcom,smem"; 577 + reg = <0 0x80900000 0 0x200000>; 578 + no-map; 579 + hwlocks = <&tcsr_mutex 3>; 580 + }; 581 + 582 + reserved-region@80b00000 { 583 + reg = <0 0x80b00000 0 0x100000>; 584 + no-map; 585 + }; 586 + 587 + reserved-region@83b00000 { 588 + reg = <0 0x83b00000 0 0x1700000>; 589 + no-map; 590 + }; 591 + 592 + reserved-region@85b00000 { 593 + reg = <0 0x85b00000 0 0xc00000>; 594 + no-map; 595 + }; 596 + 597 + pil_adsp_mem: adsp-region@86c00000 { 598 + reg = <0 0x86c00000 0 0x2000000>; 599 + no-map; 600 + }; 601 + 602 + pil_nsp0_mem: cdsp0-region@8a100000 { 603 + reg = <0 0x8a100000 0 0x1e00000>; 604 + no-map; 605 + }; 606 + 607 + pil_nsp1_mem: cdsp1-region@8c600000 { 608 + reg = <0 0x8c600000 0 0x1e00000>; 609 + no-map; 610 + }; 611 + 612 + reserved-region@aeb00000 { 613 + reg = <0 0xaeb00000 0 0x16600000>; 614 + no-map; 615 + }; 616 + }; 617 + 618 + smp2p-adsp { 619 + compatible = "qcom,smp2p"; 620 + qcom,smem = <443>, <429>; 621 + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 622 + IPCC_MPROC_SIGNAL_SMP2P 623 + IRQ_TYPE_EDGE_RISING>; 624 + mboxes = <&ipcc IPCC_CLIENT_LPASS 625 + IPCC_MPROC_SIGNAL_SMP2P>; 626 + 627 + qcom,local-pid = <0>; 628 + qcom,remote-pid = <2>; 629 + 630 + smp2p_adsp_out: master-kernel { 631 + qcom,entry-name = "master-kernel"; 632 + #qcom,smem-state-cells = <1>; 633 + }; 634 + 635 + smp2p_adsp_in: slave-kernel { 636 + qcom,entry-name = "slave-kernel"; 637 + interrupt-controller; 638 + #interrupt-cells = <2>; 639 + }; 640 + }; 641 + 642 + smp2p-nsp0 { 643 + compatible = "qcom,smp2p"; 644 + qcom,smem = <94>, <432>; 645 + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 646 + IPCC_MPROC_SIGNAL_SMP2P 647 + IRQ_TYPE_EDGE_RISING>; 648 + mboxes = <&ipcc IPCC_CLIENT_CDSP 649 + IPCC_MPROC_SIGNAL_SMP2P>; 650 + 651 + qcom,local-pid = <0>; 652 + qcom,remote-pid = <5>; 653 + 654 + smp2p_nsp0_out: master-kernel { 655 + qcom,entry-name = "master-kernel"; 656 + #qcom,smem-state-cells = <1>; 657 + }; 658 + 659 + smp2p_nsp0_in: slave-kernel { 660 + qcom,entry-name = "slave-kernel"; 661 + interrupt-controller; 662 + #interrupt-cells = <2>; 663 + }; 664 + }; 665 + 666 + smp2p-nsp1 { 667 + compatible = "qcom,smp2p"; 668 + qcom,smem = <617>, <616>; 669 + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 670 + IPCC_MPROC_SIGNAL_SMP2P 671 + IRQ_TYPE_EDGE_RISING>; 672 + mboxes = <&ipcc IPCC_CLIENT_NSP1 673 + IPCC_MPROC_SIGNAL_SMP2P>; 674 + 675 + qcom,local-pid = <0>; 676 + qcom,remote-pid = <12>; 677 + 678 + smp2p_nsp1_out: master-kernel { 679 + qcom,entry-name = "master-kernel"; 680 + #qcom,smem-state-cells = <1>; 681 + }; 682 + 683 + smp2p_nsp1_in: slave-kernel { 684 + qcom,entry-name = "slave-kernel"; 685 + interrupt-controller; 686 + #interrupt-cells = <2>; 687 + }; 688 + }; 689 + 690 + soc: soc@0 { 691 + compatible = "simple-bus"; 692 + #address-cells = <2>; 693 + #size-cells = <2>; 694 + ranges = <0 0 0 0 0x10 0>; 695 + dma-ranges = <0 0 0 0 0x10 0>; 696 + 697 + gcc: clock-controller@100000 { 698 + compatible = "qcom,gcc-sc8280xp"; 699 + reg = <0x0 0x00100000 0x0 0x1f0000>; 700 + #clock-cells = <1>; 701 + #reset-cells = <1>; 702 + #power-domain-cells = <1>; 703 + clocks = <&rpmhcc RPMH_CXO_CLK>, 704 + <&sleep_clk>, 705 + <0>, 706 + <0>, 707 + <0>, 708 + <0>, 709 + <0>, 710 + <0>, 711 + <&usb_0_ssphy>, 712 + <0>, 713 + <0>, 714 + <0>, 715 + <0>, 716 + <0>, 717 + <0>, 718 + <0>, 719 + <&usb_1_ssphy>, 720 + <0>, 721 + <0>, 722 + <0>, 723 + <0>, 724 + <0>, 725 + <0>, 726 + <0>, 727 + <0>, 728 + <0>, 729 + <0>, 730 + <0>, 731 + <0>, 732 + <0>, 733 + <0>, 734 + <0>, 735 + <0>; 736 + power-domains = <&rpmhpd SC8280XP_CX>; 737 + }; 738 + 739 + ipcc: mailbox@408000 { 740 + compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 741 + reg = <0 0x00408000 0 0x1000>; 742 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 743 + interrupt-controller; 744 + #interrupt-cells = <3>; 745 + #mbox-cells = <2>; 746 + }; 747 + 748 + qup2: geniqup@8c0000 { 749 + compatible = "qcom,geni-se-qup"; 750 + reg = <0 0x008c0000 0 0x2000>; 751 + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 752 + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 753 + clock-names = "m-ahb", "s-ahb"; 754 + iommus = <&apps_smmu 0xa3 0>; 755 + 756 + #address-cells = <2>; 757 + #size-cells = <2>; 758 + ranges; 759 + 760 + status = "disabled"; 761 + 762 + qup2_uart17: serial@884000 { 763 + compatible = "qcom,geni-uart"; 764 + reg = <0 0x00884000 0 0x4000>; 765 + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 766 + clock-names = "se"; 767 + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 768 + operating-points-v2 = <&qup_opp_table_100mhz>; 769 + power-domains = <&rpmhpd SC8280XP_CX>; 770 + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 771 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 772 + interconnect-names = "qup-core", "qup-config"; 773 + status = "disabled"; 774 + }; 775 + 776 + qup2_i2c5: i2c@894000 { 777 + compatible = "qcom,geni-i2c"; 778 + reg = <0 0x00894000 0 0x4000>; 779 + clock-names = "se"; 780 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 781 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 782 + #address-cells = <1>; 783 + #size-cells = <0>; 784 + power-domains = <&rpmhpd SC8280XP_CX>; 785 + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 786 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 787 + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 788 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 789 + status = "disabled"; 790 + }; 791 + }; 792 + 793 + qup0: geniqup@9c0000 { 794 + compatible = "qcom,geni-se-qup"; 795 + reg = <0 0x009c0000 0 0x6000>; 796 + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 797 + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 798 + clock-names = "m-ahb", "s-ahb"; 799 + iommus = <&apps_smmu 0x563 0>; 800 + 801 + #address-cells = <2>; 802 + #size-cells = <2>; 803 + ranges; 804 + 805 + status = "disabled"; 806 + 807 + qup0_i2c4: i2c@990000 { 808 + compatible = "qcom,geni-i2c"; 809 + reg = <0 0x00990000 0 0x4000>; 810 + clock-names = "se"; 811 + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 812 + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 813 + #address-cells = <1>; 814 + #size-cells = <0>; 815 + power-domains = <&rpmhpd SC8280XP_CX>; 816 + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 817 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 818 + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 819 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 820 + status = "disabled"; 821 + }; 822 + }; 823 + 824 + qup1: geniqup@ac0000 { 825 + compatible = "qcom,geni-se-qup"; 826 + reg = <0 0x00ac0000 0 0x6000>; 827 + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 828 + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 829 + clock-names = "m-ahb", "s-ahb"; 830 + iommus = <&apps_smmu 0x83 0>; 831 + 832 + #address-cells = <2>; 833 + #size-cells = <2>; 834 + ranges; 835 + 836 + status = "disabled"; 837 + }; 838 + 839 + ufs_mem_hc: ufs@1d84000 { 840 + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 841 + "jedec,ufs-2.0"; 842 + reg = <0 0x01d84000 0 0x3000>; 843 + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 844 + phys = <&ufs_mem_phy_lanes>; 845 + phy-names = "ufsphy"; 846 + lanes-per-direction = <2>; 847 + #reset-cells = <1>; 848 + resets = <&gcc GCC_UFS_PHY_BCR>; 849 + reset-names = "rst"; 850 + 851 + power-domains = <&gcc UFS_PHY_GDSC>; 852 + required-opps = <&rpmhpd_opp_nom>; 853 + 854 + iommus = <&apps_smmu 0xe0 0x0>; 855 + 856 + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 857 + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 858 + <&gcc GCC_UFS_PHY_AHB_CLK>, 859 + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 860 + <&rpmhcc RPMH_CXO_CLK>, 861 + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 862 + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 863 + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 864 + clock-names = "core_clk", 865 + "bus_aggr_clk", 866 + "iface_clk", 867 + "core_clk_unipro", 868 + "ref_clk", 869 + "tx_lane0_sync_clk", 870 + "rx_lane0_sync_clk", 871 + "rx_lane1_sync_clk"; 872 + freq-table-hz = <75000000 300000000>, 873 + <0 0>, 874 + <0 0>, 875 + <75000000 300000000>, 876 + <0 0>, 877 + <0 0>, 878 + <0 0>, 879 + <0 0>; 880 + status = "disabled"; 881 + }; 882 + 883 + ufs_mem_phy: phy@1d87000 { 884 + compatible = "qcom,sc8280xp-qmp-ufs-phy"; 885 + reg = <0 0x01d87000 0 0xe10>; 886 + #address-cells = <2>; 887 + #size-cells = <2>; 888 + ranges; 889 + clock-names = "ref", 890 + "ref_aux"; 891 + clocks = <&rpmhcc RPMH_CXO_CLK>, 892 + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 893 + 894 + resets = <&ufs_mem_hc 0>; 895 + reset-names = "ufsphy"; 896 + status = "disabled"; 897 + 898 + ufs_mem_phy_lanes: phy@1d87400 { 899 + reg = <0 0x01d87400 0 0x108>, 900 + <0 0x01d87600 0 0x1e0>, 901 + <0 0x01d87c00 0 0x1dc>, 902 + <0 0x01d87800 0 0x108>, 903 + <0 0x01d87a00 0 0x1e0>; 904 + #phy-cells = <0>; 905 + }; 906 + }; 907 + 908 + ufs_card_hc: ufs@1da4000 { 909 + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 910 + "jedec,ufs-2.0"; 911 + reg = <0 0x01da4000 0 0x3000>; 912 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 913 + phys = <&ufs_card_phy_lanes>; 914 + phy-names = "ufsphy"; 915 + lanes-per-direction = <2>; 916 + #reset-cells = <1>; 917 + resets = <&gcc GCC_UFS_CARD_BCR>; 918 + reset-names = "rst"; 919 + 920 + power-domains = <&gcc UFS_CARD_GDSC>; 921 + 922 + iommus = <&apps_smmu 0x4a0 0x0>; 923 + 924 + clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 925 + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 926 + <&gcc GCC_UFS_CARD_AHB_CLK>, 927 + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 928 + <&rpmhcc RPMH_CXO_CLK>, 929 + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 930 + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 931 + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 932 + clock-names = "core_clk", 933 + "bus_aggr_clk", 934 + "iface_clk", 935 + "core_clk_unipro", 936 + "ref_clk", 937 + "tx_lane0_sync_clk", 938 + "rx_lane0_sync_clk", 939 + "rx_lane1_sync_clk"; 940 + freq-table-hz = <75000000 300000000>, 941 + <0 0>, 942 + <0 0>, 943 + <75000000 300000000>, 944 + <0 0>, 945 + <0 0>, 946 + <0 0>, 947 + <0 0>; 948 + status = "disabled"; 949 + }; 950 + 951 + ufs_card_phy: phy@1da7000 { 952 + compatible = "qcom,sc8280xp-qmp-ufs-phy"; 953 + reg = <0 0x01da7000 0 0xe10>; 954 + #address-cells = <2>; 955 + #size-cells = <2>; 956 + ranges; 957 + clock-names = "ref", 958 + "ref_aux"; 959 + clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 960 + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 961 + 962 + resets = <&ufs_card_hc 0>; 963 + reset-names = "ufsphy"; 964 + 965 + status = "disabled"; 966 + 967 + ufs_card_phy_lanes: phy@1da7400 { 968 + reg = <0 0x01da7400 0 0x108>, 969 + <0 0x01da7600 0 0x1e0>, 970 + <0 0x01da7c00 0 0x1dc>, 971 + <0 0x01da7800 0 0x108>, 972 + <0 0x01da7a00 0 0x1e0>; 973 + #phy-cells = <0>; 974 + }; 975 + }; 976 + 977 + tcsr_mutex: hwlock@1f40000 { 978 + compatible = "qcom,tcsr-mutex"; 979 + reg = <0x0 0x01f40000 0x0 0x20000>; 980 + #hwlock-cells = <1>; 981 + }; 982 + 983 + usb_0_hsphy: phy@88e5000 { 984 + compatible = "qcom,sc8280xp-usb-hs-phy", 985 + "qcom,usb-snps-hs-5nm-phy"; 986 + reg = <0 0x088e5000 0 0x400>; 987 + clocks = <&rpmhcc RPMH_CXO_CLK>; 988 + clock-names = "ref"; 989 + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 990 + 991 + #phy-cells = <0>; 992 + 993 + status = "disabled"; 994 + }; 995 + 996 + usb_2_hsphy0: phy@88e7000 { 997 + compatible = "qcom,sc8280xp-usb-hs-phy", 998 + "qcom,usb-snps-hs-5nm-phy"; 999 + reg = <0 0x088e7000 0 0x400>; 1000 + clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 1001 + clock-names = "ref"; 1002 + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 1003 + 1004 + #phy-cells = <0>; 1005 + 1006 + status = "disabled"; 1007 + }; 1008 + 1009 + usb_2_hsphy1: phy@88e8000 { 1010 + compatible = "qcom,sc8280xp-usb-hs-phy", 1011 + "qcom,usb-snps-hs-5nm-phy"; 1012 + reg = <0 0x088e8000 0 0x400>; 1013 + clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 1014 + clock-names = "ref"; 1015 + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 1016 + 1017 + #phy-cells = <0>; 1018 + 1019 + status = "disabled"; 1020 + }; 1021 + 1022 + usb_2_hsphy2: phy@88e9000 { 1023 + compatible = "qcom,sc8280xp-usb-hs-phy", 1024 + "qcom,usb-snps-hs-5nm-phy"; 1025 + reg = <0 0x088e9000 0 0x400>; 1026 + clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 1027 + clock-names = "ref"; 1028 + resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 1029 + 1030 + #phy-cells = <0>; 1031 + 1032 + status = "disabled"; 1033 + }; 1034 + 1035 + usb_2_hsphy3: phy@88ea000 { 1036 + compatible = "qcom,sc8280xp-usb-hs-phy", 1037 + "qcom,usb-snps-hs-5nm-phy"; 1038 + reg = <0 0x088ea000 0 0x400>; 1039 + clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 1040 + clock-names = "ref"; 1041 + resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 1042 + 1043 + #phy-cells = <0>; 1044 + 1045 + status = "disabled"; 1046 + }; 1047 + 1048 + usb_2_qmpphy0: phy-wrapper@88ef000 { 1049 + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 1050 + reg = <0 0x088ef000 0 0x1c8>; 1051 + #address-cells = <2>; 1052 + #size-cells = <2>; 1053 + ranges; 1054 + 1055 + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 1056 + <&rpmhcc RPMH_CXO_CLK>, 1057 + <&gcc GCC_USB3_MP0_CLKREF_CLK>, 1058 + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; 1059 + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1060 + 1061 + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 1062 + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 1063 + reset-names = "phy", "common"; 1064 + 1065 + power-domains = <&gcc USB30_MP_GDSC>; 1066 + 1067 + status = "disabled"; 1068 + 1069 + usb_2_ssphy0: phy@88efe00 { 1070 + reg = <0 0x088efe00 0 0x160>, 1071 + <0 0x088f0000 0 0x1ec>, 1072 + <0 0x088ef200 0 0x1f0>; 1073 + #phy-cells = <0>; 1074 + #clock-cells = <0>; 1075 + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 1076 + clock-names = "pipe0"; 1077 + clock-output-names = "usb2_phy0_pipe_clk"; 1078 + }; 1079 + }; 1080 + 1081 + usb_2_qmpphy1: phy-wrapper@88f1000 { 1082 + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 1083 + reg = <0 0x088f1000 0 0x1c8>; 1084 + #address-cells = <2>; 1085 + #size-cells = <2>; 1086 + ranges; 1087 + 1088 + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 1089 + <&rpmhcc RPMH_CXO_CLK>, 1090 + <&gcc GCC_USB3_MP1_CLKREF_CLK>, 1091 + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; 1092 + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1093 + 1094 + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 1095 + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 1096 + reset-names = "phy", "common"; 1097 + 1098 + power-domains = <&gcc USB30_MP_GDSC>; 1099 + 1100 + status = "disabled"; 1101 + 1102 + usb_2_ssphy1: phy@88f1e00 { 1103 + reg = <0 0x088f1e00 0 0x160>, 1104 + <0 0x088f2000 0 0x1ec>, 1105 + <0 0x088f1200 0 0x1f0>; 1106 + #phy-cells = <0>; 1107 + #clock-cells = <0>; 1108 + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 1109 + clock-names = "pipe0"; 1110 + clock-output-names = "usb2_phy1_pipe_clk"; 1111 + }; 1112 + }; 1113 + 1114 + remoteproc_adsp: remoteproc@3000000 { 1115 + compatible = "qcom,sc8280xp-adsp-pas"; 1116 + reg = <0 0x03000000 0 0x100>; 1117 + 1118 + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1119 + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1120 + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1121 + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1122 + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 1123 + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 1124 + interrupt-names = "wdog", "fatal", "ready", 1125 + "handover", "stop-ack", "shutdown-ack"; 1126 + 1127 + clocks = <&rpmhcc RPMH_CXO_CLK>; 1128 + clock-names = "xo"; 1129 + 1130 + power-domains = <&rpmhpd SC8280XP_LCX>, 1131 + <&rpmhpd SC8280XP_LMX>; 1132 + power-domain-names = "lcx", "lmx"; 1133 + 1134 + memory-region = <&pil_adsp_mem>; 1135 + 1136 + qcom,qmp = <&aoss_qmp>; 1137 + 1138 + qcom,smem-states = <&smp2p_adsp_out 0>; 1139 + qcom,smem-state-names = "stop"; 1140 + 1141 + status = "disabled"; 1142 + 1143 + remoteproc_adsp_glink: glink-edge { 1144 + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1145 + IPCC_MPROC_SIGNAL_GLINK_QMP 1146 + IRQ_TYPE_EDGE_RISING>; 1147 + mboxes = <&ipcc IPCC_CLIENT_LPASS 1148 + IPCC_MPROC_SIGNAL_GLINK_QMP>; 1149 + 1150 + label = "lpass"; 1151 + qcom,remote-pid = <2>; 1152 + }; 1153 + }; 1154 + 1155 + usb_0_qmpphy: phy-wrapper@88ec000 { 1156 + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 1157 + reg = <0 0x088ec000 0 0x1e4>, 1158 + <0 0x088eb000 0 0x40>, 1159 + <0 0x088ed000 0 0x1c8>; 1160 + #address-cells = <2>; 1161 + #size-cells = <2>; 1162 + ranges; 1163 + 1164 + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1165 + <&rpmhcc RPMH_CXO_CLK>, 1166 + <&gcc GCC_USB4_EUD_CLKREF_CLK>, 1167 + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1168 + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1169 + 1170 + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1171 + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1172 + reset-names = "phy", "common"; 1173 + 1174 + power-domains = <&gcc USB30_PRIM_GDSC>; 1175 + 1176 + status = "disabled"; 1177 + 1178 + usb_0_ssphy: usb3-phy@88eb400 { 1179 + reg = <0 0x088eb400 0 0x100>, 1180 + <0 0x088eb600 0 0x3ec>, 1181 + <0 0x088ec400 0 0x1f0>, 1182 + <0 0x088eba00 0 0x100>, 1183 + <0 0x088ebc00 0 0x3ec>, 1184 + <0 0x088ec700 0 0x64>; 1185 + #phy-cells = <0>; 1186 + #clock-cells = <0>; 1187 + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1188 + clock-names = "pipe0"; 1189 + clock-output-names = "usb0_phy_pipe_clk_src"; 1190 + }; 1191 + 1192 + usb_0_dpphy: dp-phy@88ed200 { 1193 + reg = <0 0x088ed200 0 0x200>, 1194 + <0 0x088ed400 0 0x200>, 1195 + <0 0x088eda00 0 0x200>, 1196 + <0 0x088ea600 0 0x200>, 1197 + <0 0x088ea800 0 0x200>; 1198 + #clock-cells = <1>; 1199 + #phy-cells = <0>; 1200 + }; 1201 + }; 1202 + 1203 + usb_1_hsphy: phy@8902000 { 1204 + compatible = "qcom,sc8280xp-usb-hs-phy", 1205 + "qcom,usb-snps-hs-5nm-phy"; 1206 + reg = <0 0x08902000 0 0x400>; 1207 + #phy-cells = <0>; 1208 + 1209 + clocks = <&rpmhcc RPMH_CXO_CLK>; 1210 + clock-names = "ref"; 1211 + 1212 + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1213 + 1214 + status = "disabled"; 1215 + }; 1216 + 1217 + usb_1_qmpphy: phy-wrapper@8904000 { 1218 + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 1219 + reg = <0 0x08904000 0 0x1e4>, 1220 + <0 0x08903000 0 0x40>, 1221 + <0 0x08905000 0 0x1c8>; 1222 + #address-cells = <2>; 1223 + #size-cells = <2>; 1224 + ranges; 1225 + 1226 + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1227 + <&rpmhcc RPMH_CXO_CLK>, 1228 + <&gcc GCC_USB4_CLKREF_CLK>, 1229 + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1230 + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1231 + 1232 + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 1233 + <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 1234 + reset-names = "phy", "common"; 1235 + 1236 + power-domains = <&gcc USB30_SEC_GDSC>; 1237 + 1238 + status = "disabled"; 1239 + 1240 + usb_1_ssphy: usb3-phy@8903400 { 1241 + reg = <0 0x08903400 0 0x100>, 1242 + <0 0x08903c00 0 0x3ec>, 1243 + <0 0x08904400 0 0x1f0>, 1244 + <0 0x08903a00 0 0x100>, 1245 + <0 0x08903c00 0 0x3ec>, 1246 + <0 0x08904200 0 0x18>; 1247 + #phy-cells = <0>; 1248 + #clock-cells = <0>; 1249 + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1250 + clock-names = "pipe0"; 1251 + clock-output-names = "usb1_phy_pipe_clk_src"; 1252 + }; 1253 + 1254 + usb_1_dpphy: dp-phy@8904200 { 1255 + reg = <0 0x08904200 0 0x200>, 1256 + <0 0x08904400 0 0x200>, 1257 + <0 0x08904a00 0 0x200>, 1258 + <0 0x08904600 0 0x200>, 1259 + <0 0x08904800 0 0x200>; 1260 + #clock-cells = <1>; 1261 + #phy-cells = <0>; 1262 + }; 1263 + }; 1264 + 1265 + system-cache-controller@9200000 { 1266 + compatible = "qcom,sc8280xp-llcc"; 1267 + reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; 1268 + reg-names = "llcc_base", "llcc_broadcast_base"; 1269 + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1270 + }; 1271 + 1272 + usb_0: usb@a6f8800 { 1273 + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 1274 + reg = <0 0x0a6f8800 0 0x400>; 1275 + #address-cells = <2>; 1276 + #size-cells = <2>; 1277 + ranges; 1278 + 1279 + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1280 + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1281 + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1282 + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1283 + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1284 + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 1285 + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 1286 + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 1287 + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 1288 + clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", 1289 + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 1290 + 1291 + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1292 + <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1293 + assigned-clock-rates = <19200000>, <200000000>; 1294 + 1295 + interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 1296 + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1297 + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1298 + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 1299 + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1300 + "dm_hs_phy_irq", "ss_phy_irq"; 1301 + 1302 + power-domains = <&gcc USB30_PRIM_GDSC>; 1303 + 1304 + resets = <&gcc GCC_USB30_PRIM_BCR>; 1305 + 1306 + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1307 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 1308 + interconnect-names = "usb-ddr", "apps-usb"; 1309 + 1310 + status = "disabled"; 1311 + 1312 + usb_0_dwc3: usb@a600000 { 1313 + compatible = "snps,dwc3"; 1314 + reg = <0 0x0a600000 0 0xcd00>; 1315 + interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1316 + iommus = <&apps_smmu 0x820 0x0>; 1317 + phys = <&usb_0_hsphy>, <&usb_0_ssphy>; 1318 + phy-names = "usb2-phy", "usb3-phy"; 1319 + }; 1320 + }; 1321 + 1322 + usb_1: usb@a8f8800 { 1323 + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 1324 + reg = <0 0x0a8f8800 0 0x400>; 1325 + #address-cells = <2>; 1326 + #size-cells = <2>; 1327 + ranges; 1328 + 1329 + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, 1330 + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1331 + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1332 + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1333 + <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1334 + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 1335 + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 1336 + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 1337 + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 1338 + clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", 1339 + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 1340 + 1341 + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1342 + <&gcc GCC_USB30_SEC_MASTER_CLK>; 1343 + assigned-clock-rates = <19200000>, <200000000>; 1344 + 1345 + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1346 + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1347 + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 1348 + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 1349 + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1350 + "dm_hs_phy_irq", "ss_phy_irq"; 1351 + 1352 + power-domains = <&gcc USB30_SEC_GDSC>; 1353 + 1354 + resets = <&gcc GCC_USB30_SEC_BCR>; 1355 + 1356 + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 1357 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 1358 + interconnect-names = "usb-ddr", "apps-usb"; 1359 + 1360 + status = "disabled"; 1361 + 1362 + usb_1_dwc3: usb@a800000 { 1363 + compatible = "snps,dwc3"; 1364 + reg = <0 0x0a800000 0 0xcd00>; 1365 + interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1366 + iommus = <&apps_smmu 0x860 0x0>; 1367 + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1368 + phy-names = "usb2-phy", "usb3-phy"; 1369 + }; 1370 + }; 1371 + 1372 + pdc: interrupt-controller@b220000 { 1373 + compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 1374 + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 1375 + qcom,pdc-ranges = <0 480 40>, 1376 + <40 140 14>, 1377 + <54 263 1>, 1378 + <55 306 4>, 1379 + <59 312 3>, 1380 + <62 374 2>, 1381 + <64 434 2>, 1382 + <66 438 3>, 1383 + <69 86 1>, 1384 + <70 520 54>, 1385 + <124 609 28>, 1386 + <159 638 1>, 1387 + <160 720 8>, 1388 + <168 801 1>, 1389 + <169 728 30>, 1390 + <199 416 2>, 1391 + <201 449 1>, 1392 + <202 89 1>, 1393 + <203 451 1>, 1394 + <204 462 1>, 1395 + <205 264 1>, 1396 + <206 579 1>, 1397 + <207 653 1>, 1398 + <208 656 1>, 1399 + <209 659 1>, 1400 + <210 122 1>, 1401 + <211 699 1>, 1402 + <212 705 1>, 1403 + <213 450 1>, 1404 + <214 643 1>, 1405 + <216 646 5>, 1406 + <221 390 5>, 1407 + <226 700 3>, 1408 + <229 240 3>, 1409 + <232 269 1>, 1410 + <233 377 1>, 1411 + <234 372 1>, 1412 + <235 138 1>, 1413 + <236 857 1>, 1414 + <237 860 1>, 1415 + <238 137 1>, 1416 + <239 668 1>, 1417 + <240 366 1>, 1418 + <241 949 1>, 1419 + <242 815 5>, 1420 + <247 769 1>, 1421 + <248 768 1>, 1422 + <249 663 1>, 1423 + <250 799 2>, 1424 + <252 798 1>, 1425 + <253 765 1>, 1426 + <254 763 1>, 1427 + <255 454 1>, 1428 + <258 139 1>, 1429 + <259 786 2>, 1430 + <261 370 2>, 1431 + <263 158 2>; 1432 + #interrupt-cells = <2>; 1433 + interrupt-parent = <&intc>; 1434 + interrupt-controller; 1435 + }; 1436 + 1437 + tsens0: thermal-sensor@c263000 { 1438 + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 1439 + reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1440 + <0 0x0c222000 0 0x8>; /* SROT */ 1441 + #qcom,sensors = <14>; 1442 + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1443 + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1444 + interrupt-names = "uplow", "critical"; 1445 + #thermal-sensor-cells = <1>; 1446 + }; 1447 + 1448 + tsens1: thermal-sensor@c265000 { 1449 + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 1450 + reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1451 + <0 0x0c223000 0 0x8>; /* SROT */ 1452 + #qcom,sensors = <16>; 1453 + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1454 + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1455 + interrupt-names = "uplow", "critical"; 1456 + #thermal-sensor-cells = <1>; 1457 + }; 1458 + 1459 + aoss_qmp: power-controller@c300000 { 1460 + compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 1461 + reg = <0 0x0c300000 0 0x400>; 1462 + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 1463 + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1464 + 1465 + #clock-cells = <0>; 1466 + }; 1467 + 1468 + spmi_bus: spmi@c440000 { 1469 + compatible = "qcom,spmi-pmic-arb"; 1470 + reg = <0 0x0c440000 0 0x1100>, 1471 + <0 0x0c600000 0 0x2000000>, 1472 + <0 0x0e600000 0 0x100000>, 1473 + <0 0x0e700000 0 0xa0000>, 1474 + <0 0x0c40a000 0 0x26000>; 1475 + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1476 + interrupt-names = "periph_irq"; 1477 + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1478 + qcom,ee = <0>; 1479 + qcom,channel = <0>; 1480 + #address-cells = <1>; 1481 + #size-cells = <1>; 1482 + interrupt-controller; 1483 + #interrupt-cells = <4>; 1484 + }; 1485 + 1486 + tlmm: pinctrl@f100000 { 1487 + compatible = "qcom,sc8280xp-tlmm"; 1488 + reg = <0 0x0f100000 0 0x300000>; 1489 + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1490 + gpio-controller; 1491 + #gpio-cells = <2>; 1492 + interrupt-controller; 1493 + #interrupt-cells = <2>; 1494 + gpio-ranges = <&tlmm 0 0 230>; 1495 + }; 1496 + 1497 + apps_smmu: iommu@15000000 { 1498 + compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 1499 + reg = <0 0x15000000 0 0x100000>; 1500 + #iommu-cells = <2>; 1501 + #global-interrupts = <2>; 1502 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1503 + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1504 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1505 + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1506 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1507 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1508 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1509 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1510 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1511 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1512 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1513 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1514 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1515 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1516 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1517 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1518 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1519 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1520 + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1521 + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1522 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1523 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1524 + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1525 + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1526 + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1527 + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1528 + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1529 + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1530 + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1531 + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1532 + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1533 + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1534 + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1535 + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1536 + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1537 + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1538 + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1539 + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1540 + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1541 + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1542 + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1543 + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1544 + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1545 + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1546 + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1547 + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1548 + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1549 + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1550 + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1551 + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1552 + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1553 + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1554 + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1555 + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1556 + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1557 + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1558 + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1559 + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1560 + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1561 + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1562 + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1563 + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1564 + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1565 + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1566 + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1567 + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1568 + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1569 + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1570 + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1571 + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1572 + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1573 + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1574 + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1575 + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1576 + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1577 + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1578 + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1579 + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1580 + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1581 + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1582 + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 1583 + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1584 + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1585 + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1586 + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1587 + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 1588 + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1589 + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1590 + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1591 + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1592 + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1593 + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1594 + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1595 + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1596 + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1597 + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 1598 + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1599 + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1600 + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 1601 + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 1602 + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 1603 + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 1604 + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1605 + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 1606 + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 1607 + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 1608 + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 1609 + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 1610 + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 1611 + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 1612 + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 1613 + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 1614 + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 1615 + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 1616 + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 1617 + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 1618 + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 1619 + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 1620 + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 1621 + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 1622 + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 1623 + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 1624 + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 1625 + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 1626 + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 1627 + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 1628 + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 1629 + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 1630 + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 1631 + <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 1632 + }; 1633 + 1634 + intc: interrupt-controller@17a00000 { 1635 + compatible = "arm,gic-v3"; 1636 + interrupt-controller; 1637 + #interrupt-cells = <3>; 1638 + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1639 + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1640 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1641 + #redistributor-regions = <1>; 1642 + redistributor-stride = <0 0x20000>; 1643 + 1644 + #address-cells = <2>; 1645 + #size-cells = <2>; 1646 + ranges; 1647 + 1648 + gic-its@17a40000 { 1649 + compatible = "arm,gic-v3-its"; 1650 + reg = <0 0x17a40000 0 0x20000>; 1651 + msi-controller; 1652 + #msi-cells = <1>; 1653 + }; 1654 + }; 1655 + 1656 + watchdog@17c10000 { 1657 + compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 1658 + reg = <0 0x17c10000 0 0x1000>; 1659 + clocks = <&sleep_clk>; 1660 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1661 + }; 1662 + 1663 + timer@17c20000 { 1664 + compatible = "arm,armv7-timer-mem"; 1665 + reg = <0x0 0x17c20000 0x0 0x1000>; 1666 + #address-cells = <1>; 1667 + #size-cells = <1>; 1668 + 1669 + frame@17c21000 { 1670 + frame-number = <0>; 1671 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1672 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1673 + reg = <0x17c21000 0x1000>, 1674 + <0x17c22000 0x1000>; 1675 + }; 1676 + 1677 + frame@17c23000 { 1678 + frame-number = <1>; 1679 + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1680 + reg = <0x17c23000 0x1000>; 1681 + status = "disabled"; 1682 + }; 1683 + 1684 + frame@17c25000 { 1685 + frame-number = <2>; 1686 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1687 + reg = <0x17c25000 0x1000>; 1688 + status = "disabled"; 1689 + }; 1690 + 1691 + frame@17c27000 { 1692 + frame-number = <3>; 1693 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1694 + reg = <0x17c26000 0x1000>; 1695 + status = "disabled"; 1696 + }; 1697 + 1698 + frame@17c29000 { 1699 + frame-number = <4>; 1700 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1701 + reg = <0x17c29000 0x1000>; 1702 + status = "disabled"; 1703 + }; 1704 + 1705 + frame@17c2b000 { 1706 + frame-number = <5>; 1707 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1708 + reg = <0x17c2b000 0x1000>; 1709 + status = "disabled"; 1710 + }; 1711 + 1712 + frame@17c2d000 { 1713 + frame-number = <6>; 1714 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1715 + reg = <0x17c2d000 0x1000>; 1716 + status = "disabled"; 1717 + }; 1718 + }; 1719 + 1720 + apps_rsc: rsc@18200000 { 1721 + compatible = "qcom,rpmh-rsc"; 1722 + reg = <0x0 0x18200000 0x0 0x10000>, 1723 + <0x0 0x18210000 0x0 0x10000>, 1724 + <0x0 0x18220000 0x0 0x10000>; 1725 + reg-names = "drv-0", "drv-1", "drv-2"; 1726 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1727 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1728 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1729 + qcom,tcs-offset = <0xd00>; 1730 + qcom,drv-id = <2>; 1731 + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1732 + <WAKE_TCS 3>, <CONTROL_TCS 1>; 1733 + label = "apps_rsc"; 1734 + 1735 + apps_bcm_voter: bcm-voter { 1736 + compatible = "qcom,bcm-voter"; 1737 + }; 1738 + 1739 + rpmhcc: clock-controller { 1740 + compatible = "qcom,sc8280xp-rpmh-clk"; 1741 + #clock-cells = <1>; 1742 + clock-names = "xo"; 1743 + clocks = <&xo_board_clk>; 1744 + }; 1745 + 1746 + rpmhpd: power-controller { 1747 + compatible = "qcom,sc8280xp-rpmhpd"; 1748 + #power-domain-cells = <1>; 1749 + operating-points-v2 = <&rpmhpd_opp_table>; 1750 + 1751 + rpmhpd_opp_table: opp-table { 1752 + compatible = "operating-points-v2"; 1753 + 1754 + rpmhpd_opp_ret: opp1 { 1755 + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1756 + }; 1757 + 1758 + rpmhpd_opp_min_svs: opp2 { 1759 + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1760 + }; 1761 + 1762 + rpmhpd_opp_low_svs: opp3 { 1763 + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1764 + }; 1765 + 1766 + rpmhpd_opp_svs: opp4 { 1767 + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1768 + }; 1769 + 1770 + rpmhpd_opp_svs_l1: opp5 { 1771 + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1772 + }; 1773 + 1774 + rpmhpd_opp_nom: opp6 { 1775 + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1776 + }; 1777 + 1778 + rpmhpd_opp_nom_l1: opp7 { 1779 + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1780 + }; 1781 + 1782 + rpmhpd_opp_nom_l2: opp8 { 1783 + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1784 + }; 1785 + 1786 + rpmhpd_opp_turbo: opp9 { 1787 + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1788 + }; 1789 + 1790 + rpmhpd_opp_turbo_l1: opp10 { 1791 + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1792 + }; 1793 + }; 1794 + }; 1795 + }; 1796 + 1797 + cpufreq_hw: cpufreq@18591000 { 1798 + compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 1799 + reg = <0 0x18591000 0 0x1000>, 1800 + <0 0x18592000 0 0x1000>; 1801 + reg-names = "freq-domain0", "freq-domain1"; 1802 + 1803 + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1804 + clock-names = "xo", "alternate"; 1805 + 1806 + #freq-domain-cells = <1>; 1807 + }; 1808 + 1809 + remoteproc_nsp0: remoteproc@1b300000 { 1810 + compatible = "qcom,sc8280xp-nsp0-pas"; 1811 + reg = <0 0x1b300000 0 0x100>; 1812 + 1813 + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1814 + <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 1815 + <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 1816 + <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 1817 + <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 1818 + interrupt-names = "wdog", "fatal", "ready", 1819 + "handover", "stop-ack"; 1820 + 1821 + clocks = <&rpmhcc RPMH_CXO_CLK>; 1822 + clock-names = "xo"; 1823 + 1824 + power-domains = <&rpmhpd SC8280XP_NSP>; 1825 + power-domain-names = "nsp"; 1826 + 1827 + memory-region = <&pil_nsp0_mem>; 1828 + 1829 + qcom,smem-states = <&smp2p_nsp0_out 0>; 1830 + qcom,smem-state-names = "stop"; 1831 + 1832 + interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 1833 + 1834 + status = "disabled"; 1835 + 1836 + glink-edge { 1837 + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1838 + IPCC_MPROC_SIGNAL_GLINK_QMP 1839 + IRQ_TYPE_EDGE_RISING>; 1840 + mboxes = <&ipcc IPCC_CLIENT_CDSP 1841 + IPCC_MPROC_SIGNAL_GLINK_QMP>; 1842 + 1843 + label = "nsp0"; 1844 + qcom,remote-pid = <5>; 1845 + 1846 + fastrpc { 1847 + compatible = "qcom,fastrpc"; 1848 + qcom,glink-channels = "fastrpcglink-apps-dsp"; 1849 + label = "cdsp"; 1850 + #address-cells = <1>; 1851 + #size-cells = <0>; 1852 + 1853 + compute-cb@1 { 1854 + compatible = "qcom,fastrpc-compute-cb"; 1855 + reg = <1>; 1856 + iommus = <&apps_smmu 0x3181 0x0420>; 1857 + }; 1858 + 1859 + compute-cb@2 { 1860 + compatible = "qcom,fastrpc-compute-cb"; 1861 + reg = <2>; 1862 + iommus = <&apps_smmu 0x3182 0x0420>; 1863 + }; 1864 + 1865 + compute-cb@3 { 1866 + compatible = "qcom,fastrpc-compute-cb"; 1867 + reg = <3>; 1868 + iommus = <&apps_smmu 0x3183 0x0420>; 1869 + }; 1870 + 1871 + compute-cb@4 { 1872 + compatible = "qcom,fastrpc-compute-cb"; 1873 + reg = <4>; 1874 + iommus = <&apps_smmu 0x3184 0x0420>; 1875 + }; 1876 + 1877 + compute-cb@5 { 1878 + compatible = "qcom,fastrpc-compute-cb"; 1879 + reg = <5>; 1880 + iommus = <&apps_smmu 0x3185 0x0420>; 1881 + }; 1882 + 1883 + compute-cb@6 { 1884 + compatible = "qcom,fastrpc-compute-cb"; 1885 + reg = <6>; 1886 + iommus = <&apps_smmu 0x3186 0x0420>; 1887 + }; 1888 + 1889 + compute-cb@7 { 1890 + compatible = "qcom,fastrpc-compute-cb"; 1891 + reg = <7>; 1892 + iommus = <&apps_smmu 0x3187 0x0420>; 1893 + }; 1894 + 1895 + compute-cb@8 { 1896 + compatible = "qcom,fastrpc-compute-cb"; 1897 + reg = <8>; 1898 + iommus = <&apps_smmu 0x3188 0x0420>; 1899 + }; 1900 + 1901 + compute-cb@9 { 1902 + compatible = "qcom,fastrpc-compute-cb"; 1903 + reg = <9>; 1904 + iommus = <&apps_smmu 0x318b 0x0420>; 1905 + }; 1906 + 1907 + compute-cb@10 { 1908 + compatible = "qcom,fastrpc-compute-cb"; 1909 + reg = <10>; 1910 + iommus = <&apps_smmu 0x318b 0x0420>; 1911 + }; 1912 + 1913 + compute-cb@11 { 1914 + compatible = "qcom,fastrpc-compute-cb"; 1915 + reg = <11>; 1916 + iommus = <&apps_smmu 0x318c 0x0420>; 1917 + }; 1918 + 1919 + compute-cb@12 { 1920 + compatible = "qcom,fastrpc-compute-cb"; 1921 + reg = <12>; 1922 + iommus = <&apps_smmu 0x318d 0x0420>; 1923 + }; 1924 + 1925 + compute-cb@13 { 1926 + compatible = "qcom,fastrpc-compute-cb"; 1927 + reg = <13>; 1928 + iommus = <&apps_smmu 0x318e 0x0420>; 1929 + }; 1930 + 1931 + compute-cb@14 { 1932 + compatible = "qcom,fastrpc-compute-cb"; 1933 + reg = <14>; 1934 + iommus = <&apps_smmu 0x318f 0x0420>; 1935 + }; 1936 + }; 1937 + }; 1938 + }; 1939 + 1940 + remoteproc_nsp1: remoteproc@21300000 { 1941 + compatible = "qcom,sc8280xp-nsp1-pas"; 1942 + reg = <0 0x21300000 0 0x100>; 1943 + 1944 + interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 1945 + <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 1946 + <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 1947 + <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 1948 + <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 1949 + interrupt-names = "wdog", "fatal", "ready", 1950 + "handover", "stop-ack"; 1951 + 1952 + clocks = <&rpmhcc RPMH_CXO_CLK>; 1953 + clock-names = "xo"; 1954 + 1955 + power-domains = <&rpmhpd SC8280XP_NSP>; 1956 + power-domain-names = "nsp"; 1957 + 1958 + memory-region = <&pil_nsp1_mem>; 1959 + 1960 + qcom,smem-states = <&smp2p_nsp1_out 0>; 1961 + qcom,smem-state-names = "stop"; 1962 + 1963 + interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 1964 + 1965 + status = "disabled"; 1966 + 1967 + glink-edge { 1968 + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 1969 + IPCC_MPROC_SIGNAL_GLINK_QMP 1970 + IRQ_TYPE_EDGE_RISING>; 1971 + mboxes = <&ipcc IPCC_CLIENT_NSP1 1972 + IPCC_MPROC_SIGNAL_GLINK_QMP>; 1973 + 1974 + label = "nsp1"; 1975 + qcom,remote-pid = <12>; 1976 + }; 1977 + }; 1978 + }; 1979 + 1980 + thermal-zones { 1981 + cpu0-thermal { 1982 + polling-delay-passive = <250>; 1983 + polling-delay = <1000>; 1984 + 1985 + thermal-sensors = <&tsens0 1>; 1986 + 1987 + trips { 1988 + cpu-crit { 1989 + temperature = <110000>; 1990 + hysteresis = <1000>; 1991 + type = "critical"; 1992 + }; 1993 + }; 1994 + }; 1995 + 1996 + cpu1-thermal { 1997 + polling-delay-passive = <250>; 1998 + polling-delay = <1000>; 1999 + 2000 + thermal-sensors = <&tsens0 2>; 2001 + 2002 + trips { 2003 + cpu-crit { 2004 + temperature = <110000>; 2005 + hysteresis = <1000>; 2006 + type = "critical"; 2007 + }; 2008 + }; 2009 + }; 2010 + 2011 + cpu2-thermal { 2012 + polling-delay-passive = <250>; 2013 + polling-delay = <1000>; 2014 + 2015 + thermal-sensors = <&tsens0 3>; 2016 + 2017 + trips { 2018 + cpu-crit { 2019 + temperature = <110000>; 2020 + hysteresis = <1000>; 2021 + type = "critical"; 2022 + }; 2023 + }; 2024 + }; 2025 + 2026 + cpu3-thermal { 2027 + polling-delay-passive = <250>; 2028 + polling-delay = <1000>; 2029 + 2030 + thermal-sensors = <&tsens0 4>; 2031 + 2032 + trips { 2033 + cpu-crit { 2034 + temperature = <110000>; 2035 + hysteresis = <1000>; 2036 + type = "critical"; 2037 + }; 2038 + }; 2039 + }; 2040 + 2041 + cpu4-thermal { 2042 + polling-delay-passive = <250>; 2043 + polling-delay = <1000>; 2044 + 2045 + thermal-sensors = <&tsens0 5>; 2046 + 2047 + trips { 2048 + cpu-crit { 2049 + temperature = <110000>; 2050 + hysteresis = <1000>; 2051 + type = "critical"; 2052 + }; 2053 + }; 2054 + }; 2055 + 2056 + cpu5-thermal { 2057 + polling-delay-passive = <250>; 2058 + polling-delay = <1000>; 2059 + 2060 + thermal-sensors = <&tsens0 6>; 2061 + 2062 + trips { 2063 + cpu-crit { 2064 + temperature = <110000>; 2065 + hysteresis = <1000>; 2066 + type = "critical"; 2067 + }; 2068 + }; 2069 + }; 2070 + 2071 + cpu6-thermal { 2072 + polling-delay-passive = <250>; 2073 + polling-delay = <1000>; 2074 + 2075 + thermal-sensors = <&tsens0 7>; 2076 + 2077 + trips { 2078 + cpu-crit { 2079 + temperature = <110000>; 2080 + hysteresis = <1000>; 2081 + type = "critical"; 2082 + }; 2083 + }; 2084 + }; 2085 + 2086 + cpu7-thermal { 2087 + polling-delay-passive = <250>; 2088 + polling-delay = <1000>; 2089 + 2090 + thermal-sensors = <&tsens0 8>; 2091 + 2092 + trips { 2093 + cpu-crit { 2094 + temperature = <110000>; 2095 + hysteresis = <1000>; 2096 + type = "critical"; 2097 + }; 2098 + }; 2099 + }; 2100 + 2101 + cluster0-thermal { 2102 + polling-delay-passive = <250>; 2103 + polling-delay = <1000>; 2104 + 2105 + thermal-sensors = <&tsens0 9>; 2106 + 2107 + trips { 2108 + cpu-crit { 2109 + temperature = <110000>; 2110 + hysteresis = <1000>; 2111 + type = "critical"; 2112 + }; 2113 + }; 2114 + }; 2115 + 2116 + mem-thermal { 2117 + polling-delay-passive = <250>; 2118 + polling-delay = <1000>; 2119 + 2120 + thermal-sensors = <&tsens1 15>; 2121 + 2122 + trips { 2123 + trip-point0 { 2124 + temperature = <90000>; 2125 + hysteresis = <2000>; 2126 + type = "hot"; 2127 + }; 2128 + }; 2129 + }; 2130 + }; 2131 + 2132 + timer { 2133 + compatible = "arm,armv8-timer"; 2134 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2135 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2136 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2137 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2138 + }; 2139 + };
+461
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2021, Linaro Ltd. 4 + * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org> 5 + * Copyright (c) 2020, AngeloGioacchino Del Regno 6 + * <angelogioacchino.delregno@somainline.org> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "sdm660.dtsi" 12 + #include "pm660.dtsi" 13 + #include "pm660l.dtsi" 14 + 15 + / { 16 + model = "Inforce 6560 Single Board Computer"; 17 + compatible = "inforce,ifc6560", "qcom,sda660"; 18 + chassis-type = "embedded"; /* SBC */ 19 + 20 + aliases { 21 + serial0 = &blsp1_uart2; 22 + serial1 = &blsp2_uart1; 23 + }; 24 + 25 + chosen { 26 + stdout-path = "serial0:115200n8"; 27 + }; 28 + 29 + gpio-keys { 30 + compatible = "gpio-keys"; 31 + 32 + volup { 33 + label = "Volume Up"; 34 + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; 35 + linux,code = <KEY_VOLUMEUP>; 36 + debounce-interval = <15>; 37 + }; 38 + }; 39 + 40 + /* 41 + * Until we hook up type-c detection, we 42 + * have to stick with this. But it works. 43 + */ 44 + extcon_usb: extcon-usb { 45 + compatible = "linux,extcon-usb-gpio"; 46 + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; 47 + }; 48 + 49 + hdmi-out { 50 + compatible = "hdmi-connector"; 51 + type = "a"; 52 + 53 + port { 54 + hdmi_con: endpoint { 55 + remote-endpoint = <&adv7533_out>; 56 + }; 57 + }; 58 + }; 59 + 60 + vph_pwr: vph-pwr-regulator { 61 + compatible = "regulator-fixed"; 62 + regulator-name = "vph_pwr"; 63 + regulator-min-microvolt = <3800000>; 64 + regulator-max-microvolt = <3800000>; 65 + 66 + regulator-always-on; 67 + regulator-boot-on; 68 + }; 69 + 70 + v3p3_bck_bst: v3p3-bck-bst-regulator { 71 + compatible = "regulator-fixed"; 72 + regulator-name = "v3p3_bck_bst"; 73 + 74 + regulator-min-microvolt = <3300000>; 75 + regulator-max-microvolt = <3300000>; 76 + 77 + vin-supply = <&vph_pwr>; 78 + }; 79 + 80 + v1p2_ldo: v1p2-ldo-regulator { 81 + compatible = "regulator-fixed"; 82 + regulator-name = "v1p2_ldo"; 83 + 84 + regulator-min-microvolt = <1200000>; 85 + regulator-max-microvolt = <1200000>; 86 + 87 + vin-supply = <&vph_pwr>; 88 + }; 89 + 90 + v5p0_boost: v5p0-boost-regulator { 91 + compatible = "regulator-fixed"; 92 + regulator-name = "v5p0_boost"; 93 + 94 + regulator-min-microvolt = <5000000>; 95 + regulator-max-microvolt = <5000000>; 96 + 97 + vin-supply = <&vph_pwr>; 98 + }; 99 + }; 100 + 101 + &adsp_pil { 102 + firmware-name = "qcom/ifc6560/adsp.mbn"; 103 + }; 104 + 105 + &blsp_i2c6 { 106 + status = "okay"; 107 + 108 + adv7533: hdmi@39 { 109 + compatible = "adi,adv7535"; 110 + reg = <0x39>, <0x66>; 111 + reg-names = "main", "edid"; 112 + 113 + interrupt-parent = <&pm660l_gpios>; 114 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 115 + 116 + clocks = <&rpmcc RPM_SMD_BB_CLK2>; 117 + clock-names = "cec"; 118 + /* 119 + * Limit to 3 lanes to prevent the bridge from changing amount 120 + * of lanes in the fly. MSM DSI host doesn't like that. 121 + */ 122 + adi,dsi-lanes = <3>; 123 + avdd-supply = <&vreg_l13a_1p8>; 124 + dvdd-supply = <&vreg_l13a_1p8>; 125 + pvdd-supply = <&vreg_l13a_1p8>; 126 + a2vdd-supply = <&vreg_l13a_1p8>; 127 + v3p3-supply = <&v3p3_bck_bst>; 128 + 129 + ports { 130 + #address-cells = <1>; 131 + #size-cells = <0>; 132 + 133 + port@0 { 134 + reg = <0>; 135 + 136 + adv7533_in: endpoint { 137 + remote-endpoint = <&dsi0_out>; 138 + }; 139 + }; 140 + 141 + port@1 { 142 + reg = <1>; 143 + 144 + adv7533_out: endpoint { 145 + remote-endpoint = <&hdmi_con>; 146 + }; 147 + }; 148 + }; 149 + }; 150 + }; 151 + 152 + &blsp1_dma { 153 + /* 154 + * The board will lock up if we toggle the BLSP clock, unless the 155 + * BAM DMA interconnects support is in place. 156 + */ 157 + /delete-property/ clocks; 158 + }; 159 + 160 + &blsp1_uart2 { 161 + status = "okay"; 162 + }; 163 + 164 + &blsp2_dma { 165 + /* 166 + * The board will lock up if we toggle the BLSP clock, unless the 167 + * BAM DMA interconnects support is in place. 168 + */ 169 + /delete-property/ clocks; 170 + }; 171 + 172 + &blsp2_uart1 { 173 + status = "okay"; 174 + 175 + bluetooth { 176 + compatible = "qcom,wcn3990-bt"; 177 + 178 + vddio-supply = <&vreg_l13a_1p8>; 179 + vddxo-supply = <&vreg_l9a_1p8>; 180 + vddrf-supply = <&vreg_l6a_1p3>; 181 + vddch0-supply = <&vreg_l19a_3p3>; 182 + max-speed = <3200000>; 183 + }; 184 + }; 185 + 186 + &dsi0 { 187 + status = "okay"; 188 + vdda-supply = <&vreg_l1a_1p225>; 189 + }; 190 + 191 + &dsi0_out { 192 + remote-endpoint = <&adv7533_in>; 193 + data-lanes = <0 1 2 3>; 194 + }; 195 + 196 + &dsi0_phy { 197 + status = "okay"; 198 + vcca-supply = <&vreg_l1b_0p925>; 199 + }; 200 + 201 + &mdss { 202 + status = "okay"; 203 + }; 204 + 205 + &mmss_smmu { 206 + status = "okay"; 207 + }; 208 + 209 + &pon_pwrkey { 210 + status = "okay"; 211 + }; 212 + 213 + &pon_resin { 214 + status = "okay"; 215 + 216 + linux,code = <KEY_VOLUMEUP>; 217 + }; 218 + 219 + &qusb2phy0 { 220 + status = "okay"; 221 + 222 + vdd-supply = <&vreg_l1b_0p925>; 223 + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; 224 + }; 225 + 226 + &qusb2phy1 { 227 + status = "okay"; 228 + 229 + vdd-supply = <&vreg_l1b_0p925>; 230 + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; 231 + }; 232 + 233 + &rpm_requests { 234 + pm660-regulators { 235 + compatible = "qcom,rpm-pm660-regulators"; 236 + 237 + vdd_s1-supply = <&vph_pwr>; 238 + vdd_s2-supply = <&vph_pwr>; 239 + vdd_s3-supply = <&vph_pwr>; 240 + vdd_s4-supply = <&vph_pwr>; 241 + vdd_s5-supply = <&vph_pwr>; 242 + vdd_s6-supply = <&vph_pwr>; 243 + 244 + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; 245 + vdd_l2_l3-supply = <&vreg_s2b_1p05>; 246 + vdd_l5-supply = <&vreg_s2b_1p05>; 247 + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; 248 + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; 249 + 250 + vreg_s4a_2p04: s4 { 251 + regulator-min-microvolt = <1805000>; 252 + regulator-max-microvolt = <2040000>; 253 + regulator-enable-ramp-delay = <200>; 254 + regulator-ramp-delay = <0>; 255 + regulator-always-on; 256 + }; 257 + 258 + vreg_s5a_1p35: s5 { 259 + regulator-min-microvolt = <1224000>; 260 + regulator-max-microvolt = <1350000>; 261 + regulator-enable-ramp-delay = <200>; 262 + regulator-ramp-delay = <0>; 263 + }; 264 + 265 + vreg_l1a_1p225: l1 { 266 + regulator-min-microvolt = <1150000>; 267 + regulator-max-microvolt = <1250000>; 268 + regulator-enable-ramp-delay = <250>; 269 + regulator-allow-set-load; 270 + }; 271 + 272 + vreg_l6a_1p3: l6 { 273 + regulator-min-microvolt = <1304000>; 274 + regulator-max-microvolt = <1368000>; 275 + regulator-enable-ramp-delay = <250>; 276 + regulator-ramp-delay = <0>; 277 + regulator-allow-set-load; 278 + }; 279 + 280 + vreg_l8a_1p8: l8 { 281 + regulator-min-microvolt = <1800000>; 282 + regulator-max-microvolt = <1800000>; 283 + regulator-enable-ramp-delay = <250>; 284 + regulator-ramp-delay = <0>; 285 + regulator-system-load = <325000>; 286 + regulator-allow-set-load; 287 + }; 288 + 289 + vreg_l9a_1p8: l9 { 290 + regulator-min-microvolt = <1804000>; 291 + regulator-max-microvolt = <1896000>; 292 + regulator-enable-ramp-delay = <250>; 293 + regulator-ramp-delay = <0>; 294 + regulator-allow-set-load; 295 + }; 296 + 297 + vreg_l13a_1p8: l13 { 298 + /* This gives power to the LPDDR4: never turn it off! */ 299 + regulator-min-microvolt = <1800000>; 300 + regulator-max-microvolt = <1944000>; 301 + regulator-enable-ramp-delay = <250>; 302 + regulator-ramp-delay = <0>; 303 + regulator-always-on; 304 + regulator-boot-on; 305 + }; 306 + 307 + vreg_l19a_3p3: l19 { 308 + regulator-min-microvolt = <3312000>; 309 + regulator-max-microvolt = <3400000>; 310 + regulator-enable-ramp-delay = <250>; 311 + regulator-ramp-delay = <0>; 312 + regulator-allow-set-load; 313 + }; 314 + }; 315 + 316 + pm660l-regulators { 317 + compatible = "qcom,rpm-pm660l-regulators"; 318 + 319 + vdd_s1-supply = <&vph_pwr>; 320 + vdd_s2-supply = <&vph_pwr>; 321 + vdd_s3_s4-supply = <&vph_pwr>; 322 + vdd_s5-supply = <&vph_pwr>; 323 + vdd_s6-supply = <&vph_pwr>; 324 + 325 + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; 326 + vdd_l2-supply = <&vreg_bob>; 327 + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; 328 + vdd_l4_l6-supply = <&vreg_bob>; 329 + vdd_bob-supply = <&vph_pwr>; 330 + 331 + vreg_s2b_1p05: s2 { 332 + regulator-min-microvolt = <1050000>; 333 + regulator-max-microvolt = <1050000>; 334 + regulator-enable-ramp-delay = <200>; 335 + regulator-ramp-delay = <0>; 336 + }; 337 + 338 + vreg_l1b_0p925: l1 { 339 + regulator-min-microvolt = <800000>; 340 + regulator-max-microvolt = <925000>; 341 + regulator-enable-ramp-delay = <250>; 342 + regulator-allow-set-load; 343 + }; 344 + 345 + vreg_l2b_2p95: l2 { 346 + regulator-min-microvolt = <1648000>; 347 + regulator-max-microvolt = <3100000>; 348 + regulator-enable-ramp-delay = <250>; 349 + regulator-ramp-delay = <0>; 350 + regulator-allow-set-load; 351 + }; 352 + 353 + vreg_l4b_2p95: l4 { 354 + regulator-min-microvolt = <2944000>; 355 + regulator-max-microvolt = <2952000>; 356 + regulator-enable-ramp-delay = <250>; 357 + regulator-ramp-delay = <0>; 358 + 359 + regulator-min-microamp = <200>; 360 + regulator-max-microamp = <600000>; 361 + regulator-system-load = <570000>; 362 + regulator-allow-set-load; 363 + }; 364 + 365 + /* 366 + * Downstream specifies a range of 1721-3600mV, 367 + * but the only assigned consumers are SDHCI2 VMMC 368 + * and Coresight QPDI that both request pinned 2.95V. 369 + * Tighten the range to 1.8-3.328 (closest to 3.3) to 370 + * make the mmc driver happy. 371 + */ 372 + vreg_l5b_2p95: l5 { 373 + regulator-min-microvolt = <1800000>; 374 + regulator-max-microvolt = <3328000>; 375 + regulator-enable-ramp-delay = <250>; 376 + regulator-system-load = <800000>; 377 + regulator-ramp-delay = <0>; 378 + regulator-allow-set-load; 379 + }; 380 + 381 + vreg_l7b_3p125: l7 { 382 + regulator-min-microvolt = <2700000>; 383 + regulator-max-microvolt = <3125000>; 384 + regulator-enable-ramp-delay = <250>; 385 + }; 386 + 387 + vreg_l8b_3p3: l8 { 388 + regulator-min-microvolt = <2800000>; 389 + regulator-max-microvolt = <3400000>; 390 + regulator-enable-ramp-delay = <250>; 391 + regulator-ramp-delay = <0>; 392 + }; 393 + 394 + vreg_bob: bob { 395 + regulator-min-microvolt = <3300000>; 396 + regulator-max-microvolt = <3624000>; 397 + regulator-enable-ramp-delay = <500>; 398 + regulator-ramp-delay = <0>; 399 + }; 400 + }; 401 + }; 402 + 403 + &sdc2_state_on { 404 + sd-cd { 405 + pins = "gpio54"; 406 + bias-pull-up; 407 + drive-strength = <2>; 408 + }; 409 + }; 410 + 411 + &sdc2_state_off { 412 + sd-cd { 413 + pins = "gpio54"; 414 + bias-disable; 415 + drive-strength = <2>; 416 + }; 417 + }; 418 + 419 + &sdhc_1 { 420 + status = "okay"; 421 + supports-cqe; 422 + 423 + vmmc-supply = <&vreg_l4b_2p95>; 424 + vqmmc-supply = <&vreg_l8a_1p8>; 425 + 426 + mmc-ddr-1_8v; 427 + mmc-hs400-1_8v; 428 + mmc-hs400-enhanced-strobe; 429 + }; 430 + 431 + &sdhc_2 { 432 + status = "okay"; 433 + 434 + vmmc-supply = <&vreg_l5b_2p95>; 435 + vqmmc-supply = <&vreg_l2b_2p95>; 436 + 437 + cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; 438 + no-sdio; 439 + no-emmc; 440 + }; 441 + 442 + &tlmm { 443 + gpio-reserved-ranges = <0 4>, <8 4>; 444 + }; 445 + 446 + &usb2 { 447 + status = "okay"; 448 + }; 449 + 450 + &usb2_dwc3 { 451 + dr_mode = "host"; 452 + }; 453 + 454 + &usb3 { 455 + status = "okay"; 456 + }; 457 + 458 + &usb3_dwc3 { 459 + dr_mode = "peripheral"; 460 + extcon = <&extcon_usb>; 461 + };
+52 -9
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
··· 10 10 #include <dt-bindings/gpio/gpio.h> 11 11 #include <dt-bindings/input/input.h> 12 12 #include <dt-bindings/input/gpio-keys.h> 13 + #include <dt-bindings/leds/common.h> 13 14 14 15 / { 15 16 /* required for bootloader to select correct board */ ··· 35 34 height = <1920>; 36 35 stride = <(1080 * 4)>; 37 36 format = "a8r8g8b8"; 38 - status= "okay"; 37 + status = "okay"; 39 38 }; 40 39 }; 41 40 ··· 88 87 pinctrl-0 = <&imx300_vana_default>; 89 88 }; 90 89 91 - gpio_keys { 92 - status = "okay"; 90 + gpio-keys { 93 91 compatible = "gpio-keys"; 94 - #address-cells = <1>; 95 - #size-cells = <0>; 96 92 97 - camera_focus { 93 + key-camera-focus { 98 94 label = "Camera Focus"; 99 95 gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 100 96 linux,input-type = <1>; ··· 99 101 debounce-interval = <15>; 100 102 }; 101 103 102 - camera_snapshot { 104 + key-camera-snapshot { 103 105 label = "Camera Snapshot"; 104 106 gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; 105 107 linux,input-type = <1>; ··· 107 109 debounce-interval = <15>; 108 110 }; 109 111 110 - vol_down { 112 + key-vol-down { 111 113 label = "Volume Down"; 112 114 gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; 113 115 linux,input-type = <1>; ··· 212 214 /* HCI Bluetooth */ 213 215 }; 214 216 217 + &pm660l_lpg { 218 + qcom,power-source = <1>; 219 + 220 + status = "okay"; 221 + 222 + multi-led { 223 + color = <LED_COLOR_ID_RGB>; 224 + function = LED_FUNCTION_STATUS; 225 + 226 + #address-cells = <1>; 227 + #size-cells = <0>; 228 + 229 + led@1 { 230 + reg = <1>; 231 + color = <LED_COLOR_ID_BLUE>; 232 + }; 233 + 234 + led@2 { 235 + reg = <2>; 236 + color = <LED_COLOR_ID_GREEN>; 237 + }; 238 + 239 + led@3 { 240 + reg = <3>; 241 + color = <LED_COLOR_ID_RED>; 242 + }; 243 + }; 244 + }; 245 + 215 246 &pon_pwrkey { 216 247 status = "okay"; 217 248 }; ··· 251 224 linux,code = <KEY_VOLUMEUP>; 252 225 }; 253 226 254 - &qusb2phy { 227 + &qusb2phy0 { 255 228 status = "okay"; 256 229 257 230 vdd-supply = <&vreg_l1b_0p925>; ··· 573 546 regulator-ramp-delay = <0>; 574 547 regulator-allow-set-load; 575 548 }; 549 + }; 550 + }; 551 + 552 + &sdc2_state_on { 553 + sd-cd { 554 + pins = "gpio54"; 555 + bias-pull-up; 556 + drive-strength = <2>; 557 + }; 558 + }; 559 + 560 + &sdc2_state_off { 561 + sd-cd { 562 + pins = "gpio54"; 563 + bias-disable; 564 + drive-strength = <2>; 576 565 }; 577 566 }; 578 567
+191 -141
arch/arm64/boot/dts/qcom/sdm630.dtsi
··· 8 8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9 9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10 10 #include <dt-bindings/clock/qcom,rpmcc.h> 11 + #include <dt-bindings/interconnect/qcom,sdm660.h> 11 12 #include <dt-bindings/power/qcom-rpmpd.h> 12 13 #include <dt-bindings/gpio/gpio.h> 13 14 #include <dt-bindings/interrupt-controller/arm-gic.h> ··· 553 552 }; 554 553 555 554 qfprom: qfprom@780000 { 556 - compatible = "qcom,qfprom"; 555 + compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 557 556 reg = <0x00780000 0x621c>; 558 557 #address-cells = <1>; 559 558 #size-cells = <1>; 560 559 561 560 qusb2_hstx_trim: hstx-trim@240 { 562 - reg = <0x240 0x1>; 563 - bits = <25 3>; 561 + reg = <0x243 0x1>; 562 + bits = <1 3>; 564 563 }; 565 564 566 565 gpu_speed_bin: gpu-speed-bin@41a0 { 567 - reg = <0x41a0 0x1>; 568 - bits = <21 7>; 566 + reg = <0x41a2 0x1>; 567 + bits = <5 7>; 569 568 }; 570 569 }; 571 570 ··· 983 982 bias-pull-up; 984 983 drive-strength = <10>; 985 984 }; 986 - 987 - sd-cd { 988 - pins = "gpio54"; 989 - bias-pull-up; 990 - drive-strength = <2>; 991 - }; 992 985 }; 993 986 994 987 sdc2_state_off: sdc2-off { ··· 1001 1006 data { 1002 1007 pins = "sdc2_data"; 1003 1008 bias-pull-up; 1004 - drive-strength = <2>; 1005 - }; 1006 - 1007 - sd-cd { 1008 - pins = "gpio54"; 1009 - bias-disable; 1010 1009 drive-strength = <2>; 1011 1010 }; 1012 1011 }; ··· 1034 1045 nvmem-cells = <&gpu_speed_bin>; 1035 1046 nvmem-cell-names = "speed_bin"; 1036 1047 1037 - interconnects = <&gnoc 1 &bimc 5>; 1048 + interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1038 1049 interconnect-names = "gfx-mem"; 1039 1050 1040 1051 operating-points-v2 = <&gpu_sdm630_opp_table>; 1041 1052 1053 + status = "disabled"; 1054 + 1042 1055 gpu_sdm630_opp_table: opp-table { 1043 - compatible = "operating-points-v2"; 1056 + compatible = "operating-points-v2"; 1044 1057 opp-775000000 { 1045 1058 opp-hz = /bits/ 64 <775000000>; 1046 1059 opp-level = <RPM_SMD_LEVEL_TURBO>; ··· 1243 1252 * haven't seen any devices making use of it. 1244 1253 */ 1245 1254 maximum-speed = "high-speed"; 1246 - phys = <&qusb2phy>; 1255 + phys = <&qusb2phy0>; 1247 1256 phy-names = "usb2-phy"; 1248 1257 snps,hird-threshold = /bits/ 8 <0>; 1249 1258 }; 1250 1259 }; 1251 1260 1252 - qusb2phy: phy@c012000 { 1261 + qusb2phy0: phy@c012000 { 1253 1262 compatible = "qcom,sdm660-qusb2-phy"; 1254 1263 reg = <0x0c012000 0x180>; 1255 1264 #phy-cells = <0>; 1256 1265 1257 1266 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1258 - <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1267 + <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1259 1268 clock-names = "cfg_ahb", "ref"; 1260 1269 1261 1270 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; ··· 1263 1272 status = "disabled"; 1264 1273 }; 1265 1274 1266 - sdhc_2: sdhci@c084000 { 1275 + qusb2phy1: phy@c014000 { 1276 + compatible = "qcom,sdm660-qusb2-phy"; 1277 + reg = <0x0c014000 0x180>; 1278 + #phy-cells = <0>; 1279 + 1280 + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1281 + <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1282 + clock-names = "cfg_ahb", "ref"; 1283 + 1284 + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1285 + nvmem-cells = <&qusb2_hstx_trim>; 1286 + status = "disabled"; 1287 + }; 1288 + 1289 + sdhc_2: mmc@c084000 { 1267 1290 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1268 1291 reg = <0x0c084000 0x1000>; 1269 1292 reg-names = "hc"; ··· 1287 1282 interrupt-names = "hc_irq", "pwr_irq"; 1288 1283 1289 1284 bus-width = <4>; 1290 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1291 - <&gcc GCC_SDCC2_AHB_CLK>, 1285 + 1286 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1287 + <&gcc GCC_SDCC2_APPS_CLK>, 1292 1288 <&xo_board>; 1293 - clock-names = "core", "iface", "xo"; 1289 + clock-names = "iface", "core", "xo"; 1290 + 1294 1291 1295 1292 interconnects = <&a2noc 3 &a2noc 10>, 1296 1293 <&gnoc 0 &cnoc 28>; 1294 + interconnect-names = "sdhc-ddr","cpu-sdhc"; 1297 1295 operating-points-v2 = <&sdhc2_opp_table>; 1298 1296 1299 1297 pinctrl-names = "default", "sleep"; ··· 1330 1322 }; 1331 1323 }; 1332 1324 1333 - sdhc_1: sdhci@c0c4000 { 1325 + sdhc_1: mmc@c0c4000 { 1334 1326 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1335 1327 reg = <0x0c0c4000 0x1000>, 1336 1328 <0x0c0c5000 0x1000>, ··· 1341 1333 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1342 1334 interrupt-names = "hc_irq", "pwr_irq"; 1343 1335 1344 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1345 - <&gcc GCC_SDCC1_AHB_CLK>, 1336 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1337 + <&gcc GCC_SDCC1_APPS_CLK>, 1346 1338 <&xo_board>, 1347 1339 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1348 - clock-names = "core", "iface", "xo", "ice"; 1340 + clock-names = "iface", "core", "xo", "ice"; 1349 1341 1350 1342 interconnects = <&a2noc 2 &a2noc 10>, 1351 1343 <&gnoc 0 &cnoc 27>; 1352 - interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1344 + interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1353 1345 operating-points-v2 = <&sdhc1_opp_table>; 1354 1346 pinctrl-names = "default", "sleep"; 1355 1347 pinctrl-0 = <&sdc1_state_on>; ··· 1385 1377 }; 1386 1378 }; 1387 1379 1380 + usb2: usb@c2f8800 { 1381 + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1382 + reg = <0x0c2f8800 0x400>; 1383 + status = "disabled"; 1384 + #address-cells = <1>; 1385 + #size-cells = <1>; 1386 + ranges; 1387 + 1388 + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1389 + <&gcc GCC_USB20_MASTER_CLK>, 1390 + <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1391 + <&gcc GCC_USB20_SLEEP_CLK>; 1392 + clock-names = "cfg_noc", "core", 1393 + "mock_utmi", "sleep"; 1394 + 1395 + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1396 + <&gcc GCC_USB20_MASTER_CLK>; 1397 + assigned-clock-rates = <19200000>, <60000000>; 1398 + 1399 + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1400 + interrupt-names = "hs_phy_irq"; 1401 + 1402 + qcom,select-utmi-as-pipe-clk; 1403 + 1404 + resets = <&gcc GCC_USB_20_BCR>; 1405 + 1406 + usb2_dwc3: usb@c200000 { 1407 + compatible = "snps,dwc3"; 1408 + reg = <0x0c200000 0xc8d0>; 1409 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1410 + snps,dis_u2_susphy_quirk; 1411 + snps,dis_enblslpm_quirk; 1412 + 1413 + /* This is the HS-only host */ 1414 + maximum-speed = "high-speed"; 1415 + phys = <&qusb2phy1>; 1416 + phy-names = "usb2-phy"; 1417 + snps,hird-threshold = /bits/ 8 <0>; 1418 + }; 1419 + }; 1420 + 1388 1421 mmcc: clock-controller@c8c0000 { 1389 1422 compatible = "qcom,mmcc-sdm630"; 1390 1423 reg = <0x0c8c0000 0x40000>; ··· 1454 1405 <0>; 1455 1406 }; 1456 1407 1457 - dsi_opp_table: dsi-opp-table { 1408 + dsi_opp_table: opp-table-dsi { 1458 1409 compatible = "operating-points-v2"; 1459 1410 1460 1411 opp-131250000 { ··· 1543 1494 }; 1544 1495 }; 1545 1496 1546 - mdp_opp_table: mdp-opp { 1497 + mdp_opp_table: opp-table { 1547 1498 compatible = "operating-points-v2"; 1548 1499 1549 1500 opp-150000000 { ··· 1612 1563 phys = <&dsi0_phy>; 1613 1564 phy-names = "dsi"; 1614 1565 1566 + status = "disabled"; 1567 + 1615 1568 ports { 1616 1569 #address-cells = <1>; 1617 1570 #size-cells = <0>; ··· 1647 1596 1648 1597 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1649 1598 clock-names = "iface", "ref"; 1599 + status = "disabled"; 1650 1600 }; 1651 1601 }; 1652 1602 ··· 1881 1829 status = "disabled"; 1882 1830 }; 1883 1831 1884 - imem@146bf000 { 1885 - compatible = "simple-mfd"; 1832 + sram@146bf000 { 1833 + compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1886 1834 reg = <0x146bf000 0x1000>; 1887 1835 1888 1836 #address-cells = <1>; ··· 1898 1846 1899 1847 camss: camss@ca00000 { 1900 1848 compatible = "qcom,sdm660-camss"; 1901 - reg = <0x0c824000 0x1000>, 1849 + reg = <0x0ca00020 0x10>, 1850 + <0x0ca30000 0x100>, 1851 + <0x0ca30400 0x100>, 1852 + <0x0ca30800 0x100>, 1853 + <0x0ca30c00 0x100>, 1854 + <0x0c824000 0x1000>, 1902 1855 <0x0ca00120 0x4>, 1903 1856 <0x0c825000 0x1000>, 1904 1857 <0x0ca00124 0x4>, 1905 1858 <0x0c826000 0x1000>, 1906 1859 <0x0ca00128 0x4>, 1907 - <0x0ca30000 0x100>, 1908 - <0x0ca30400 0x100>, 1909 - <0x0ca30800 0x100>, 1910 - <0x0ca30c00 0x100>, 1911 1860 <0x0ca31000 0x500>, 1912 - <0x0ca00020 0x10>, 1913 1861 <0x0ca10000 0x1000>, 1914 1862 <0x0ca14000 0x1000>; 1915 - reg-names = "csiphy0", 1863 + reg-names = "csi_clk_mux", 1864 + "csid0", 1865 + "csid1", 1866 + "csid2", 1867 + "csid3", 1868 + "csiphy0", 1916 1869 "csiphy0_clk_mux", 1917 1870 "csiphy1", 1918 1871 "csiphy1_clk_mux", 1919 1872 "csiphy2", 1920 1873 "csiphy2_clk_mux", 1921 - "csid0", 1922 - "csid1", 1923 - "csid2", 1924 - "csid3", 1925 1874 "ispif", 1926 - "csi_clk_mux", 1927 1875 "vfe0", 1928 1876 "vfe1"; 1929 - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1930 - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1931 - <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1932 - <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1877 + interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1933 1878 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1934 1879 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1935 1880 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1881 + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1882 + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1883 + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1936 1884 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1937 1885 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1938 1886 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1939 - interrupt-names = "csiphy0", 1940 - "csiphy1", 1941 - "csiphy2", 1942 - "csid0", 1887 + interrupt-names = "csid0", 1943 1888 "csid1", 1944 1889 "csid2", 1945 1890 "csid3", 1891 + "csiphy0", 1892 + "csiphy1", 1893 + "csiphy2", 1946 1894 "ispif", 1947 1895 "vfe0", 1948 1896 "vfe1"; 1949 - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1950 - <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1951 - <&mmcc CAMSS_ISPIF_AHB_CLK>, 1952 - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1953 - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1954 - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1955 - <&mmcc CAMSS_CSI0_AHB_CLK>, 1956 - <&mmcc CAMSS_CSI0_CLK>, 1957 - <&mmcc CAMSS_CPHY_CSID0_CLK>, 1958 - <&mmcc CAMSS_CSI0PIX_CLK>, 1959 - <&mmcc CAMSS_CSI0RDI_CLK>, 1960 - <&mmcc CAMSS_CSI1_AHB_CLK>, 1961 - <&mmcc CAMSS_CSI1_CLK>, 1962 - <&mmcc CAMSS_CPHY_CSID1_CLK>, 1963 - <&mmcc CAMSS_CSI1PIX_CLK>, 1964 - <&mmcc CAMSS_CSI1RDI_CLK>, 1965 - <&mmcc CAMSS_CSI2_AHB_CLK>, 1966 - <&mmcc CAMSS_CSI2_CLK>, 1967 - <&mmcc CAMSS_CPHY_CSID2_CLK>, 1968 - <&mmcc CAMSS_CSI2PIX_CLK>, 1969 - <&mmcc CAMSS_CSI2RDI_CLK>, 1970 - <&mmcc CAMSS_CSI3_AHB_CLK>, 1971 - <&mmcc CAMSS_CSI3_CLK>, 1972 - <&mmcc CAMSS_CPHY_CSID3_CLK>, 1973 - <&mmcc CAMSS_CSI3PIX_CLK>, 1974 - <&mmcc CAMSS_CSI3RDI_CLK>, 1975 - <&mmcc CAMSS_AHB_CLK>, 1976 - <&mmcc CAMSS_VFE0_CLK>, 1977 - <&mmcc CAMSS_CSI_VFE0_CLK>, 1978 - <&mmcc CAMSS_VFE0_AHB_CLK>, 1979 - <&mmcc CAMSS_VFE0_STREAM_CLK>, 1980 - <&mmcc CAMSS_VFE1_CLK>, 1981 - <&mmcc CAMSS_CSI_VFE1_CLK>, 1982 - <&mmcc CAMSS_VFE1_AHB_CLK>, 1983 - <&mmcc CAMSS_VFE1_STREAM_CLK>, 1984 - <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1985 - <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, 1986 - <&mmcc CSIPHY_AHB2CRIF_CLK>, 1987 - <&mmcc CAMSS_CPHY_CSID0_CLK>, 1988 - <&mmcc CAMSS_CPHY_CSID1_CLK>, 1989 - <&mmcc CAMSS_CPHY_CSID2_CLK>, 1990 - <&mmcc CAMSS_CPHY_CSID3_CLK>; 1991 - clock-names = "top_ahb", 1992 - "throttle_axi", 1993 - "ispif_ahb", 1994 - "csiphy0_timer", 1995 - "csiphy1_timer", 1996 - "csiphy2_timer", 1997 - "csi0_ahb", 1998 - "csi0", 1999 - "csi0_phy", 2000 - "csi0_pix", 2001 - "csi0_rdi", 2002 - "csi1_ahb", 2003 - "csi1", 2004 - "csi1_phy", 2005 - "csi1_pix", 2006 - "csi1_rdi", 2007 - "csi2_ahb", 2008 - "csi2", 2009 - "csi2_phy", 2010 - "csi2_pix", 2011 - "csi2_rdi", 2012 - "csi3_ahb", 2013 - "csi3", 2014 - "csi3_phy", 2015 - "csi3_pix", 2016 - "csi3_rdi", 2017 - "ahb", 2018 - "vfe0", 2019 - "csi_vfe0", 2020 - "vfe0_ahb", 2021 - "vfe0_stream", 2022 - "vfe1", 2023 - "csi_vfe1", 2024 - "vfe1_ahb", 2025 - "vfe1_stream", 2026 - "vfe_ahb", 2027 - "vfe_axi", 2028 - "csiphy_ahb2crif", 2029 - "cphy_csid0", 2030 - "cphy_csid1", 2031 - "cphy_csid2", 2032 - "cphy_csid3"; 1897 + clocks = <&mmcc CAMSS_AHB_CLK>, 1898 + <&mmcc CAMSS_CPHY_CSID0_CLK>, 1899 + <&mmcc CAMSS_CPHY_CSID1_CLK>, 1900 + <&mmcc CAMSS_CPHY_CSID2_CLK>, 1901 + <&mmcc CAMSS_CPHY_CSID3_CLK>, 1902 + <&mmcc CAMSS_CSI0_AHB_CLK>, 1903 + <&mmcc CAMSS_CSI0_CLK>, 1904 + <&mmcc CAMSS_CPHY_CSID0_CLK>, 1905 + <&mmcc CAMSS_CSI0PIX_CLK>, 1906 + <&mmcc CAMSS_CSI0RDI_CLK>, 1907 + <&mmcc CAMSS_CSI1_AHB_CLK>, 1908 + <&mmcc CAMSS_CSI1_CLK>, 1909 + <&mmcc CAMSS_CPHY_CSID1_CLK>, 1910 + <&mmcc CAMSS_CSI1PIX_CLK>, 1911 + <&mmcc CAMSS_CSI1RDI_CLK>, 1912 + <&mmcc CAMSS_CSI2_AHB_CLK>, 1913 + <&mmcc CAMSS_CSI2_CLK>, 1914 + <&mmcc CAMSS_CPHY_CSID2_CLK>, 1915 + <&mmcc CAMSS_CSI2PIX_CLK>, 1916 + <&mmcc CAMSS_CSI2RDI_CLK>, 1917 + <&mmcc CAMSS_CSI3_AHB_CLK>, 1918 + <&mmcc CAMSS_CSI3_CLK>, 1919 + <&mmcc CAMSS_CPHY_CSID3_CLK>, 1920 + <&mmcc CAMSS_CSI3PIX_CLK>, 1921 + <&mmcc CAMSS_CSI3RDI_CLK>, 1922 + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1923 + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1924 + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1925 + <&mmcc CSIPHY_AHB2CRIF_CLK>, 1926 + <&mmcc CAMSS_CSI_VFE0_CLK>, 1927 + <&mmcc CAMSS_CSI_VFE1_CLK>, 1928 + <&mmcc CAMSS_ISPIF_AHB_CLK>, 1929 + <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1930 + <&mmcc CAMSS_TOP_AHB_CLK>, 1931 + <&mmcc CAMSS_VFE0_AHB_CLK>, 1932 + <&mmcc CAMSS_VFE0_CLK>, 1933 + <&mmcc CAMSS_VFE0_STREAM_CLK>, 1934 + <&mmcc CAMSS_VFE1_AHB_CLK>, 1935 + <&mmcc CAMSS_VFE1_CLK>, 1936 + <&mmcc CAMSS_VFE1_STREAM_CLK>, 1937 + <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1938 + <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1939 + clock-names = "ahb", 1940 + "cphy_csid0", 1941 + "cphy_csid1", 1942 + "cphy_csid2", 1943 + "cphy_csid3", 1944 + "csi0_ahb", 1945 + "csi0", 1946 + "csi0_phy", 1947 + "csi0_pix", 1948 + "csi0_rdi", 1949 + "csi1_ahb", 1950 + "csi1", 1951 + "csi1_phy", 1952 + "csi1_pix", 1953 + "csi1_rdi", 1954 + "csi2_ahb", 1955 + "csi2", 1956 + "csi2_phy", 1957 + "csi2_pix", 1958 + "csi2_rdi", 1959 + "csi3_ahb", 1960 + "csi3", 1961 + "csi3_phy", 1962 + "csi3_pix", 1963 + "csi3_rdi", 1964 + "csiphy0_timer", 1965 + "csiphy1_timer", 1966 + "csiphy2_timer", 1967 + "csiphy_ahb2crif", 1968 + "csi_vfe0", 1969 + "csi_vfe1", 1970 + "ispif_ahb", 1971 + "throttle_axi", 1972 + "top_ahb", 1973 + "vfe0_ahb", 1974 + "vfe0", 1975 + "vfe0_stream", 1976 + "vfe1_ahb", 1977 + "vfe1", 1978 + "vfe1_stream", 1979 + "vfe_ahb", 1980 + "vfe_axi"; 2033 1981 interconnects = <&mnoc 5 &bimc 5>; 2034 1982 interconnect-names = "vfe-mem"; 2035 1983 iommus = <&mmss_smmu 0xc00>, ··· 2210 2158 label = "lpass"; 2211 2159 mboxes = <&apcs_glb 9>; 2212 2160 qcom,remote-pid = <2>; 2213 - #address-cells = <1>; 2214 - #size-cells = <0>; 2215 2161 2216 2162 apr { 2217 2163 compatible = "qcom,apr-v2";
+1 -1
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
··· 27 27 gpio-keys { 28 28 compatible = "gpio-keys"; 29 29 30 - volume-up { 30 + key-volume-up { 31 31 label = "volume_up"; 32 32 linux,code = <KEY_VOLUMEUP>; 33 33 gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts
··· 19 19 }; 20 20 21 21 &sdc2_state_on { 22 - pinconf-clk { 22 + clk { 23 23 drive-strength = <14>; 24 24 }; 25 25 };
+26 -2
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
··· 51 51 gpio-keys { 52 52 compatible = "gpio-keys"; 53 53 54 - volup { 54 + key-volup { 55 55 label = "Volume Up"; 56 56 gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; 57 57 linux,code = <KEY_VOLUMEUP>; ··· 103 103 linux,code = <KEY_VOLUMEDOWN>; 104 104 }; 105 105 106 - &qusb2phy { 106 + &qusb2phy0 { 107 107 status = "okay"; 108 108 109 109 vdd-supply = <&vreg_l1b_0p925>; ··· 360 360 regulator-enable-ramp-delay = <250>; 361 361 regulator-allow-set-load; 362 362 }; 363 + }; 364 + }; 365 + 366 + &pm660l_wled { 367 + status = "okay"; 368 + 369 + qcom,switching-freq = <800>; 370 + qcom,current-limit-microamp = <20000>; 371 + qcom,num-strings = <2>; 372 + }; 373 + 374 + &sdc2_state_on { 375 + sd-cd { 376 + pins = "gpio54"; 377 + bias-pull-up; 378 + drive-strength = <2>; 379 + }; 380 + }; 381 + 382 + &sdc2_state_off { 383 + sd-cd { 384 + pins = "gpio54"; 385 + bias-disable; 386 + drive-strength = <2>; 363 387 }; 364 388 }; 365 389
+4 -1
arch/arm64/boot/dts/qcom/sdm660.dtsi
··· 14 14 operating-points-v2 = <&gpu_sdm660_opp_table>; 15 15 16 16 gpu_sdm660_opp_table: opp-table { 17 - compatible = "operating-points-v2"; 17 + compatible = "operating-points-v2"; 18 18 19 19 /* 20 20 * 775MHz is only available on the highest speed bin ··· 192 192 phys = <&dsi1_phy>; 193 193 phy-names = "dsi"; 194 194 195 + status = "disabled"; 196 + 195 197 ports { 196 198 #address-cells = <1>; 197 199 #size-cells = <0>; ··· 227 225 228 226 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 229 227 clock-names = "iface", "ref"; 228 + status = "disabled"; 230 229 }; 231 230 }; 232 231
+134 -2
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
··· 119 119 pinctrl-names = "default"; 120 120 pinctrl-0 = <&pen_eject_odl>; 121 121 122 - pen-insert { 122 + switch-pen-insert { 123 123 label = "Pen Insert"; 124 124 /* Insert = low, eject = high */ 125 125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; ··· 130 130 }; 131 131 132 132 panel: panel { 133 - compatible ="innolux,p120zdg-bf1"; 133 + compatible = "innolux,p120zdg-bf1"; 134 134 power-supply = <&pp3300_dx_edp>; 135 135 backlight = <&backlight>; 136 136 no-hpd; ··· 143 143 }; 144 144 }; 145 145 }; 146 + }; 147 + 148 + &psci { 149 + /delete-node/ cpu0; 150 + /delete-node/ cpu1; 151 + /delete-node/ cpu2; 152 + /delete-node/ cpu3; 153 + /delete-node/ cpu4; 154 + /delete-node/ cpu5; 155 + /delete-node/ cpu6; 156 + /delete-node/ cpu7; 157 + /delete-node/ cpu-cluster0; 158 + }; 159 + 160 + &cpus { 161 + /delete-node/ domain-idle-states; 162 + }; 163 + 164 + &cpu_idle_states { 165 + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 166 + compatible = "arm,idle-state"; 167 + idle-state-name = "little-power-down"; 168 + arm,psci-suspend-param = <0x40000003>; 169 + entry-latency-us = <350>; 170 + exit-latency-us = <461>; 171 + min-residency-us = <1890>; 172 + local-timer-stop; 173 + }; 174 + 175 + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 176 + compatible = "arm,idle-state"; 177 + idle-state-name = "little-rail-power-down"; 178 + arm,psci-suspend-param = <0x40000004>; 179 + entry-latency-us = <360>; 180 + exit-latency-us = <531>; 181 + min-residency-us = <3934>; 182 + local-timer-stop; 183 + }; 184 + 185 + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 186 + compatible = "arm,idle-state"; 187 + idle-state-name = "big-power-down"; 188 + arm,psci-suspend-param = <0x40000003>; 189 + entry-latency-us = <264>; 190 + exit-latency-us = <621>; 191 + min-residency-us = <952>; 192 + local-timer-stop; 193 + }; 194 + 195 + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 196 + compatible = "arm,idle-state"; 197 + idle-state-name = "big-rail-power-down"; 198 + arm,psci-suspend-param = <0x40000004>; 199 + entry-latency-us = <702>; 200 + exit-latency-us = <1061>; 201 + min-residency-us = <4488>; 202 + local-timer-stop; 203 + }; 204 + 205 + CLUSTER_SLEEP_0: cluster-sleep-0 { 206 + compatible = "arm,idle-state"; 207 + idle-state-name = "cluster-power-down"; 208 + arm,psci-suspend-param = <0x400000F4>; 209 + entry-latency-us = <3263>; 210 + exit-latency-us = <6562>; 211 + min-residency-us = <9987>; 212 + local-timer-stop; 213 + }; 214 + }; 215 + 216 + &CPU0 { 217 + /delete-property/ power-domains; 218 + /delete-property/ power-domain-names; 219 + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 220 + &LITTLE_CPU_SLEEP_1 221 + &CLUSTER_SLEEP_0>; 222 + }; 223 + 224 + &CPU1 { 225 + /delete-property/ power-domains; 226 + /delete-property/ power-domain-names; 227 + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 + &LITTLE_CPU_SLEEP_1 229 + &CLUSTER_SLEEP_0>; 230 + }; 231 + 232 + &CPU2 { 233 + /delete-property/ power-domains; 234 + /delete-property/ power-domain-names; 235 + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 + &LITTLE_CPU_SLEEP_1 237 + &CLUSTER_SLEEP_0>; 238 + }; 239 + 240 + &CPU3 { 241 + /delete-property/ power-domains; 242 + /delete-property/ power-domain-names; 243 + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 + &LITTLE_CPU_SLEEP_1 245 + &CLUSTER_SLEEP_0>; 246 + }; 247 + 248 + &CPU4 { 249 + /delete-property/ power-domains; 250 + /delete-property/ power-domain-names; 251 + cpu-idle-states = <&BIG_CPU_SLEEP_0 252 + &BIG_CPU_SLEEP_1 253 + &CLUSTER_SLEEP_0>; 254 + }; 255 + 256 + &CPU5 { 257 + /delete-property/ power-domains; 258 + /delete-property/ power-domain-names; 259 + cpu-idle-states = <&BIG_CPU_SLEEP_0 260 + &BIG_CPU_SLEEP_1 261 + &CLUSTER_SLEEP_0>; 262 + }; 263 + 264 + &CPU6 { 265 + /delete-property/ power-domains; 266 + /delete-property/ power-domain-names; 267 + cpu-idle-states = <&BIG_CPU_SLEEP_0 268 + &BIG_CPU_SLEEP_1 269 + &CLUSTER_SLEEP_0>; 270 + }; 271 + 272 + &CPU7 { 273 + /delete-property/ power-domains; 274 + /delete-property/ power-domain-names; 275 + cpu-idle-states = <&BIG_CPU_SLEEP_0 276 + &BIG_CPU_SLEEP_1 277 + &CLUSTER_SLEEP_0>; 146 278 }; 147 279 148 280 /*
+50 -12
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
··· 5 5 6 6 /dts-v1/; 7 7 8 + #include <dt-bindings/leds/common.h> 8 9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 9 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 10 11 #include <dt-bindings/sound/qcom,q6afe.h> ··· 44 43 regulator-always-on; 45 44 }; 46 45 47 - gpio_keys { 46 + gpio-keys { 48 47 compatible = "gpio-keys"; 49 48 autorepeat; 50 49 51 50 pinctrl-names = "default"; 52 51 pinctrl-0 = <&vol_up_pin_a>; 53 52 54 - vol-up { 53 + key-vol-up { 55 54 label = "Volume Up"; 56 55 linux,code = <KEY_VOLUMEUP>; 57 56 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; ··· 61 60 leds { 62 61 compatible = "gpio-leds"; 63 62 64 - user4 { 63 + led-0 { 65 64 label = "green:user4"; 65 + function = LED_FUNCTION_INDICATOR; 66 + color = <LED_COLOR_ID_GREEN>; 66 67 gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; 67 68 linux,default-trigger = "panic-indicator"; 68 69 default-state = "off"; 69 70 }; 70 71 71 - wlan { 72 + led-1 { 72 73 label = "yellow:wlan"; 74 + function = LED_FUNCTION_WLAN; 75 + color = <LED_COLOR_ID_YELLOW>; 73 76 gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; 74 77 linux,default-trigger = "phy0tx"; 75 78 default-state = "off"; 76 79 }; 77 80 78 - bt { 81 + led-2 { 79 82 label = "blue:bt"; 83 + function = LED_FUNCTION_BLUETOOTH; 84 + color = <LED_COLOR_ID_BLUE>; 80 85 gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; 81 86 linux,default-trigger = "bluetooth-power"; 82 87 default-state = "off"; ··· 576 569 "OPTION2", 577 570 "PM845_SLB"; 578 571 579 - cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { 572 + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state { 580 573 pins = "gpio12"; 581 574 function = "normal"; 582 575 ··· 585 578 qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; 586 579 }; 587 580 588 - cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { 581 + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { 589 582 pins = "gpio10"; 590 583 function = "normal"; 591 584 ··· 594 587 qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; 595 588 }; 596 589 597 - vol_up_pin_a: vol-up-active { 590 + vol_up_pin_a: vol-up-active-state { 598 591 pins = "gpio6"; 599 592 function = "normal"; 600 593 input-enable; ··· 613 606 }; 614 607 }; 615 608 609 + &pmi8998_lpg { 610 + status = "okay"; 611 + 612 + qcom,power-source = <1>; 613 + 614 + led@3 { 615 + reg = <3>; 616 + color = <LED_COLOR_ID_GREEN>; 617 + function = LED_FUNCTION_HEARTBEAT; 618 + function-enumerator = <3>; 619 + 620 + linux,default-trigger = "heartbeat"; 621 + default-state = "on"; 622 + }; 623 + 624 + led@4 { 625 + reg = <4>; 626 + color = <LED_COLOR_ID_GREEN>; 627 + function = LED_FUNCTION_INDICATOR; 628 + function-enumerator = <2>; 629 + }; 630 + 631 + led@5 { 632 + reg = <5>; 633 + color = <LED_COLOR_ID_GREEN>; 634 + function = LED_FUNCTION_INDICATOR; 635 + function-enumerator = <1>; 636 + }; 637 + }; 638 + 616 639 /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ 617 640 &q6afedai { 618 641 qi2s@22 { 619 - reg = <22>; 642 + reg = <QUATERNARY_MI2S_RX>; 620 643 qcom,sd-lines = <0 1 2 3>; 621 644 }; 622 645 }; ··· 755 718 }; 756 719 757 720 codec { 758 - sound-dai = <&lt9611_codec 0>; 721 + sound-dai = <&lt9611_codec 0>; 759 722 }; 760 723 }; 761 724 ··· 770 733 }; 771 734 772 735 codec { 773 - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 736 + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 774 737 }; 775 738 }; 776 739 ··· 1181 1144 }; 1182 1145 1183 1146 &camss { 1184 - vdda-supply = <&vreg_l1a_0p875>; 1147 + vdda-phy-supply = <&vreg_l1a_0p875>; 1148 + vdda-pll-supply = <&vreg_l26a_1p2>; 1185 1149 1186 1150 status = "ok"; 1187 1151
+614
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * SDM845 LG G7 / V35 (judyln / judyp) common device tree 4 + * 5 + * Copyright (c) 2022, The Linux Foundation. All rights reserved. 6 + */ 7 + 8 + #include <dt-bindings/gpio/gpio.h> 9 + #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 10 + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 + 12 + #include "sdm845.dtsi" 13 + #include "pm8998.dtsi" 14 + #include "pmi8998.dtsi" 15 + 16 + /delete-node/ &adsp_mem; 17 + /delete-node/ &cdsp_mem; 18 + /delete-node/ &gpu_mem; 19 + /delete-node/ &ipa_fw_mem; 20 + /delete-node/ &mba_region; 21 + /delete-node/ &mpss_region; 22 + /delete-node/ &qseecom_mem; 23 + /delete-node/ &rmtfs_mem; 24 + /delete-node/ &slpi_mem; 25 + /delete-node/ &spss_mem; 26 + /delete-node/ &venus_mem; 27 + /delete-node/ &wlan_msa_mem; 28 + 29 + / { 30 + chosen { 31 + #address-cells = <2>; 32 + #size-cells = <2>; 33 + ranges; 34 + }; 35 + 36 + reserved-memory { 37 + #address-cells = <2>; 38 + #size-cells = <2>; 39 + ranges; 40 + 41 + qseecom_mem: memory@b2000000 { 42 + reg = <0 0xb2000000 0 0x1800000>; 43 + no-map; 44 + }; 45 + 46 + gpu_mem: memory@8c415000 { 47 + reg = <0 0x8c415000 0 0x2000>; 48 + no-map; 49 + }; 50 + 51 + ipa_fw_mem: memory@8c400000 { 52 + reg = <0 0x8c400000 0 0x10000>; 53 + no-map; 54 + }; 55 + 56 + adsp_mem: memory@8c500000 { 57 + reg = <0 0x8c500000 0 0x1e00000>; 58 + no-map; 59 + }; 60 + 61 + wlan_msa_mem: memory@8e300000 { 62 + reg = <0 0x8e300000 0 0x100000>; 63 + no-map; 64 + }; 65 + 66 + mpss_region: memory@8e400000 { 67 + reg = <0 0x8e400000 0 0x8900000>; 68 + no-map; 69 + }; 70 + 71 + venus_mem: memory@96d00000 { 72 + reg = <0 0x96d00000 0 0x500000>; 73 + no-map; 74 + }; 75 + 76 + cdsp_mem: memory@97200000 { 77 + reg = <0 0x97200000 0 0x800000>; 78 + no-map; 79 + }; 80 + 81 + mba_region: memory@97a00000 { 82 + reg = <0 0x97a00000 0 0x200000>; 83 + no-map; 84 + }; 85 + 86 + slpi_mem: memory@97c00000 { 87 + reg = <0 0x97c00000 0 0x1400000>; 88 + no-map; 89 + }; 90 + 91 + spss_mem: memory@99000000 { 92 + reg = <0 0x99000000 0 0x100000>; 93 + no-map; 94 + }; 95 + 96 + /* Framebuffer region */ 97 + memory@9d400000 { 98 + reg = <0x0 0x9d400000 0x0 0x2400000>; 99 + no-map; 100 + }; 101 + 102 + /* rmtfs lower guard */ 103 + memory@f0800000 { 104 + reg = <0 0xf0800000 0 0x1000>; 105 + no-map; 106 + }; 107 + 108 + rmtfs_mem: memory@f0801000 { 109 + compatible = "qcom,rmtfs-mem"; 110 + reg = <0 0xf0801000 0 0x200000>; 111 + no-map; 112 + 113 + qcom,client-id = <1>; 114 + qcom,vmid = <15>; 115 + }; 116 + 117 + /* rmtfs upper guard */ 118 + memory@f0a01000 { 119 + reg = <0 0xf0a01000 0 0x1000>; 120 + no-map; 121 + }; 122 + }; 123 + 124 + gpio-keys { 125 + compatible = "gpio-keys"; 126 + 127 + pinctrl-names = "default"; 128 + pinctrl-0 = <&vol_up_pin_a>; 129 + 130 + label = "GPIO Buttons"; 131 + 132 + key-vol-up { 133 + label = "Volume up"; 134 + linux,code = <KEY_VOLUMEUP>; 135 + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; 136 + }; 137 + }; 138 + 139 + vph_pwr: vph-pwr-regulator { 140 + compatible = "regulator-fixed"; 141 + regulator-name = "vph_pwr"; 142 + regulator-min-microvolt = <3700000>; 143 + regulator-max-microvolt = <3700000>; 144 + }; 145 + 146 + /* 147 + * Apparently RPMh does not provide support for PM8998 S4 because it 148 + * is always-on; model it as a fixed regulator. 149 + */ 150 + vreg_s4a_1p8: pm8998-smps4-regulator { 151 + compatible = "regulator-fixed"; 152 + regulator-name = "vreg_s4a_1p8"; 153 + 154 + regulator-min-microvolt = <1800000>; 155 + regulator-max-microvolt = <1800000>; 156 + 157 + regulator-always-on; 158 + regulator-boot-on; 159 + 160 + vin-supply = <&vph_pwr>; 161 + }; 162 + }; 163 + 164 + &adsp_pas { 165 + status = "okay"; 166 + }; 167 + 168 + &apps_rsc { 169 + pm8998-rpmh-regulators { 170 + compatible = "qcom,pm8998-rpmh-regulators"; 171 + qcom,pmic-id = "a"; 172 + 173 + vdd-s1-supply = <&vph_pwr>; 174 + vdd-s2-supply = <&vph_pwr>; 175 + vdd-s3-supply = <&vph_pwr>; 176 + vdd-s4-supply = <&vph_pwr>; 177 + vdd-s5-supply = <&vph_pwr>; 178 + vdd-s6-supply = <&vph_pwr>; 179 + vdd-s7-supply = <&vph_pwr>; 180 + vdd-s8-supply = <&vph_pwr>; 181 + vdd-s9-supply = <&vph_pwr>; 182 + vdd-s10-supply = <&vph_pwr>; 183 + vdd-s11-supply = <&vph_pwr>; 184 + vdd-s12-supply = <&vph_pwr>; 185 + vdd-s13-supply = <&vph_pwr>; 186 + vdd-l1-l27-supply = <&vreg_s7a_1p025>; 187 + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; 188 + vdd-l3-l11-supply = <&vreg_s7a_1p025>; 189 + vdd-l4-l5-supply = <&vreg_s7a_1p025>; 190 + vdd-l6-supply = <&vph_pwr>; 191 + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; 192 + vdd-l9-supply = <&vreg_bob>; 193 + vdd-l10-l23-l25-supply = <&vreg_bob>; 194 + vdd-l13-l19-l21-supply = <&vreg_bob>; 195 + vdd-l16-l28-supply = <&vreg_bob>; 196 + vdd-l18-l22-supply = <&vreg_bob>; 197 + vdd-l20-l24-supply = <&vreg_bob>; 198 + vdd-l26-supply = <&vreg_s3a_1p35>; 199 + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; 200 + 201 + vreg_s2a_1p125: smps2 { 202 + regulator-min-microvolt = <1100000>; 203 + regulator-max-microvolt = <1100000>; 204 + }; 205 + 206 + vreg_s3a_1p35: smps3 { 207 + regulator-min-microvolt = <1352000>; 208 + regulator-max-microvolt = <1352000>; 209 + }; 210 + 211 + vreg_s5a_2p04: smps5 { 212 + regulator-min-microvolt = <1904000>; 213 + regulator-max-microvolt = <2040000>; 214 + }; 215 + 216 + vreg_s7a_1p025: smps7 { 217 + regulator-min-microvolt = <900000>; 218 + regulator-max-microvolt = <1028000>; 219 + }; 220 + 221 + vdd_qusb_hs0: 222 + vdda_hp_pcie_core: 223 + vdda_mipi_csi0_0p9: 224 + vdda_mipi_csi1_0p9: 225 + vdda_mipi_csi2_0p9: 226 + vdda_mipi_dsi0_pll: 227 + vdda_mipi_dsi1_pll: 228 + vdda_qlink_lv: 229 + vdda_qlink_lv_ck: 230 + vdda_qrefs_0p875: 231 + vdda_pcie_core: 232 + vdda_pll_cc_ebi01: 233 + vdda_pll_cc_ebi23: 234 + vdda_sp_sensor: 235 + vdda_ufs1_core: 236 + vdda_ufs2_core: 237 + vdda_usb1_ss_core: 238 + vdda_usb2_ss_core: 239 + vreg_l1a_0p875: ldo1 { 240 + regulator-min-microvolt = <880000>; 241 + regulator-max-microvolt = <880000>; 242 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 243 + }; 244 + 245 + vddpx_10: 246 + vreg_l2a_1p2: ldo2 { 247 + regulator-min-microvolt = <1200000>; 248 + regulator-max-microvolt = <1200000>; 249 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 250 + regulator-always-on; 251 + }; 252 + 253 + vreg_l3a_1p0: ldo3 { 254 + regulator-min-microvolt = <1000000>; 255 + regulator-max-microvolt = <1000000>; 256 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 257 + }; 258 + 259 + vdd_wcss_cx: 260 + vdd_wcss_mx: 261 + vdda_wcss_pll: 262 + vreg_l5a_0p8: ldo5 { 263 + regulator-min-microvolt = <800000>; 264 + regulator-max-microvolt = <800000>; 265 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 266 + }; 267 + 268 + vddpx_13: 269 + vreg_l6a_1p8: ldo6 { 270 + regulator-min-microvolt = <1856000>; 271 + regulator-max-microvolt = <1856000>; 272 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 273 + }; 274 + 275 + vreg_l7a_1p8: ldo7 { 276 + regulator-min-microvolt = <1800000>; 277 + regulator-max-microvolt = <1800000>; 278 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 279 + }; 280 + 281 + vreg_l8a_1p2: ldo8 { 282 + regulator-min-microvolt = <1200000>; 283 + regulator-max-microvolt = <1248000>; 284 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 285 + }; 286 + 287 + vreg_l9a_1p8: ldo9 { 288 + regulator-min-microvolt = <1704000>; 289 + regulator-max-microvolt = <2928000>; 290 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 291 + }; 292 + 293 + vreg_l10a_1p8: ldo10 { 294 + regulator-min-microvolt = <1704000>; 295 + regulator-max-microvolt = <2928000>; 296 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 297 + }; 298 + 299 + vreg_l11a_1p0: ldo11 { 300 + regulator-min-microvolt = <1000000>; 301 + regulator-max-microvolt = <1048000>; 302 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 303 + }; 304 + 305 + vdd_qfprom: 306 + vdd_qfprom_sp: 307 + vdda_apc1_cs_1p8: 308 + vdda_gfx_cs_1p8: 309 + vdda_qrefs_1p8: 310 + vdda_qusb_hs0_1p8: 311 + vddpx_11: 312 + vreg_l12a_1p8: ldo12 { 313 + regulator-min-microvolt = <1800000>; 314 + regulator-max-microvolt = <1800000>; 315 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 316 + }; 317 + 318 + vddpx_2: 319 + vreg_l13a_2p95: ldo13 { 320 + regulator-min-microvolt = <1800000>; 321 + regulator-max-microvolt = <2960000>; 322 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 323 + }; 324 + 325 + vreg_l14a_1p88: ldo14 { 326 + regulator-min-microvolt = <1800000>; 327 + regulator-max-microvolt = <1880000>; 328 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 329 + }; 330 + 331 + vreg_l15a_1p8: ldo15 { 332 + regulator-min-microvolt = <1800000>; 333 + regulator-max-microvolt = <1800000>; 334 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 335 + }; 336 + 337 + vreg_l17a_1p3: ldo17 { 338 + regulator-min-microvolt = <1304000>; 339 + regulator-max-microvolt = <1304000>; 340 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 341 + }; 342 + 343 + vreg_l18a_2p7: ldo18 { 344 + regulator-min-microvolt = <2704000>; 345 + regulator-max-microvolt = <2960000>; 346 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 347 + }; 348 + 349 + vreg_l20a_2p95: ldo20 { 350 + regulator-min-microvolt = <2704000>; 351 + regulator-max-microvolt = <2960000>; 352 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 353 + }; 354 + 355 + vreg_l21a_2p95: ldo21 { 356 + regulator-min-microvolt = <2704000>; 357 + regulator-max-microvolt = <2960000>; 358 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 359 + }; 360 + 361 + vreg_l22a_2p85: ldo22 { 362 + regulator-min-microvolt = <2800000>; 363 + regulator-max-microvolt = <2800000>; 364 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 365 + }; 366 + 367 + vreg_l23a_3p3: ldo23 { 368 + regulator-min-microvolt = <3000000>; 369 + regulator-max-microvolt = <3312000>; 370 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 371 + }; 372 + 373 + vdda_qusb_hs0_3p1: 374 + vreg_l24a_3p075: ldo24 { 375 + regulator-min-microvolt = <3088000>; 376 + regulator-max-microvolt = <3088000>; 377 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 378 + }; 379 + 380 + vreg_l25a_3p3: ldo25 { 381 + regulator-min-microvolt = <3000000>; 382 + regulator-max-microvolt = <3312000>; 383 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 384 + }; 385 + 386 + vdda_hp_pcie_1p2: 387 + vdda_hv_ebi0: 388 + vdda_hv_ebi1: 389 + vdda_hv_ebi2: 390 + vdda_hv_ebi3: 391 + vdda_mipi_csi_1p25: 392 + vdda_mipi_dsi0_1p2: 393 + vdda_mipi_dsi1_1p2: 394 + vdda_pcie_1p2: 395 + vdda_ufs1_1p2: 396 + vdda_ufs2_1p2: 397 + vdda_usb1_ss_1p2: 398 + vdda_usb2_ss_1p2: 399 + vreg_l26a_1p2: ldo26 { 400 + regulator-min-microvolt = <1200000>; 401 + regulator-max-microvolt = <1200000>; 402 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 403 + }; 404 + 405 + vreg_l28a_3p0: ldo28 { 406 + regulator-min-microvolt = <1800000>; 407 + regulator-max-microvolt = <1800000>; 408 + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 409 + }; 410 + 411 + vreg_lvs1a_1p8: lvs1 { 412 + regulator-min-microvolt = <1800000>; 413 + regulator-max-microvolt = <1800000>; 414 + }; 415 + 416 + vreg_lvs2a_1p8: lvs2 { 417 + regulator-min-microvolt = <1800000>; 418 + regulator-max-microvolt = <1800000>; 419 + }; 420 + }; 421 + 422 + pmi8998-rpmh-regulators { 423 + compatible = "qcom,pmi8998-rpmh-regulators"; 424 + qcom,pmic-id = "b"; 425 + 426 + vdd-bob-supply = <&vph_pwr>; 427 + 428 + vreg_bob: bob { 429 + regulator-min-microvolt = <3312000>; 430 + regulator-max-microvolt = <3600000>; 431 + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; 432 + regulator-allow-bypass; 433 + }; 434 + }; 435 + 436 + pm8005-rpmh-regulators { 437 + compatible = "qcom,pm8005-rpmh-regulators"; 438 + qcom,pmic-id = "c"; 439 + 440 + vdd-s1-supply = <&vph_pwr>; 441 + vdd-s2-supply = <&vph_pwr>; 442 + vdd-s3-supply = <&vph_pwr>; 443 + vdd-s4-supply = <&vph_pwr>; 444 + 445 + vreg_s3c_0p6: smps3 { 446 + regulator-min-microvolt = <600000>; 447 + regulator-max-microvolt = <600000>; 448 + }; 449 + }; 450 + }; 451 + 452 + &cdsp_pas { 453 + status = "okay"; 454 + }; 455 + 456 + &dispcc { 457 + status = "disabled"; 458 + }; 459 + 460 + &gcc { 461 + protected-clocks = <GCC_QSPI_CORE_CLK>, 462 + <GCC_QSPI_CORE_CLK_SRC>, 463 + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 464 + <GCC_LPASS_Q6_AXI_CLK>, 465 + <GCC_LPASS_SWAY_CLK>; 466 + }; 467 + 468 + &gpu { 469 + status = "okay"; 470 + 471 + zap-shader { 472 + memory-region = <&gpu_mem>; 473 + }; 474 + }; 475 + 476 + &ipa { 477 + status = "okay"; 478 + modem-init; 479 + }; 480 + 481 + &mss_pil { 482 + status = "okay"; 483 + }; 484 + 485 + &pm8998_pon { 486 + resin { 487 + compatible = "qcom,pm8941-resin"; 488 + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; 489 + debounce = <15625>; 490 + bias-pull-up; 491 + linux,code = <KEY_VOLUMEDOWN>; 492 + }; 493 + }; 494 + 495 + &sdhc_2 { 496 + status = "okay"; 497 + 498 + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; 499 + 500 + pinctrl-names = "default"; 501 + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; 502 + 503 + vmmc-supply = <&vreg_l21a_2p95>; 504 + vqmmc-supply = <&vddpx_2>; 505 + }; 506 + 507 + /* 508 + * UFS works partially and only with clk_ignore_unused. 509 + * Sometimes it crashes with I/O errors. 510 + */ 511 + &ufs_mem_hc { 512 + status = "okay"; 513 + 514 + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 515 + 516 + vcc-supply = <&vreg_l20a_2p95>; 517 + vcc-max-microamp = <600000>; 518 + }; 519 + 520 + &ufs_mem_phy { 521 + status = "okay"; 522 + 523 + vdda-phy-supply = <&vdda_ufs1_core>; 524 + vdda-pll-supply = <&vdda_ufs1_1p2>; 525 + }; 526 + 527 + &usb_1 { 528 + status = "okay"; 529 + }; 530 + 531 + &usb_1_dwc3 { 532 + /* TODO: these devices have usb id pin */ 533 + dr_mode = "peripheral"; 534 + }; 535 + 536 + &usb_1_hsphy { 537 + status = "okay"; 538 + 539 + vdd-supply = <&vdda_usb1_ss_core>; 540 + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 541 + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 542 + 543 + qcom,imp-res-offset-value = <8>; 544 + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 545 + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 546 + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 547 + }; 548 + 549 + &usb_1_qmpphy { 550 + status = "okay"; 551 + 552 + vdda-phy-supply = <&vdda_usb1_ss_1p2>; 553 + vdda-pll-supply = <&vdda_usb1_ss_core>; 554 + }; 555 + 556 + /* PINCTRL - additions to nodes defined in sdm845.dtsi */ 557 + 558 + &tlmm { 559 + gpio-reserved-ranges = <28 4>, <81 4>; 560 + 561 + sdc2_clk: sdc2-clk { 562 + pinconf { 563 + pins = "sdc2_clk"; 564 + bias-disable; 565 + 566 + /* 567 + * It seems that mmc_test reports errors if drive 568 + * strength is not 16 on clk, cmd, and data pins. 569 + * 570 + * TODO: copy-pasted from mtp, try other values 571 + * on these devices. 572 + */ 573 + drive-strength = <16>; 574 + }; 575 + }; 576 + 577 + sdc2_cmd: sdc2-cmd { 578 + pinconf { 579 + pins = "sdc2_cmd"; 580 + bias-pull-up; 581 + drive-strength = <16>; 582 + }; 583 + }; 584 + 585 + sdc2_data: sdc2-data { 586 + pinconf { 587 + pins = "sdc2_data"; 588 + bias-pull-up; 589 + drive-strength = <16>; 590 + }; 591 + }; 592 + 593 + sd_card_det_n: sd-card-det-n { 594 + pinmux { 595 + pins = "gpio126"; 596 + function = "gpio"; 597 + }; 598 + 599 + pinconf { 600 + pins = "gpio126"; 601 + bias-pull-up; 602 + }; 603 + }; 604 + }; 605 + 606 + &pm8998_gpio { 607 + vol_up_pin_a: vol-up-active-pins { 608 + pins = "gpio6"; 609 + function = "normal"; 610 + input-enable; 611 + bias-pull-up; 612 + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 613 + }; 614 + };
+68
arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * SDM845 LG G7 (judyln) device tree. 4 + * 5 + * Copyright (c) 2022, The Linux Foundation. All rights reserved. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sdm845-lg-common.dtsi" 11 + 12 + / { 13 + model = "LG G7 ThinQ"; 14 + compatible = "lg,judyln", "qcom,sdm845"; 15 + 16 + chosen { 17 + framebuffer@9d400000 { 18 + compatible = "simple-framebuffer"; 19 + reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>; 20 + width = <1440>; 21 + height = <3120>; 22 + stride = <(1440 * 4)>; 23 + format = "a8r8g8b8"; 24 + lab-supply = <&lab>; 25 + ibb-supply = <&ibb>; 26 + }; 27 + }; 28 + 29 + /* Additional ThinQ key */ 30 + gpio-keys { 31 + pinctrl-0 = <&vol_up_pin_a &thinq_key_default>; 32 + 33 + key-thinq { 34 + label = "ThinQ"; 35 + linux,code = <KEY_ASSISTANT>; 36 + interrupt-parent = <&tlmm>; 37 + interrupts = <89 IRQ_TYPE_LEVEL_LOW>; 38 + }; 39 + }; 40 + }; 41 + 42 + &adsp_pas { 43 + firmware-name = "qcom/sdm845/judyln/adsp.mbn"; 44 + }; 45 + 46 + &cdsp_pas { 47 + firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; 48 + }; 49 + 50 + &gpu { 51 + zap-shader { 52 + firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; 53 + }; 54 + }; 55 + 56 + &mss_pil { 57 + firmware-name = "qcom/sdm845/judyln/mba.mbn", "qcom/sdm845/judyln/modem.mbn"; 58 + }; 59 + 60 + &tlmm { 61 + thinq_key_default: thinq-key-default { 62 + pins = "gpio89"; 63 + function = "gpio"; 64 + 65 + drive-strength = <2>; 66 + bias-pull-up; 67 + }; 68 + };
+44
arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * SDM845 LG V35 (judyp) device tree. 4 + * 5 + * Copyright (c) 2022, The Linux Foundation. All rights reserved. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "sdm845-lg-common.dtsi" 11 + 12 + / { 13 + model = "LG V35 ThinQ"; 14 + compatible = "lg,judyp", "qcom,sdm845"; 15 + 16 + chosen { 17 + framebuffer@9d400000 { 18 + compatible = "simple-framebuffer"; 19 + reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>; 20 + width = <1440>; 21 + height = <2880>; 22 + stride = <(1440 * 4)>; 23 + format = "a8r8g8b8"; 24 + }; 25 + }; 26 + }; 27 + 28 + &adsp_pas { 29 + firmware-name = "qcom/sdm845/judyp/adsp.mbn"; 30 + }; 31 + 32 + &cdsp_pas { 33 + firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; 34 + }; 35 + 36 + &gpu { 37 + zap-shader { 38 + firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; 39 + }; 40 + }; 41 + 42 + &mss_pil { 43 + firmware-name = "qcom/sdm845/judyp/mba.mbn", "qcom/sdm845/judyp/modem.mbn"; 44 + };
+4 -4
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
··· 34 34 pinctrl-names = "default"; 35 35 pinctrl-0 = <&volume_down_gpio &volume_up_gpio>; 36 36 37 - vol-down { 37 + key-vol-down { 38 38 label = "Volume down"; 39 39 linux,code = <KEY_VOLUMEDOWN>; 40 40 gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; 41 41 debounce-interval = <15>; 42 42 }; 43 43 44 - vol-up { 44 + key-vol-up { 45 45 label = "Volume up"; 46 46 linux,code = <KEY_VOLUMEUP>; 47 47 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; ··· 440 440 }; 441 441 442 442 &pm8998_gpio { 443 - volume_down_gpio: pm8998_gpio5 { 443 + volume_down_gpio: pm8998-gpio5-state { 444 444 pinconf { 445 445 pins = "gpio5"; 446 446 function = "normal"; ··· 450 450 }; 451 451 }; 452 452 453 - volume_up_gpio: pm8998_gpio6 { 453 + volume_up_gpio: pm8998-gpio6-state { 454 454 pinconf { 455 455 pins = "gpio6"; 456 456 function = "normal";
+32 -3
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
··· 2 2 /* 3 3 * Copyright (c) 2022, Alexander Martinz <amartinz@shiftphones.com> 4 4 * Copyright (c) 2022, Caleb Connolly <caleb@connolly.tech> 5 + * Copyright (c) 2022, Dylan Van Assche <me@dylanvanassche.be> 5 6 */ 6 7 7 8 /dts-v1/; 8 9 9 10 #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/leds/common.h> 10 12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 13 #include "sdm845.dtsi" 12 14 #include "pm8998.dtsi" ··· 50 48 pinctrl-names = "default"; 51 49 pinctrl-0 = <&volume_up_gpio>; 52 50 53 - vol-up { 51 + key-vol-up { 54 52 label = "volume_up"; 55 53 linux,code = <KEY_VOLUMEUP>; 56 54 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; ··· 470 468 }; 471 469 472 470 &i2c5 { 473 - status="okay"; 471 + status = "okay"; 474 472 475 473 touchscreen@38 { 476 474 compatible = "focaltech,fts8719"; ··· 510 508 }; 511 509 512 510 &pm8998_gpio { 513 - volume_up_gpio: pm8998_gpio6 { 511 + volume_up_gpio: pm8998-gpio6-state { 514 512 pinconf { 515 513 pins = "gpio6"; 516 514 function = "normal"; ··· 528 526 debounce = <15625>; 529 527 bias-pull-up; 530 528 linux,code = <KEY_VOLUMEDOWN>; 529 + }; 530 + }; 531 + 532 + &pmi8998_lpg { 533 + status = "okay"; 534 + 535 + multi-led { 536 + color = <LED_COLOR_ID_RGB>; 537 + function = LED_FUNCTION_STATUS; 538 + 539 + #address-cells = <1>; 540 + #size-cells = <0>; 541 + 542 + led@3 { 543 + reg = <3>; 544 + color = <LED_COLOR_ID_BLUE>; 545 + }; 546 + 547 + led@4 { 548 + reg = <4>; 549 + color = <LED_COLOR_ID_GREEN>; 550 + }; 551 + 552 + led@5 { 553 + reg = <5>; 554 + color = <LED_COLOR_ID_RED>; 555 + }; 531 556 }; 532 557 }; 533 558
+3 -2
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts
··· 19 19 }; 20 20 21 21 &vreg_l22a_2p8 { 22 - regulator-min-microvolt = <2700000>; 23 - regulator-max-microvolt = <2700000>; 22 + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ 23 + regulator-min-microvolt = <2696000>; 24 + regulator-max-microvolt = <2696000>; 24 25 }; 25 26 26 27 &vreg_l28a_2p8 {
+1 -1
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
··· 19 19 20 20 /* Neither Camera Focus, nor Camera Shutter seem to work... */ 21 21 22 - vol-down { 22 + key-vol-down { 23 23 label = "volume_down"; 24 24 gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; 25 25 linux,code = <KEY_VOLUMEDOWN>;
+4 -4
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
··· 45 45 pinctrl-names = "default"; 46 46 pinctrl-0 = <&vol_up_pin_a>; 47 47 48 - vol-up { 48 + key-vol-up { 49 49 label = "Volume Up"; 50 50 linux,code = <KEY_VOLUMEUP>; 51 51 gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; ··· 306 306 }; 307 307 308 308 &pm8998_gpio { 309 - vol_up_pin_a: vol-up-active { 309 + vol_up_pin_a: vol-up-active-state { 310 310 pins = "gpio6"; 311 311 function = "normal"; 312 312 input-enable; ··· 339 339 /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ 340 340 &q6afedai { 341 341 qi2s@22 { 342 - reg = <22>; 342 + reg = <QUATERNARY_MI2S_RX>; 343 343 qcom,sd-lines = <0>; 344 344 }; 345 345 }; ··· 419 419 }; 420 420 421 421 codec { 422 - sound-dai = <&wcd9340 0>; 422 + sound-dai = <&wcd9340 0>; 423 423 }; 424 424 }; 425 425
+151 -92
arch/arm64/boot/dts/qcom/sdm845.dtsi
··· 188 188 }; 189 189 }; 190 190 191 - cpus { 191 + cpus: cpus { 192 192 #address-cells = <2>; 193 193 #size-cells = <0>; 194 194 ··· 197 197 compatible = "qcom,kryo385"; 198 198 reg = <0x0 0x0>; 199 199 enable-method = "psci"; 200 - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 201 - &LITTLE_CPU_SLEEP_1 202 - &CLUSTER_SLEEP_0>; 203 200 capacity-dmips-mhz = <611>; 204 201 dynamic-power-coefficient = <290>; 205 202 qcom,freq-domain = <&cpufreq_hw 0>; 206 203 operating-points-v2 = <&cpu0_opp_table>; 207 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 208 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 206 + power-domains = <&CPU_PD0>; 207 + power-domain-names = "psci"; 209 208 #cooling-cells = <2>; 210 209 next-level-cache = <&L2_0>; 211 210 L2_0: l2-cache { ··· 221 222 compatible = "qcom,kryo385"; 222 223 reg = <0x0 0x100>; 223 224 enable-method = "psci"; 224 - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 - &LITTLE_CPU_SLEEP_1 226 - &CLUSTER_SLEEP_0>; 227 225 capacity-dmips-mhz = <611>; 228 226 dynamic-power-coefficient = <290>; 229 227 qcom,freq-domain = <&cpufreq_hw 0>; 230 228 operating-points-v2 = <&cpu0_opp_table>; 231 229 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 232 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 231 + power-domains = <&CPU_PD1>; 232 + power-domain-names = "psci"; 233 233 #cooling-cells = <2>; 234 234 next-level-cache = <&L2_100>; 235 235 L2_100: l2-cache { ··· 242 244 compatible = "qcom,kryo385"; 243 245 reg = <0x0 0x200>; 244 246 enable-method = "psci"; 245 - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 246 - &LITTLE_CPU_SLEEP_1 247 - &CLUSTER_SLEEP_0>; 248 247 capacity-dmips-mhz = <611>; 249 248 dynamic-power-coefficient = <290>; 250 249 qcom,freq-domain = <&cpufreq_hw 0>; 251 250 operating-points-v2 = <&cpu0_opp_table>; 252 251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 253 252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 253 + power-domains = <&CPU_PD2>; 254 + power-domain-names = "psci"; 254 255 #cooling-cells = <2>; 255 256 next-level-cache = <&L2_200>; 256 257 L2_200: l2-cache { ··· 263 266 compatible = "qcom,kryo385"; 264 267 reg = <0x0 0x300>; 265 268 enable-method = "psci"; 266 - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 267 - &LITTLE_CPU_SLEEP_1 268 - &CLUSTER_SLEEP_0>; 269 269 capacity-dmips-mhz = <611>; 270 270 dynamic-power-coefficient = <290>; 271 271 qcom,freq-domain = <&cpufreq_hw 0>; ··· 270 276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 271 277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 272 278 #cooling-cells = <2>; 279 + power-domains = <&CPU_PD3>; 280 + power-domain-names = "psci"; 273 281 next-level-cache = <&L2_300>; 274 282 L2_300: l2-cache { 275 283 compatible = "cache"; ··· 285 289 reg = <0x0 0x400>; 286 290 enable-method = "psci"; 287 291 capacity-dmips-mhz = <1024>; 288 - cpu-idle-states = <&BIG_CPU_SLEEP_0 289 - &BIG_CPU_SLEEP_1 290 - &CLUSTER_SLEEP_0>; 291 292 dynamic-power-coefficient = <442>; 292 293 qcom,freq-domain = <&cpufreq_hw 1>; 293 294 operating-points-v2 = <&cpu4_opp_table>; 294 295 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 296 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 297 + power-domains = <&CPU_PD4>; 298 + power-domain-names = "psci"; 296 299 #cooling-cells = <2>; 297 300 next-level-cache = <&L2_400>; 298 301 L2_400: l2-cache { ··· 306 311 reg = <0x0 0x500>; 307 312 enable-method = "psci"; 308 313 capacity-dmips-mhz = <1024>; 309 - cpu-idle-states = <&BIG_CPU_SLEEP_0 310 - &BIG_CPU_SLEEP_1 311 - &CLUSTER_SLEEP_0>; 312 314 dynamic-power-coefficient = <442>; 313 315 qcom,freq-domain = <&cpufreq_hw 1>; 314 316 operating-points-v2 = <&cpu4_opp_table>; 315 317 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 316 318 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 319 + power-domains = <&CPU_PD5>; 320 + power-domain-names = "psci"; 317 321 #cooling-cells = <2>; 318 322 next-level-cache = <&L2_500>; 319 323 L2_500: l2-cache { ··· 327 333 reg = <0x0 0x600>; 328 334 enable-method = "psci"; 329 335 capacity-dmips-mhz = <1024>; 330 - cpu-idle-states = <&BIG_CPU_SLEEP_0 331 - &BIG_CPU_SLEEP_1 332 - &CLUSTER_SLEEP_0>; 333 336 dynamic-power-coefficient = <442>; 334 337 qcom,freq-domain = <&cpufreq_hw 1>; 335 338 operating-points-v2 = <&cpu4_opp_table>; 336 339 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 337 340 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 341 + power-domains = <&CPU_PD6>; 342 + power-domain-names = "psci"; 338 343 #cooling-cells = <2>; 339 344 next-level-cache = <&L2_600>; 340 345 L2_600: l2-cache { ··· 348 355 reg = <0x0 0x700>; 349 356 enable-method = "psci"; 350 357 capacity-dmips-mhz = <1024>; 351 - cpu-idle-states = <&BIG_CPU_SLEEP_0 352 - &BIG_CPU_SLEEP_1 353 - &CLUSTER_SLEEP_0>; 354 358 dynamic-power-coefficient = <442>; 355 359 qcom,freq-domain = <&cpufreq_hw 1>; 356 360 operating-points-v2 = <&cpu4_opp_table>; 357 361 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 358 362 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 363 + power-domains = <&CPU_PD7>; 364 + power-domain-names = "psci"; 359 365 #cooling-cells = <2>; 360 366 next-level-cache = <&L2_700>; 361 367 L2_700: l2-cache { ··· 399 407 }; 400 408 }; 401 409 402 - idle-states { 410 + cpu_idle_states: idle-states { 403 411 entry-method = "psci"; 404 412 405 413 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 406 414 compatible = "arm,idle-state"; 407 - idle-state-name = "little-power-down"; 408 - arm,psci-suspend-param = <0x40000003>; 415 + idle-state-name = "little-rail-power-collapse"; 416 + arm,psci-suspend-param = <0x40000004>; 409 417 entry-latency-us = <350>; 410 418 exit-latency-us = <461>; 411 419 min-residency-us = <1890>; 412 420 local-timer-stop; 413 421 }; 414 422 415 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 416 - compatible = "arm,idle-state"; 417 - idle-state-name = "little-rail-power-down"; 418 - arm,psci-suspend-param = <0x40000004>; 419 - entry-latency-us = <360>; 420 - exit-latency-us = <531>; 421 - min-residency-us = <3934>; 422 - local-timer-stop; 423 - }; 424 - 425 423 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 426 424 compatible = "arm,idle-state"; 427 - idle-state-name = "big-power-down"; 428 - arm,psci-suspend-param = <0x40000003>; 425 + idle-state-name = "big-rail-power-collapse"; 426 + arm,psci-suspend-param = <0x40000004>; 429 427 entry-latency-us = <264>; 430 428 exit-latency-us = <621>; 431 429 min-residency-us = <952>; 432 430 local-timer-stop; 433 431 }; 432 + }; 434 433 435 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 436 - compatible = "arm,idle-state"; 437 - idle-state-name = "big-rail-power-down"; 438 - arm,psci-suspend-param = <0x40000004>; 439 - entry-latency-us = <702>; 440 - exit-latency-us = <1061>; 441 - min-residency-us = <4488>; 442 - local-timer-stop; 443 - }; 444 - 434 + domain-idle-states { 445 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 446 - compatible = "arm,idle-state"; 447 - idle-state-name = "cluster-power-down"; 448 - arm,psci-suspend-param = <0x400000F4>; 436 + compatible = "domain-idle-state"; 437 + idle-state-name = "cluster-power-collapse"; 438 + arm,psci-suspend-param = <0x4100c244>; 449 439 entry-latency-us = <3263>; 450 440 exit-latency-us = <6562>; 451 441 min-residency-us = <9987>; ··· 436 462 }; 437 463 }; 438 464 439 - cpu0_opp_table: cpu0_opp_table { 465 + cpu0_opp_table: opp-table-cpu0 { 440 466 compatible = "operating-points-v2"; 441 467 opp-shared; 442 468 ··· 531 557 }; 532 558 }; 533 559 534 - cpu4_opp_table: cpu4_opp_table { 560 + cpu4_opp_table: opp-table-cpu4 { 535 561 compatible = "operating-points-v2"; 536 562 opp-shared; 537 563 ··· 1024 1050 }; 1025 1051 }; 1026 1052 1027 - psci { 1053 + psci: psci { 1028 1054 compatible = "arm,psci-1.0"; 1029 1055 method = "smc"; 1056 + 1057 + CPU_PD0: power-domain-cpu0 { 1058 + #power-domain-cells = <0>; 1059 + power-domains = <&CLUSTER_PD>; 1060 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1061 + }; 1062 + 1063 + CPU_PD1: power-domain-cpu1 { 1064 + #power-domain-cells = <0>; 1065 + power-domains = <&CLUSTER_PD>; 1066 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1067 + }; 1068 + 1069 + CPU_PD2: power-domain-cpu2 { 1070 + #power-domain-cells = <0>; 1071 + power-domains = <&CLUSTER_PD>; 1072 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1073 + }; 1074 + 1075 + CPU_PD3: power-domain-cpu3 { 1076 + #power-domain-cells = <0>; 1077 + power-domains = <&CLUSTER_PD>; 1078 + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1079 + }; 1080 + 1081 + CPU_PD4: power-domain-cpu4 { 1082 + #power-domain-cells = <0>; 1083 + power-domains = <&CLUSTER_PD>; 1084 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 1085 + }; 1086 + 1087 + CPU_PD5: power-domain-cpu5 { 1088 + #power-domain-cells = <0>; 1089 + power-domains = <&CLUSTER_PD>; 1090 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 1091 + }; 1092 + 1093 + CPU_PD6: power-domain-cpu6 { 1094 + #power-domain-cells = <0>; 1095 + power-domains = <&CLUSTER_PD>; 1096 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 1097 + }; 1098 + 1099 + CPU_PD7: power-domain-cpu7 { 1100 + #power-domain-cells = <0>; 1101 + power-domains = <&CLUSTER_PD>; 1102 + domain-idle-states = <&BIG_CPU_SLEEP_0>; 1103 + }; 1104 + 1105 + CLUSTER_PD: power-domain-cluster { 1106 + #power-domain-cells = <0>; 1107 + domain-idle-states = <&CLUSTER_SLEEP_0>; 1108 + }; 1030 1109 }; 1031 1110 1032 1111 soc: soc@0 { ··· 1131 1104 clock-names = "core"; 1132 1105 }; 1133 1106 1134 - qup_opp_table: qup-opp-table { 1107 + qup_opp_table: opp-table-qup { 1135 1108 compatible = "operating-points-v2"; 1136 1109 1137 1110 opp-50000000 { ··· 2051 2024 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 2052 2025 reg-names = "llcc_base", "llcc_broadcast_base"; 2053 2026 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2027 + }; 2028 + 2029 + pmu@1436400 { 2030 + compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; 2031 + reg = <0 0x01436400 0 0x600>; 2032 + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2033 + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2034 + 2035 + operating-points-v2 = <&cpu_bwmon_opp_table>; 2036 + 2037 + cpu_bwmon_opp_table: opp-table { 2038 + compatible = "operating-points-v2"; 2039 + 2040 + /* 2041 + * The interconnect path bandwidth taken from 2042 + * cpu4_opp_table bandwidth for OSM L3 2043 + * interconnect. This also matches the OSM L3 2044 + * from bandwidth table of qcom,cpu4-l3lat-mon 2045 + * (qcom,core-dev-table, bus width: 16 bytes) 2046 + * from msm-4.9 downstream kernel. 2047 + */ 2048 + opp-0 { 2049 + opp-peak-kBps = <4800000>; 2050 + }; 2051 + opp-1 { 2052 + opp-peak-kBps = <9216000>; 2053 + }; 2054 + opp-2 { 2055 + opp-peak-kBps = <15052800>; 2056 + }; 2057 + opp-3 { 2058 + opp-peak-kBps = <20889600>; 2059 + }; 2060 + opp-4 { 2061 + opp-peak-kBps = <25497600>; 2062 + }; 2063 + }; 2054 2064 }; 2055 2065 2056 2066 pcie0: pci@1c00000 { ··· 3615 3551 }; 3616 3552 }; 3617 3553 3618 - sdhc_2: sdhci@8804000 { 3554 + sdhc_2: mmc@8804000 { 3619 3555 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3620 3556 reg = <0 0x08804000 0 0x1000>; 3621 3557 ··· 3633 3569 3634 3570 status = "disabled"; 3635 3571 3636 - sdhc2_opp_table: sdhc2-opp-table { 3572 + sdhc2_opp_table: opp-table { 3637 3573 compatible = "operating-points-v2"; 3638 3574 3639 3575 opp-9600000 { ··· 3658 3594 }; 3659 3595 }; 3660 3596 3661 - qspi_opp_table: qspi-opp-table { 3597 + qspi_opp_table: opp-table-qspi { 3662 3598 compatible = "operating-points-v2"; 3663 3599 3664 3600 opp-19200000 { ··· 3704 3640 qcom,apps-ch-pipes = <0x780000>; 3705 3641 qcom,ea-pc = <0x270>; 3706 3642 status = "okay"; 3707 - dmas = <&slimbam 3>, <&slimbam 4>, 3643 + dmas = <&slimbam 3>, <&slimbam 4>, 3708 3644 <&slimbam 5>, <&slimbam 6>; 3709 3645 dma-names = "rx", "tx", "tx2", "rx2"; 3710 3646 ··· 3719 3655 3720 3656 wcd9340_ifd: ifd@0{ 3721 3657 compatible = "slim217,250"; 3722 - reg = <0 0>; 3658 + reg = <0 0>; 3723 3659 }; 3724 3660 3725 3661 wcd9340: codec@1{ 3726 3662 compatible = "slim217,250"; 3727 - reg = <1 0>; 3728 - slim-ifc-dev = <&wcd9340_ifd>; 3663 + reg = <1 0>; 3664 + slim-ifc-dev = <&wcd9340_ifd>; 3729 3665 3730 3666 #sound-dai-cells = <1>; 3731 3667 ··· 3756 3692 reg = <0xc85 0x40>; 3757 3693 interrupts-extended = <&wcd9340 20>; 3758 3694 3759 - qcom,dout-ports = <6>; 3760 - qcom,din-ports = <2>; 3695 + qcom,dout-ports = <6>; 3696 + qcom,din-ports = <2>; 3761 3697 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3762 3698 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3763 3699 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; ··· 4035 3971 compatible = "venus-encoder"; 4036 3972 }; 4037 3973 4038 - venus_opp_table: venus-opp-table { 3974 + venus_opp_table: opp-table { 4039 3975 compatible = "operating-points-v2"; 4040 3976 4041 3977 opp-100000000 { ··· 4272 4208 clock-names = "bi_tcxo"; 4273 4209 }; 4274 4210 4275 - dsi_opp_table: dsi-opp-table { 4211 + dsi_opp_table: opp-table-dsi { 4276 4212 compatible = "operating-points-v2"; 4277 4213 4278 4214 opp-19200000 { ··· 4308 4244 4309 4245 power-domains = <&dispcc MDSS_GDSC>; 4310 4246 4311 - clocks = <&gcc GCC_DISP_AHB_CLK>, 4247 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4312 4248 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4313 4249 clock-names = "iface", "core"; 4314 - 4315 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 4316 - assigned-clock-rates = <300000000>; 4317 4250 4318 4251 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4319 4252 interrupt-controller; ··· 4342 4281 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4343 4282 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4344 4283 4345 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 4346 - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4347 - assigned-clock-rates = <300000000>, 4348 - <19200000>; 4284 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4285 + assigned-clock-rates = <19200000>; 4349 4286 operating-points-v2 = <&mdp_opp_table>; 4350 4287 power-domains = <&rpmhpd SDM845_CX>; 4351 4288 ··· 4369 4310 }; 4370 4311 }; 4371 4312 4372 - mdp_opp_table: mdp-opp-table { 4313 + mdp_opp_table: opp-table { 4373 4314 compatible = "operating-points-v2"; 4374 4315 4375 4316 opp-19200000 { ··· 4633 4574 }; 4634 4575 4635 4576 gmu: gmu@506a000 { 4636 - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4577 + compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4637 4578 4638 4579 reg = <0 0x506a000 0 0x30000>, 4639 4580 <0 0xb280000 0 0x10000>, ··· 4780 4721 cell-index = <0>; 4781 4722 }; 4782 4723 4783 - imem@146bf000 { 4784 - compatible = "simple-mfd"; 4724 + sram@146bf000 { 4725 + compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 4785 4726 reg = <0 0x146bf000 0 0x1000>; 4786 4727 4787 4728 #address-cells = <1>; ··· 4998 4939 compatible = "qcom,bam-v1.7.0"; 4999 4940 qcom,controlled-remotely; 5000 4941 reg = <0 0x17184000 0 0x2a000>; 5001 - num-channels = <31>; 4942 + num-channels = <31>; 5002 4943 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5003 4944 #dma-cells = <1>; 5004 4945 qcom,ee = <1>; ··· 5007 4948 }; 5008 4949 5009 4950 timer@17c90000 { 5010 - #address-cells = <2>; 5011 - #size-cells = <2>; 5012 - ranges; 4951 + #address-cells = <1>; 4952 + #size-cells = <1>; 4953 + ranges = <0 0 0 0x20000000>; 5013 4954 compatible = "arm,armv7-timer-mem"; 5014 4955 reg = <0 0x17c90000 0 0x1000>; 5015 4956 ··· 5017 4958 frame-number = <0>; 5018 4959 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5019 4960 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5020 - reg = <0 0x17ca0000 0 0x1000>, 5021 - <0 0x17cb0000 0 0x1000>; 4961 + reg = <0x17ca0000 0x1000>, 4962 + <0x17cb0000 0x1000>; 5022 4963 }; 5023 4964 5024 4965 frame@17cc0000 { 5025 4966 frame-number = <1>; 5026 4967 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5027 - reg = <0 0x17cc0000 0 0x1000>; 4968 + reg = <0x17cc0000 0x1000>; 5028 4969 status = "disabled"; 5029 4970 }; 5030 4971 5031 4972 frame@17cd0000 { 5032 4973 frame-number = <2>; 5033 4974 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5034 - reg = <0 0x17cd0000 0 0x1000>; 4975 + reg = <0x17cd0000 0x1000>; 5035 4976 status = "disabled"; 5036 4977 }; 5037 4978 5038 4979 frame@17ce0000 { 5039 4980 frame-number = <3>; 5040 4981 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5041 - reg = <0 0x17ce0000 0 0x1000>; 4982 + reg = <0x17ce0000 0x1000>; 5042 4983 status = "disabled"; 5043 4984 }; 5044 4985 5045 4986 frame@17cf0000 { 5046 4987 frame-number = <4>; 5047 4988 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5048 - reg = <0 0x17cf0000 0 0x1000>; 4989 + reg = <0x17cf0000 0x1000>; 5049 4990 status = "disabled"; 5050 4991 }; 5051 4992 5052 4993 frame@17d00000 { 5053 4994 frame-number = <5>; 5054 4995 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5055 - reg = <0 0x17d00000 0 0x1000>; 4996 + reg = <0x17d00000 0x1000>; 5056 4997 status = "disabled"; 5057 4998 }; 5058 4999 5059 5000 frame@17d10000 { 5060 5001 frame-number = <6>; 5061 5002 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5062 - reg = <0 0x17d10000 0 0x1000>; 5003 + reg = <0x17d10000 0x1000>; 5063 5004 status = "disabled"; 5064 5005 }; 5065 5006 };
+5 -5
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
··· 41 41 pinctrl-names = "default"; 42 42 pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; 43 43 44 - lid { 44 + switch-lid { 45 45 gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; 46 46 linux,input-type = <EV_SW>; 47 47 linux,code = <SW_LID>; ··· 49 49 wakeup-event-action = <EV_ACT_DEASSERTED>; 50 50 }; 51 51 52 - mode { 52 + switch-mode { 53 53 gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 54 54 linux,input-type = <EV_SW>; 55 55 linux,code = <SW_TABLET_MODE>; ··· 581 581 }; 582 582 583 583 codec { 584 - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 584 + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 585 585 }; 586 586 }; 587 587 ··· 611 611 }; 612 612 613 613 codec { 614 - sound-dai = <&wcd9340 2>; 614 + sound-dai = <&wcd9340 2>; 615 615 }; 616 616 }; 617 617 }; ··· 817 817 818 818 &crypto { 819 819 /* FIXME: qce_start triggers an SError */ 820 - status= "disable"; 820 + status = "disable"; 821 821 };
+2 -2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
··· 509 509 }; 510 510 511 511 codec { 512 - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 512 + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; 513 513 }; 514 514 }; 515 515 ··· 539 539 }; 540 540 541 541 codec { 542 - sound-dai = <&wcd9340 2>; 542 + sound-dai = <&wcd9340 2>; 543 543 }; 544 544 }; 545 545 };
+11 -31
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
··· 42 42 gpio-keys { 43 43 status = "okay"; 44 44 compatible = "gpio-keys"; 45 - #address-cells = <1>; 46 - #size-cells = <0>; 47 45 autorepeat; 48 46 49 - vol-dn { 47 + key-vol-dn { 50 48 label = "Volume Down"; 51 49 gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; 52 50 linux,input-type = <1>; ··· 86 88 status = "okay"; 87 89 }; 88 90 89 - &sdc2_state_off { 91 + &sdc2_off_state { 90 92 sd-cd { 91 93 pins = "gpio98"; 92 - bias-disable; 93 94 drive-strength = <2>; 95 + bias-disable; 96 + }; 97 + }; 98 + 99 + &sdc2_on_state { 100 + sd-cd { 101 + pins = "gpio98"; 102 + drive-strength = <2>; 103 + bias-pull-up; 94 104 }; 95 105 }; 96 106 ··· 108 102 109 103 &tlmm { 110 104 gpio-reserved-ranges = <22 2>, <28 6>; 111 - 112 - sdc2_state_on: sdc2-on { 113 - clk { 114 - pins = "sdc2_clk"; 115 - bias-disable; 116 - drive-strength = <16>; 117 - }; 118 - 119 - cmd { 120 - pins = "sdc2_cmd"; 121 - bias-pull-up; 122 - drive-strength = <10>; 123 - }; 124 - 125 - data { 126 - pins = "sdc2_data"; 127 - bias-pull-up; 128 - drive-strength = <10>; 129 - }; 130 - 131 - sd-cd { 132 - pins = "gpio98"; 133 - bias-pull-up; 134 - drive-strength = <2>; 135 - }; 136 - }; 137 105 }; 138 106 139 107 &usb3 {
+34 -8
arch/arm64/boot/dts/qcom/sm6125.dtsi
··· 386 386 interrupt-controller; 387 387 #interrupt-cells = <2>; 388 388 389 - sdc2_state_off: sdc2-off { 389 + sdc2_off_state: sdc2-off-state { 390 390 clk { 391 391 pins = "sdc2_clk"; 392 - bias-disable; 393 392 drive-strength = <2>; 393 + bias-disable; 394 394 }; 395 395 396 396 cmd { 397 397 pins = "sdc2_cmd"; 398 - bias-pull-up; 399 398 drive-strength = <2>; 399 + bias-pull-up; 400 400 }; 401 401 402 402 data { 403 403 pins = "sdc2_data"; 404 - bias-pull-up; 405 404 drive-strength = <2>; 405 + bias-pull-up; 406 + }; 407 + }; 408 + 409 + sdc2_on_state: sdc2-on-state { 410 + clk { 411 + pins = "sdc2_clk"; 412 + drive-strength = <16>; 413 + bias-disable; 414 + }; 415 + 416 + cmd { 417 + pins = "sdc2_cmd"; 418 + drive-strength = <10>; 419 + bias-pull-up; 420 + }; 421 + 422 + data { 423 + pins = "sdc2_data"; 424 + drive-strength = <10>; 425 + bias-pull-up; 406 426 }; 407 427 }; 408 428 }; ··· 455 435 reg = <0x045f0000 0x7000>; 456 436 }; 457 437 458 - sdhc_1: sdhci@4744000 { 438 + sdhc_1: mmc@4744000 { 459 439 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 460 440 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 461 441 reg-names = "hc", "core"; ··· 471 451 472 452 power-domains = <&rpmpd SM6125_VDDCX>; 473 453 454 + qcom,dll-config = <0x000f642c>; 455 + qcom,ddr-config = <0x80040873>; 456 + 474 457 bus-width = <8>; 475 458 non-removable; 476 459 status = "disabled"; 477 460 }; 478 461 479 - sdhc_2: sdhci@4784000 { 462 + sdhc_2: mmc@4784000 { 480 463 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 481 464 reg = <0x04784000 0x1000>; 482 465 reg-names = "hc"; ··· 493 470 <&xo_board>; 494 471 clock-names = "iface", "core", "xo"; 495 472 496 - pinctrl-0 = <&sdc2_state_on>; 497 - pinctrl-1 = <&sdc2_state_off>; 473 + pinctrl-0 = <&sdc2_on_state>; 474 + pinctrl-1 = <&sdc2_off_state>; 498 475 pinctrl-names = "default", "sleep"; 499 476 500 477 power-domains = <&rpmpd SM6125_VDDCX>; 478 + 479 + qcom,dll-config = <0x0007642c>; 480 + qcom,ddr-config = <0x80040873>; 501 481 502 482 bus-width = <4>; 503 483 status = "disabled";
+15 -15
arch/arm64/boot/dts/qcom/sm6350.dtsi
··· 472 472 clock-names = "core"; 473 473 }; 474 474 475 - sdhc_1: sdhci@7c4000 { 475 + sdhc_1: mmc@7c4000 { 476 476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 477 477 reg = <0 0x007c4000 0 0x1000>, 478 478 <0 0x007c5000 0 0x1000>, ··· 497 497 498 498 status = "disabled"; 499 499 500 - sdhc1_opp_table: sdhc1-opp-table { 500 + sdhc1_opp_table: opp-table { 501 501 compatible = "operating-points-v2"; 502 502 503 503 opp-19200000 { ··· 921 921 }; 922 922 }; 923 923 924 - sdhc_2: sdhci@8804000 { 924 + sdhc_2: mmc@8804000 { 925 925 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 926 926 reg = <0 0x08804000 0 0x1000>; 927 927 ··· 941 941 942 942 status = "disabled"; 943 943 944 - sdhc2_opp_table: sdhc2-opp-table { 944 + sdhc2_opp_table: opp-table { 945 945 compatible = "operating-points-v2"; 946 946 947 947 opp-100000000 { ··· 1304 1304 compatible = "arm,armv7-timer-mem"; 1305 1305 reg = <0x0 0x17c20000 0x0 0x1000>; 1306 1306 clock-frequency = <19200000>; 1307 - #address-cells = <2>; 1308 - #size-cells = <2>; 1309 - ranges; 1307 + #address-cells = <1>; 1308 + #size-cells = <1>; 1309 + ranges = <0 0 0 0x20000000>; 1310 1310 1311 1311 frame@17c21000 { 1312 1312 frame-number = <0>; 1313 1313 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1314 1314 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1315 - reg = <0x0 0x17c21000 0x0 0x1000>, 1316 - <0x0 0x17c22000 0x0 0x1000>; 1315 + reg = <0x17c21000 0x1000>, 1316 + <0x17c22000 0x1000>; 1317 1317 }; 1318 1318 1319 1319 frame@17c23000 { 1320 1320 frame-number = <1>; 1321 1321 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1322 - reg = <0x0 0x17c23000 0x0 0x1000>; 1322 + reg = <0x17c23000 0x1000>; 1323 1323 status = "disabled"; 1324 1324 }; 1325 1325 1326 1326 frame@17c25000 { 1327 1327 frame-number = <2>; 1328 1328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1329 - reg = <0x0 0x17c25000 0x0 0x1000>; 1329 + reg = <0x17c25000 0x1000>; 1330 1330 status = "disabled"; 1331 1331 }; 1332 1332 1333 1333 frame@17c27000 { 1334 1334 frame-number = <3>; 1335 1335 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1336 - reg = <0x0 0x17c27000 0x0 0x1000>; 1336 + reg = <0x17c27000 0x1000>; 1337 1337 status = "disabled"; 1338 1338 }; 1339 1339 1340 1340 frame@17c29000 { 1341 1341 frame-number = <4>; 1342 1342 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1343 - reg = <0x0 0x17c29000 0x0 0x1000>; 1343 + reg = <0x17c29000 0x1000>; 1344 1344 status = "disabled"; 1345 1345 }; 1346 1346 1347 1347 frame@17c2b000 { 1348 1348 frame-number = <5>; 1349 1349 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1350 - reg = <0x0 0x17c2b000 0x0 0x1000>; 1350 + reg = <0x17c2b000 0x1000>; 1351 1351 status = "disabled"; 1352 1352 }; 1353 1353 1354 1354 frame@17c2d000 { 1355 1355 frame-number = <6>; 1356 1356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1357 - reg = <0x0 0x17c2d000 0x0 0x1000>; 1357 + reg = <0x17c2d000 0x1000>; 1358 1358 status = "disabled"; 1359 1359 }; 1360 1360 };
+2 -2
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
··· 48 48 pinctrl-names = "default"; 49 49 pinctrl-0 = <&gpio_keys_pin>; 50 50 51 - volume-up { 51 + key-volume-up { 52 52 label = "volume_up"; 53 53 linux,code = <KEY_VOLUMEUP>; 54 54 gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; ··· 339 339 }; 340 340 341 341 &pm6350_gpios { 342 - gpio_keys_pin: gpio-keys-pin { 342 + gpio_keys_pin: gpio-keys-state { 343 343 pins = "gpio2"; 344 344 function = PMIC_GPIO_FUNC_NORMAL; 345 345 bias-pull-up;
+2 -2
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
··· 44 44 vin-supply = <&vph_pwr>; 45 45 }; 46 46 47 - gpio_keys { 47 + gpio-keys { 48 48 compatible = "gpio-keys"; 49 49 50 - vol-up { 50 + key-vol-up { 51 51 label = "Volume Up"; 52 52 linux,code = <KEY_VOLUMEUP>; 53 53 gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+2 -2
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
··· 49 49 vin-supply = <&vph_pwr>; 50 50 }; 51 51 52 - gpio_keys { 52 + gpio-keys { 53 53 compatible = "gpio-keys"; 54 54 55 - vol_up { 55 + key-vol-up { 56 56 label = "Volume Up"; 57 57 gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; 58 58 linux,code = <KEY_VOLUMEUP>;
+18 -18
arch/arm64/boot/dts/qcom/sm8150.dtsi
··· 288 288 }; 289 289 }; 290 290 291 - cpu0_opp_table: cpu0_opp_table { 291 + cpu0_opp_table: opp-table-cpu0 { 292 292 compatible = "operating-points-v2"; 293 293 opp-shared; 294 294 ··· 383 383 }; 384 384 }; 385 385 386 - cpu4_opp_table: cpu4_opp_table { 386 + cpu4_opp_table: opp-table-cpu4 { 387 387 compatible = "operating-points-v2"; 388 388 opp-shared; 389 389 ··· 473 473 }; 474 474 }; 475 475 476 - cpu7_opp_table: cpu7_opp_table { 476 + cpu7_opp_table: opp-table-cpu7 { 477 477 compatible = "operating-points-v2"; 478 478 opp-shared; 479 479 ··· 2187 2187 }; 2188 2188 2189 2189 gmu: gmu@2c6a000 { 2190 - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2190 + compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2191 2191 2192 2192 reg = <0 0x02c6a000 0 0x30000>, 2193 2193 <0 0x0b290000 0 0x10000>, ··· 3543 3543 }; 3544 3544 }; 3545 3545 3546 - sdhc_2: sdhci@8804000 { 3546 + sdhc_2: mmc@8804000 { 3547 3547 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3548 3548 reg = <0 0x08804000 0 0x1000>; 3549 3549 ··· 3563 3563 3564 3564 status = "disabled"; 3565 3565 3566 - sdhc2_opp_table: sdhc2-opp-table { 3566 + sdhc2_opp_table: opp-table { 3567 3567 compatible = "operating-points-v2"; 3568 3568 3569 3569 opp-19200000 { ··· 3718 3718 }; 3719 3719 3720 3720 aoss_qmp: power-controller@c300000 { 3721 - compatible = "qcom,sm8150-aoss-qmp"; 3721 + compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3722 3722 reg = <0x0 0x0c300000 0x0 0x400>; 3723 3723 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3724 3724 mboxes = <&apss_shared 0>; ··· 3944 3944 }; 3945 3945 3946 3946 timer@17c20000 { 3947 - #address-cells = <2>; 3948 - #size-cells = <2>; 3949 - ranges; 3947 + #address-cells = <1>; 3948 + #size-cells = <1>; 3949 + ranges = <0 0 0 0x20000000>; 3950 3950 compatible = "arm,armv7-timer-mem"; 3951 3951 reg = <0x0 0x17c20000 0x0 0x1000>; 3952 3952 clock-frequency = <19200000>; ··· 3955 3955 frame-number = <0>; 3956 3956 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3957 3957 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3958 - reg = <0x0 0x17c21000 0x0 0x1000>, 3959 - <0x0 0x17c22000 0x0 0x1000>; 3958 + reg = <0x17c21000 0x1000>, 3959 + <0x17c22000 0x1000>; 3960 3960 }; 3961 3961 3962 3962 frame@17c23000 { 3963 3963 frame-number = <1>; 3964 3964 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3965 - reg = <0x0 0x17c23000 0x0 0x1000>; 3965 + reg = <0x17c23000 0x1000>; 3966 3966 status = "disabled"; 3967 3967 }; 3968 3968 3969 3969 frame@17c25000 { 3970 3970 frame-number = <2>; 3971 3971 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3972 - reg = <0x0 0x17c25000 0x0 0x1000>; 3972 + reg = <0x17c25000 0x1000>; 3973 3973 status = "disabled"; 3974 3974 }; 3975 3975 3976 3976 frame@17c27000 { 3977 3977 frame-number = <3>; 3978 3978 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3979 - reg = <0x0 0x17c26000 0x0 0x1000>; 3979 + reg = <0x17c26000 0x1000>; 3980 3980 status = "disabled"; 3981 3981 }; 3982 3982 3983 3983 frame@17c29000 { 3984 3984 frame-number = <4>; 3985 3985 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3986 - reg = <0x0 0x17c29000 0x0 0x1000>; 3986 + reg = <0x17c29000 0x1000>; 3987 3987 status = "disabled"; 3988 3988 }; 3989 3989 3990 3990 frame@17c2b000 { 3991 3991 frame-number = <5>; 3992 3992 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3993 - reg = <0x0 0x17c2b000 0x0 0x1000>; 3993 + reg = <0x17c2b000 0x1000>; 3994 3994 status = "disabled"; 3995 3995 }; 3996 3996 3997 3997 frame@17c2d000 { 3998 3998 frame-number = <6>; 3999 3999 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4000 - reg = <0x0 0x17c2d000 0x0 0x1000>; 4000 + reg = <0x17c2d000 0x1000>; 4001 4001 status = "disabled"; 4002 4002 }; 4003 4003 };
+2 -2
arch/arm64/boot/dts/qcom/sm8250-hdk.dts
··· 53 53 vin-supply = <&vph_pwr>; 54 54 }; 55 55 56 - gpio_keys { 56 + gpio-keys { 57 57 compatible = "gpio-keys"; 58 58 59 - vol-up { 59 + key-vol-up { 60 60 label = "Volume Up"; 61 61 linux,code = <KEY_VOLUMEUP>; 62 62 gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
··· 57 57 * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). 58 58 */ 59 59 60 - vol-down { 60 + key-vol-down { 61 61 label = "Volume Down"; 62 62 linux,code = <KEY_VOLUMEDOWN>; 63 63 gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+57 -53
arch/arm64/boot/dts/qcom/sm8250.dtsi
··· 8 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 9 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 + #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12 + #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 11 13 #include <dt-bindings/dma/qcom-gpi.h> 12 14 #include <dt-bindings/gpio/gpio.h> 13 15 #include <dt-bindings/interconnect/qcom,osm-l3.h> ··· 338 336 }; 339 337 }; 340 338 341 - cpu0_opp_table: cpu0_opp_table { 339 + cpu0_opp_table: opp-table-cpu0 { 342 340 compatible = "operating-points-v2"; 343 341 opp-shared; 344 342 ··· 428 426 }; 429 427 }; 430 428 431 - cpu4_opp_table: cpu4_opp_table { 429 + cpu4_opp_table: opp-table-cpu4 { 432 430 compatible = "operating-points-v2"; 433 431 opp-shared; 434 432 ··· 523 521 }; 524 522 }; 525 523 526 - cpu7_opp_table: cpu7_opp_table { 524 + cpu7_opp_table: opp-table-cpu7 { 527 525 compatible = "operating-points-v2"; 528 526 opp-shared; 529 527 ··· 630 628 631 629 firmware { 632 630 scm: scm { 633 - compatible = "qcom,scm"; 631 + compatible = "qcom,scm-sm8250", "qcom,scm"; 634 632 #reset-cells = <1>; 635 633 }; 636 634 }; ··· 701 699 CLUSTER_PD: cpu-cluster0 { 702 700 #power-domain-cells = <0>; 703 701 domain-idle-states = <&CLUSTER_SLEEP_0>; 702 + }; 703 + }; 704 + 705 + qup_opp_table: opp-table-qup { 706 + compatible = "operating-points-v2"; 707 + 708 + opp-50000000 { 709 + opp-hz = /bits/ 64 <50000000>; 710 + required-opps = <&rpmhpd_opp_min_svs>; 711 + }; 712 + 713 + opp-75000000 { 714 + opp-hz = /bits/ 64 <75000000>; 715 + required-opps = <&rpmhpd_opp_low_svs>; 716 + }; 717 + 718 + opp-120000000 { 719 + opp-hz = /bits/ 64 <120000000>; 720 + required-opps = <&rpmhpd_opp_svs>; 704 721 }; 705 722 }; 706 723 ··· 933 912 reg = <0 0x00793000 0 0x1000>; 934 913 clocks = <&gcc GCC_PRNG_AHB_CLK>; 935 914 clock-names = "core"; 936 - }; 937 - 938 - qup_opp_table: qup-opp-table { 939 - compatible = "operating-points-v2"; 940 - 941 - opp-50000000 { 942 - opp-hz = /bits/ 64 <50000000>; 943 - required-opps = <&rpmhpd_opp_min_svs>; 944 - }; 945 - 946 - opp-75000000 { 947 - opp-hz = /bits/ 64 <75000000>; 948 - required-opps = <&rpmhpd_opp_low_svs>; 949 - }; 950 - 951 - opp-120000000 { 952 - opp-hz = /bits/ 64 <120000000>; 953 - required-opps = <&rpmhpd_opp_svs>; 954 - }; 955 915 }; 956 916 957 917 gpi_dma2: dma-controller@800000 { ··· 1886 1884 clock-names = "pipe0"; 1887 1885 1888 1886 #phy-cells = <0>; 1887 + 1888 + #clock-cells = <0>; 1889 1889 clock-output-names = "pcie_0_pipe_clk"; 1890 1890 }; 1891 1891 }; ··· 1994 1990 clock-names = "pipe0"; 1995 1991 1996 1992 #phy-cells = <0>; 1993 + 1994 + #clock-cells = <0>; 1997 1995 clock-output-names = "pcie_1_pipe_clk"; 1998 1996 }; 1999 1997 }; ··· 2102 2096 clock-names = "pipe0"; 2103 2097 2104 2098 #phy-cells = <0>; 2099 + 2100 + #clock-cells = <0>; 2105 2101 clock-output-names = "pcie_2_pipe_clk"; 2106 2102 }; 2107 2103 }; ··· 2196 2188 wsamacro: codec@3240000 { 2197 2189 compatible = "qcom,sm8250-lpass-wsa-macro"; 2198 2190 reg = <0 0x03240000 0 0x1000>; 2199 - clocks = <&audiocc 1>, 2200 - <&audiocc 0>, 2191 + clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2192 + <&audiocc LPASS_CDC_WSA_NPL>, 2201 2193 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2202 2194 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2203 - <&aoncc 0>, 2195 + <&aoncc LPASS_CDC_VA_MCLK>, 2204 2196 <&vamacro>; 2205 2197 2206 2198 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; ··· 2247 2239 vamacro: codec@3370000 { 2248 2240 compatible = "qcom,sm8250-lpass-va-macro"; 2249 2241 reg = <0 0x03370000 0 0x1000>; 2250 - clocks = <&aoncc 0>, 2242 + clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2251 2243 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2252 2244 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2253 2245 ··· 2577 2569 }; 2578 2570 2579 2571 gmu: gmu@3d6a000 { 2580 - compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2572 + compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2581 2573 2582 2574 reg = <0 0x03d6a000 0 0x30000>, 2583 2575 <0 0x3de0000 0 0x10000>, ··· 2631 2623 }; 2632 2624 2633 2625 adreno_smmu: iommu@3da0000 { 2634 - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2626 + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2635 2627 reg = <0 0x03da0000 0 0x10000>; 2636 2628 #iommu-cells = <2>; 2637 2629 #global-interrupts = <2>; ··· 2925 2917 }; 2926 2918 }; 2927 2919 2928 - sdhc_2: sdhci@8804000 { 2920 + sdhc_2: mmc@8804000 { 2929 2921 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2930 2922 reg = <0 0x08804000 0 0x1000>; 2931 2923 ··· 2945 2937 2946 2938 status = "disabled"; 2947 2939 2948 - sdhc2_opp_table: sdhc2-opp-table { 2940 + sdhc2_opp_table: opp-table { 2949 2941 compatible = "operating-points-v2"; 2950 2942 2951 2943 opp-19200000 { ··· 3131 3123 compatible = "venus-encoder"; 3132 3124 }; 3133 3125 3134 - venus_opp_table: venus-opp-table { 3126 + venus_opp_table: opp-table { 3135 3127 compatible = "operating-points-v2"; 3136 3128 3137 3129 opp-720000000 { ··· 3415 3407 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3416 3408 power-domains = <&rpmhpd SM8250_MMCX>; 3417 3409 required-opps = <&rpmhpd_opp_low_svs>; 3410 + status = "disabled"; 3418 3411 #clock-cells = <1>; 3419 3412 #reset-cells = <1>; 3420 3413 #power-domain-cells = <1>; ··· 3437 3428 <&gcc GCC_DISP_SF_AXI_CLK>, 3438 3429 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3439 3430 clock-names = "iface", "bus", "nrt_bus", "core"; 3440 - 3441 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3442 - assigned-clock-rates = <460000000>; 3443 3431 3444 3432 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3445 3433 interrupt-controller; ··· 3462 3456 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3463 3457 clock-names = "iface", "bus", "core", "vsync"; 3464 3458 3465 - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3466 - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3467 - assigned-clock-rates = <460000000>, 3468 - <19200000>; 3459 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3460 + assigned-clock-rates = <19200000>; 3469 3461 3470 3462 operating-points-v2 = <&mdp_opp_table>; 3471 3463 power-domains = <&rpmhpd SM8250_MMCX>; ··· 3490 3486 }; 3491 3487 }; 3492 3488 3493 - mdp_opp_table: mdp-opp-table { 3489 + mdp_opp_table: opp-table { 3494 3490 compatible = "operating-points-v2"; 3495 3491 3496 3492 opp-200000000 { ··· 3660 3656 3661 3657 status = "disabled"; 3662 3658 3663 - dsi_opp_table: dsi-opp-table { 3659 + dsi_opp_table: opp-table { 3664 3660 compatible = "operating-points-v2"; 3665 3661 3666 3662 opp-187500000 { ··· 3738 3734 }; 3739 3735 3740 3736 aoss_qmp: power-controller@c300000 { 3741 - compatible = "qcom,sm8250-aoss-qmp"; 3737 + compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 3742 3738 reg = <0 0x0c300000 0 0x400>; 3743 3739 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3744 3740 IPCC_MPROC_SIGNAL_GLINK_QMP ··· 4871 4867 }; 4872 4868 4873 4869 timer@17c20000 { 4874 - #address-cells = <2>; 4875 - #size-cells = <2>; 4876 - ranges; 4870 + #address-cells = <1>; 4871 + #size-cells = <1>; 4872 + ranges = <0 0 0 0x20000000>; 4877 4873 compatible = "arm,armv7-timer-mem"; 4878 4874 reg = <0x0 0x17c20000 0x0 0x1000>; 4879 4875 clock-frequency = <19200000>; ··· 4882 4878 frame-number = <0>; 4883 4879 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4884 4880 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4885 - reg = <0x0 0x17c21000 0x0 0x1000>, 4886 - <0x0 0x17c22000 0x0 0x1000>; 4881 + reg = <0x17c21000 0x1000>, 4882 + <0x17c22000 0x1000>; 4887 4883 }; 4888 4884 4889 4885 frame@17c23000 { 4890 4886 frame-number = <1>; 4891 4887 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4892 - reg = <0x0 0x17c23000 0x0 0x1000>; 4888 + reg = <0x17c23000 0x1000>; 4893 4889 status = "disabled"; 4894 4890 }; 4895 4891 4896 4892 frame@17c25000 { 4897 4893 frame-number = <2>; 4898 4894 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4899 - reg = <0x0 0x17c25000 0x0 0x1000>; 4895 + reg = <0x17c25000 0x1000>; 4900 4896 status = "disabled"; 4901 4897 }; 4902 4898 4903 4899 frame@17c27000 { 4904 4900 frame-number = <3>; 4905 4901 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4906 - reg = <0x0 0x17c27000 0x0 0x1000>; 4902 + reg = <0x17c27000 0x1000>; 4907 4903 status = "disabled"; 4908 4904 }; 4909 4905 4910 4906 frame@17c29000 { 4911 4907 frame-number = <4>; 4912 4908 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4913 - reg = <0x0 0x17c29000 0x0 0x1000>; 4909 + reg = <0x17c29000 0x1000>; 4914 4910 status = "disabled"; 4915 4911 }; 4916 4912 4917 4913 frame@17c2b000 { 4918 4914 frame-number = <5>; 4919 4915 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4920 - reg = <0x0 0x17c2b000 0x0 0x1000>; 4916 + reg = <0x17c2b000 0x1000>; 4921 4917 status = "disabled"; 4922 4918 }; 4923 4919 4924 4920 frame@17c2d000 { 4925 4921 frame-number = <6>; 4926 4922 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4927 - reg = <0x0 0x17c2d000 0x0 0x1000>; 4923 + reg = <0x17c2d000 0x1000>; 4928 4924 status = "disabled"; 4929 4925 }; 4930 4926 };
-2
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
··· 336 336 status = "okay"; 337 337 338 338 vdda-phy-supply = <&vreg_l5b_0p88>; 339 - vdda-max-microamp = <91600>; 340 339 vdda-pll-supply = <&vreg_l6b_1p2>; 341 - vdda-pll-max-microamp = <19000>; 342 340 }; 343 341 344 342 &usb_1 {
+1 -1
arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
··· 49 49 50 50 /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ 51 51 52 - vol-down { 52 + key-vol-down { 53 53 label = "Volume Down"; 54 54 linux,code = <KEY_VOLUMEDOWN>; 55 55 gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>;
+86 -62
arch/arm64/boot/dts/qcom/sm8350.dtsi
··· 4 4 */ 5 5 6 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/clock/qcom,dispcc-sm8350.h> 7 8 #include <dt-bindings/clock/qcom,gcc-sm8350.h> 8 9 #include <dt-bindings/clock/qcom,rpmh.h> 9 10 #include <dt-bindings/dma/qcom-gpi.h> ··· 342 341 }; 343 342 }; 344 343 344 + qup_opp_table_100mhz: opp-table-qup100mhz { 345 + compatible = "operating-points-v2"; 346 + 347 + opp-50000000 { 348 + opp-hz = /bits/ 64 <50000000>; 349 + required-opps = <&rpmhpd_opp_min_svs>; 350 + }; 351 + 352 + opp-75000000 { 353 + opp-hz = /bits/ 64 <75000000>; 354 + required-opps = <&rpmhpd_opp_low_svs>; 355 + }; 356 + 357 + opp-100000000 { 358 + opp-hz = /bits/ 64 <100000000>; 359 + required-opps = <&rpmhpd_opp_svs>; 360 + }; 361 + }; 362 + 363 + qup_opp_table_120mhz: opp-table-qup120mhz { 364 + compatible = "operating-points-v2"; 365 + 366 + opp-50000000 { 367 + opp-hz = /bits/ 64 <50000000>; 368 + required-opps = <&rpmhpd_opp_min_svs>; 369 + }; 370 + 371 + opp-75000000 { 372 + opp-hz = /bits/ 64 <75000000>; 373 + required-opps = <&rpmhpd_opp_low_svs>; 374 + }; 375 + 376 + opp-120000000 { 377 + opp-hz = /bits/ 64 <120000000>; 378 + required-opps = <&rpmhpd_opp_svs>; 379 + }; 380 + }; 381 + 345 382 reserved_memory: reserved-memory { 346 383 #address-cells = <2>; 347 384 #size-cells = <2>; ··· 675 636 interrupt-controller; 676 637 #interrupt-cells = <3>; 677 638 #mbox-cells = <2>; 678 - }; 679 - 680 - qup_opp_table_100mhz: qup-100mhz-opp-table { 681 - compatible = "operating-points-v2"; 682 - 683 - opp-50000000 { 684 - opp-hz = /bits/ 64 <50000000>; 685 - required-opps = <&rpmhpd_opp_min_svs>; 686 - }; 687 - 688 - opp-75000000 { 689 - opp-hz = /bits/ 64 <75000000>; 690 - required-opps = <&rpmhpd_opp_low_svs>; 691 - }; 692 - 693 - opp-100000000 { 694 - opp-hz = /bits/ 64 <100000000>; 695 - required-opps = <&rpmhpd_opp_svs>; 696 - }; 697 - }; 698 - 699 - qup_opp_table_120mhz: qup-120mhz-opp-table { 700 - compatible = "operating-points-v2"; 701 - 702 - opp-50000000 { 703 - opp-hz = /bits/ 64 <50000000>; 704 - required-opps = <&rpmhpd_opp_min_svs>; 705 - }; 706 - 707 - opp-75000000 { 708 - opp-hz = /bits/ 64 <75000000>; 709 - required-opps = <&rpmhpd_opp_low_svs>; 710 - }; 711 - 712 - opp-120000000 { 713 - opp-hz = /bits/ 64 <120000000>; 714 - required-opps = <&rpmhpd_opp_svs>; 715 - }; 716 639 }; 717 640 718 641 gpi_dma2: dma-controller@800000 { ··· 1657 1656 clocks = <&rpmhcc RPMH_CXO_CLK>; 1658 1657 clock-names = "xo"; 1659 1658 1660 - power-domains = <&rpmhpd 0>, 1661 - <&rpmhpd 12>; 1659 + power-domains = <&rpmhpd SM8350_CX>, 1660 + <&rpmhpd SM8350_MSS>; 1662 1661 power-domain-names = "cx", "mss"; 1663 1662 1664 1663 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; ··· 1678 1677 IRQ_TYPE_EDGE_RISING>; 1679 1678 mboxes = <&ipcc IPCC_CLIENT_MPSS 1680 1679 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1681 - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1682 1680 label = "modem"; 1683 1681 qcom,remote-pid = <1>; 1684 1682 }; ··· 1718 1718 }; 1719 1719 1720 1720 aoss_qmp: power-controller@c300000 { 1721 - compatible = "qcom,sm8350-aoss-qmp"; 1721 + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 1722 1722 reg = <0 0x0c300000 0 0x400>; 1723 1723 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1724 1724 IRQ_TYPE_EDGE_RISING>; ··· 1933 1933 1934 1934 timer@17c20000 { 1935 1935 compatible = "arm,armv7-timer-mem"; 1936 - #address-cells = <2>; 1937 - #size-cells = <2>; 1938 - ranges; 1936 + #address-cells = <1>; 1937 + #size-cells = <1>; 1938 + ranges = <0 0 0 0x20000000>; 1939 1939 reg = <0x0 0x17c20000 0x0 0x1000>; 1940 1940 clock-frequency = <19200000>; 1941 1941 ··· 1943 1943 frame-number = <0>; 1944 1944 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1945 1945 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1946 - reg = <0x0 0x17c21000 0x0 0x1000>, 1947 - <0x0 0x17c22000 0x0 0x1000>; 1946 + reg = <0x17c21000 0x1000>, 1947 + <0x17c22000 0x1000>; 1948 1948 }; 1949 1949 1950 1950 frame@17c23000 { 1951 1951 frame-number = <1>; 1952 1952 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1953 - reg = <0x0 0x17c23000 0x0 0x1000>; 1953 + reg = <0x17c23000 0x1000>; 1954 1954 status = "disabled"; 1955 1955 }; 1956 1956 1957 1957 frame@17c25000 { 1958 1958 frame-number = <2>; 1959 1959 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1960 - reg = <0x0 0x17c25000 0x0 0x1000>; 1960 + reg = <0x17c25000 0x1000>; 1961 1961 status = "disabled"; 1962 1962 }; 1963 1963 1964 1964 frame@17c27000 { 1965 1965 frame-number = <3>; 1966 1966 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1967 - reg = <0x0 0x17c27000 0x0 0x1000>; 1967 + reg = <0x17c27000 0x1000>; 1968 1968 status = "disabled"; 1969 1969 }; 1970 1970 1971 1971 frame@17c29000 { 1972 1972 frame-number = <4>; 1973 1973 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1974 - reg = <0x0 0x17c29000 0x0 0x1000>; 1974 + reg = <0x17c29000 0x1000>; 1975 1975 status = "disabled"; 1976 1976 }; 1977 1977 1978 1978 frame@17c2b000 { 1979 1979 frame-number = <5>; 1980 1980 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1981 - reg = <0x0 0x17c2b000 0x0 0x1000>; 1981 + reg = <0x17c2b000 0x1000>; 1982 1982 status = "disabled"; 1983 1983 }; 1984 1984 1985 1985 frame@17c2d000 { 1986 1986 frame-number = <6>; 1987 1987 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1988 - reg = <0x0 0x17c2d000 0x0 0x1000>; 1988 + reg = <0x17c2d000 0x1000>; 1989 1989 status = "disabled"; 1990 1990 }; 1991 1991 }; ··· 2148 2148 <0 0x01d87800 0 0x108>, 2149 2149 <0 0x01d87a00 0 0x1e0>; 2150 2150 #phy-cells = <0>; 2151 - #clock-cells = <0>; 2152 2151 }; 2153 2152 }; 2154 2153 ··· 2166 2167 clocks = <&rpmhcc RPMH_CXO_CLK>; 2167 2168 clock-names = "xo"; 2168 2169 2169 - power-domains = <&rpmhpd 4>, 2170 - <&rpmhpd 5>; 2170 + power-domains = <&rpmhpd SM8350_LCX>, 2171 + <&rpmhpd SM8350_LMX>; 2171 2172 power-domain-names = "lcx", "lmx"; 2172 2173 2173 2174 memory-region = <&pil_slpi_mem>; ··· 2234 2235 clocks = <&rpmhcc RPMH_CXO_CLK>; 2235 2236 clock-names = "xo"; 2236 2237 2237 - power-domains = <&rpmhpd 0>, 2238 - <&rpmhpd 10>; 2238 + power-domains = <&rpmhpd SM8350_CX>, 2239 + <&rpmhpd SM8350_MXC>; 2239 2240 power-domain-names = "cx", "mxc"; 2240 2241 2241 2242 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; ··· 2380 2381 <0 0x088e9800 0 0x200>, 2381 2382 <0 0x088e9a00 0 0x100>; 2382 2383 #phy-cells = <0>; 2383 - #clock-cells = <1>; 2384 + #clock-cells = <0>; 2384 2385 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2385 2386 clock-names = "pipe0"; 2386 2387 clock-output-names = "usb3_phy_pipe_clk_src"; ··· 2410 2411 <0 0x088ec000 0 0x200>, 2411 2412 <0 0x088eb200 0 0x1100>; 2412 2413 #phy-cells = <0>; 2413 - #clock-cells = <1>; 2414 + #clock-cells = <0>; 2414 2415 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2415 2416 clock-names = "pipe0"; 2416 2417 clock-output-names = "usb3_uni_phy_pipe_clk_src"; ··· 2531 2532 }; 2532 2533 }; 2533 2534 2535 + dispcc: clock-controller@af00000 { 2536 + compatible = "qcom,sm8350-dispcc"; 2537 + reg = <0 0x0af00000 0 0x10000>; 2538 + clocks = <&rpmhcc RPMH_CXO_CLK>, 2539 + <0>, 2540 + <0>, 2541 + <0>, 2542 + <0>, 2543 + <0>, 2544 + <0>; 2545 + clock-names = "bi_tcxo", 2546 + "dsi0_phy_pll_out_byteclk", 2547 + "dsi0_phy_pll_out_dsiclk", 2548 + "dsi1_phy_pll_out_byteclk", 2549 + "dsi1_phy_pll_out_dsiclk", 2550 + "dp_phy_pll_link_clk", 2551 + "dp_phy_pll_vco_div_clk"; 2552 + #clock-cells = <1>; 2553 + #reset-cells = <1>; 2554 + #power-domain-cells = <1>; 2555 + 2556 + power-domains = <&rpmhpd SM8350_MMCX>; 2557 + power-domain-names = "mmcx"; 2558 + }; 2559 + 2534 2560 adsp: remoteproc@17300000 { 2535 2561 compatible = "qcom,sm8350-adsp-pas"; 2536 2562 reg = <0 0x17300000 0 0x100>; ··· 2571 2547 clocks = <&rpmhcc RPMH_CXO_CLK>; 2572 2548 clock-names = "xo"; 2573 2549 2574 - power-domains = <&rpmhpd 4>, 2575 - <&rpmhpd 5>; 2550 + power-domains = <&rpmhpd SM8350_LCX>, 2551 + <&rpmhpd SM8350_LMX>; 2576 2552 power-domain-names = "lcx", "lmx"; 2577 2553 2578 2554 memory-region = <&pil_adsp_mem>;
-2
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
··· 418 418 419 419 vdda-phy-supply = <&vreg_l5b_0p88>; 420 420 vdda-pll-supply = <&vreg_l6b_1p2>; 421 - vdda-max-microamp = <173000>; 422 - vdda-pll-max-microamp = <24900>; 423 421 }; 424 422 425 423 &usb_1 {
-2
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
··· 424 424 425 425 vdda-phy-supply = <&vreg_l5b_0p88>; 426 426 vdda-pll-supply = <&vreg_l6b_1p2>; 427 - vdda-max-microamp = <173000>; 428 - vdda-pll-max-microamp = <24900>; 429 427 }; 430 428 431 429 &usb_1 {
+67 -23
arch/arm64/boot/dts/qcom/sm8450.dtsi
··· 6 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 8 8 #include <dt-bindings/clock/qcom,rpmh.h> 9 + #include <dt-bindings/clock/qcom,sm8450-camcc.h> 9 10 #include <dt-bindings/dma/qcom-gpi.h> 10 11 #include <dt-bindings/gpio/gpio.h> 11 12 #include <dt-bindings/mailbox/qcom-ipcc.h> ··· 259 258 firmware { 260 259 scm: scm { 261 260 compatible = "qcom,scm-sm8450", "qcom,scm"; 261 + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 262 262 #reset-cells = <1>; 263 263 }; 264 264 }; 265 265 266 - clk_virt: interconnect@0 { 266 + clk_virt: interconnect-0 { 267 267 compatible = "qcom,sm8450-clk-virt"; 268 268 #interconnect-cells = <2>; 269 269 qcom,bcm-voters = <&apps_bcm_voter>; 270 270 }; 271 271 272 - mc_virt: interconnect@1 { 272 + mc_virt: interconnect-1 { 273 273 compatible = "qcom,sm8450-mc-virt"; 274 274 #interconnect-cells = <2>; 275 275 qcom,bcm-voters = <&apps_bcm_voter>; ··· 345 343 }; 346 344 }; 347 345 348 - qup_opp_table_100mhz: qup-100mhz-opp-table { 346 + qup_opp_table_100mhz: opp-table-qup { 349 347 compatible = "operating-points-v2"; 350 348 351 349 opp-50000000 { ··· 975 973 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 976 974 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 977 975 dma-names = "tx", "rx"; 976 + status = "disabled"; 977 + }; 978 + 979 + uart20: serial@894000 { 980 + compatible = "qcom,geni-uart"; 981 + reg = <0 0x00894000 0 0x4000>; 982 + clock-names = "se"; 983 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 984 + pinctrl-names = "default"; 985 + pinctrl-0 = <&qup_uart20_default>; 986 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 987 + #address-cells = <1>; 988 + #size-cells = <0>; 978 989 status = "disabled"; 979 990 }; 980 991 ··· 2016 2001 <0 0x088e9800 0 0x200>, 2017 2002 <0 0x088e9a00 0 0x100>; 2018 2003 #phy-cells = <0>; 2019 - #clock-cells = <1>; 2004 + #clock-cells = <0>; 2020 2005 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2021 2006 clock-names = "pipe0"; 2022 2007 clock-output-names = "usb3_phy_pipe_clk_src"; ··· 2027 2012 compatible = "qcom,sm8450-slpi-pas"; 2028 2013 reg = <0 0x02400000 0 0x4000>; 2029 2014 2030 - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2015 + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2031 2016 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2032 2017 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2033 2018 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, ··· 2094 2079 compatible = "qcom,sm8450-adsp-pas"; 2095 2080 reg = <0 0x030000000 0 0x100>; 2096 2081 2097 - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2082 + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2098 2083 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2099 2084 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2100 2085 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, ··· 2160 2145 compatible = "qcom,sm8450-cdsp-pas"; 2161 2146 reg = <0 0x032300000 0 0x1400000>; 2162 2147 2163 - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2148 + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2164 2149 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2165 2150 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2166 2151 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, ··· 2266 2251 compatible = "qcom,sm8450-mpss-pas"; 2267 2252 reg = <0x0 0x04080000 0x0 0x4040>; 2268 2253 2269 - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2254 + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2270 2255 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2271 2256 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2272 2257 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, ··· 2297 2282 IRQ_TYPE_EDGE_RISING>; 2298 2283 mboxes = <&ipcc IPCC_CLIENT_MPSS 2299 2284 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2300 - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2301 2285 label = "modem"; 2302 2286 qcom,remote-pid = <1>; 2303 2287 }; 2288 + }; 2289 + 2290 + camcc: clock-controller@ade0000 { 2291 + compatible = "qcom,sm8450-camcc"; 2292 + reg = <0 0x0ade0000 0 0x20000>; 2293 + clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2294 + <&rpmhcc RPMH_CXO_CLK>, 2295 + <&rpmhcc RPMH_CXO_CLK_A>, 2296 + <&sleep_clk>; 2297 + power-domains = <&rpmhpd SM8450_MMCX>; 2298 + required-opps = <&rpmhpd_opp_low_svs>; 2299 + #clock-cells = <1>; 2300 + #reset-cells = <1>; 2301 + #power-domain-cells = <1>; 2302 + status = "disabled"; 2304 2303 }; 2305 2304 2306 2305 pdc: interrupt-controller@b220000 { ··· 2767 2738 drive-strength = <2>; 2768 2739 bias-disable; 2769 2740 }; 2741 + 2742 + qup_uart20_default: qup-uart20-default { 2743 + pins = "gpio76", "gpio77", "gpio78", "gpio79"; 2744 + function = "qup20"; 2745 + }; 2746 + 2770 2747 }; 2771 2748 2772 2749 apps_smmu: iommu@15000000 { ··· 2888 2853 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 2889 2854 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 2890 2855 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2856 + #address-cells = <2>; 2857 + #size-cells = <2>; 2858 + ranges; 2859 + 2860 + gic_its: msi-controller@17140000 { 2861 + compatible = "arm,gic-v3-its"; 2862 + reg = <0x0 0x17140000 0x0 0x20000>; 2863 + msi-controller; 2864 + #msi-cells = <1>; 2865 + }; 2891 2866 }; 2892 2867 2893 2868 timer@17420000 { 2894 2869 compatible = "arm,armv7-timer-mem"; 2895 - #address-cells = <2>; 2896 - #size-cells = <2>; 2897 - ranges; 2870 + #address-cells = <1>; 2871 + #size-cells = <1>; 2872 + ranges = <0 0 0 0x20000000>; 2898 2873 reg = <0x0 0x17420000 0x0 0x1000>; 2899 2874 clock-frequency = <19200000>; 2900 2875 ··· 2912 2867 frame-number = <0>; 2913 2868 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2914 2869 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2915 - reg = <0x0 0x17421000 0x0 0x1000>, 2916 - <0x0 0x17422000 0x0 0x1000>; 2870 + reg = <0x17421000 0x1000>, 2871 + <0x17422000 0x1000>; 2917 2872 }; 2918 2873 2919 2874 frame@17423000 { 2920 2875 frame-number = <1>; 2921 2876 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2922 - reg = <0x0 0x17423000 0x0 0x1000>; 2877 + reg = <0x17423000 0x1000>; 2923 2878 status = "disabled"; 2924 2879 }; 2925 2880 2926 2881 frame@17425000 { 2927 2882 frame-number = <2>; 2928 2883 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2929 - reg = <0x0 0x17425000 0x0 0x1000>; 2884 + reg = <0x17425000 0x1000>; 2930 2885 status = "disabled"; 2931 2886 }; 2932 2887 2933 2888 frame@17427000 { 2934 2889 frame-number = <3>; 2935 2890 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2936 - reg = <0x0 0x17427000 0x0 0x1000>; 2891 + reg = <0x17427000 0x1000>; 2937 2892 status = "disabled"; 2938 2893 }; 2939 2894 2940 2895 frame@17429000 { 2941 2896 frame-number = <4>; 2942 2897 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2943 - reg = <0x0 0x17429000 0x0 0x1000>; 2898 + reg = <0x17429000 0x1000>; 2944 2899 status = "disabled"; 2945 2900 }; 2946 2901 2947 2902 frame@1742b000 { 2948 2903 frame-number = <5>; 2949 2904 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2950 - reg = <0x0 0x1742b000 0x0 0x1000>; 2905 + reg = <0x1742b000 0x1000>; 2951 2906 status = "disabled"; 2952 2907 }; 2953 2908 2954 2909 frame@1742d000 { 2955 2910 frame-number = <6>; 2956 2911 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2957 - reg = <0x0 0x1742d000 0x0 0x1000>; 2912 + reg = <0x1742d000 0x1000>; 2958 2913 status = "disabled"; 2959 2914 }; 2960 2915 }; ··· 3082 3037 3083 3038 iommus = <&apps_smmu 0xe0 0x0>; 3084 3039 3085 - interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 3086 - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 3040 + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 3041 + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 3087 3042 interconnect-names = "ufs-ddr", "cpu-ufs"; 3088 3043 clock-names = 3089 3044 "core_clk", ··· 3137 3092 <0 0x01d87800 0 0x108>, 3138 3093 <0 0x01d87a00 0 0x1e0>; 3139 3094 #phy-cells = <0>; 3140 - #clock-cells = <0>; 3141 3095 }; 3142 3096 }; 3143 3097
+3
include/dt-bindings/clock/qcom,gcc-ipq8074.h
··· 367 367 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 368 368 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 369 369 370 + #define USB0_GDSC 0 371 + #define USB1_GDSC 1 372 + 370 373 #endif
+52
include/dt-bindings/clock/qcom,gpucc-sm8350.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H 7 + #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H 8 + 9 + /* GPU_CC clocks */ 10 + #define GPU_CC_AHB_CLK 0 11 + #define GPU_CC_CB_CLK 1 12 + #define GPU_CC_CRC_AHB_CLK 2 13 + #define GPU_CC_CX_APB_CLK 3 14 + #define GPU_CC_CX_GMU_CLK 4 15 + #define GPU_CC_CX_QDSS_AT_CLK 5 16 + #define GPU_CC_CX_QDSS_TRIG_CLK 6 17 + #define GPU_CC_CX_QDSS_TSCTR_CLK 7 18 + #define GPU_CC_CX_SNOC_DVM_CLK 8 19 + #define GPU_CC_CXO_AON_CLK 9 20 + #define GPU_CC_CXO_CLK 10 21 + #define GPU_CC_FREQ_MEASURE_CLK 11 22 + #define GPU_CC_GMU_CLK_SRC 12 23 + #define GPU_CC_GX_GMU_CLK 13 24 + #define GPU_CC_GX_QDSS_TSCTR_CLK 14 25 + #define GPU_CC_GX_VSENSE_CLK 15 26 + #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 27 + #define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 28 + #define GPU_CC_HUB_AON_CLK 18 29 + #define GPU_CC_HUB_CLK_SRC 19 30 + #define GPU_CC_HUB_CX_INT_CLK 20 31 + #define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 32 + #define GPU_CC_MND1X_0_GFX3D_CLK 22 33 + #define GPU_CC_MND1X_1_GFX3D_CLK 23 34 + #define GPU_CC_PLL0 24 35 + #define GPU_CC_PLL1 25 36 + #define GPU_CC_SLEEP_CLK 26 37 + 38 + /* GPU_CC resets */ 39 + #define GPUCC_GPU_CC_ACD_BCR 0 40 + #define GPUCC_GPU_CC_CB_BCR 1 41 + #define GPUCC_GPU_CC_CX_BCR 2 42 + #define GPUCC_GPU_CC_FAST_HUB_BCR 3 43 + #define GPUCC_GPU_CC_GFX3D_AON_BCR 4 44 + #define GPUCC_GPU_CC_GMU_BCR 5 45 + #define GPUCC_GPU_CC_GX_BCR 6 46 + #define GPUCC_GPU_CC_XO_BCR 7 47 + 48 + /* GPU_CC GDSCRs */ 49 + #define GPU_CX_GDSC 0 50 + #define GPU_GX_GDSC 1 51 + 52 + #endif
+159
include/dt-bindings/clock/qcom,sm8450-camcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H 7 + #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H 8 + 9 + /* CAM_CC clocks */ 10 + #define CAM_CC_BPS_AHB_CLK 0 11 + #define CAM_CC_BPS_CLK 1 12 + #define CAM_CC_BPS_CLK_SRC 2 13 + #define CAM_CC_BPS_FAST_AHB_CLK 3 14 + #define CAM_CC_CAMNOC_AXI_CLK 4 15 + #define CAM_CC_CAMNOC_AXI_CLK_SRC 5 16 + #define CAM_CC_CAMNOC_DCD_XO_CLK 6 17 + #define CAM_CC_CCI_0_CLK 7 18 + #define CAM_CC_CCI_0_CLK_SRC 8 19 + #define CAM_CC_CCI_1_CLK 9 20 + #define CAM_CC_CCI_1_CLK_SRC 10 21 + #define CAM_CC_CORE_AHB_CLK 11 22 + #define CAM_CC_CPAS_AHB_CLK 12 23 + #define CAM_CC_CPAS_BPS_CLK 13 24 + #define CAM_CC_CPAS_FAST_AHB_CLK 14 25 + #define CAM_CC_CPAS_IFE_0_CLK 15 26 + #define CAM_CC_CPAS_IFE_1_CLK 16 27 + #define CAM_CC_CPAS_IFE_2_CLK 17 28 + #define CAM_CC_CPAS_IFE_LITE_CLK 18 29 + #define CAM_CC_CPAS_IPE_NPS_CLK 19 30 + #define CAM_CC_CPAS_SBI_CLK 20 31 + #define CAM_CC_CPAS_SFE_0_CLK 21 32 + #define CAM_CC_CPAS_SFE_1_CLK 22 33 + #define CAM_CC_CPHY_RX_CLK_SRC 23 34 + #define CAM_CC_CSI0PHYTIMER_CLK 24 35 + #define CAM_CC_CSI0PHYTIMER_CLK_SRC 25 36 + #define CAM_CC_CSI1PHYTIMER_CLK 26 37 + #define CAM_CC_CSI1PHYTIMER_CLK_SRC 27 38 + #define CAM_CC_CSI2PHYTIMER_CLK 28 39 + #define CAM_CC_CSI2PHYTIMER_CLK_SRC 29 40 + #define CAM_CC_CSI3PHYTIMER_CLK 30 41 + #define CAM_CC_CSI3PHYTIMER_CLK_SRC 31 42 + #define CAM_CC_CSI4PHYTIMER_CLK 32 43 + #define CAM_CC_CSI4PHYTIMER_CLK_SRC 33 44 + #define CAM_CC_CSI5PHYTIMER_CLK 34 45 + #define CAM_CC_CSI5PHYTIMER_CLK_SRC 35 46 + #define CAM_CC_CSID_CLK 36 47 + #define CAM_CC_CSID_CLK_SRC 37 48 + #define CAM_CC_CSID_CSIPHY_RX_CLK 38 49 + #define CAM_CC_CSIPHY0_CLK 39 50 + #define CAM_CC_CSIPHY1_CLK 40 51 + #define CAM_CC_CSIPHY2_CLK 41 52 + #define CAM_CC_CSIPHY3_CLK 42 53 + #define CAM_CC_CSIPHY4_CLK 43 54 + #define CAM_CC_CSIPHY5_CLK 44 55 + #define CAM_CC_FAST_AHB_CLK_SRC 45 56 + #define CAM_CC_GDSC_CLK 46 57 + #define CAM_CC_ICP_AHB_CLK 47 58 + #define CAM_CC_ICP_CLK 48 59 + #define CAM_CC_ICP_CLK_SRC 49 60 + #define CAM_CC_IFE_0_CLK 50 61 + #define CAM_CC_IFE_0_CLK_SRC 51 62 + #define CAM_CC_IFE_0_DSP_CLK 52 63 + #define CAM_CC_IFE_0_FAST_AHB_CLK 53 64 + #define CAM_CC_IFE_1_CLK 54 65 + #define CAM_CC_IFE_1_CLK_SRC 55 66 + #define CAM_CC_IFE_1_DSP_CLK 56 67 + #define CAM_CC_IFE_1_FAST_AHB_CLK 57 68 + #define CAM_CC_IFE_2_CLK 58 69 + #define CAM_CC_IFE_2_CLK_SRC 59 70 + #define CAM_CC_IFE_2_DSP_CLK 60 71 + #define CAM_CC_IFE_2_FAST_AHB_CLK 61 72 + #define CAM_CC_IFE_LITE_AHB_CLK 62 73 + #define CAM_CC_IFE_LITE_CLK 63 74 + #define CAM_CC_IFE_LITE_CLK_SRC 64 75 + #define CAM_CC_IFE_LITE_CPHY_RX_CLK 65 76 + #define CAM_CC_IFE_LITE_CSID_CLK 66 77 + #define CAM_CC_IFE_LITE_CSID_CLK_SRC 67 78 + #define CAM_CC_IPE_NPS_AHB_CLK 68 79 + #define CAM_CC_IPE_NPS_CLK 69 80 + #define CAM_CC_IPE_NPS_CLK_SRC 70 81 + #define CAM_CC_IPE_NPS_FAST_AHB_CLK 71 82 + #define CAM_CC_IPE_PPS_CLK 72 83 + #define CAM_CC_IPE_PPS_FAST_AHB_CLK 73 84 + #define CAM_CC_JPEG_CLK 74 85 + #define CAM_CC_JPEG_CLK_SRC 75 86 + #define CAM_CC_MCLK0_CLK 76 87 + #define CAM_CC_MCLK0_CLK_SRC 77 88 + #define CAM_CC_MCLK1_CLK 78 89 + #define CAM_CC_MCLK1_CLK_SRC 79 90 + #define CAM_CC_MCLK2_CLK 80 91 + #define CAM_CC_MCLK2_CLK_SRC 81 92 + #define CAM_CC_MCLK3_CLK 82 93 + #define CAM_CC_MCLK3_CLK_SRC 83 94 + #define CAM_CC_MCLK4_CLK 84 95 + #define CAM_CC_MCLK4_CLK_SRC 85 96 + #define CAM_CC_MCLK5_CLK 86 97 + #define CAM_CC_MCLK5_CLK_SRC 87 98 + #define CAM_CC_MCLK6_CLK 88 99 + #define CAM_CC_MCLK6_CLK_SRC 89 100 + #define CAM_CC_MCLK7_CLK 90 101 + #define CAM_CC_MCLK7_CLK_SRC 91 102 + #define CAM_CC_PLL0 92 103 + #define CAM_CC_PLL0_OUT_EVEN 93 104 + #define CAM_CC_PLL0_OUT_ODD 94 105 + #define CAM_CC_PLL1 95 106 + #define CAM_CC_PLL1_OUT_EVEN 96 107 + #define CAM_CC_PLL2 97 108 + #define CAM_CC_PLL3 98 109 + #define CAM_CC_PLL3_OUT_EVEN 99 110 + #define CAM_CC_PLL4 100 111 + #define CAM_CC_PLL4_OUT_EVEN 101 112 + #define CAM_CC_PLL5 102 113 + #define CAM_CC_PLL5_OUT_EVEN 103 114 + #define CAM_CC_PLL6 104 115 + #define CAM_CC_PLL6_OUT_EVEN 105 116 + #define CAM_CC_PLL7 106 117 + #define CAM_CC_PLL7_OUT_EVEN 107 118 + #define CAM_CC_PLL8 108 119 + #define CAM_CC_PLL8_OUT_EVEN 109 120 + #define CAM_CC_QDSS_DEBUG_CLK 110 121 + #define CAM_CC_QDSS_DEBUG_CLK_SRC 111 122 + #define CAM_CC_QDSS_DEBUG_XO_CLK 112 123 + #define CAM_CC_SBI_AHB_CLK 113 124 + #define CAM_CC_SBI_CLK 114 125 + #define CAM_CC_SFE_0_CLK 115 126 + #define CAM_CC_SFE_0_CLK_SRC 116 127 + #define CAM_CC_SFE_0_FAST_AHB_CLK 117 128 + #define CAM_CC_SFE_1_CLK 118 129 + #define CAM_CC_SFE_1_CLK_SRC 119 130 + #define CAM_CC_SFE_1_FAST_AHB_CLK 120 131 + #define CAM_CC_SLEEP_CLK 121 132 + #define CAM_CC_SLEEP_CLK_SRC 122 133 + #define CAM_CC_SLOW_AHB_CLK_SRC 123 134 + #define CAM_CC_XO_CLK_SRC 124 135 + 136 + /* CAM_CC resets */ 137 + #define CAM_CC_BPS_BCR 0 138 + #define CAM_CC_ICP_BCR 1 139 + #define CAM_CC_IFE_0_BCR 2 140 + #define CAM_CC_IFE_1_BCR 3 141 + #define CAM_CC_IFE_2_BCR 4 142 + #define CAM_CC_IPE_0_BCR 5 143 + #define CAM_CC_QDSS_DEBUG_BCR 6 144 + #define CAM_CC_SBI_BCR 7 145 + #define CAM_CC_SFE_0_BCR 8 146 + #define CAM_CC_SFE_1_BCR 9 147 + 148 + /* CAM_CC GDSCRs */ 149 + #define BPS_GDSC 0 150 + #define IPE_0_GDSC 1 151 + #define SBI_GDSC 2 152 + #define IFE_0_GDSC 3 153 + #define IFE_1_GDSC 4 154 + #define IFE_2_GDSC 5 155 + #define SFE_0_GDSC 6 156 + #define SFE_1_GDSC 7 157 + #define TITAN_TOP_GDSC 8 158 + 159 + #endif
+1
include/dt-bindings/mailbox/qcom-ipcc.h
··· 30 30 #define IPCC_CLIENT_PCIE1 14 31 31 #define IPCC_CLIENT_PCIE2 15 32 32 #define IPCC_CLIENT_SPSS 16 33 + #define IPCC_CLIENT_NSP1 18 33 34 #define IPCC_CLIENT_TME 23 34 35 #define IPCC_CLIENT_WPSS 24 35 36