Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] SMTC: Make ack_bad_irq() safe with no IM backstop.
+32
-30
+1
-4
arch/mips/kernel/i8259.c
+1
-4
arch/mips/kernel/i8259.c
···
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outb(cached_master_mask, PIC_MASTER_IMR);
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outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
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}
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-
#ifdef CONFIG_MIPS_MT_SMTC
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-
if (irq_hwmask[irq] & ST0_IM)
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-
set_c0_status(irq_hwmask[irq] & ST0_IM);
183
-
#endif /* CONFIG_MIPS_MT_SMTC */
180
+
smtc_im_ack_irq(irq);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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183
+2
-8
arch/mips/kernel/irq-msc01.c
+2
-8
arch/mips/kernel/irq-msc01.c
···
52
52
mask_msc_irq(irq);
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53
if (!cpu_has_veic)
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MSCIC_WRITE(MSC01_IC_EOI, 0);
55
-
#ifdef CONFIG_MIPS_MT_SMTC
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55
/* This actually needs to be a call into platform code */
57
-
if (irq_hwmask[irq] & ST0_IM)
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-
set_c0_status(irq_hwmask[irq] & ST0_IM);
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-
#endif /* CONFIG_MIPS_MT_SMTC */
56
+
smtc_im_ack_irq(irq);
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57
}
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/*
···
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MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
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MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
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}
73
-
#ifdef CONFIG_MIPS_MT_SMTC
74
-
if (irq_hwmask[irq] & ST0_IM)
75
-
set_c0_status(irq_hwmask[irq] & ST0_IM);
76
-
#endif /* CONFIG_MIPS_MT_SMTC */
76
+
smtc_im_ack_irq(irq);
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}
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79
/*
+1
-9
arch/mips/kernel/irq.c
+1
-9
arch/mips/kernel/irq.c
···
74
74
*/
75
75
void ack_bad_irq(unsigned int irq)
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76
{
77
+
smtc_im_ack_irq(irq);
77
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printk("unexpected IRQ # %d\n", irq);
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}
79
80
80
81
atomic_t irq_err_count;
81
-
82
-
#ifdef CONFIG_MIPS_MT_SMTC
83
-
/*
84
-
* SMTC Kernel needs to manipulate low-level CPU interrupt mask
85
-
* in do_IRQ. These are passed in setup_irq_smtc() and stored
86
-
* in this table.
87
-
*/
88
-
unsigned long irq_hwmask[NR_IRQS];
89
-
#endif /* CONFIG_MIPS_MT_SMTC */
90
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83
/*
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84
* Generic, controller-independent functions:
+4
-1
arch/mips/kernel/smtc.c
+4
-1
arch/mips/kernel/smtc.c
···
25
25
#include <asm/smtc_proc.h>
26
26
27
27
/*
28
-
* This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
28
+
* SMTC Kernel needs to manipulate low-level CPU interrupt mask
29
+
* in do_IRQ. These are passed in setup_irq_smtc() and stored
30
+
* in this table.
29
31
*/
32
+
unsigned long irq_hwmask[NR_IRQS];
30
33
31
34
#define LOCK_MT_PRA() \
32
35
local_irq_save(flags); \
+24
-8
include/asm-mips/irq.h
+24
-8
include/asm-mips/irq.h
···
24
24
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
25
25
#endif
26
26
27
+
#ifdef CONFIG_MIPS_MT_SMTC
28
+
29
+
struct irqaction;
30
+
31
+
extern unsigned long irq_hwmask[];
32
+
extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
33
+
unsigned long hwmask);
34
+
35
+
static inline void smtc_im_ack_irq(unsigned int irq)
36
+
{
37
+
if (irq_hwmask[irq] & ST0_IM)
38
+
set_c0_status(irq_hwmask[irq] & ST0_IM);
39
+
}
40
+
41
+
#else
42
+
43
+
static inline void smtc_im_ack_irq(unsigned int irq)
44
+
{
45
+
}
46
+
47
+
#endif /* CONFIG_MIPS_MT_SMTC */
48
+
27
49
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
50
+
28
51
/*
29
52
* Clear interrupt mask handling "backstop" if irq_hwmask
30
53
* entry so indicates. This implies that the ack() or end()
···
61
38
~(irq_hwmask[irq] & 0x0000ff00)); \
62
39
} while (0)
63
40
#else
41
+
64
42
#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0)
65
43
#endif
66
44
···
83
59
84
60
extern void arch_init_irq(void);
85
61
extern void spurious_interrupt(void);
86
-
87
-
#ifdef CONFIG_MIPS_MT_SMTC
88
-
struct irqaction;
89
-
90
-
extern unsigned long irq_hwmask[];
91
-
extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
92
-
unsigned long hwmask);
93
-
#endif /* CONFIG_MIPS_MT_SMTC */
94
62
95
63
extern int allocate_irqno(void);
96
64
extern void alloc_legacy_irqno(void);