+5 -5

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

reviewed

··· 35 35 (optional) NAND flash cache range (if at non-standard offset) 36 36 - reg-names : a list of the names corresponding to the previous register 37 37 ranges. Should contain "nand" and (optionally) 38 38 - "flash-dma" and/or "nand-cache". 39 39 - - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) 40 40 - FLASH_DMA_DONE 41 41 - - interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as 42 42 - individual interrupts. 38 38 + "flash-dma" or "flash-edu" and/or "nand-cache". 39 39 + - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available) 40 40 + FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE 41 41 + - interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done", 42 42 + if broken out as individual interrupts. 43 43 May be "nand", if the SoC has the individual NAND 44 44 interrupts multiplexed behind another custom piece of 45 45 hardware

+27

Documentation/devicetree/bindings/mtd/nand-macronix.txt

reviewed

··· 1 1 + Macronix NANDs Device Tree Bindings 2 2 + ----------------------------------- 3 3 + 4 4 + Macronix NANDs support randomizer operation for scrambling user data, 5 5 + which can be enabled with a SET_FEATURE. The penalty when using the 6 6 + randomizer are subpage accesses prohibited and more time period needed 7 7 + for program operation, i.e., tPROG 300us to 340us (randomizer enabled). 8 8 + Enabling the randomizer is a one time persistent and non reversible 9 9 + operation. 10 10 + 11 11 + For more high-reliability concern, if subpage write is not available 12 12 + with hardware ECC and not enabled at UBI level, then enabling the 13 13 + randomizer is recommended by default by adding a new specific property 14 14 + in children nodes. 15 15 + 16 16 + Required NAND chip properties in children mode: 17 17 + - randomizer enable: should be "mxic,enable-randomizer-otp" 18 18 + 19 19 + Example: 20 20 + 21 21 + nand: nand-controller@unit-address { 22 22 + 23 23 + nand@0 { 24 24 + reg = <0>; 25 25 + mxic,enable-randomizer-otp; 26 26 + }; 27 27 + };

+7 -1

MAINTAINERS

reviewed

··· 1945 1945 F: arch/arm/boot/dts/lpc43* 1946 1946 F: drivers/i2c/busses/i2c-lpc2k.c 1947 1947 F: drivers/memory/pl172.c 1948 1948 - F: drivers/mtd/spi-nor/nxp-spifi.c 1948 1948 + F: drivers/mtd/spi-nor/controllers/nxp-spifi.c 1949 1949 F: drivers/rtc/rtc-lpc24xx.c 1950 1950 N: lpc18xx 1951 1951 ··· 7851 7851 7852 7852 HYPERBUS SUPPORT 7853 7853 M: Vignesh Raghavendra <vigneshr@ti.com> 7854 7854 + L: linux-mtd@lists.infradead.org 7855 7855 + Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ 7856 7856 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git cfi/next 7857 7857 + C: irc://irc.oftc.net/mtd 7854 7858 S: Supported 7855 7859 F: drivers/mtd/hyperbus/ 7856 7860 F: include/linux/mtd/hyperbus.h ··· 11556 11552 W: http://www.linux-mtd.infradead.org/ 11557 11553 Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ 11558 11554 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next 11555 11555 + C: irc://irc.oftc.net/mtd 11559 11556 S: Maintained 11560 11557 F: drivers/mtd/nand/ 11561 11558 F: include/linux/mtd/*nand*.h ··· 15840 15835 W: http://www.linux-mtd.infradead.org/ 15841 15836 Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ 15842 15837 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/next 15838 15838 + C: irc://irc.oftc.net/mtd 15843 15839 S: Maintained 15844 15840 F: drivers/mtd/spi-nor/ 15845 15841 F: include/linux/mtd/spi-nor.h

+43 -4

arch/arm/mach-omap1/board-ams-delta.c

reviewed

··· 17 17 #include <linux/input.h> 18 18 #include <linux/interrupt.h> 19 19 #include <linux/leds.h> 20 20 + #include <linux/mtd/nand-gpio.h> 21 21 + #include <linux/mtd/partitions.h> 20 22 #include <linux/platform_device.h> 21 23 #include <linux/regulator/consumer.h> 22 24 #include <linux/regulator/fixed.h> ··· 296 294 297 295 static struct modem_private_data modem_priv; 298 296 297 297 + /* 298 298 + * Define partitions for flash device 299 299 + */ 300 300 + 301 301 + static struct mtd_partition partition_info[] = { 302 302 + { .name = "Kernel", 303 303 + .offset = 0, 304 304 + .size = 3 * SZ_1M + SZ_512K }, 305 305 + { .name = "u-boot", 306 306 + .offset = 3 * SZ_1M + SZ_512K, 307 307 + .size = SZ_256K }, 308 308 + { .name = "u-boot params", 309 309 + .offset = 3 * SZ_1M + SZ_512K + SZ_256K, 310 310 + .size = SZ_256K }, 311 311 + { .name = "Amstrad LDR", 312 312 + .offset = 4 * SZ_1M, 313 313 + .size = SZ_256K }, 314 314 + { .name = "File system", 315 315 + .offset = 4 * SZ_1M + 1 * SZ_256K, 316 316 + .size = 27 * SZ_1M }, 317 317 + { .name = "PBL reserved", 318 318 + .offset = 32 * SZ_1M - 3 * SZ_256K, 319 319 + .size = 3 * SZ_256K }, 320 320 + }; 321 321 + 322 322 + static struct gpio_nand_platdata nand_platdata = { 323 323 + .parts = partition_info, 324 324 + .num_parts = ARRAY_SIZE(partition_info), 325 325 + }; 326 326 + 299 327 static struct platform_device ams_delta_nand_device = { 300 328 .name = "ams-delta-nand", 301 329 .id = -1, 330 330 + .dev = { 331 331 + .platform_data = &nand_platdata, 332 332 + }, 302 333 }; 303 334 304 335 #define OMAP_GPIO_LABEL "gpio-0-15" ··· 341 306 .table = { 342 307 GPIO_LOOKUP(OMAP_GPIO_LABEL, AMS_DELTA_GPIO_PIN_NAND_RB, "rdy", 343 308 0), 344 344 - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce", 0), 345 345 - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre", 0), 346 346 - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp", 0), 347 347 - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe", 0), 309 309 + GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce", 310 310 + GPIO_ACTIVE_LOW), 311 311 + GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre", 312 312 + GPIO_ACTIVE_LOW), 313 313 + GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp", 314 314 + GPIO_ACTIVE_LOW), 315 315 + GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe", 316 316 + GPIO_ACTIVE_LOW), 348 317 GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_ALE, "ale", 0), 349 318 GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_CLE, "cle", 0), 350 319 GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 0, "data", 0, 0),

+2 -2

arch/mips/boot/dts/brcm/bcm7425.dtsi

reviewed

··· 403 403 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 404 404 #address-cells = <1>; 405 405 #size-cells = <0>; 406 406 - reg-names = "nand"; 407 407 - reg = <0x41b800 0x400>; 406 406 + reg-names = "nand", "flash-edu"; 407 407 + reg = <0x41b800 0x400>, <0x41bc00 0x24>; 408 408 interrupt-parent = <&hif_l2_intc>; 409 409 interrupts = <24>; 410 410 status = "disabled";

+2 -2

drivers/mtd/chips/cfi_cmdset_0001.c

reviewed

··· 834 834 /* Someone else might have been playing with it. */ 835 835 return -EAGAIN; 836 836 } 837 837 - /* Fall through */ 837 837 + fallthrough; 838 838 case FL_READY: 839 839 case FL_CFI_QUERY: 840 840 case FL_JEDEC_QUERY: ··· 907 907 /* Only if there's no operation suspended... */ 908 908 if (mode == FL_READY && chip->oldstate == FL_READY) 909 909 return 0; 910 910 - /* Fall through */ 910 910 + fallthrough; 911 911 default: 912 912 sleep: 913 913 set_current_state(TASK_UNINTERRUPTIBLE);

+2 -3

drivers/mtd/chips/cfi_cmdset_0002.c

reviewed

··· 966 966 /* Only if there's no operation suspended... */ 967 967 if (mode == FL_READY && chip->oldstate == FL_READY) 968 968 return 0; 969 969 - /* fall through */ 970 970 - 969 969 + fallthrough; 971 970 default: 972 971 sleep: 973 972 set_current_state(TASK_UNINTERRUPTIBLE); ··· 2934 2935 * as the whole point is that nobody can do anything 2935 2936 * with the chip now anyway. 2936 2937 */ 2937 2937 - /* fall through */ 2938 2938 + fallthrough; 2938 2939 case FL_SYNCING: 2939 2940 mutex_unlock(&chip->mutex); 2940 2941 break;

+6 -11

drivers/mtd/chips/cfi_cmdset_0020.c

reviewed

··· 324 324 case FL_JEDEC_QUERY: 325 325 map_write(map, CMD(0x70), cmd_addr); 326 326 chip->state = FL_STATUS; 327 327 - /* Fall through */ 328 328 - 327 327 + fallthrough; 329 328 case FL_STATUS: 330 329 status = map_read(map, cmd_addr); 331 330 if (map_word_andequal(map, status, status_OK, status_OK)) { ··· 461 462 #ifdef DEBUG_CFI_FEATURES 462 463 printk("%s: 1 status[%x]\n", __func__, map_read(map, cmd_adr)); 463 464 #endif 464 464 - /* Fall through */ 465 465 - 465 465 + fallthrough; 466 466 case FL_STATUS: 467 467 status = map_read(map, cmd_adr); 468 468 if (map_word_andequal(map, status, status_OK, status_OK)) ··· 754 756 case FL_READY: 755 757 map_write(map, CMD(0x70), adr); 756 758 chip->state = FL_STATUS; 757 757 - /* Fall through */ 758 758 - 759 759 + fallthrough; 759 760 case FL_STATUS: 760 761 status = map_read(map, adr); 761 762 if (map_word_andequal(map, status, status_OK, status_OK)) ··· 995 998 * as the whole point is that nobody can do anything 996 999 * with the chip now anyway. 997 1000 */ 998 998 - /* Fall through */ 1001 1001 + fallthrough; 999 1002 case FL_SYNCING: 1000 1003 mutex_unlock(&chip->mutex); 1001 1004 break; ··· 1051 1054 case FL_READY: 1052 1055 map_write(map, CMD(0x70), adr); 1053 1056 chip->state = FL_STATUS; 1054 1054 - /* Fall through */ 1055 1055 - 1057 1057 + fallthrough; 1056 1058 case FL_STATUS: 1057 1059 status = map_read(map, adr); 1058 1060 if (map_word_andequal(map, status, status_OK, status_OK)) ··· 1197 1201 case FL_READY: 1198 1202 map_write(map, CMD(0x70), adr); 1199 1203 chip->state = FL_STATUS; 1200 1200 - /* Fall through */ 1201 1201 - 1204 1204 + fallthrough; 1202 1205 case FL_STATUS: 1203 1206 status = map_read(map, adr); 1204 1207 if (map_word_andequal(map, status, status_OK, status_OK))

+6 -6

drivers/mtd/chips/cfi_util.c

reviewed

··· 109 109 case 8: 110 110 onecmd |= (onecmd << (chip_mode * 32)); 111 111 #endif 112 112 - /* fall through */ 112 112 + fallthrough; 113 113 case 4: 114 114 onecmd |= (onecmd << (chip_mode * 16)); 115 115 - /* fall through */ 115 115 + fallthrough; 116 116 case 2: 117 117 onecmd |= (onecmd << (chip_mode * 8)); 118 118 - /* fall through */ 118 118 + fallthrough; 119 119 case 1: 120 120 ; 121 121 } ··· 165 165 case 8: 166 166 res |= (onestat >> (chip_mode * 32)); 167 167 #endif 168 168 - /* fall through */ 168 168 + fallthrough; 169 169 case 4: 170 170 res |= (onestat >> (chip_mode * 16)); 171 171 - /* fall through */ 171 171 + fallthrough; 172 172 case 2: 173 173 res |= (onestat >> (chip_mode * 8)); 174 174 - /* fall through */ 174 174 + fallthrough; 175 175 case 1: 176 176 ; 177 177 }

+2 -2

drivers/mtd/devices/block2mtd.c

reviewed

··· 329 329 switch (**endp) { 330 330 case 'G' : 331 331 result *= 1024; 332 332 - /* fall through */ 332 332 + fallthrough; 333 333 case 'M': 334 334 result *= 1024; 335 335 - /* fall through */ 335 335 + fallthrough; 336 336 case 'K': 337 337 case 'k': 338 338 result *= 1024;

+11 -8

drivers/mtd/devices/phram.c

reviewed

··· 148 148 switch (token[len - 2]) { 149 149 case 'G': 150 150 shift += 10; 151 151 - /* fall through */ 151 151 + fallthrough; 152 152 case 'M': 153 153 shift += 10; 154 154 - /* fall through */ 154 154 + fallthrough; 155 155 case 'k': 156 156 shift += 10; 157 157 token[len - 2] = 0; ··· 243 243 244 244 ret = parse_num64(&start, token[1]); 245 245 if (ret) { 246 246 - kfree(name); 247 246 parse_err("illegal start address\n"); 247 247 + goto error; 248 248 } 249 249 250 250 ret = parse_num64(&len, token[2]); 251 251 if (ret) { 252 252 - kfree(name); 253 252 parse_err("illegal device length\n"); 253 253 + goto error; 254 254 } 255 255 256 256 ret = register_device(name, start, len); 257 257 - if (!ret) 258 258 - pr_info("%s device: %#llx at %#llx\n", name, len, start); 259 259 - else 260 260 - kfree(name); 257 257 + if (ret) 258 258 + goto error; 261 259 260 260 + pr_info("%s device: %#llx at %#llx\n", name, len, start); 261 261 + return 0; 262 262 + 263 263 + error: 264 264 + kfree(name); 262 265 return ret; 263 266 } 264 267

+12

drivers/mtd/hyperbus/hbmc-am654.c

reviewed

··· 11 11 #include <linux/mtd/mtd.h> 12 12 #include <linux/mux/consumer.h> 13 13 #include <linux/of.h> 14 14 + #include <linux/of_address.h> 14 15 #include <linux/platform_device.h> 15 16 #include <linux/pm_runtime.h> 16 17 #include <linux/types.h> ··· 58 57 59 58 static int am654_hbmc_probe(struct platform_device *pdev) 60 59 { 60 60 + struct device_node *np = pdev->dev.of_node; 61 61 struct device *dev = &pdev->dev; 62 62 struct am654_hbmc_priv *priv; 63 63 + struct resource res; 63 64 int ret; 64 65 65 66 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 69 66 return -ENOMEM; 70 67 71 68 platform_set_drvdata(pdev, priv); 69 69 + 70 70 + ret = of_address_to_resource(np, 0, &res); 71 71 + if (ret) 72 72 + return ret; 72 73 73 74 if (of_property_read_bool(dev->of_node, "mux-controls")) { 74 75 struct mux_control *control = devm_mux_control_get(dev, NULL); ··· 94 87 pm_runtime_put_noidle(dev); 95 88 goto disable_pm; 96 89 } 90 90 + 91 91 + priv->hbdev.map.size = resource_size(&res); 92 92 + priv->hbdev.map.virt = devm_ioremap_resource(dev, &res); 93 93 + if (IS_ERR(priv->hbdev.map.virt)) 94 94 + return PTR_ERR(priv->hbdev.map.virt); 97 95 98 96 priv->ctlr.dev = dev; 99 97 priv->ctlr.ops = &am654_hbmc_ops;

+3 -12

drivers/mtd/hyperbus/hyperbus-core.c

reviewed

··· 10 10 #include <linux/mtd/map.h> 11 11 #include <linux/mtd/mtd.h> 12 12 #include <linux/of.h> 13 13 - #include <linux/of_address.h> 14 13 #include <linux/types.h> 15 14 16 15 static struct hyperbus_device *map_to_hbdev(struct map_info *map) ··· 61 62 struct hyperbus_ctlr *ctlr; 62 63 struct device_node *np; 63 64 struct map_info *map; 64 64 - struct resource res; 65 65 struct device *dev; 66 66 int ret; 67 67 ··· 71 73 72 74 np = hbdev->np; 73 75 ctlr = hbdev->ctlr; 74 74 - if (!of_device_is_compatible(np, "cypress,hyperflash")) 76 76 + if (!of_device_is_compatible(np, "cypress,hyperflash")) { 77 77 + dev_err(ctlr->dev, "\"cypress,hyperflash\" compatible missing\n"); 75 78 return -ENODEV; 79 79 + } 76 80 77 81 hbdev->memtype = HYPERFLASH; 78 82 79 79 - ret = of_address_to_resource(np, 0, &res); 80 80 - if (ret) 81 81 - return ret; 82 82 - 83 83 dev = ctlr->dev; 84 84 map = &hbdev->map; 85 85 - map->size = resource_size(&res); 86 86 - map->virt = devm_ioremap_resource(dev, &res); 87 87 - if (IS_ERR(map->virt)) 88 88 - return PTR_ERR(map->virt); 89 89 - 90 85 map->name = dev_name(dev); 91 86 map->bankwidth = 2; 92 87 map->device_node = np;

+1 -1

drivers/mtd/inftlmount.c

reviewed

··· 130 130 " NoOfBootImageBlocks = %d\n" 131 131 " NoOfBinaryPartitions = %d\n" 132 132 " NoOfBDTLPartitions = %d\n" 133 133 - " BlockMultiplerBits = %d\n" 133 133 + " BlockMultiplierBits = %d\n" 134 134 " FormatFlgs = %d\n" 135 135 " OsakVersion = 0x%x\n" 136 136 " PercentUsed = %d\n",

+1 -3

drivers/mtd/lpddr/lpddr_cmds.c

reviewed

··· 68 68 shared = kmalloc_array(lpddr->numchips, sizeof(struct flchip_shared), 69 69 GFP_KERNEL); 70 70 if (!shared) { 71 71 - kfree(lpddr); 72 71 kfree(mtd); 73 72 return NULL; 74 73 } ··· 304 305 /* Only if there's no operation suspended... */ 305 306 if (mode == FL_READY && chip->oldstate == FL_READY) 306 307 return 0; 307 307 - /* fall through */ 308 308 - 308 308 + fallthrough; 309 309 default: 310 310 sleep: 311 311 set_current_state(TASK_UNINTERRUPTIBLE);

+2 -3

drivers/mtd/maps/sa1100-flash.c

reviewed

··· 34 34 struct sa_info { 35 35 struct mtd_info *mtd; 36 36 int num_subdev; 37 37 - struct sa_subdev_info subdev[0]; 37 37 + struct sa_subdev_info subdev[]; 38 38 }; 39 39 40 40 static DEFINE_SPINLOCK(sa1100_vpp_lock); ··· 81 81 default: 82 82 printk(KERN_WARNING "SA1100 flash: unknown base address " 83 83 "0x%08lx, assuming CS0\n", phys); 84 84 - /* Fall through */ 85 85 - 84 84 + fallthrough; 86 85 case SA1100_CS0_PHYS: 87 86 subdev->map.bankwidth = (MSC0 & MSC_RBW) ? 2 : 4; 88 87 break;

+3 -2

drivers/mtd/mtdblock.c

reviewed

··· 294 294 static int mtdblock_flush(struct mtd_blktrans_dev *dev) 295 295 { 296 296 struct mtdblk_dev *mtdblk = container_of(dev, struct mtdblk_dev, mbd); 297 297 + int ret; 297 298 298 299 mutex_lock(&mtdblk->cache_mutex); 299 299 - write_cached_data(mtdblk); 300 300 + ret = write_cached_data(mtdblk); 300 301 mutex_unlock(&mtdblk->cache_mutex); 301 302 mtd_sync(dev->mtd); 302 302 - return 0; 303 303 + return ret; 303 304 } 304 305 305 306 static void mtdblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)

+7 -5

drivers/mtd/mtdchar.c

reviewed

··· 349 349 uint64_t start, uint32_t length, void __user *ptr, 350 350 uint32_t __user *retp) 351 351 { 352 352 + struct mtd_info *master = mtd_get_master(mtd); 352 353 struct mtd_file_info *mfi = file->private_data; 353 354 struct mtd_oob_ops ops = {}; 354 355 uint32_t retlen; ··· 361 360 if (length > 4096) 362 361 return -EINVAL; 363 362 364 364 - if (!mtd->_write_oob) 363 363 + if (!master->_write_oob) 365 364 return -EOPNOTSUPP; 366 365 367 366 ops.ooblen = length; ··· 587 586 static int mtdchar_write_ioctl(struct mtd_info *mtd, 588 587 struct mtd_write_req __user *argp) 589 588 { 589 589 + struct mtd_info *master = mtd_get_master(mtd); 590 590 struct mtd_write_req req; 591 591 struct mtd_oob_ops ops = {}; 592 592 const void __user *usr_data, *usr_oob; ··· 599 597 usr_data = (const void __user *)(uintptr_t)req.usr_data; 600 598 usr_oob = (const void __user *)(uintptr_t)req.usr_oob; 601 599 602 602 - if (!mtd->_write_oob) 600 600 + if (!master->_write_oob) 603 601 return -EOPNOTSUPP; 604 604 - 605 602 ops.mode = req.mode; 606 603 ops.len = (size_t)req.len; 607 604 ops.ooblen = (size_t)req.ooblen; ··· 636 635 { 637 636 struct mtd_file_info *mfi = file->private_data; 638 637 struct mtd_info *mtd = mfi->mtd; 638 638 + struct mtd_info *master = mtd_get_master(mtd); 639 639 void __user *argp = (void __user *)arg; 640 640 int ret = 0; 641 641 struct mtd_info_user info; ··· 826 824 { 827 825 struct nand_oobinfo oi; 828 826 829 829 - if (!mtd->ooblayout) 827 827 + if (!master->ooblayout) 830 828 return -EOPNOTSUPP; 831 829 832 830 ret = get_oobinfo(mtd, &oi); ··· 920 918 { 921 919 struct nand_ecclayout_user *usrlay; 922 920 923 923 - if (!mtd->ooblayout) 921 921 + if (!master->ooblayout) 924 922 return -EOPNOTSUPP; 925 923 926 924 usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL);

+179 -71

drivers/mtd/mtdcore.c

reviewed

··· 456 456 int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit, 457 457 struct mtd_pairing_info *info) 458 458 { 459 459 - int npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd); 459 459 + struct mtd_info *master = mtd_get_master(mtd); 460 460 + int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master); 460 461 461 462 if (wunit < 0 || wunit >= npairs) 462 463 return -EINVAL; 463 464 464 464 - if (mtd->pairing && mtd->pairing->get_info) 465 465 - return mtd->pairing->get_info(mtd, wunit, info); 465 465 + if (master->pairing && master->pairing->get_info) 466 466 + return master->pairing->get_info(master, wunit, info); 466 467 467 468 info->group = 0; 468 469 info->pair = wunit; ··· 499 498 int mtd_pairing_info_to_wunit(struct mtd_info *mtd, 500 499 const struct mtd_pairing_info *info) 501 500 { 502 502 - int ngroups = mtd_pairing_groups(mtd); 503 503 - int npairs = mtd_wunit_per_eb(mtd) / ngroups; 501 501 + struct mtd_info *master = mtd_get_master(mtd); 502 502 + int ngroups = mtd_pairing_groups(master); 503 503 + int npairs = mtd_wunit_per_eb(master) / ngroups; 504 504 505 505 if (!info || info->pair < 0 || info->pair >= npairs || 506 506 info->group < 0 || info->group >= ngroups) 507 507 return -EINVAL; 508 508 509 509 - if (mtd->pairing && mtd->pairing->get_wunit) 510 510 - return mtd->pairing->get_wunit(mtd, info); 509 509 + if (master->pairing && master->pairing->get_wunit) 510 510 + return mtd->pairing->get_wunit(master, info); 511 511 512 512 return info->pair; 513 513 } ··· 526 524 */ 527 525 int mtd_pairing_groups(struct mtd_info *mtd) 528 526 { 529 529 - if (!mtd->pairing || !mtd->pairing->ngroups) 527 527 + struct mtd_info *master = mtd_get_master(mtd); 528 528 + 529 529 + if (!master->pairing || !master->pairing->ngroups) 530 530 return 1; 531 531 532 532 - return mtd->pairing->ngroups; 532 532 + return master->pairing->ngroups; 533 533 } 534 534 EXPORT_SYMBOL_GPL(mtd_pairing_groups); 535 535 ··· 591 587 592 588 int add_mtd_device(struct mtd_info *mtd) 593 589 { 590 590 + struct mtd_info *master = mtd_get_master(mtd); 594 591 struct mtd_notifier *not; 595 592 int i, error; 596 593 ··· 613 608 (mtd->_read && mtd->_read_oob))) 614 609 return -EINVAL; 615 610 616 616 - if (WARN_ON((!mtd->erasesize || !mtd->_erase) && 611 611 + if (WARN_ON((!mtd->erasesize || !master->_erase) && 617 612 !(mtd->flags & MTD_NO_ERASE))) 618 613 return -EINVAL; 619 614 ··· 770 765 pr_debug("mtd device won't show a device symlink in sysfs\n"); 771 766 } 772 767 773 773 - mtd->orig_flags = mtd->flags; 768 768 + INIT_LIST_HEAD(&mtd->partitions); 769 769 + mutex_init(&mtd->master.partitions_lock); 774 770 } 775 771 776 772 /** ··· 977 971 978 972 int __get_mtd_device(struct mtd_info *mtd) 979 973 { 974 974 + struct mtd_info *master = mtd_get_master(mtd); 980 975 int err; 981 976 982 982 - if (!try_module_get(mtd->owner)) 977 977 + if (!try_module_get(master->owner)) 983 978 return -ENODEV; 984 979 985 985 - if (mtd->_get_device) { 986 986 - err = mtd->_get_device(mtd); 980 980 + if (master->_get_device) { 981 981 + err = master->_get_device(mtd); 987 982 988 983 if (err) { 989 989 - module_put(mtd->owner); 984 984 + module_put(master->owner); 990 985 return err; 991 986 } 992 987 } 993 993 - mtd->usecount++; 988 988 + 989 989 + while (mtd->parent) { 990 990 + mtd->usecount++; 991 991 + mtd = mtd->parent; 992 992 + } 993 993 + 994 994 return 0; 995 995 } 996 996 EXPORT_SYMBOL_GPL(__get_mtd_device); ··· 1050 1038 1051 1039 void __put_mtd_device(struct mtd_info *mtd) 1052 1040 { 1053 1053 - --mtd->usecount; 1054 1054 - BUG_ON(mtd->usecount < 0); 1041 1041 + struct mtd_info *master = mtd_get_master(mtd); 1055 1042 1056 1056 - if (mtd->_put_device) 1057 1057 - mtd->_put_device(mtd); 1043 1043 + while (mtd->parent) { 1044 1044 + --mtd->usecount; 1045 1045 + BUG_ON(mtd->usecount < 0); 1046 1046 + mtd = mtd->parent; 1047 1047 + } 1058 1048 1059 1059 - module_put(mtd->owner); 1049 1049 + if (master->_put_device) 1050 1050 + master->_put_device(master); 1051 1051 + 1052 1052 + module_put(master->owner); 1060 1053 } 1061 1054 EXPORT_SYMBOL_GPL(__put_mtd_device); 1062 1055 ··· 1072 1055 */ 1073 1056 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) 1074 1057 { 1058 1058 + struct mtd_info *master = mtd_get_master(mtd); 1059 1059 + u64 mst_ofs = mtd_get_master_ofs(mtd, 0); 1060 1060 + int ret; 1061 1061 + 1075 1062 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; 1076 1063 1077 1077 - if (!mtd->erasesize || !mtd->_erase) 1064 1064 + if (!mtd->erasesize || !master->_erase) 1078 1065 return -ENOTSUPP; 1079 1066 1080 1067 if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr) ··· 1090 1069 return 0; 1091 1070 1092 1071 ledtrig_mtd_activity(); 1093 1093 - return mtd->_erase(mtd, instr); 1072 1072 + 1073 1073 + instr->addr += mst_ofs; 1074 1074 + ret = master->_erase(master, instr); 1075 1075 + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) 1076 1076 + instr->fail_addr -= mst_ofs; 1077 1077 + 1078 1078 + instr->addr -= mst_ofs; 1079 1079 + return ret; 1094 1080 } 1095 1081 EXPORT_SYMBOL_GPL(mtd_erase); 1096 1082 ··· 1107 1079 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, 1108 1080 void **virt, resource_size_t *phys) 1109 1081 { 1082 1082 + struct mtd_info *master = mtd_get_master(mtd); 1083 1083 + 1110 1084 *retlen = 0; 1111 1085 *virt = NULL; 1112 1086 if (phys) 1113 1087 *phys = 0; 1114 1114 - if (!mtd->_point) 1088 1088 + if (!master->_point) 1115 1089 return -EOPNOTSUPP; 1116 1090 if (from < 0 || from >= mtd->size || len > mtd->size - from) 1117 1091 return -EINVAL; 1118 1092 if (!len) 1119 1093 return 0; 1120 1120 - return mtd->_point(mtd, from, len, retlen, virt, phys); 1094 1094 + 1095 1095 + from = mtd_get_master_ofs(mtd, from); 1096 1096 + return master->_point(master, from, len, retlen, virt, phys); 1121 1097 } 1122 1098 EXPORT_SYMBOL_GPL(mtd_point); 1123 1099 1124 1100 /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ 1125 1101 int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len) 1126 1102 { 1127 1127 - if (!mtd->_unpoint) 1103 1103 + struct mtd_info *master = mtd_get_master(mtd); 1104 1104 + 1105 1105 + if (!master->_unpoint) 1128 1106 return -EOPNOTSUPP; 1129 1107 if (from < 0 || from >= mtd->size || len > mtd->size - from) 1130 1108 return -EINVAL; 1131 1109 if (!len) 1132 1110 return 0; 1133 1133 - return mtd->_unpoint(mtd, from, len); 1111 1111 + return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len); 1134 1112 } 1135 1113 EXPORT_SYMBOL_GPL(mtd_unpoint); 1136 1114 ··· 1162 1128 return (unsigned long)virt; 1163 1129 } 1164 1130 EXPORT_SYMBOL_GPL(mtd_get_unmapped_area); 1131 1131 + 1132 1132 + static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master, 1133 1133 + const struct mtd_ecc_stats *old_stats) 1134 1134 + { 1135 1135 + struct mtd_ecc_stats diff; 1136 1136 + 1137 1137 + if (master == mtd) 1138 1138 + return; 1139 1139 + 1140 1140 + diff = master->ecc_stats; 1141 1141 + diff.failed -= old_stats->failed; 1142 1142 + diff.corrected -= old_stats->corrected; 1143 1143 + 1144 1144 + while (mtd->parent) { 1145 1145 + mtd->ecc_stats.failed += diff.failed; 1146 1146 + mtd->ecc_stats.corrected += diff.corrected; 1147 1147 + mtd = mtd->parent; 1148 1148 + } 1149 1149 + } 1165 1150 1166 1151 int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, 1167 1152 u_char *buf) ··· 1224 1171 int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, 1225 1172 const u_char *buf) 1226 1173 { 1174 1174 + struct mtd_info *master = mtd_get_master(mtd); 1175 1175 + 1227 1176 *retlen = 0; 1228 1228 - if (!mtd->_panic_write) 1177 1177 + if (!master->_panic_write) 1229 1178 return -EOPNOTSUPP; 1230 1179 if (to < 0 || to >= mtd->size || len > mtd->size - to) 1231 1180 return -EINVAL; ··· 1238 1183 if (!mtd->oops_panic_write) 1239 1184 mtd->oops_panic_write = true; 1240 1185 1241 1241 - return mtd->_panic_write(mtd, to, len, retlen, buf); 1186 1186 + return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len, 1187 1187 + retlen, buf); 1242 1188 } 1243 1189 EXPORT_SYMBOL_GPL(mtd_panic_write); 1244 1190 ··· 1278 1222 1279 1223 int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) 1280 1224 { 1225 1225 + struct mtd_info *master = mtd_get_master(mtd); 1226 1226 + struct mtd_ecc_stats old_stats = master->ecc_stats; 1281 1227 int ret_code; 1228 1228 + 1282 1229 ops->retlen = ops->oobretlen = 0; 1283 1230 1284 1231 ret_code = mtd_check_oob_ops(mtd, from, ops); ··· 1291 1232 ledtrig_mtd_activity(); 1292 1233 1293 1234 /* Check the validity of a potential fallback on mtd->_read */ 1294 1294 - if (!mtd->_read_oob && (!mtd->_read || ops->oobbuf)) 1235 1235 + if (!master->_read_oob && (!master->_read || ops->oobbuf)) 1295 1236 return -EOPNOTSUPP; 1296 1237 1297 1297 - if (mtd->_read_oob) 1298 1298 - ret_code = mtd->_read_oob(mtd, from, ops); 1238 1238 + from = mtd_get_master_ofs(mtd, from); 1239 1239 + if (master->_read_oob) 1240 1240 + ret_code = master->_read_oob(master, from, ops); 1299 1241 else 1300 1300 - ret_code = mtd->_read(mtd, from, ops->len, &ops->retlen, 1301 1301 - ops->datbuf); 1242 1242 + ret_code = master->_read(master, from, ops->len, &ops->retlen, 1243 1243 + ops->datbuf); 1244 1244 + 1245 1245 + mtd_update_ecc_stats(mtd, master, &old_stats); 1302 1246 1303 1247 /* 1304 1248 * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics ··· 1320 1258 int mtd_write_oob(struct mtd_info *mtd, loff_t to, 1321 1259 struct mtd_oob_ops *ops) 1322 1260 { 1261 1261 + struct mtd_info *master = mtd_get_master(mtd); 1323 1262 int ret; 1324 1263 1325 1264 ops->retlen = ops->oobretlen = 0; ··· 1335 1272 ledtrig_mtd_activity(); 1336 1273 1337 1274 /* Check the validity of a potential fallback on mtd->_write */ 1338 1338 - if (!mtd->_write_oob && (!mtd->_write || ops->oobbuf)) 1275 1275 + if (!master->_write_oob && (!master->_write || ops->oobbuf)) 1339 1276 return -EOPNOTSUPP; 1340 1277 1341 1341 - if (mtd->_write_oob) 1342 1342 - return mtd->_write_oob(mtd, to, ops); 1278 1278 + to = mtd_get_master_ofs(mtd, to); 1279 1279 + 1280 1280 + if (master->_write_oob) 1281 1281 + return master->_write_oob(master, to, ops); 1343 1282 else 1344 1344 - return mtd->_write(mtd, to, ops->len, &ops->retlen, 1345 1345 - ops->datbuf); 1283 1283 + return master->_write(master, to, ops->len, &ops->retlen, 1284 1284 + ops->datbuf); 1346 1285 } 1347 1286 EXPORT_SYMBOL_GPL(mtd_write_oob); 1348 1287 ··· 1367 1302 int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, 1368 1303 struct mtd_oob_region *oobecc) 1369 1304 { 1305 1305 + struct mtd_info *master = mtd_get_master(mtd); 1306 1306 + 1370 1307 memset(oobecc, 0, sizeof(*oobecc)); 1371 1308 1372 1372 - if (!mtd || section < 0) 1309 1309 + if (!master || section < 0) 1373 1310 return -EINVAL; 1374 1311 1375 1375 - if (!mtd->ooblayout || !mtd->ooblayout->ecc) 1312 1312 + if (!master->ooblayout || !master->ooblayout->ecc) 1376 1313 return -ENOTSUPP; 1377 1314 1378 1378 - return mtd->ooblayout->ecc(mtd, section, oobecc); 1315 1315 + return master->ooblayout->ecc(master, section, oobecc); 1379 1316 } 1380 1317 EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc); 1381 1318 ··· 1401 1334 int mtd_ooblayout_free(struct mtd_info *mtd, int section, 1402 1335 struct mtd_oob_region *oobfree) 1403 1336 { 1337 1337 + struct mtd_info *master = mtd_get_master(mtd); 1338 1338 + 1404 1339 memset(oobfree, 0, sizeof(*oobfree)); 1405 1340 1406 1406 - if (!mtd || section < 0) 1341 1341 + if (!master || section < 0) 1407 1342 return -EINVAL; 1408 1343 1409 1409 - if (!mtd->ooblayout || !mtd->ooblayout->free) 1344 1344 + if (!master->ooblayout || !master->ooblayout->free) 1410 1345 return -ENOTSUPP; 1411 1346 1412 1412 - return mtd->ooblayout->free(mtd, section, oobfree); 1347 1347 + return master->ooblayout->free(master, section, oobfree); 1413 1348 } 1414 1349 EXPORT_SYMBOL_GPL(mtd_ooblayout_free); 1415 1350 ··· 1720 1651 int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, 1721 1652 struct otp_info *buf) 1722 1653 { 1723 1723 - if (!mtd->_get_fact_prot_info) 1654 1654 + struct mtd_info *master = mtd_get_master(mtd); 1655 1655 + 1656 1656 + if (!master->_get_fact_prot_info) 1724 1657 return -EOPNOTSUPP; 1725 1658 if (!len) 1726 1659 return 0; 1727 1727 - return mtd->_get_fact_prot_info(mtd, len, retlen, buf); 1660 1660 + return master->_get_fact_prot_info(master, len, retlen, buf); 1728 1661 } 1729 1662 EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info); 1730 1663 1731 1664 int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, 1732 1665 size_t *retlen, u_char *buf) 1733 1666 { 1667 1667 + struct mtd_info *master = mtd_get_master(mtd); 1668 1668 + 1734 1669 *retlen = 0; 1735 1735 - if (!mtd->_read_fact_prot_reg) 1670 1670 + if (!master->_read_fact_prot_reg) 1736 1671 return -EOPNOTSUPP; 1737 1672 if (!len) 1738 1673 return 0; 1739 1739 - return mtd->_read_fact_prot_reg(mtd, from, len, retlen, buf); 1674 1674 + return master->_read_fact_prot_reg(master, from, len, retlen, buf); 1740 1675 } 1741 1676 EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg); 1742 1677 1743 1678 int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, 1744 1679 struct otp_info *buf) 1745 1680 { 1746 1746 - if (!mtd->_get_user_prot_info) 1681 1681 + struct mtd_info *master = mtd_get_master(mtd); 1682 1682 + 1683 1683 + if (!master->_get_user_prot_info) 1747 1684 return -EOPNOTSUPP; 1748 1685 if (!len) 1749 1686 return 0; 1750 1750 - return mtd->_get_user_prot_info(mtd, len, retlen, buf); 1687 1687 + return master->_get_user_prot_info(master, len, retlen, buf); 1751 1688 } 1752 1689 EXPORT_SYMBOL_GPL(mtd_get_user_prot_info); 1753 1690 1754 1691 int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, 1755 1692 size_t *retlen, u_char *buf) 1756 1693 { 1694 1694 + struct mtd_info *master = mtd_get_master(mtd); 1695 1695 + 1757 1696 *retlen = 0; 1758 1758 - if (!mtd->_read_user_prot_reg) 1697 1697 + if (!master->_read_user_prot_reg) 1759 1698 return -EOPNOTSUPP; 1760 1699 if (!len) 1761 1700 return 0; 1762 1762 - return mtd->_read_user_prot_reg(mtd, from, len, retlen, buf); 1701 1701 + return master->_read_user_prot_reg(master, from, len, retlen, buf); 1763 1702 } 1764 1703 EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg); 1765 1704 1766 1705 int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len, 1767 1706 size_t *retlen, u_char *buf) 1768 1707 { 1708 1708 + struct mtd_info *master = mtd_get_master(mtd); 1769 1709 int ret; 1770 1710 1771 1711 *retlen = 0; 1772 1772 - if (!mtd->_write_user_prot_reg) 1712 1712 + if (!master->_write_user_prot_reg) 1773 1713 return -EOPNOTSUPP; 1774 1714 if (!len) 1775 1715 return 0; 1776 1776 - ret = mtd->_write_user_prot_reg(mtd, to, len, retlen, buf); 1716 1716 + ret = master->_write_user_prot_reg(master, to, len, retlen, buf); 1777 1717 if (ret) 1778 1718 return ret; 1779 1719 ··· 1796 1718 1797 1719 int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len) 1798 1720 { 1799 1799 - if (!mtd->_lock_user_prot_reg) 1721 1721 + struct mtd_info *master = mtd_get_master(mtd); 1722 1722 + 1723 1723 + if (!master->_lock_user_prot_reg) 1800 1724 return -EOPNOTSUPP; 1801 1725 if (!len) 1802 1726 return 0; 1803 1803 - return mtd->_lock_user_prot_reg(mtd, from, len); 1727 1727 + return master->_lock_user_prot_reg(master, from, len); 1804 1728 } 1805 1729 EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg); 1806 1730 1807 1731 /* Chip-supported device locking */ 1808 1732 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1809 1733 { 1810 1810 - if (!mtd->_lock) 1734 1734 + struct mtd_info *master = mtd_get_master(mtd); 1735 1735 + 1736 1736 + if (!master->_lock) 1811 1737 return -EOPNOTSUPP; 1812 1738 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) 1813 1739 return -EINVAL; 1814 1740 if (!len) 1815 1741 return 0; 1816 1816 - return mtd->_lock(mtd, ofs, len); 1742 1742 + return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len); 1817 1743 } 1818 1744 EXPORT_SYMBOL_GPL(mtd_lock); 1819 1745 1820 1746 int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1821 1747 { 1822 1822 - if (!mtd->_unlock) 1748 1748 + struct mtd_info *master = mtd_get_master(mtd); 1749 1749 + 1750 1750 + if (!master->_unlock) 1823 1751 return -EOPNOTSUPP; 1824 1752 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) 1825 1753 return -EINVAL; 1826 1754 if (!len) 1827 1755 return 0; 1828 1828 - return mtd->_unlock(mtd, ofs, len); 1756 1756 + return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len); 1829 1757 } 1830 1758 EXPORT_SYMBOL_GPL(mtd_unlock); 1831 1759 1832 1760 int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1833 1761 { 1834 1834 - if (!mtd->_is_locked) 1762 1762 + struct mtd_info *master = mtd_get_master(mtd); 1763 1763 + 1764 1764 + if (!master->_is_locked) 1835 1765 return -EOPNOTSUPP; 1836 1766 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) 1837 1767 return -EINVAL; 1838 1768 if (!len) 1839 1769 return 0; 1840 1840 - return mtd->_is_locked(mtd, ofs, len); 1770 1770 + return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len); 1841 1771 } 1842 1772 EXPORT_SYMBOL_GPL(mtd_is_locked); 1843 1773 1844 1774 int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs) 1845 1775 { 1776 1776 + struct mtd_info *master = mtd_get_master(mtd); 1777 1777 + 1846 1778 if (ofs < 0 || ofs >= mtd->size) 1847 1779 return -EINVAL; 1848 1848 - if (!mtd->_block_isreserved) 1780 1780 + if (!master->_block_isreserved) 1849 1781 return 0; 1850 1850 - return mtd->_block_isreserved(mtd, ofs); 1782 1782 + return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs)); 1851 1783 } 1852 1784 EXPORT_SYMBOL_GPL(mtd_block_isreserved); 1853 1785 1854 1786 int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) 1855 1787 { 1788 1788 + struct mtd_info *master = mtd_get_master(mtd); 1789 1789 + 1856 1790 if (ofs < 0 || ofs >= mtd->size) 1857 1791 return -EINVAL; 1858 1858 - if (!mtd->_block_isbad) 1792 1792 + if (!master->_block_isbad) 1859 1793 return 0; 1860 1860 - return mtd->_block_isbad(mtd, ofs); 1794 1794 + return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs)); 1861 1795 } 1862 1796 EXPORT_SYMBOL_GPL(mtd_block_isbad); 1863 1797 1864 1798 int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) 1865 1799 { 1866 1866 - if (!mtd->_block_markbad) 1800 1800 + struct mtd_info *master = mtd_get_master(mtd); 1801 1801 + int ret; 1802 1802 + 1803 1803 + if (!master->_block_markbad) 1867 1804 return -EOPNOTSUPP; 1868 1805 if (ofs < 0 || ofs >= mtd->size) 1869 1806 return -EINVAL; 1870 1807 if (!(mtd->flags & MTD_WRITEABLE)) 1871 1808 return -EROFS; 1872 1872 - return mtd->_block_markbad(mtd, ofs); 1809 1809 + 1810 1810 + ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs)); 1811 1811 + if (ret) 1812 1812 + return ret; 1813 1813 + 1814 1814 + while (mtd->parent) { 1815 1815 + mtd->ecc_stats.badblocks++; 1816 1816 + mtd = mtd->parent; 1817 1817 + } 1818 1818 + 1819 1819 + return 0; 1873 1820 } 1874 1821 EXPORT_SYMBOL_GPL(mtd_block_markbad); 1875 1822 ··· 1944 1841 int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, 1945 1842 unsigned long count, loff_t to, size_t *retlen) 1946 1843 { 1844 1844 + struct mtd_info *master = mtd_get_master(mtd); 1845 1845 + 1947 1846 *retlen = 0; 1948 1847 if (!(mtd->flags & MTD_WRITEABLE)) 1949 1848 return -EROFS; 1950 1950 - if (!mtd->_writev) 1849 1849 + 1850 1850 + if (!master->_writev) 1951 1851 return default_mtd_writev(mtd, vecs, count, to, retlen); 1952 1952 - return mtd->_writev(mtd, vecs, count, to, retlen); 1852 1852 + 1853 1853 + return master->_writev(master, vecs, count, 1854 1854 + mtd_get_master_ofs(mtd, to), retlen); 1953 1855 } 1954 1856 EXPORT_SYMBOL_GPL(mtd_writev); 1955 1857

+176 -517

drivers/mtd/mtdpart.c

reviewed

··· 20 20 21 21 #include "mtdcore.h" 22 22 23 23 - /* Our partition linked list */ 24 24 - static LIST_HEAD(mtd_partitions); 25 25 - static DEFINE_MUTEX(mtd_partitions_mutex); 26 26 - 27 27 - /** 28 28 - * struct mtd_part - our partition node structure 29 29 - * 30 30 - * @mtd: struct holding partition details 31 31 - * @parent: parent mtd - flash device or another partition 32 32 - * @offset: partition offset relative to the *flash device* 33 33 - */ 34 34 - struct mtd_part { 35 35 - struct mtd_info mtd; 36 36 - struct mtd_info *parent; 37 37 - uint64_t offset; 38 38 - struct list_head list; 39 39 - }; 40 40 - 41 41 - /* 42 42 - * Given a pointer to the MTD object in the mtd_part structure, we can retrieve 43 43 - * the pointer to that structure. 44 44 - */ 45 45 - static inline struct mtd_part *mtd_to_part(const struct mtd_info *mtd) 46 46 - { 47 47 - return container_of(mtd, struct mtd_part, mtd); 48 48 - } 49 49 - 50 50 - static u64 part_absolute_offset(struct mtd_info *mtd) 51 51 - { 52 52 - struct mtd_part *part = mtd_to_part(mtd); 53 53 - 54 54 - if (!mtd_is_partition(mtd)) 55 55 - return 0; 56 56 - 57 57 - return part_absolute_offset(part->parent) + part->offset; 58 58 - } 59 59 - 60 23 /* 61 24 * MTD methods which simply translate the effective address and pass through 62 25 * to the _real_ device. 63 26 */ 64 27 65 65 - static int part_read(struct mtd_info *mtd, loff_t from, size_t len, 66 66 - size_t *retlen, u_char *buf) 28 28 + static inline void free_partition(struct mtd_info *mtd) 67 29 { 68 68 - struct mtd_part *part = mtd_to_part(mtd); 69 69 - struct mtd_ecc_stats stats; 70 70 - int res; 71 71 - 72 72 - stats = part->parent->ecc_stats; 73 73 - res = part->parent->_read(part->parent, from + part->offset, len, 74 74 - retlen, buf); 75 75 - if (unlikely(mtd_is_eccerr(res))) 76 76 - mtd->ecc_stats.failed += 77 77 - part->parent->ecc_stats.failed - stats.failed; 78 78 - else 79 79 - mtd->ecc_stats.corrected += 80 80 - part->parent->ecc_stats.corrected - stats.corrected; 81 81 - return res; 30 30 + kfree(mtd->name); 31 31 + kfree(mtd); 82 32 } 83 33 84 84 - static int part_point(struct mtd_info *mtd, loff_t from, size_t len, 85 85 - size_t *retlen, void **virt, resource_size_t *phys) 86 86 - { 87 87 - struct mtd_part *part = mtd_to_part(mtd); 88 88 - 89 89 - return part->parent->_point(part->parent, from + part->offset, len, 90 90 - retlen, virt, phys); 91 91 - } 92 92 - 93 93 - static int part_unpoint(struct mtd_info *mtd, loff_t from, size_t len) 94 94 - { 95 95 - struct mtd_part *part = mtd_to_part(mtd); 96 96 - 97 97 - return part->parent->_unpoint(part->parent, from + part->offset, len); 98 98 - } 99 99 - 100 100 - static int part_read_oob(struct mtd_info *mtd, loff_t from, 101 101 - struct mtd_oob_ops *ops) 102 102 - { 103 103 - struct mtd_part *part = mtd_to_part(mtd); 104 104 - struct mtd_ecc_stats stats; 105 105 - int res; 106 106 - 107 107 - stats = part->parent->ecc_stats; 108 108 - res = part->parent->_read_oob(part->parent, from + part->offset, ops); 109 109 - if (unlikely(mtd_is_eccerr(res))) 110 110 - mtd->ecc_stats.failed += 111 111 - part->parent->ecc_stats.failed - stats.failed; 112 112 - else 113 113 - mtd->ecc_stats.corrected += 114 114 - part->parent->ecc_stats.corrected - stats.corrected; 115 115 - return res; 116 116 - } 117 117 - 118 118 - static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from, 119 119 - size_t len, size_t *retlen, u_char *buf) 120 120 - { 121 121 - struct mtd_part *part = mtd_to_part(mtd); 122 122 - return part->parent->_read_user_prot_reg(part->parent, from, len, 123 123 - retlen, buf); 124 124 - } 125 125 - 126 126 - static int part_get_user_prot_info(struct mtd_info *mtd, size_t len, 127 127 - size_t *retlen, struct otp_info *buf) 128 128 - { 129 129 - struct mtd_part *part = mtd_to_part(mtd); 130 130 - return part->parent->_get_user_prot_info(part->parent, len, retlen, 131 131 - buf); 132 132 - } 133 133 - 134 134 - static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, 135 135 - size_t len, size_t *retlen, u_char *buf) 136 136 - { 137 137 - struct mtd_part *part = mtd_to_part(mtd); 138 138 - return part->parent->_read_fact_prot_reg(part->parent, from, len, 139 139 - retlen, buf); 140 140 - } 141 141 - 142 142 - static int part_get_fact_prot_info(struct mtd_info *mtd, size_t len, 143 143 - size_t *retlen, struct otp_info *buf) 144 144 - { 145 145 - struct mtd_part *part = mtd_to_part(mtd); 146 146 - return part->parent->_get_fact_prot_info(part->parent, len, retlen, 147 147 - buf); 148 148 - } 149 149 - 150 150 - static int part_write(struct mtd_info *mtd, loff_t to, size_t len, 151 151 - size_t *retlen, const u_char *buf) 152 152 - { 153 153 - struct mtd_part *part = mtd_to_part(mtd); 154 154 - return part->parent->_write(part->parent, to + part->offset, len, 155 155 - retlen, buf); 156 156 - } 157 157 - 158 158 - static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 159 159 - size_t *retlen, const u_char *buf) 160 160 - { 161 161 - struct mtd_part *part = mtd_to_part(mtd); 162 162 - return part->parent->_panic_write(part->parent, to + part->offset, len, 163 163 - retlen, buf); 164 164 - } 165 165 - 166 166 - static int part_write_oob(struct mtd_info *mtd, loff_t to, 167 167 - struct mtd_oob_ops *ops) 168 168 - { 169 169 - struct mtd_part *part = mtd_to_part(mtd); 170 170 - 171 171 - return part->parent->_write_oob(part->parent, to + part->offset, ops); 172 172 - } 173 173 - 174 174 - static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from, 175 175 - size_t len, size_t *retlen, u_char *buf) 176 176 - { 177 177 - struct mtd_part *part = mtd_to_part(mtd); 178 178 - return part->parent->_write_user_prot_reg(part->parent, from, len, 179 179 - retlen, buf); 180 180 - } 181 181 - 182 182 - static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, 183 183 - size_t len) 184 184 - { 185 185 - struct mtd_part *part = mtd_to_part(mtd); 186 186 - return part->parent->_lock_user_prot_reg(part->parent, from, len); 187 187 - } 188 188 - 189 189 - static int part_writev(struct mtd_info *mtd, const struct kvec *vecs, 190 190 - unsigned long count, loff_t to, size_t *retlen) 191 191 - { 192 192 - struct mtd_part *part = mtd_to_part(mtd); 193 193 - return part->parent->_writev(part->parent, vecs, count, 194 194 - to + part->offset, retlen); 195 195 - } 196 196 - 197 197 - static int part_erase(struct mtd_info *mtd, struct erase_info *instr) 198 198 - { 199 199 - struct mtd_part *part = mtd_to_part(mtd); 200 200 - int ret; 201 201 - 202 202 - instr->addr += part->offset; 203 203 - ret = part->parent->_erase(part->parent, instr); 204 204 - if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) 205 205 - instr->fail_addr -= part->offset; 206 206 - instr->addr -= part->offset; 207 207 - 208 208 - return ret; 209 209 - } 210 210 - 211 211 - static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 212 212 - { 213 213 - struct mtd_part *part = mtd_to_part(mtd); 214 214 - return part->parent->_lock(part->parent, ofs + part->offset, len); 215 215 - } 216 216 - 217 217 - static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 218 218 - { 219 219 - struct mtd_part *part = mtd_to_part(mtd); 220 220 - return part->parent->_unlock(part->parent, ofs + part->offset, len); 221 221 - } 222 222 - 223 223 - static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 224 224 - { 225 225 - struct mtd_part *part = mtd_to_part(mtd); 226 226 - return part->parent->_is_locked(part->parent, ofs + part->offset, len); 227 227 - } 228 228 - 229 229 - static void part_sync(struct mtd_info *mtd) 230 230 - { 231 231 - struct mtd_part *part = mtd_to_part(mtd); 232 232 - part->parent->_sync(part->parent); 233 233 - } 234 234 - 235 235 - static int part_suspend(struct mtd_info *mtd) 236 236 - { 237 237 - struct mtd_part *part = mtd_to_part(mtd); 238 238 - return part->parent->_suspend(part->parent); 239 239 - } 240 240 - 241 241 - static void part_resume(struct mtd_info *mtd) 242 242 - { 243 243 - struct mtd_part *part = mtd_to_part(mtd); 244 244 - part->parent->_resume(part->parent); 245 245 - } 246 246 - 247 247 - static int part_block_isreserved(struct mtd_info *mtd, loff_t ofs) 248 248 - { 249 249 - struct mtd_part *part = mtd_to_part(mtd); 250 250 - ofs += part->offset; 251 251 - return part->parent->_block_isreserved(part->parent, ofs); 252 252 - } 253 253 - 254 254 - static int part_block_isbad(struct mtd_info *mtd, loff_t ofs) 255 255 - { 256 256 - struct mtd_part *part = mtd_to_part(mtd); 257 257 - ofs += part->offset; 258 258 - return part->parent->_block_isbad(part->parent, ofs); 259 259 - } 260 260 - 261 261 - static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) 262 262 - { 263 263 - struct mtd_part *part = mtd_to_part(mtd); 264 264 - int res; 265 265 - 266 266 - ofs += part->offset; 267 267 - res = part->parent->_block_markbad(part->parent, ofs); 268 268 - if (!res) 269 269 - mtd->ecc_stats.badblocks++; 270 270 - return res; 271 271 - } 272 272 - 273 273 - static int part_get_device(struct mtd_info *mtd) 274 274 - { 275 275 - struct mtd_part *part = mtd_to_part(mtd); 276 276 - return part->parent->_get_device(part->parent); 277 277 - } 278 278 - 279 279 - static void part_put_device(struct mtd_info *mtd) 280 280 - { 281 281 - struct mtd_part *part = mtd_to_part(mtd); 282 282 - part->parent->_put_device(part->parent); 283 283 - } 284 284 - 285 285 - static int part_ooblayout_ecc(struct mtd_info *mtd, int section, 286 286 - struct mtd_oob_region *oobregion) 287 287 - { 288 288 - struct mtd_part *part = mtd_to_part(mtd); 289 289 - 290 290 - return mtd_ooblayout_ecc(part->parent, section, oobregion); 291 291 - } 292 292 - 293 293 - static int part_ooblayout_free(struct mtd_info *mtd, int section, 294 294 - struct mtd_oob_region *oobregion) 295 295 - { 296 296 - struct mtd_part *part = mtd_to_part(mtd); 297 297 - 298 298 - return mtd_ooblayout_free(part->parent, section, oobregion); 299 299 - } 300 300 - 301 301 - static const struct mtd_ooblayout_ops part_ooblayout_ops = { 302 302 - .ecc = part_ooblayout_ecc, 303 303 - .free = part_ooblayout_free, 304 304 - }; 305 305 - 306 306 - static int part_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) 307 307 - { 308 308 - struct mtd_part *part = mtd_to_part(mtd); 309 309 - 310 310 - return part->parent->_max_bad_blocks(part->parent, 311 311 - ofs + part->offset, len); 312 312 - } 313 313 - 314 314 - static inline void free_partition(struct mtd_part *p) 315 315 - { 316 316 - kfree(p->mtd.name); 317 317 - kfree(p); 318 318 - } 319 319 - 320 320 - static struct mtd_part *allocate_partition(struct mtd_info *parent, 321 321 - const struct mtd_partition *part, int partno, 322 322 - uint64_t cur_offset) 34 34 + static struct mtd_info *allocate_partition(struct mtd_info *parent, 35 35 + const struct mtd_partition *part, 36 36 + int partno, uint64_t cur_offset) 323 37 { 324 38 int wr_alignment = (parent->flags & MTD_NO_ERASE) ? parent->writesize : 325 39 parent->erasesize; 326 326 - struct mtd_part *slave; 40 40 + struct mtd_info *child, *master = mtd_get_master(parent); 327 41 u32 remainder; 328 42 char *name; 329 43 u64 tmp; 330 44 331 45 /* allocate the partition structure */ 332 332 - slave = kzalloc(sizeof(*slave), GFP_KERNEL); 46 46 + child = kzalloc(sizeof(*child), GFP_KERNEL); 333 47 name = kstrdup(part->name, GFP_KERNEL); 334 334 - if (!name || !slave) { 48 48 + if (!name || !child) { 335 49 printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n", 336 50 parent->name); 337 51 kfree(name); 338 338 - kfree(slave); 52 52 + kfree(child); 339 53 return ERR_PTR(-ENOMEM); 340 54 } 341 55 342 56 /* set up the MTD object for this partition */ 343 343 - slave->mtd.type = parent->type; 344 344 - slave->mtd.flags = parent->orig_flags & ~part->mask_flags; 345 345 - slave->mtd.orig_flags = slave->mtd.flags; 346 346 - slave->mtd.size = part->size; 347 347 - slave->mtd.writesize = parent->writesize; 348 348 - slave->mtd.writebufsize = parent->writebufsize; 349 349 - slave->mtd.oobsize = parent->oobsize; 350 350 - slave->mtd.oobavail = parent->oobavail; 351 351 - slave->mtd.subpage_sft = parent->subpage_sft; 352 352 - slave->mtd.pairing = parent->pairing; 57 57 + child->type = parent->type; 58 58 + child->part.flags = parent->flags & ~part->mask_flags; 59 59 + child->flags = child->part.flags; 60 60 + child->size = part->size; 61 61 + child->writesize = parent->writesize; 62 62 + child->writebufsize = parent->writebufsize; 63 63 + child->oobsize = parent->oobsize; 64 64 + child->oobavail = parent->oobavail; 65 65 + child->subpage_sft = parent->subpage_sft; 353 66 354 354 - slave->mtd.name = name; 355 355 - slave->mtd.owner = parent->owner; 67 67 + child->name = name; 68 68 + child->owner = parent->owner; 356 69 357 70 /* NOTE: Historically, we didn't arrange MTDs as a tree out of 358 71 * concern for showing the same data in multiple partitions. ··· 73 360 * so the MTD_PARTITIONED_MASTER option allows that. The master 74 361 * will have device nodes etc only if this is set, so make the 75 362 * parent conditional on that option. Note, this is a way to 76 76 - * distinguish between the master and the partition in sysfs. 363 363 + * distinguish between the parent and its partitions in sysfs. 77 364 */ 78 78 - slave->mtd.dev.parent = IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd_is_partition(parent) ? 79 79 - &parent->dev : 80 80 - parent->dev.parent; 81 81 - slave->mtd.dev.of_node = part->of_node; 365 365 + child->dev.parent = IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd_is_partition(parent) ? 366 366 + &parent->dev : parent->dev.parent; 367 367 + child->dev.of_node = part->of_node; 368 368 + child->parent = parent; 369 369 + child->part.offset = part->offset; 370 370 + INIT_LIST_HEAD(&child->partitions); 82 371 83 83 - if (parent->_read) 84 84 - slave->mtd._read = part_read; 85 85 - if (parent->_write) 86 86 - slave->mtd._write = part_write; 87 87 - 88 88 - if (parent->_panic_write) 89 89 - slave->mtd._panic_write = part_panic_write; 90 90 - 91 91 - if (parent->_point && parent->_unpoint) { 92 92 - slave->mtd._point = part_point; 93 93 - slave->mtd._unpoint = part_unpoint; 94 94 - } 95 95 - 96 96 - if (parent->_read_oob) 97 97 - slave->mtd._read_oob = part_read_oob; 98 98 - if (parent->_write_oob) 99 99 - slave->mtd._write_oob = part_write_oob; 100 100 - if (parent->_read_user_prot_reg) 101 101 - slave->mtd._read_user_prot_reg = part_read_user_prot_reg; 102 102 - if (parent->_read_fact_prot_reg) 103 103 - slave->mtd._read_fact_prot_reg = part_read_fact_prot_reg; 104 104 - if (parent->_write_user_prot_reg) 105 105 - slave->mtd._write_user_prot_reg = part_write_user_prot_reg; 106 106 - if (parent->_lock_user_prot_reg) 107 107 - slave->mtd._lock_user_prot_reg = part_lock_user_prot_reg; 108 108 - if (parent->_get_user_prot_info) 109 109 - slave->mtd._get_user_prot_info = part_get_user_prot_info; 110 110 - if (parent->_get_fact_prot_info) 111 111 - slave->mtd._get_fact_prot_info = part_get_fact_prot_info; 112 112 - if (parent->_sync) 113 113 - slave->mtd._sync = part_sync; 114 114 - if (!partno && !parent->dev.class && parent->_suspend && 115 115 - parent->_resume) { 116 116 - slave->mtd._suspend = part_suspend; 117 117 - slave->mtd._resume = part_resume; 118 118 - } 119 119 - if (parent->_writev) 120 120 - slave->mtd._writev = part_writev; 121 121 - if (parent->_lock) 122 122 - slave->mtd._lock = part_lock; 123 123 - if (parent->_unlock) 124 124 - slave->mtd._unlock = part_unlock; 125 125 - if (parent->_is_locked) 126 126 - slave->mtd._is_locked = part_is_locked; 127 127 - if (parent->_block_isreserved) 128 128 - slave->mtd._block_isreserved = part_block_isreserved; 129 129 - if (parent->_block_isbad) 130 130 - slave->mtd._block_isbad = part_block_isbad; 131 131 - if (parent->_block_markbad) 132 132 - slave->mtd._block_markbad = part_block_markbad; 133 133 - if (parent->_max_bad_blocks) 134 134 - slave->mtd._max_bad_blocks = part_max_bad_blocks; 135 135 - 136 136 - if (parent->_get_device) 137 137 - slave->mtd._get_device = part_get_device; 138 138 - if (parent->_put_device) 139 139 - slave->mtd._put_device = part_put_device; 140 140 - 141 141 - slave->mtd._erase = part_erase; 142 142 - slave->parent = parent; 143 143 - slave->offset = part->offset; 144 144 - 145 145 - if (slave->offset == MTDPART_OFS_APPEND) 146 146 - slave->offset = cur_offset; 147 147 - if (slave->offset == MTDPART_OFS_NXTBLK) { 372 372 + if (child->part.offset == MTDPART_OFS_APPEND) 373 373 + child->part.offset = cur_offset; 374 374 + if (child->part.offset == MTDPART_OFS_NXTBLK) { 148 375 tmp = cur_offset; 149 149 - slave->offset = cur_offset; 376 376 + child->part.offset = cur_offset; 150 377 remainder = do_div(tmp, wr_alignment); 151 378 if (remainder) { 152 152 - slave->offset += wr_alignment - remainder; 379 379 + child->part.offset += wr_alignment - remainder; 153 380 printk(KERN_NOTICE "Moving partition %d: " 154 381 "0x%012llx -> 0x%012llx\n", partno, 155 155 - (unsigned long long)cur_offset, (unsigned long long)slave->offset); 382 382 + (unsigned long long)cur_offset, 383 383 + child->part.offset); 156 384 } 157 385 } 158 158 - if (slave->offset == MTDPART_OFS_RETAIN) { 159 159 - slave->offset = cur_offset; 160 160 - if (parent->size - slave->offset >= slave->mtd.size) { 161 161 - slave->mtd.size = parent->size - slave->offset 162 162 - - slave->mtd.size; 386 386 + if (child->part.offset == MTDPART_OFS_RETAIN) { 387 387 + child->part.offset = cur_offset; 388 388 + if (parent->size - child->part.offset >= child->size) { 389 389 + child->size = parent->size - child->part.offset - 390 390 + child->size; 163 391 } else { 164 392 printk(KERN_ERR "mtd partition \"%s\" doesn't have enough space: %#llx < %#llx, disabled\n", 165 165 - part->name, parent->size - slave->offset, 166 166 - slave->mtd.size); 393 393 + part->name, parent->size - child->part.offset, 394 394 + child->size); 167 395 /* register to preserve ordering */ 168 396 goto out_register; 169 397 } 170 398 } 171 171 - if (slave->mtd.size == MTDPART_SIZ_FULL) 172 172 - slave->mtd.size = parent->size - slave->offset; 399 399 + if (child->size == MTDPART_SIZ_FULL) 400 400 + child->size = parent->size - child->part.offset; 173 401 174 174 - printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset, 175 175 - (unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name); 402 402 + printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", 403 403 + child->part.offset, child->part.offset + child->size, 404 404 + child->name); 176 405 177 406 /* let's do some sanity checks */ 178 178 - if (slave->offset >= parent->size) { 407 407 + if (child->part.offset >= parent->size) { 179 408 /* let's register it anyway to preserve ordering */ 180 180 - slave->offset = 0; 181 181 - slave->mtd.size = 0; 409 409 + child->part.offset = 0; 410 410 + child->size = 0; 182 411 183 412 /* Initialize ->erasesize to make add_mtd_device() happy. */ 184 184 - slave->mtd.erasesize = parent->erasesize; 185 185 - 413 413 + child->erasesize = parent->erasesize; 186 414 printk(KERN_ERR"mtd: partition \"%s\" is out of reach -- disabled\n", 187 415 part->name); 188 416 goto out_register; 189 417 } 190 190 - if (slave->offset + slave->mtd.size > parent->size) { 191 191 - slave->mtd.size = parent->size - slave->offset; 418 418 + if (child->part.offset + child->size > parent->size) { 419 419 + child->size = parent->size - child->part.offset; 192 420 printk(KERN_WARNING"mtd: partition \"%s\" extends beyond the end of device \"%s\" -- size truncated to %#llx\n", 193 193 - part->name, parent->name, (unsigned long long)slave->mtd.size); 421 421 + part->name, parent->name, child->size); 194 422 } 195 423 if (parent->numeraseregions > 1) { 196 424 /* Deal with variable erase size stuff */ 197 425 int i, max = parent->numeraseregions; 198 198 - u64 end = slave->offset + slave->mtd.size; 426 426 + u64 end = child->part.offset + child->size; 199 427 struct mtd_erase_region_info *regions = parent->eraseregions; 200 428 201 429 /* Find the first erase regions which is part of this 202 430 * partition. */ 203 203 - for (i = 0; i < max && regions[i].offset <= slave->offset; i++) 431 431 + for (i = 0; i < max && regions[i].offset <= child->part.offset; 432 432 + i++) 204 433 ; 205 434 /* The loop searched for the region _behind_ the first one */ 206 435 if (i > 0) ··· 150 495 151 496 /* Pick biggest erasesize */ 152 497 for (; i < max && regions[i].offset < end; i++) { 153 153 - if (slave->mtd.erasesize < regions[i].erasesize) { 154 154 - slave->mtd.erasesize = regions[i].erasesize; 155 155 - } 498 498 + if (child->erasesize < regions[i].erasesize) 499 499 + child->erasesize = regions[i].erasesize; 156 500 } 157 157 - BUG_ON(slave->mtd.erasesize == 0); 501 501 + BUG_ON(child->erasesize == 0); 158 502 } else { 159 503 /* Single erase size */ 160 160 - slave->mtd.erasesize = parent->erasesize; 504 504 + child->erasesize = parent->erasesize; 161 505 } 162 506 163 507 /* 164 164 - * Slave erasesize might differ from the master one if the master 508 508 + * Child erasesize might differ from the parent one if the parent 165 509 * exposes several regions with different erasesize. Adjust 166 510 * wr_alignment accordingly. 167 511 */ 168 168 - if (!(slave->mtd.flags & MTD_NO_ERASE)) 169 169 - wr_alignment = slave->mtd.erasesize; 512 512 + if (!(child->flags & MTD_NO_ERASE)) 513 513 + wr_alignment = child->erasesize; 170 514 171 171 - tmp = part_absolute_offset(parent) + slave->offset; 515 515 + tmp = mtd_get_master_ofs(child, 0); 172 516 remainder = do_div(tmp, wr_alignment); 173 173 - if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) { 517 517 + if ((child->flags & MTD_WRITEABLE) && remainder) { 174 518 /* Doesn't start on a boundary of major erase size */ 175 519 /* FIXME: Let it be writable if it is on a boundary of 176 520 * _minor_ erase size though */ 177 177 - slave->mtd.flags &= ~MTD_WRITEABLE; 521 521 + child->flags &= ~MTD_WRITEABLE; 178 522 printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n", 179 523 part->name); 180 524 } 181 525 182 182 - tmp = part_absolute_offset(parent) + slave->mtd.size; 526 526 + tmp = mtd_get_master_ofs(child, 0) + child->size; 183 527 remainder = do_div(tmp, wr_alignment); 184 184 - if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) { 185 185 - slave->mtd.flags &= ~MTD_WRITEABLE; 528 528 + if ((child->flags & MTD_WRITEABLE) && remainder) { 529 529 + child->flags &= ~MTD_WRITEABLE; 186 530 printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n", 187 531 part->name); 188 532 } 189 533 190 190 - mtd_set_ooblayout(&slave->mtd, &part_ooblayout_ops); 191 191 - slave->mtd.ecc_step_size = parent->ecc_step_size; 192 192 - slave->mtd.ecc_strength = parent->ecc_strength; 193 193 - slave->mtd.bitflip_threshold = parent->bitflip_threshold; 534 534 + child->ecc_step_size = parent->ecc_step_size; 535 535 + child->ecc_strength = parent->ecc_strength; 536 536 + child->bitflip_threshold = parent->bitflip_threshold; 194 537 195 195 - if (parent->_block_isbad) { 538 538 + if (master->_block_isbad) { 196 539 uint64_t offs = 0; 197 540 198 198 - while (offs < slave->mtd.size) { 199 199 - if (mtd_block_isreserved(parent, offs + slave->offset)) 200 200 - slave->mtd.ecc_stats.bbtblocks++; 201 201 - else if (mtd_block_isbad(parent, offs + slave->offset)) 202 202 - slave->mtd.ecc_stats.badblocks++; 203 203 - offs += slave->mtd.erasesize; 541 541 + while (offs < child->size) { 542 542 + if (mtd_block_isreserved(child, offs)) 543 543 + child->ecc_stats.bbtblocks++; 544 544 + else if (mtd_block_isbad(child, offs)) 545 545 + child->ecc_stats.badblocks++; 546 546 + offs += child->erasesize; 204 547 } 205 548 } 206 549 207 550 out_register: 208 208 - return slave; 551 551 + return child; 209 552 } 210 553 211 554 static ssize_t mtd_partition_offset_show(struct device *dev, 212 555 struct device_attribute *attr, char *buf) 213 556 { 214 557 struct mtd_info *mtd = dev_get_drvdata(dev); 215 215 - struct mtd_part *part = mtd_to_part(mtd); 216 216 - return snprintf(buf, PAGE_SIZE, "%llu\n", part->offset); 558 558 + 559 559 + return snprintf(buf, PAGE_SIZE, "%lld\n", mtd->part.offset); 217 560 } 218 561 219 562 static DEVICE_ATTR(offset, S_IRUGO, mtd_partition_offset_show, NULL); ··· 221 568 NULL 222 569 }; 223 570 224 224 - static int mtd_add_partition_attrs(struct mtd_part *new) 571 571 + static int mtd_add_partition_attrs(struct mtd_info *new) 225 572 { 226 226 - int ret = sysfs_create_files(&new->mtd.dev.kobj, mtd_partition_attrs); 573 573 + int ret = sysfs_create_files(&new->dev.kobj, mtd_partition_attrs); 227 574 if (ret) 228 575 printk(KERN_WARNING 229 576 "mtd: failed to create partition attrs, err=%d\n", ret); ··· 233 580 int mtd_add_partition(struct mtd_info *parent, const char *name, 234 581 long long offset, long long length) 235 582 { 583 583 + struct mtd_info *master = mtd_get_master(parent); 236 584 struct mtd_partition part; 237 237 - struct mtd_part *new; 585 585 + struct mtd_info *child; 238 586 int ret = 0; 239 587 240 588 /* the direct offset is expected */ ··· 254 600 part.size = length; 255 601 part.offset = offset; 256 602 257 257 - new = allocate_partition(parent, &part, -1, offset); 258 258 - if (IS_ERR(new)) 259 259 - return PTR_ERR(new); 603 603 + child = allocate_partition(parent, &part, -1, offset); 604 604 + if (IS_ERR(child)) 605 605 + return PTR_ERR(child); 260 606 261 261 - mutex_lock(&mtd_partitions_mutex); 262 262 - list_add(&new->list, &mtd_partitions); 263 263 - mutex_unlock(&mtd_partitions_mutex); 607 607 + mutex_lock(&master->master.partitions_lock); 608 608 + list_add_tail(&child->part.node, &parent->partitions); 609 609 + mutex_unlock(&master->master.partitions_lock); 264 610 265 265 - ret = add_mtd_device(&new->mtd); 611 611 + ret = add_mtd_device(child); 266 612 if (ret) 267 613 goto err_remove_part; 268 614 269 269 - mtd_add_partition_attrs(new); 615 615 + mtd_add_partition_attrs(child); 270 616 271 617 return 0; 272 618 273 619 err_remove_part: 274 274 - mutex_lock(&mtd_partitions_mutex); 275 275 - list_del(&new->list); 276 276 - mutex_unlock(&mtd_partitions_mutex); 620 620 + mutex_lock(&master->master.partitions_lock); 621 621 + list_del(&child->part.node); 622 622 + mutex_unlock(&master->master.partitions_lock); 277 623 278 278 - free_partition(new); 624 624 + free_partition(child); 279 625 280 626 return ret; 281 627 } ··· 284 630 /** 285 631 * __mtd_del_partition - delete MTD partition 286 632 * 287 287 - * @priv: internal MTD struct for partition to be deleted 633 633 + * @priv: MTD structure to be deleted 288 634 * 289 635 * This function must be called with the partitions mutex locked. 290 636 */ 291 291 - static int __mtd_del_partition(struct mtd_part *priv) 637 637 + static int __mtd_del_partition(struct mtd_info *mtd) 292 638 { 293 293 - struct mtd_part *child, *next; 639 639 + struct mtd_info *child, *next; 294 640 int err; 295 641 296 296 - list_for_each_entry_safe(child, next, &mtd_partitions, list) { 297 297 - if (child->parent == &priv->mtd) { 298 298 - err = __mtd_del_partition(child); 299 299 - if (err) 300 300 - return err; 301 301 - } 642 642 + list_for_each_entry_safe(child, next, &mtd->partitions, part.node) { 643 643 + err = __mtd_del_partition(child); 644 644 + if (err) 645 645 + return err; 302 646 } 303 647 304 304 - sysfs_remove_files(&priv->mtd.dev.kobj, mtd_partition_attrs); 648 648 + sysfs_remove_files(&mtd->dev.kobj, mtd_partition_attrs); 305 649 306 306 - err = del_mtd_device(&priv->mtd); 650 650 + err = del_mtd_device(mtd); 307 651 if (err) 308 652 return err; 309 653 310 310 - list_del(&priv->list); 311 311 - free_partition(priv); 654 654 + list_del(&child->part.node); 655 655 + free_partition(mtd); 312 656 313 657 return 0; 314 658 } 315 659 316 660 /* 317 661 * This function unregisters and destroy all slave MTD objects which are 318 318 - * attached to the given MTD object. 662 662 + * attached to the given MTD object, recursively. 319 663 */ 320 320 - int del_mtd_partitions(struct mtd_info *mtd) 664 664 + static int __del_mtd_partitions(struct mtd_info *mtd) 321 665 { 322 322 - struct mtd_part *slave, *next; 666 666 + struct mtd_info *child, *next; 667 667 + LIST_HEAD(tmp_list); 323 668 int ret, err = 0; 324 669 325 325 - mutex_lock(&mtd_partitions_mutex); 326 326 - list_for_each_entry_safe(slave, next, &mtd_partitions, list) 327 327 - if (slave->parent == mtd) { 328 328 - ret = __mtd_del_partition(slave); 329 329 - if (ret < 0) 330 330 - err = ret; 670 670 + list_for_each_entry_safe(child, next, &mtd->partitions, part.node) { 671 671 + if (mtd_has_partitions(child)) 672 672 + del_mtd_partitions(child); 673 673 + 674 674 + pr_info("Deleting %s MTD partition\n", child->name); 675 675 + ret = del_mtd_device(child); 676 676 + if (ret < 0) { 677 677 + pr_err("Error when deleting partition \"%s\" (%d)\n", 678 678 + child->name, ret); 679 679 + err = ret; 680 680 + continue; 331 681 } 332 332 - mutex_unlock(&mtd_partitions_mutex); 682 682 + 683 683 + list_del(&child->part.node); 684 684 + free_partition(child); 685 685 + } 333 686 334 687 return err; 335 688 } 336 689 690 690 + int del_mtd_partitions(struct mtd_info *mtd) 691 691 + { 692 692 + struct mtd_info *master = mtd_get_master(mtd); 693 693 + int ret; 694 694 + 695 695 + pr_info("Deleting MTD partitions on \"%s\":\n", mtd->name); 696 696 + 697 697 + mutex_lock(&master->master.partitions_lock); 698 698 + ret = __del_mtd_partitions(mtd); 699 699 + mutex_unlock(&master->master.partitions_lock); 700 700 + 701 701 + return ret; 702 702 + } 703 703 + 337 704 int mtd_del_partition(struct mtd_info *mtd, int partno) 338 705 { 339 339 - struct mtd_part *slave, *next; 706 706 + struct mtd_info *child, *master = mtd_get_master(mtd); 340 707 int ret = -EINVAL; 341 708 342 342 - mutex_lock(&mtd_partitions_mutex); 343 343 - list_for_each_entry_safe(slave, next, &mtd_partitions, list) 344 344 - if ((slave->parent == mtd) && 345 345 - (slave->mtd.index == partno)) { 346 346 - ret = __mtd_del_partition(slave); 709 709 + mutex_lock(&master->master.partitions_lock); 710 710 + list_for_each_entry(child, &mtd->partitions, part.node) { 711 711 + if (child->index == partno) { 712 712 + ret = __mtd_del_partition(child); 347 713 break; 348 714 } 349 349 - mutex_unlock(&mtd_partitions_mutex); 715 715 + } 716 716 + mutex_unlock(&master->master.partitions_lock); 350 717 351 718 return ret; 352 719 } 353 720 EXPORT_SYMBOL_GPL(mtd_del_partition); 354 721 355 722 /* 356 356 - * This function, given a master MTD object and a partition table, creates 357 357 - * and registers slave MTD objects which are bound to the master according to 358 358 - * the partition definitions. 723 723 + * This function, given a parent MTD object and a partition table, creates 724 724 + * and registers the child MTD objects which are bound to the parent according 725 725 + * to the partition definitions. 359 726 * 360 360 - * For historical reasons, this function's caller only registers the master 727 727 + * For historical reasons, this function's caller only registers the parent 361 728 * if the MTD_PARTITIONED_MASTER config option is set. 362 729 */ 363 730 364 364 - int add_mtd_partitions(struct mtd_info *master, 731 731 + int add_mtd_partitions(struct mtd_info *parent, 365 732 const struct mtd_partition *parts, 366 733 int nbparts) 367 734 { 368 368 - struct mtd_part *slave; 735 735 + struct mtd_info *child, *master = mtd_get_master(parent); 369 736 uint64_t cur_offset = 0; 370 737 int i, ret; 371 738 372 372 - printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); 739 739 + printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", 740 740 + nbparts, parent->name); 373 741 374 742 for (i = 0; i < nbparts; i++) { 375 375 - slave = allocate_partition(master, parts + i, i, cur_offset); 376 376 - if (IS_ERR(slave)) { 377 377 - ret = PTR_ERR(slave); 743 743 + child = allocate_partition(parent, parts + i, i, cur_offset); 744 744 + if (IS_ERR(child)) { 745 745 + ret = PTR_ERR(child); 378 746 goto err_del_partitions; 379 747 } 380 748 381 381 - mutex_lock(&mtd_partitions_mutex); 382 382 - list_add(&slave->list, &mtd_partitions); 383 383 - mutex_unlock(&mtd_partitions_mutex); 749 749 + mutex_lock(&master->master.partitions_lock); 750 750 + list_add_tail(&child->part.node, &parent->partitions); 751 751 + mutex_unlock(&master->master.partitions_lock); 384 752 385 385 - ret = add_mtd_device(&slave->mtd); 753 753 + ret = add_mtd_device(child); 386 754 if (ret) { 387 387 - mutex_lock(&mtd_partitions_mutex); 388 388 - list_del(&slave->list); 389 389 - mutex_unlock(&mtd_partitions_mutex); 755 755 + mutex_lock(&master->master.partitions_lock); 756 756 + list_del(&child->part.node); 757 757 + mutex_unlock(&master->master.partitions_lock); 390 758 391 391 - free_partition(slave); 759 759 + free_partition(child); 392 760 goto err_del_partitions; 393 761 } 394 762 395 395 - mtd_add_partition_attrs(slave); 396 396 - /* Look for subpartitions */ 397 397 - parse_mtd_partitions(&slave->mtd, parts[i].types, NULL); 763 763 + mtd_add_partition_attrs(child); 398 764 399 399 - cur_offset = slave->offset + slave->mtd.size; 765 765 + /* Look for subpartitions */ 766 766 + parse_mtd_partitions(child, parts[i].types, NULL); 767 767 + 768 768 + cur_offset = child->part.offset + child->size; 400 769 } 401 770 402 771 return 0; ··· 700 1023 } 701 1024 } 702 1025 703 703 - int mtd_is_partition(const struct mtd_info *mtd) 704 704 - { 705 705 - struct mtd_part *part; 706 706 - int ispart = 0; 707 707 - 708 708 - mutex_lock(&mtd_partitions_mutex); 709 709 - list_for_each_entry(part, &mtd_partitions, list) 710 710 - if (&part->mtd == mtd) { 711 711 - ispart = 1; 712 712 - break; 713 713 - } 714 714 - mutex_unlock(&mtd_partitions_mutex); 715 715 - 716 716 - return ispart; 717 717 - } 718 718 - EXPORT_SYMBOL_GPL(mtd_is_partition); 719 719 - 720 1026 /* Returns the size of the entire flash chip */ 721 1027 uint64_t mtd_get_device_size(const struct mtd_info *mtd) 722 1028 { 723 723 - if (!mtd_is_partition(mtd)) 724 724 - return mtd->size; 1029 1029 + struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd); 725 1030 726 726 - return mtd_get_device_size(mtd_to_part(mtd)->parent); 1031 1031 + return master->size; 727 1032 } 728 1033 EXPORT_SYMBOL_GPL(mtd_get_device_size);

+1 -1

drivers/mtd/nand/onenand/onenand_base.c

reviewed

··· 3259 3259 switch (density) { 3260 3260 case ONENAND_DEVICE_DENSITY_8Gb: 3261 3261 this->options |= ONENAND_HAS_NOP_1; 3262 3262 - /* fall through */ 3262 3262 + fallthrough; 3263 3263 case ONENAND_DEVICE_DENSITY_4Gb: 3264 3264 if (ONENAND_IS_DDP(this)) 3265 3265 this->options |= ONENAND_HAS_2PLANE;

+155 -82

drivers/mtd/nand/raw/ams-delta.c

reviewed

··· 19 19 #include <linux/delay.h> 20 20 #include <linux/gpio/consumer.h> 21 21 #include <linux/mtd/mtd.h> 22 22 + #include <linux/mtd/nand-gpio.h> 22 23 #include <linux/mtd/rawnand.h> 23 24 #include <linux/mtd/partitions.h> 25 25 + #include <linux/of_device.h> 24 26 #include <linux/platform_device.h> 25 27 #include <linux/sizes.h> 26 28 27 29 /* 28 30 * MTD structure for E3 (Delta) 29 31 */ 30 30 - struct ams_delta_nand { 32 32 + struct gpio_nand { 31 33 struct nand_controller base; 32 34 struct nand_chip nand_chip; 33 35 struct gpio_desc *gpiod_rdy; ··· 41 39 struct gpio_desc *gpiod_cle; 42 40 struct gpio_descs *data_gpiods; 43 41 bool data_in; 42 42 + unsigned int tRP; 43 43 + unsigned int tWP; 44 44 + u8 (*io_read)(struct gpio_nand *this); 45 45 + void (*io_write)(struct gpio_nand *this, u8 byte); 44 46 }; 45 47 46 46 - /* 47 47 - * Define partitions for flash devices 48 48 - */ 49 49 - 50 50 - static const struct mtd_partition partition_info[] = { 51 51 - { .name = "Kernel", 52 52 - .offset = 0, 53 53 - .size = 3 * SZ_1M + SZ_512K }, 54 54 - { .name = "u-boot", 55 55 - .offset = 3 * SZ_1M + SZ_512K, 56 56 - .size = SZ_256K }, 57 57 - { .name = "u-boot params", 58 58 - .offset = 3 * SZ_1M + SZ_512K + SZ_256K, 59 59 - .size = SZ_256K }, 60 60 - { .name = "Amstrad LDR", 61 61 - .offset = 4 * SZ_1M, 62 62 - .size = SZ_256K }, 63 63 - { .name = "File system", 64 64 - .offset = 4 * SZ_1M + 1 * SZ_256K, 65 65 - .size = 27 * SZ_1M }, 66 66 - { .name = "PBL reserved", 67 67 - .offset = 32 * SZ_1M - 3 * SZ_256K, 68 68 - .size = 3 * SZ_256K }, 69 69 - }; 70 70 - 71 71 - static void ams_delta_write_commit(struct ams_delta_nand *priv) 48 48 + static void gpio_nand_write_commit(struct gpio_nand *priv) 72 49 { 73 73 - gpiod_set_value(priv->gpiod_nwe, 0); 74 74 - ndelay(40); 75 50 gpiod_set_value(priv->gpiod_nwe, 1); 51 51 + ndelay(priv->tWP); 52 52 + gpiod_set_value(priv->gpiod_nwe, 0); 76 53 } 77 54 78 78 - static void ams_delta_io_write(struct ams_delta_nand *priv, u8 byte) 55 55 + static void gpio_nand_io_write(struct gpio_nand *priv, u8 byte) 79 56 { 80 57 struct gpio_descs *data_gpiods = priv->data_gpiods; 81 58 DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, }; ··· 62 81 gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc, 63 82 data_gpiods->info, values); 64 83 65 65 - ams_delta_write_commit(priv); 84 84 + gpio_nand_write_commit(priv); 66 85 } 67 86 68 68 - static void ams_delta_dir_output(struct ams_delta_nand *priv, u8 byte) 87 87 + static void gpio_nand_dir_output(struct gpio_nand *priv, u8 byte) 69 88 { 70 89 struct gpio_descs *data_gpiods = priv->data_gpiods; 71 90 DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, }; ··· 75 94 gpiod_direction_output_raw(data_gpiods->desc[i], 76 95 test_bit(i, values)); 77 96 78 78 - ams_delta_write_commit(priv); 97 97 + gpio_nand_write_commit(priv); 79 98 80 99 priv->data_in = false; 81 100 } 82 101 83 83 - static u8 ams_delta_io_read(struct ams_delta_nand *priv) 102 102 + static u8 gpio_nand_io_read(struct gpio_nand *priv) 84 103 { 85 104 u8 res; 86 105 struct gpio_descs *data_gpiods = priv->data_gpiods; 87 106 DECLARE_BITMAP(values, BITS_PER_TYPE(res)) = { 0, }; 88 107 89 89 - gpiod_set_value(priv->gpiod_nre, 0); 90 90 - ndelay(40); 108 108 + gpiod_set_value(priv->gpiod_nre, 1); 109 109 + ndelay(priv->tRP); 91 110 92 111 gpiod_get_raw_array_value(data_gpiods->ndescs, data_gpiods->desc, 93 112 data_gpiods->info, values); 94 113 95 95 - gpiod_set_value(priv->gpiod_nre, 1); 114 114 + gpiod_set_value(priv->gpiod_nre, 0); 96 115 97 116 res = values[0]; 98 117 return res; 99 118 } 100 119 101 101 - static void ams_delta_dir_input(struct ams_delta_nand *priv) 120 120 + static void gpio_nand_dir_input(struct gpio_nand *priv) 102 121 { 103 122 struct gpio_descs *data_gpiods = priv->data_gpiods; 104 123 int i; ··· 109 128 priv->data_in = true; 110 129 } 111 130 112 112 - static void ams_delta_write_buf(struct ams_delta_nand *priv, const u8 *buf, 113 113 - int len) 131 131 + static void gpio_nand_write_buf(struct gpio_nand *priv, const u8 *buf, int len) 114 132 { 115 133 int i = 0; 116 134 117 135 if (len > 0 && priv->data_in) 118 118 - ams_delta_dir_output(priv, buf[i++]); 136 136 + gpio_nand_dir_output(priv, buf[i++]); 119 137 120 138 while (i < len) 121 121 - ams_delta_io_write(priv, buf[i++]); 139 139 + priv->io_write(priv, buf[i++]); 122 140 } 123 141 124 124 - static void ams_delta_read_buf(struct ams_delta_nand *priv, u8 *buf, int len) 142 142 + static void gpio_nand_read_buf(struct gpio_nand *priv, u8 *buf, int len) 125 143 { 126 144 int i; 127 145 128 128 - if (!priv->data_in) 129 129 - ams_delta_dir_input(priv); 146 146 + if (priv->data_gpiods && !priv->data_in) 147 147 + gpio_nand_dir_input(priv); 130 148 131 149 for (i = 0; i < len; i++) 132 132 - buf[i] = ams_delta_io_read(priv); 150 150 + buf[i] = priv->io_read(priv); 133 151 } 134 152 135 135 - static void ams_delta_ctrl_cs(struct ams_delta_nand *priv, bool assert) 153 153 + static void gpio_nand_ctrl_cs(struct gpio_nand *priv, bool assert) 136 154 { 137 137 - gpiod_set_value(priv->gpiod_nce, assert ? 0 : 1); 155 155 + gpiod_set_value(priv->gpiod_nce, assert); 138 156 } 139 157 140 140 - static int ams_delta_exec_op(struct nand_chip *this, 158 158 + static int gpio_nand_exec_op(struct nand_chip *this, 141 159 const struct nand_operation *op, bool check_only) 142 160 { 143 143 - struct ams_delta_nand *priv = nand_get_controller_data(this); 161 161 + struct gpio_nand *priv = nand_get_controller_data(this); 144 162 const struct nand_op_instr *instr; 145 163 int ret = 0; 146 164 147 165 if (check_only) 148 166 return 0; 149 167 150 150 - ams_delta_ctrl_cs(priv, 1); 168 168 + gpio_nand_ctrl_cs(priv, 1); 151 169 152 170 for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) { 153 171 switch (instr->type) { 154 172 case NAND_OP_CMD_INSTR: 155 173 gpiod_set_value(priv->gpiod_cle, 1); 156 156 - ams_delta_write_buf(priv, &instr->ctx.cmd.opcode, 1); 174 174 + gpio_nand_write_buf(priv, &instr->ctx.cmd.opcode, 1); 157 175 gpiod_set_value(priv->gpiod_cle, 0); 158 176 break; 159 177 160 178 case NAND_OP_ADDR_INSTR: 161 179 gpiod_set_value(priv->gpiod_ale, 1); 162 162 - ams_delta_write_buf(priv, instr->ctx.addr.addrs, 180 180 + gpio_nand_write_buf(priv, instr->ctx.addr.addrs, 163 181 instr->ctx.addr.naddrs); 164 182 gpiod_set_value(priv->gpiod_ale, 0); 165 183 break; 166 184 167 185 case NAND_OP_DATA_IN_INSTR: 168 168 - ams_delta_read_buf(priv, instr->ctx.data.buf.in, 186 186 + gpio_nand_read_buf(priv, instr->ctx.data.buf.in, 169 187 instr->ctx.data.len); 170 188 break; 171 189 172 190 case NAND_OP_DATA_OUT_INSTR: 173 173 - ams_delta_write_buf(priv, instr->ctx.data.buf.out, 191 191 + gpio_nand_write_buf(priv, instr->ctx.data.buf.out, 174 192 instr->ctx.data.len); 175 193 break; 176 194 ··· 186 206 break; 187 207 } 188 208 189 189 - ams_delta_ctrl_cs(priv, 0); 209 209 + gpio_nand_ctrl_cs(priv, 0); 190 210 191 211 return ret; 192 212 } 193 213 194 194 - static const struct nand_controller_ops ams_delta_ops = { 195 195 - .exec_op = ams_delta_exec_op, 214 214 + static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline, 215 215 + const struct nand_data_interface *cf) 216 216 + { 217 217 + struct gpio_nand *priv = nand_get_controller_data(this); 218 218 + const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf); 219 219 + struct device *dev = &nand_to_mtd(this)->dev; 220 220 + 221 221 + if (IS_ERR(sdr)) 222 222 + return PTR_ERR(sdr); 223 223 + 224 224 + if (csline == NAND_DATA_IFACE_CHECK_ONLY) 225 225 + return 0; 226 226 + 227 227 + if (priv->gpiod_nre) { 228 228 + priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000); 229 229 + dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP); 230 230 + } 231 231 + 232 232 + priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000); 233 233 + dev_dbg(dev, "using %u ns write pulse width\n", priv->tWP); 234 234 + 235 235 + return 0; 236 236 + } 237 237 + 238 238 + static const struct nand_controller_ops gpio_nand_ops = { 239 239 + .exec_op = gpio_nand_exec_op, 240 240 + .setup_data_interface = gpio_nand_setup_data_interface, 196 241 }; 197 242 198 243 /* 199 244 * Main initialization routine 200 245 */ 201 201 - static int ams_delta_init(struct platform_device *pdev) 246 246 + static int gpio_nand_probe(struct platform_device *pdev) 202 247 { 203 203 - struct ams_delta_nand *priv; 248 248 + struct gpio_nand_platdata *pdata = dev_get_platdata(&pdev->dev); 249 249 + const struct mtd_partition *partitions = NULL; 250 250 + int num_partitions = 0; 251 251 + struct gpio_nand *priv; 204 252 struct nand_chip *this; 205 253 struct mtd_info *mtd; 206 206 - struct gpio_descs *data_gpiods; 254 254 + int (*probe)(struct platform_device *pdev, struct gpio_nand *priv); 207 255 int err = 0; 208 256 257 257 + if (pdata) { 258 258 + partitions = pdata->parts; 259 259 + num_partitions = pdata->num_parts; 260 260 + } 261 261 + 209 262 /* Allocate memory for MTD device structure and private data */ 210 210 - priv = devm_kzalloc(&pdev->dev, sizeof(struct ams_delta_nand), 263 263 + priv = devm_kzalloc(&pdev->dev, sizeof(struct gpio_nand), 211 264 GFP_KERNEL); 212 265 if (!priv) 213 266 return -ENOMEM; ··· 251 238 mtd->dev.parent = &pdev->dev; 252 239 253 240 nand_set_controller_data(this, priv); 241 241 + nand_set_flash_node(this, pdev->dev.of_node); 254 242 255 243 priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN); 256 244 if (IS_ERR(priv->gpiod_rdy)) { ··· 265 251 266 252 platform_set_drvdata(pdev, priv); 267 253 268 268 - /* Set chip enabled, but */ 269 269 - priv->gpiod_nwp = devm_gpiod_get(&pdev->dev, "nwp", GPIOD_OUT_HIGH); 254 254 + /* Set chip enabled but write protected */ 255 255 + priv->gpiod_nwp = devm_gpiod_get_optional(&pdev->dev, "nwp", 256 256 + GPIOD_OUT_HIGH); 270 257 if (IS_ERR(priv->gpiod_nwp)) { 271 258 err = PTR_ERR(priv->gpiod_nwp); 272 259 dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err); 273 260 return err; 274 261 } 275 262 276 276 - priv->gpiod_nce = devm_gpiod_get(&pdev->dev, "nce", GPIOD_OUT_HIGH); 263 263 + priv->gpiod_nce = devm_gpiod_get_optional(&pdev->dev, "nce", 264 264 + GPIOD_OUT_LOW); 277 265 if (IS_ERR(priv->gpiod_nce)) { 278 266 err = PTR_ERR(priv->gpiod_nce); 279 267 dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err); 280 268 return err; 281 269 } 282 270 283 283 - priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_HIGH); 271 271 + priv->gpiod_nre = devm_gpiod_get_optional(&pdev->dev, "nre", 272 272 + GPIOD_OUT_LOW); 284 273 if (IS_ERR(priv->gpiod_nre)) { 285 274 err = PTR_ERR(priv->gpiod_nre); 286 275 dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err); 287 276 return err; 288 277 } 289 278 290 290 - priv->gpiod_nwe = devm_gpiod_get(&pdev->dev, "nwe", GPIOD_OUT_HIGH); 279 279 + priv->gpiod_nwe = devm_gpiod_get_optional(&pdev->dev, "nwe", 280 280 + GPIOD_OUT_LOW); 291 281 if (IS_ERR(priv->gpiod_nwe)) { 292 282 err = PTR_ERR(priv->gpiod_nwe); 293 283 dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err); ··· 313 295 } 314 296 315 297 /* Request array of data pins, initialize them as input */ 316 316 - data_gpiods = devm_gpiod_get_array(&pdev->dev, "data", GPIOD_IN); 317 317 - if (IS_ERR(data_gpiods)) { 318 318 - err = PTR_ERR(data_gpiods); 298 298 + priv->data_gpiods = devm_gpiod_get_array_optional(&pdev->dev, "data", 299 299 + GPIOD_IN); 300 300 + if (IS_ERR(priv->data_gpiods)) { 301 301 + err = PTR_ERR(priv->data_gpiods); 319 302 dev_err(&pdev->dev, "data GPIO request failed: %d\n", err); 320 303 return err; 321 304 } 322 322 - priv->data_gpiods = data_gpiods; 323 323 - priv->data_in = true; 305 305 + if (priv->data_gpiods) { 306 306 + if (!priv->gpiod_nwe) { 307 307 + dev_err(&pdev->dev, 308 308 + "mandatory NWE pin not provided by platform\n"); 309 309 + return -ENODEV; 310 310 + } 324 311 325 325 - /* Initialize the NAND controller object embedded in ams_delta_nand. */ 326 326 - priv->base.ops = &ams_delta_ops; 312 312 + priv->io_read = gpio_nand_io_read; 313 313 + priv->io_write = gpio_nand_io_write; 314 314 + priv->data_in = true; 315 315 + } 316 316 + 317 317 + if (pdev->id_entry) 318 318 + probe = (void *) pdev->id_entry->driver_data; 319 319 + else 320 320 + probe = of_device_get_match_data(&pdev->dev); 321 321 + if (probe) 322 322 + err = probe(pdev, priv); 323 323 + if (err) 324 324 + return err; 325 325 + 326 326 + if (!priv->io_read || !priv->io_write) { 327 327 + dev_err(&pdev->dev, "incomplete device configuration\n"); 328 328 + return -ENODEV; 329 329 + } 330 330 + 331 331 + /* Initialize the NAND controller object embedded in gpio_nand. */ 332 332 + priv->base.ops = &gpio_nand_ops; 327 333 nand_controller_init(&priv->base); 328 334 this->controller = &priv->base; 335 335 + 336 336 + /* 337 337 + * FIXME: We should release write protection only after nand_scan() to 338 338 + * be on the safe side but we can't do that until we have a generic way 339 339 + * to assert/deassert WP from the core. Even if the core shouldn't 340 340 + * write things in the nand_scan() path, it should have control on this 341 341 + * pin just in case we ever need to disable write protection during 342 342 + * chip detection/initialization. 343 343 + */ 344 344 + /* Release write protection */ 345 345 + gpiod_set_value(priv->gpiod_nwp, 0); 329 346 330 347 /* Scan to find existence of the device */ 331 348 err = nand_scan(this, 1); ··· 368 315 return err; 369 316 370 317 /* Register the partitions */ 371 371 - err = mtd_device_register(mtd, partition_info, 372 372 - ARRAY_SIZE(partition_info)); 318 318 + err = mtd_device_register(mtd, partitions, num_partitions); 373 319 if (err) 374 320 goto err_nand_cleanup; 375 321 ··· 383 331 /* 384 332 * Clean up routine 385 333 */ 386 386 - static int ams_delta_cleanup(struct platform_device *pdev) 334 334 + static int gpio_nand_remove(struct platform_device *pdev) 387 335 { 388 388 - struct ams_delta_nand *priv = platform_get_drvdata(pdev); 336 336 + struct gpio_nand *priv = platform_get_drvdata(pdev); 389 337 struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip); 338 338 + 339 339 + /* Apply write protection */ 340 340 + gpiod_set_value(priv->gpiod_nwp, 1); 390 341 391 342 /* Unregister device */ 392 343 nand_release(mtd_to_nand(mtd)); ··· 397 342 return 0; 398 343 } 399 344 400 400 - static struct platform_driver ams_delta_nand_driver = { 401 401 - .probe = ams_delta_init, 402 402 - .remove = ams_delta_cleanup, 345 345 + static const struct of_device_id gpio_nand_of_id_table[] = { 346 346 + { 347 347 + /* sentinel */ 348 348 + }, 349 349 + }; 350 350 + MODULE_DEVICE_TABLE(of, gpio_nand_of_id_table); 351 351 + 352 352 + static const struct platform_device_id gpio_nand_plat_id_table[] = { 353 353 + { 354 354 + .name = "ams-delta-nand", 355 355 + }, { 356 356 + /* sentinel */ 357 357 + }, 358 358 + }; 359 359 + MODULE_DEVICE_TABLE(platform, gpio_nand_plat_id_table); 360 360 + 361 361 + static struct platform_driver gpio_nand_driver = { 362 362 + .probe = gpio_nand_probe, 363 363 + .remove = gpio_nand_remove, 364 364 + .id_table = gpio_nand_plat_id_table, 403 365 .driver = { 404 366 .name = "ams-delta-nand", 367 367 + .of_match_table = of_match_ptr(gpio_nand_of_id_table), 405 368 }, 406 369 }; 407 370 408 408 - module_platform_driver(ams_delta_nand_driver); 371 371 + module_platform_driver(gpio_nand_driver); 409 372 410 373 MODULE_LICENSE("GPL v2"); 411 374 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");

+287 -6

drivers/mtd/nand/raw/brcmnand/brcmnand.c

reviewed

··· 102 102 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 103 103 #define NAND_POLL_STATUS_TIMEOUT_MS 100 104 104 105 105 + #define EDU_CMD_WRITE 0x00 106 106 + #define EDU_CMD_READ 0x01 107 107 + #define EDU_STATUS_ACTIVE BIT(0) 108 108 + #define EDU_ERR_STATUS_ERRACK BIT(0) 109 109 + #define EDU_DONE_MASK GENMASK(1, 0) 110 110 + 111 111 + #define EDU_CONFIG_MODE_NAND BIT(0) 112 112 + #define EDU_CONFIG_SWAP_BYTE BIT(1) 113 113 + #ifdef CONFIG_CPU_BIG_ENDIAN 114 114 + #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE 115 115 + #else 116 116 + #define EDU_CONFIG_SWAP_CFG 0 117 117 + #endif 118 118 + 119 119 + /* edu registers */ 120 120 + enum edu_reg { 121 121 + EDU_CONFIG = 0, 122 122 + EDU_DRAM_ADDR, 123 123 + EDU_EXT_ADDR, 124 124 + EDU_LENGTH, 125 125 + EDU_CMD, 126 126 + EDU_STOP, 127 127 + EDU_STATUS, 128 128 + EDU_DONE, 129 129 + EDU_ERR_STATUS, 130 130 + }; 131 131 + 132 132 + static const u16 edu_regs[] = { 133 133 + [EDU_CONFIG] = 0x00, 134 134 + [EDU_DRAM_ADDR] = 0x04, 135 135 + [EDU_EXT_ADDR] = 0x08, 136 136 + [EDU_LENGTH] = 0x0c, 137 137 + [EDU_CMD] = 0x10, 138 138 + [EDU_STOP] = 0x14, 139 139 + [EDU_STATUS] = 0x18, 140 140 + [EDU_DONE] = 0x1c, 141 141 + [EDU_ERR_STATUS] = 0x20, 142 142 + }; 143 143 + 105 144 /* flash_dma registers */ 106 145 enum flash_dma_reg { 107 146 FLASH_DMA_REVISION = 0, ··· 206 167 BRCMNAND_HAS_WP = BIT(3), 207 168 }; 208 169 170 170 + struct brcmnand_host; 171 171 + 209 172 struct brcmnand_controller { 210 173 struct device *dev; 211 174 struct nand_controller controller; ··· 226 185 227 186 int cmd_pending; 228 187 bool dma_pending; 188 188 + bool edu_pending; 229 189 struct completion done; 230 190 struct completion dma_done; 191 191 + struct completion edu_done; 231 192 232 193 /* List of NAND hosts (one for each chip-select) */ 233 194 struct list_head host_list; 195 195 + 196 196 + /* EDU info, per-transaction */ 197 197 + const u16 *edu_offsets; 198 198 + void __iomem *edu_base; 199 199 + int edu_irq; 200 200 + int edu_count; 201 201 + u64 edu_dram_addr; 202 202 + u32 edu_ext_addr; 203 203 + u32 edu_cmd; 204 204 + u32 edu_config; 234 205 235 206 /* flash_dma reg */ 236 207 const u16 *flash_dma_offsets; 237 208 struct brcm_nand_dma_desc *dma_desc; 238 209 dma_addr_t dma_pa; 210 210 + 211 211 + int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf, 212 212 + u32 len, u8 dma_cmd); 239 213 240 214 /* in-memory cache of the FLASH_CACHE, used only for some commands */ 241 215 u8 flash_cache[FC_BYTES]; ··· 272 216 u32 nand_cs_nand_xor; 273 217 u32 corr_stat_threshold; 274 218 u32 flash_dma_mode; 219 219 + u32 flash_edu_mode; 275 220 bool pio_poll_mode; 276 221 }; 277 222 ··· 714 657 __raw_writel(val, ctrl->nand_fc + word * 4); 715 658 } 716 659 660 660 + static inline void edu_writel(struct brcmnand_controller *ctrl, 661 661 + enum edu_reg reg, u32 val) 662 662 + { 663 663 + u16 offs = ctrl->edu_offsets[reg]; 664 664 + 665 665 + brcmnand_writel(val, ctrl->edu_base + offs); 666 666 + } 667 667 + 668 668 + static inline u32 edu_readl(struct brcmnand_controller *ctrl, 669 669 + enum edu_reg reg) 670 670 + { 671 671 + u16 offs = ctrl->edu_offsets[reg]; 672 672 + 673 673 + return brcmnand_readl(ctrl->edu_base + offs); 674 674 + } 675 675 + 717 676 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) 718 677 { 719 678 ··· 997 924 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 998 925 { 999 926 return ctrl->flash_dma_base; 927 927 + } 928 928 + 929 929 + static inline bool has_edu(struct brcmnand_controller *ctrl) 930 930 + { 931 931 + return ctrl->edu_base; 932 932 + } 933 933 + 934 934 + static inline bool use_dma(struct brcmnand_controller *ctrl) 935 935 + { 936 936 + return has_flash_dma(ctrl) || has_edu(ctrl); 1000 937 } 1001 938 1002 939 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) ··· 1382 1299 return tbytes; 1383 1300 } 1384 1301 1302 1302 + static void brcmnand_edu_init(struct brcmnand_controller *ctrl) 1303 1303 + { 1304 1304 + /* initialize edu */ 1305 1305 + edu_writel(ctrl, EDU_ERR_STATUS, 0); 1306 1306 + edu_readl(ctrl, EDU_ERR_STATUS); 1307 1307 + edu_writel(ctrl, EDU_DONE, 0); 1308 1308 + edu_writel(ctrl, EDU_DONE, 0); 1309 1309 + edu_writel(ctrl, EDU_DONE, 0); 1310 1310 + edu_writel(ctrl, EDU_DONE, 0); 1311 1311 + edu_readl(ctrl, EDU_DONE); 1312 1312 + } 1313 1313 + 1314 1314 + /* edu irq */ 1315 1315 + static irqreturn_t brcmnand_edu_irq(int irq, void *data) 1316 1316 + { 1317 1317 + struct brcmnand_controller *ctrl = data; 1318 1318 + 1319 1319 + if (ctrl->edu_count) { 1320 1320 + ctrl->edu_count--; 1321 1321 + while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) 1322 1322 + udelay(1); 1323 1323 + edu_writel(ctrl, EDU_DONE, 0); 1324 1324 + edu_readl(ctrl, EDU_DONE); 1325 1325 + } 1326 1326 + 1327 1327 + if (ctrl->edu_count) { 1328 1328 + ctrl->edu_dram_addr += FC_BYTES; 1329 1329 + ctrl->edu_ext_addr += FC_BYTES; 1330 1330 + 1331 1331 + edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1332 1332 + edu_readl(ctrl, EDU_DRAM_ADDR); 1333 1333 + edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1334 1334 + edu_readl(ctrl, EDU_EXT_ADDR); 1335 1335 + 1336 1336 + mb(); /* flush previous writes */ 1337 1337 + edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1338 1338 + edu_readl(ctrl, EDU_CMD); 1339 1339 + 1340 1340 + return IRQ_HANDLED; 1341 1341 + } 1342 1342 + 1343 1343 + complete(&ctrl->edu_done); 1344 1344 + 1345 1345 + return IRQ_HANDLED; 1346 1346 + } 1347 1347 + 1385 1348 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 1386 1349 { 1387 1350 struct brcmnand_controller *ctrl = data; ··· 1435 1306 /* Discard all NAND_CTLRDY interrupts during DMA */ 1436 1307 if (ctrl->dma_pending) 1437 1308 return IRQ_HANDLED; 1309 1309 + 1310 1310 + /* check if you need to piggy back on the ctrlrdy irq */ 1311 1311 + if (ctrl->edu_pending) { 1312 1312 + if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) 1313 1313 + /* Discard interrupts while using dedicated edu irq */ 1314 1314 + return IRQ_HANDLED; 1315 1315 + 1316 1316 + /* no registered edu irq, call handler */ 1317 1317 + return brcmnand_edu_irq(irq, data); 1318 1318 + } 1438 1319 1439 1320 complete(&ctrl->done); 1440 1321 return IRQ_HANDLED; ··· 1784 1645 } 1785 1646 1786 1647 /** 1648 1648 + * Kick EDU engine 1649 1649 + */ 1650 1650 + static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 1651 1651 + u32 len, u8 cmd) 1652 1652 + { 1653 1653 + struct brcmnand_controller *ctrl = host->ctrl; 1654 1654 + unsigned long timeo = msecs_to_jiffies(200); 1655 1655 + int ret = 0; 1656 1656 + int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 1657 1657 + u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE); 1658 1658 + unsigned int trans = len >> FC_SHIFT; 1659 1659 + dma_addr_t pa; 1660 1660 + 1661 1661 + pa = dma_map_single(ctrl->dev, buf, len, dir); 1662 1662 + if (dma_mapping_error(ctrl->dev, pa)) { 1663 1663 + dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); 1664 1664 + return -ENOMEM; 1665 1665 + } 1666 1666 + 1667 1667 + ctrl->edu_pending = true; 1668 1668 + ctrl->edu_dram_addr = pa; 1669 1669 + ctrl->edu_ext_addr = addr; 1670 1670 + ctrl->edu_cmd = edu_cmd; 1671 1671 + ctrl->edu_count = trans; 1672 1672 + 1673 1673 + edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1674 1674 + edu_readl(ctrl, EDU_DRAM_ADDR); 1675 1675 + edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1676 1676 + edu_readl(ctrl, EDU_EXT_ADDR); 1677 1677 + edu_writel(ctrl, EDU_LENGTH, FC_BYTES); 1678 1678 + edu_readl(ctrl, EDU_LENGTH); 1679 1679 + 1680 1680 + /* Start edu engine */ 1681 1681 + mb(); /* flush previous writes */ 1682 1682 + edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1683 1683 + edu_readl(ctrl, EDU_CMD); 1684 1684 + 1685 1685 + if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { 1686 1686 + dev_err(ctrl->dev, 1687 1687 + "timeout waiting for EDU; status %#x, error status %#x\n", 1688 1688 + edu_readl(ctrl, EDU_STATUS), 1689 1689 + edu_readl(ctrl, EDU_ERR_STATUS)); 1690 1690 + } 1691 1691 + 1692 1692 + dma_unmap_single(ctrl->dev, pa, len, dir); 1693 1693 + 1694 1694 + /* for program page check NAND status */ 1695 1695 + if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1696 1696 + INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) && 1697 1697 + edu_cmd == EDU_CMD_WRITE) { 1698 1698 + dev_info(ctrl->dev, "program failed at %llx\n", 1699 1699 + (unsigned long long)addr); 1700 1700 + ret = -EIO; 1701 1701 + } 1702 1702 + 1703 1703 + /* Make sure the EDU status is clean */ 1704 1704 + if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) 1705 1705 + dev_warn(ctrl->dev, "EDU still active: %#x\n", 1706 1706 + edu_readl(ctrl, EDU_STATUS)); 1707 1707 + 1708 1708 + if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { 1709 1709 + dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", 1710 1710 + (unsigned long long)addr); 1711 1711 + ret = -EIO; 1712 1712 + } 1713 1713 + 1714 1714 + ctrl->edu_pending = false; 1715 1715 + brcmnand_edu_init(ctrl); 1716 1716 + edu_writel(ctrl, EDU_STOP, 0); /* force stop */ 1717 1717 + edu_readl(ctrl, EDU_STOP); 1718 1718 + 1719 1719 + return ret; 1720 1720 + } 1721 1721 + 1722 1722 + /** 1787 1723 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 1788 1724 * following ahead of time: 1789 1725 * - Is this descriptor the beginning or end of a linked list? ··· 2064 1850 try_dmaread: 2065 1851 brcmnand_clear_ecc_addr(ctrl); 2066 1852 2067 2067 - if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 2068 2068 - err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES, 2069 2069 - CMD_PAGE_READ); 1853 1853 + if (ctrl->dma_trans && !oob && flash_dma_buf_ok(buf)) { 1854 1854 + err = ctrl->dma_trans(host, addr, buf, 1855 1855 + trans * FC_BYTES, 1856 1856 + CMD_PAGE_READ); 1857 1857 + 2070 1858 if (err) { 2071 1859 if (mtd_is_bitflip_or_eccerr(err)) 2072 1860 err_addr = addr; ··· 2204 1988 for (i = 0; i < ctrl->max_oob; i += 4) 2205 1989 oob_reg_write(ctrl, i, 0xffffffff); 2206 1990 2207 2207 - if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 2208 2208 - if (brcmnand_dma_trans(host, addr, (u32 *)buf, 2209 2209 - mtd->writesize, CMD_PROGRAM_PAGE)) 1991 1991 + if (use_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 1992 1992 + if (ctrl->dma_trans(host, addr, (u32 *)buf, mtd->writesize, 1993 1993 + CMD_PROGRAM_PAGE)) 1994 1994 + 2210 1995 ret = -EIO; 1996 1996 + 2211 1997 goto out; 2212 1998 } 2213 1999 ··· 2712 2494 2713 2495 if (has_flash_dma(ctrl)) 2714 2496 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 2497 2497 + else if (has_edu(ctrl)) 2498 2498 + ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2715 2499 2716 2500 return 0; 2717 2501 } ··· 2726 2506 if (has_flash_dma(ctrl)) { 2727 2507 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 2728 2508 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 2509 2509 + } 2510 2510 + 2511 2511 + if (has_edu(ctrl)) 2512 2512 + ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2513 2513 + else { 2514 2514 + edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); 2515 2515 + edu_readl(ctrl, EDU_CONFIG); 2516 2516 + brcmnand_edu_init(ctrl); 2729 2517 } 2730 2518 2731 2519 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); ··· 2781 2553 /*********************************************************************** 2782 2554 * Platform driver setup (per controller) 2783 2555 ***********************************************************************/ 2556 2556 + static int brcmnand_edu_setup(struct platform_device *pdev) 2557 2557 + { 2558 2558 + struct device *dev = &pdev->dev; 2559 2559 + struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 2560 2560 + struct resource *res; 2561 2561 + int ret; 2562 2562 + 2563 2563 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); 2564 2564 + if (res) { 2565 2565 + ctrl->edu_base = devm_ioremap_resource(dev, res); 2566 2566 + if (IS_ERR(ctrl->edu_base)) 2567 2567 + return PTR_ERR(ctrl->edu_base); 2568 2568 + 2569 2569 + ctrl->edu_offsets = edu_regs; 2570 2570 + 2571 2571 + edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | 2572 2572 + EDU_CONFIG_SWAP_CFG); 2573 2573 + edu_readl(ctrl, EDU_CONFIG); 2574 2574 + 2575 2575 + /* initialize edu */ 2576 2576 + brcmnand_edu_init(ctrl); 2577 2577 + 2578 2578 + ctrl->edu_irq = platform_get_irq_optional(pdev, 1); 2579 2579 + if (ctrl->edu_irq < 0) { 2580 2580 + dev_warn(dev, 2581 2581 + "FLASH EDU enabled, using ctlrdy irq\n"); 2582 2582 + } else { 2583 2583 + ret = devm_request_irq(dev, ctrl->edu_irq, 2584 2584 + brcmnand_edu_irq, 0, 2585 2585 + "brcmnand-edu", ctrl); 2586 2586 + if (ret < 0) { 2587 2587 + dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", 2588 2588 + ctrl->edu_irq, ret); 2589 2589 + return ret; 2590 2590 + } 2591 2591 + 2592 2592 + dev_info(dev, "FLASH EDU enabled using irq %u\n", 2593 2593 + ctrl->edu_irq); 2594 2594 + } 2595 2595 + } 2596 2596 + 2597 2597 + return 0; 2598 2598 + } 2784 2599 2785 2600 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 2786 2601 { ··· 2849 2578 2850 2579 init_completion(&ctrl->done); 2851 2580 init_completion(&ctrl->dma_done); 2581 2581 + init_completion(&ctrl->edu_done); 2852 2582 nand_controller_init(&ctrl->controller); 2853 2583 ctrl->controller.ops = &brcmnand_controller_ops; 2854 2584 INIT_LIST_HEAD(&ctrl->host_list); ··· 2947 2675 } 2948 2676 2949 2677 dev_info(dev, "enabling FLASH_DMA\n"); 2678 2678 + /* set flash dma transfer function to call */ 2679 2679 + ctrl->dma_trans = brcmnand_dma_trans; 2680 2680 + } else { 2681 2681 + ret = brcmnand_edu_setup(pdev); 2682 2682 + if (ret < 0) 2683 2683 + goto err; 2684 2684 + 2685 2685 + /* set edu transfer function to call */ 2686 2686 + ctrl->dma_trans = brcmnand_edu_trans; 2950 2687 } 2951 2688 2952 2689 /* Disable automatic device ID config, direct addressing */

+20 -14

drivers/mtd/nand/raw/cadence-nand-controller.c

reviewed

··· 30 30 * Generic mode is used for executing rest of commands. 31 31 */ 32 32 33 33 - #define MAX_OOB_SIZE_PER_SECTOR 32 34 33 #define MAX_ADDRESS_CYC 6 35 34 #define MAX_ERASE_ADDRESS_CYC 3 36 35 #define MAX_DATA_SIZE 0xFFFC ··· 189 190 190 191 /* BCH Engine identification register 3. */ 191 192 #define BCH_CFG_3 0x844 193 193 + #define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16) 192 194 193 195 /* Ready/Busy# line status. */ 194 196 #define RBN_SETINGS 0x1004 ··· 499 499 500 500 unsigned long assigned_cs; 501 501 struct list_head chips; 502 502 + u8 bch_metadata_size; 502 503 }; 503 504 504 505 struct cdns_nand_chip { ··· 998 997 return status; 999 998 1000 999 cadence_nand_reset_irq(cdns_ctrl); 1000 1000 + reinit_completion(&cdns_ctrl->complete); 1001 1001 1002 1002 writel_relaxed((u32)cdns_ctrl->dma_cdma_desc, 1003 1003 cdns_ctrl->reg + CMD_REG2); ··· 1078 1076 struct nand_ecc_caps *ecc_caps = &cdns_ctrl->ecc_caps; 1079 1077 int max_step_size = 0, nstrengths, i; 1080 1078 u32 reg; 1079 1079 + 1080 1080 + reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3); 1081 1081 + cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg); 1082 1082 + if (cdns_ctrl->bch_metadata_size < 4) { 1083 1083 + dev_err(cdns_ctrl->dev, 1084 1084 + "Driver needs at least 4 bytes of BCH meta data\n"); 1085 1085 + return -EIO; 1086 1086 + } 1081 1087 1082 1088 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0); 1083 1089 cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg); ··· 1180 1170 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); 1181 1171 1182 1172 cadence_nand_get_caps(cdns_ctrl); 1183 1183 - cadence_nand_read_bch_caps(cdns_ctrl); 1173 1173 + if (cadence_nand_read_bch_caps(cdns_ctrl)) 1174 1174 + return -EIO; 1184 1175 1185 1176 /* 1186 1177 * Set IO width access to 8. ··· 2596 2585 { 2597 2586 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); 2598 2587 struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); 2599 2599 - u32 ecc_size = cdns_chip->sector_count * chip->ecc.bytes; 2588 2588 + u32 ecc_size; 2600 2589 struct mtd_info *mtd = nand_to_mtd(chip); 2601 2601 - u32 max_oob_data_size; 2602 2590 int ret; 2603 2591 2604 2592 if (chip->options & NAND_BUSWIDTH_16) { ··· 2613 2603 chip->options |= NAND_NO_SUBPAGE_WRITE; 2614 2604 2615 2605 cdns_chip->bbm_offs = chip->badblockpos; 2616 2616 - if (chip->options & NAND_BUSWIDTH_16) { 2617 2617 - cdns_chip->bbm_offs &= ~0x01; 2618 2618 - cdns_chip->bbm_len = 2; 2619 2619 - } else { 2620 2620 - cdns_chip->bbm_len = 1; 2621 2621 - } 2606 2606 + cdns_chip->bbm_offs &= ~0x01; 2607 2607 + /* this value should be even number */ 2608 2608 + cdns_chip->bbm_len = 2; 2622 2609 2623 2610 ret = nand_ecc_choose_conf(chip, 2624 2611 &cdns_ctrl->ecc_caps, ··· 2632 2625 /* Error correction configuration. */ 2633 2626 cdns_chip->sector_size = chip->ecc.size; 2634 2627 cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size; 2628 2628 + ecc_size = cdns_chip->sector_count * chip->ecc.bytes; 2635 2629 2636 2630 cdns_chip->avail_oob_size = mtd->oobsize - ecc_size; 2637 2631 2638 2638 - max_oob_data_size = MAX_OOB_SIZE_PER_SECTOR; 2639 2639 - 2640 2640 - if (cdns_chip->avail_oob_size > max_oob_data_size) 2641 2641 - cdns_chip->avail_oob_size = max_oob_data_size; 2632 2632 + if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size) 2633 2633 + cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size; 2642 2634 2643 2635 if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size) 2644 2636 > mtd->oobsize)

+1

drivers/mtd/nand/raw/denali.c

reviewed

··· 1317 1317 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1318 1318 iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); 1319 1319 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1320 1320 + iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT); 1320 1321 1321 1322 denali_clear_irq_all(denali); 1322 1323

+1 -1

drivers/mtd/nand/raw/denali.h

reviewed

··· 328 328 struct nand_chip chip; 329 329 struct list_head node; 330 330 unsigned int nsels; 331 331 - struct denali_chip_sel sels[0]; 331 331 + struct denali_chip_sel sels[]; 332 332 }; 333 333 334 334 /**

+2 -2

drivers/mtd/nand/raw/diskonchip.c

reviewed

··· 1169 1169 " NoOfBootImageBlocks = %d\n" 1170 1170 " NoOfBinaryPartitions = %d\n" 1171 1171 " NoOfBDTLPartitions = %d\n" 1172 1172 - " BlockMultiplerBits = %d\n" 1172 1172 + " BlockMultiplierBits = %d\n" 1173 1173 " FormatFlgs = %d\n" 1174 1174 " OsakVersion = %d.%d.%d.%d\n" 1175 1175 " PercentUsed = %d\n", ··· 1482 1482 break; 1483 1483 case DOC_ChipID_DocMilPlus32: 1484 1484 pr_err("DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); 1485 1485 - /* fall through */ 1485 1485 + fallthrough; 1486 1486 default: 1487 1487 ret = -ENODEV; 1488 1488 goto notfound;

+1 -2

drivers/mtd/nand/raw/fsl_elbc_nand.c

reviewed

··· 324 324 /* READ0 and READ1 read the entire buffer to use hardware ECC. */ 325 325 case NAND_CMD_READ1: 326 326 column += 256; 327 327 - 328 328 - /* fall-through */ 327 327 + fallthrough; 329 328 case NAND_CMD_READ0: 330 329 dev_dbg(priv->dev, 331 330 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"

+11 -10

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

reviewed

··· 1148 1148 { 1149 1149 struct platform_device *pdev = this->pdev; 1150 1150 struct dma_chan *dma_chan; 1151 1151 + int ret = 0; 1151 1152 1152 1153 /* request dma channel */ 1153 1153 - dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx"); 1154 1154 - if (!dma_chan) { 1155 1155 - dev_err(this->dev, "Failed to request DMA channel.\n"); 1156 1156 - goto acquire_err; 1154 1154 + dma_chan = dma_request_chan(&pdev->dev, "rx-tx"); 1155 1155 + if (IS_ERR(dma_chan)) { 1156 1156 + ret = PTR_ERR(dma_chan); 1157 1157 + if (ret != -EPROBE_DEFER) 1158 1158 + dev_err(this->dev, "DMA channel request failed: %d\n", 1159 1159 + ret); 1160 1160 + release_dma_channels(this); 1161 1161 + } else { 1162 1162 + this->dma_chans[0] = dma_chan; 1157 1163 } 1158 1164 1159 1159 - this->dma_chans[0] = dma_chan; 1160 1160 - return 0; 1161 1161 - 1162 1162 - acquire_err: 1163 1163 - release_dma_channels(this); 1164 1164 - return -EINVAL; 1165 1165 + return ret; 1165 1166 } 1166 1167 1167 1168 static int gpmi_get_clks(struct gpmi_nand_data *this)

+1

drivers/mtd/nand/raw/ingenic/Kconfig

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 config MTD_NAND_JZ4780 3 3 tristate "JZ4780 NAND controller" 4 4 + depends on MIPS || COMPILE_TEST 4 5 depends on JZ4780_NEMC 5 6 help 6 7 Enables support for NAND Flash connected to the NEMC on JZ4780 SoC

+1 -3

drivers/mtd/nand/raw/ingenic/ingenic_ecc.c

reviewed

··· 124 124 { 125 125 struct device *dev = &pdev->dev; 126 126 struct ingenic_ecc *ecc; 127 127 - struct resource *res; 128 127 129 128 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); 130 129 if (!ecc) ··· 133 134 if (!ecc->ops) 134 135 return -EINVAL; 135 136 136 136 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 137 137 - ecc->base = devm_ioremap_resource(dev, res); 137 137 + ecc->base = devm_platform_ioremap_resource(pdev, 0); 138 138 if (IS_ERR(ecc->base)) 139 139 return PTR_ERR(ecc->base); 140 140

+1 -1

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

reviewed

··· 253 253 chip->ecc.hwctl = ingenic_nand_ecc_hwctl; 254 254 chip->ecc.calculate = ingenic_nand_ecc_calculate; 255 255 chip->ecc.correct = ingenic_nand_ecc_correct; 256 256 - /* fall through */ 256 256 + fallthrough; 257 257 case NAND_ECC_SOFT: 258 258 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n", 259 259 (nfc->ecc) ? "hardware ECC" : "software ECC",

+2 -2

drivers/mtd/nand/raw/ingenic/jz4725b_bch.c

reviewed

··· 145 145 switch (size8) { 146 146 case 3: 147 147 dest8[2] = (val >> 16) & 0xff; 148 148 - /* fall-through */ 148 148 + fallthrough; 149 149 case 2: 150 150 dest8[1] = (val >> 8) & 0xff; 151 151 - /* fall-through */ 151 151 + fallthrough; 152 152 case 1: 153 153 dest8[0] = val & 0xff; 154 154 break;

+2 -2

drivers/mtd/nand/raw/ingenic/jz4780_bch.c

reviewed

··· 123 123 switch (size8) { 124 124 case 3: 125 125 dest8[2] = (val >> 16) & 0xff; 126 126 - /* fall through */ 126 126 + fallthrough; 127 127 case 2: 128 128 dest8[1] = (val >> 8) & 0xff; 129 129 - /* fall through */ 129 129 + fallthrough; 130 130 case 1: 131 131 dest8[0] = val & 0xff; 132 132 break;

+1

drivers/mtd/nand/raw/internals.h

reviewed

··· 30 30 #define NAND_MFR_SAMSUNG 0xec 31 31 #define NAND_MFR_SANDISK 0x45 32 32 #define NAND_MFR_STMICRO 0x20 33 33 + /* Kioxia is new name of Toshiba memory. */ 33 34 #define NAND_MFR_TOSHIBA 0x98 34 35 #define NAND_MFR_WINBOND 0xef 35 36

+28 -12

drivers/mtd/nand/raw/marvell_nand.c

reviewed

··· 334 334 int addr_cyc; 335 335 int selected_die; 336 336 unsigned int nsels; 337 337 - struct marvell_nand_chip_sel sels[0]; 337 337 + struct marvell_nand_chip_sel sels[]; 338 338 }; 339 339 340 340 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) ··· 2743 2743 if (ret) 2744 2744 return ret; 2745 2745 2746 2746 - nfc->dma_chan = dma_request_slave_channel(nfc->dev, "data"); 2747 2747 - if (!nfc->dma_chan) { 2748 2748 - dev_err(nfc->dev, 2749 2749 - "Unable to request data DMA channel\n"); 2750 2750 - return -ENODEV; 2746 2746 + nfc->dma_chan = dma_request_chan(nfc->dev, "data"); 2747 2747 + if (IS_ERR(nfc->dma_chan)) { 2748 2748 + ret = PTR_ERR(nfc->dma_chan); 2749 2749 + nfc->dma_chan = NULL; 2750 2750 + if (ret != -EPROBE_DEFER) 2751 2751 + dev_err(nfc->dev, "DMA channel request failed: %d\n", 2752 2752 + ret); 2753 2753 + return ret; 2751 2754 } 2752 2755 2753 2756 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2754 2754 - if (!r) 2755 2755 - return -ENXIO; 2757 2757 + if (!r) { 2758 2758 + ret = -ENXIO; 2759 2759 + goto release_channel; 2760 2760 + } 2756 2761 2757 2762 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2758 2763 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ··· 2768 2763 ret = dmaengine_slave_config(nfc->dma_chan, &config); 2769 2764 if (ret < 0) { 2770 2765 dev_err(nfc->dev, "Failed to configure DMA channel\n"); 2771 2771 - return ret; 2766 2766 + goto release_channel; 2772 2767 } 2773 2768 2774 2769 /* ··· 2778 2773 * the provided buffer. 2779 2774 */ 2780 2775 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 2781 2781 - if (!nfc->dma_buf) 2782 2782 - return -ENOMEM; 2776 2776 + if (!nfc->dma_buf) { 2777 2777 + ret = -ENOMEM; 2778 2778 + goto release_channel; 2779 2779 + } 2783 2780 2784 2781 nfc->use_dma = true; 2785 2782 2786 2783 return 0; 2784 2784 + 2785 2785 + release_channel: 2786 2786 + dma_release_channel(nfc->dma_chan); 2787 2787 + nfc->dma_chan = NULL; 2788 2788 + 2789 2789 + return ret; 2787 2790 } 2788 2791 2789 2792 static void marvell_nfc_reset(struct marvell_nfc *nfc) ··· 2933 2920 2934 2921 ret = marvell_nand_chips_init(dev, nfc); 2935 2922 if (ret) 2936 2936 - goto unprepare_reg_clk; 2923 2923 + goto release_dma; 2937 2924 2938 2925 return 0; 2939 2926 2927 2927 + release_dma: 2928 2928 + if (nfc->use_dma) 2929 2929 + dma_release_channel(nfc->dma_chan); 2940 2930 unprepare_reg_clk: 2941 2931 clk_disable_unprepare(nfc->reg_clk); 2942 2932 unprepare_core_clk:

+1 -1

drivers/mtd/nand/raw/meson_nand.c

reviewed

··· 118 118 u8 *data_buf; 119 119 __le64 *info_buf; 120 120 u32 nsels; 121 121 - u8 sels[0]; 121 121 + u8 sels[]; 122 122 }; 123 123 124 124 struct meson_nand_ecc {

+1 -1

drivers/mtd/nand/raw/mtk_nand.c

reviewed

··· 131 131 u32 spare_per_sector; 132 132 133 133 int nsels; 134 134 - u8 sels[0]; 134 134 + u8 sels[]; 135 135 /* nothing after this field */ 136 136 }; 137 137

+58 -13

drivers/mtd/nand/raw/nand_base.c

reviewed

··· 683 683 if (ret) 684 684 return ret; 685 685 686 686 - timeout_ms = jiffies + msecs_to_jiffies(timeout_ms); 686 686 + /* 687 687 + * +1 below is necessary because if we are now in the last fraction 688 688 + * of jiffy and msecs_to_jiffies is 1 then we will wait only that 689 689 + * small jiffy fraction - possibly leading to false timeout 690 690 + */ 691 691 + timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 687 692 do { 688 693 ret = nand_read_data_op(chip, &status, sizeof(status), true); 689 694 if (ret) ··· 4326 4321 /** 4327 4322 * nand_suspend - [MTD Interface] Suspend the NAND flash 4328 4323 * @mtd: MTD device structure 4324 4324 + * 4325 4325 + * Returns 0 for success or negative error code otherwise. 4329 4326 */ 4330 4327 static int nand_suspend(struct mtd_info *mtd) 4331 4328 { 4332 4329 struct nand_chip *chip = mtd_to_nand(mtd); 4330 4330 + int ret = 0; 4333 4331 4334 4332 mutex_lock(&chip->lock); 4335 4335 - chip->suspended = 1; 4333 4333 + if (chip->suspend) 4334 4334 + ret = chip->suspend(chip); 4335 4335 + if (!ret) 4336 4336 + chip->suspended = 1; 4336 4337 mutex_unlock(&chip->lock); 4337 4338 4338 4338 - return 0; 4339 4339 + return ret; 4339 4340 } 4340 4341 4341 4342 /** ··· 4353 4342 struct nand_chip *chip = mtd_to_nand(mtd); 4354 4343 4355 4344 mutex_lock(&chip->lock); 4356 4356 - if (chip->suspended) 4345 4345 + if (chip->suspended) { 4346 4346 + if (chip->resume) 4347 4347 + chip->resume(chip); 4357 4348 chip->suspended = 0; 4358 4358 - else 4349 4349 + } else { 4359 4350 pr_err("%s called for a chip which is not in suspended state\n", 4360 4351 __func__); 4352 4352 + } 4361 4353 mutex_unlock(&chip->lock); 4362 4354 } 4363 4355 ··· 4372 4358 static void nand_shutdown(struct mtd_info *mtd) 4373 4359 { 4374 4360 nand_suspend(mtd); 4361 4361 + } 4362 4362 + 4363 4363 + /** 4364 4364 + * nand_lock - [MTD Interface] Lock the NAND flash 4365 4365 + * @mtd: MTD device structure 4366 4366 + * @ofs: offset byte address 4367 4367 + * @len: number of bytes to lock (must be a multiple of block/page size) 4368 4368 + */ 4369 4369 + static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4370 4370 + { 4371 4371 + struct nand_chip *chip = mtd_to_nand(mtd); 4372 4372 + 4373 4373 + if (!chip->lock_area) 4374 4374 + return -ENOTSUPP; 4375 4375 + 4376 4376 + return chip->lock_area(chip, ofs, len); 4377 4377 + } 4378 4378 + 4379 4379 + /** 4380 4380 + * nand_unlock - [MTD Interface] Unlock the NAND flash 4381 4381 + * @mtd: MTD device structure 4382 4382 + * @ofs: offset byte address 4383 4383 + * @len: number of bytes to unlock (must be a multiple of block/page size) 4384 4384 + */ 4385 4385 + static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4386 4386 + { 4387 4387 + struct nand_chip *chip = mtd_to_nand(mtd); 4388 4388 + 4389 4389 + if (!chip->unlock_area) 4390 4390 + return -ENOTSUPP; 4391 4391 + 4392 4392 + return chip->unlock_area(chip, ofs, len); 4375 4393 } 4376 4394 4377 4395 /* Set default functions */ ··· 5637 5591 } 5638 5592 if (!ecc->read_page) 5639 5593 ecc->read_page = nand_read_page_hwecc_oob_first; 5640 5640 - /* fall through */ 5641 5641 - 5594 5594 + fallthrough; 5642 5595 case NAND_ECC_HW: 5643 5596 /* Use standard hwecc read page function? */ 5644 5597 if (!ecc->read_page) ··· 5656 5611 ecc->read_subpage = nand_read_subpage; 5657 5612 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5658 5613 ecc->write_subpage = nand_write_subpage_hwecc; 5659 5659 - /* fall through */ 5660 5660 - 5614 5614 + fallthrough; 5661 5615 case NAND_ECC_HW_SYNDROME: 5662 5616 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5663 5617 (!ecc->read_page || ··· 5693 5649 ecc->size, mtd->writesize); 5694 5650 ecc->mode = NAND_ECC_SOFT; 5695 5651 ecc->algo = NAND_ECC_HAMMING; 5696 5696 - /* fall through */ 5697 5697 - 5652 5652 + fallthrough; 5698 5653 case NAND_ECC_SOFT: 5699 5654 ret = nand_set_ecc_soft_ops(chip); 5700 5655 if (ret) { ··· 5829 5786 mtd->_read_oob = nand_read_oob; 5830 5787 mtd->_write_oob = nand_write_oob; 5831 5788 mtd->_sync = nand_sync; 5832 5832 - mtd->_lock = NULL; 5833 5833 - mtd->_unlock = NULL; 5789 5789 + mtd->_lock = nand_lock; 5790 5790 + mtd->_unlock = nand_unlock; 5834 5791 mtd->_suspend = nand_suspend; 5835 5792 mtd->_resume = nand_resume; 5836 5793 mtd->_reboot = nand_shutdown; ··· 5949 5906 if (chip->ecc.mode == NAND_ECC_SOFT && 5950 5907 chip->ecc.algo == NAND_ECC_BCH) 5951 5908 nand_bch_free((struct nand_bch_control *)chip->ecc.priv); 5909 5909 + 5910 5910 + nanddev_cleanup(&chip->base); 5952 5911 5953 5912 /* Free bad block table memory */ 5954 5913 kfree(chip->bbt);

+1 -1

drivers/mtd/nand/raw/nand_hynix.c

reviewed

··· 26 26 struct hynix_read_retry { 27 27 int nregs; 28 28 const u8 *regs; 29 29 - u8 values[0]; 29 29 + u8 values[]; 30 30 }; 31 31 32 32 /**

+2 -4

drivers/mtd/nand/raw/nand_legacy.c

reviewed

··· 331 331 */ 332 332 if (column == -1 && page_addr == -1) 333 333 return; 334 334 - /* fall through */ 335 335 - 334 334 + fallthrough; 336 335 default: 337 336 /* 338 337 * If we don't have access to the busy pin, we apply the given ··· 482 483 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 483 484 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 484 485 NAND_NCE | NAND_CTRL_CHANGE); 485 485 - 486 486 - /* fall through - This applies to read commands */ 486 486 + fallthrough; /* This applies to read commands */ 487 487 default: 488 488 /* 489 489 * If we don't have access to the busy pin, we apply the given

+227

drivers/mtd/nand/raw/nand_macronix.c

reviewed

··· 6 6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 7 7 */ 8 8 9 9 + #include "linux/delay.h" 9 10 #include "internals.h" 10 11 11 12 #define MACRONIX_READ_RETRY_BIT BIT(0) 12 13 #define MACRONIX_NUM_READ_RETRY_MODES 6 14 14 + 15 15 + #define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0 16 16 + #define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38 17 17 + #define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0 18 18 + 19 19 + #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0 20 20 + #define MACRONIX_RANDOMIZER_BIT BIT(1) 21 21 + #define MACRONIX_RANDOMIZER_ENPGM BIT(0) 22 22 + #define MACRONIX_RANDOMIZER_RANDEN BIT(1) 23 23 + #define MACRONIX_RANDOMIZER_RANDOPT BIT(2) 24 24 + #define MACRONIX_RANDOMIZER_MODE_ENTER \ 25 25 + (MACRONIX_RANDOMIZER_ENPGM | \ 26 26 + MACRONIX_RANDOMIZER_RANDEN | \ 27 27 + MACRONIX_RANDOMIZER_RANDOPT) 28 28 + #define MACRONIX_RANDOMIZER_MODE_EXIT \ 29 29 + (MACRONIX_RANDOMIZER_RANDEN | \ 30 30 + MACRONIX_RANDOMIZER_RANDOPT) 31 31 + 32 32 + #define MXIC_CMD_POWER_DOWN 0xB9 13 33 14 34 struct nand_onfi_vendor_macronix { 15 35 u8 reserved; ··· 49 29 return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature); 50 30 } 51 31 32 32 + static int macronix_nand_randomizer_check_enable(struct nand_chip *chip) 33 33 + { 34 34 + u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; 35 35 + int ret; 36 36 + 37 37 + ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 38 38 + feature); 39 39 + if (ret < 0) 40 40 + return ret; 41 41 + 42 42 + if (feature[0]) 43 43 + return feature[0]; 44 44 + 45 45 + feature[0] = MACRONIX_RANDOMIZER_MODE_ENTER; 46 46 + ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 47 47 + feature); 48 48 + if (ret < 0) 49 49 + return ret; 50 50 + 51 51 + /* RANDEN and RANDOPT OTP bits are programmed */ 52 52 + feature[0] = 0x0; 53 53 + ret = nand_prog_page_op(chip, 0, 0, feature, 1); 54 54 + if (ret < 0) 55 55 + return ret; 56 56 + 57 57 + ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 58 58 + feature); 59 59 + if (ret < 0) 60 60 + return ret; 61 61 + 62 62 + feature[0] &= MACRONIX_RANDOMIZER_MODE_EXIT; 63 63 + ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 64 64 + feature); 65 65 + if (ret < 0) 66 66 + return ret; 67 67 + 68 68 + return 0; 69 69 + } 70 70 + 52 71 static void macronix_nand_onfi_init(struct nand_chip *chip) 53 72 { 54 73 struct nand_parameters *p = &chip->parameters; 55 74 struct nand_onfi_vendor_macronix *mxic; 75 75 + struct device_node *dn = nand_get_flash_node(chip); 76 76 + int rand_otp = 0; 77 77 + int ret; 56 78 57 79 if (!p->onfi) 58 80 return; 59 81 82 82 + if (of_find_property(dn, "mxic,enable-randomizer-otp", NULL)) 83 83 + rand_otp = 1; 84 84 + 60 85 mxic = (struct nand_onfi_vendor_macronix *)p->onfi->vendor; 86 86 + /* Subpage write is prohibited in randomizer operatoin */ 87 87 + if (rand_otp && chip->options & NAND_NO_SUBPAGE_WRITE && 88 88 + mxic->reliability_func & MACRONIX_RANDOMIZER_BIT) { 89 89 + if (p->supports_set_get_features) { 90 90 + bitmap_set(p->set_feature_list, 91 91 + ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1); 92 92 + bitmap_set(p->get_feature_list, 93 93 + ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1); 94 94 + ret = macronix_nand_randomizer_check_enable(chip); 95 95 + if (ret < 0) { 96 96 + bitmap_clear(p->set_feature_list, 97 97 + ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 98 98 + 1); 99 99 + bitmap_clear(p->get_feature_list, 100 100 + ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 101 101 + 1); 102 102 + pr_info("Macronix NAND randomizer failed\n"); 103 103 + } else { 104 104 + pr_info("Macronix NAND randomizer enabled\n"); 105 105 + } 106 106 + } 107 107 + } 108 108 + 61 109 if ((mxic->reliability_func & MACRONIX_READ_RETRY_BIT) == 0) 62 110 return; 63 111 ··· 179 91 ONFI_FEATURE_ADDR_TIMING_MODE, 1); 180 92 } 181 93 94 94 + /* 95 95 + * Macronix NAND supports Block Protection by Protectoin(PT) pin; 96 96 + * active high at power-on which protects the entire chip even the #WP is 97 97 + * disabled. Lock/unlock protection area can be partition according to 98 98 + * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on. 99 99 + */ 100 100 + static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len) 101 101 + { 102 102 + u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; 103 103 + int ret; 104 104 + 105 105 + feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK; 106 106 + nand_select_target(chip, 0); 107 107 + ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, 108 108 + feature); 109 109 + nand_deselect_target(chip); 110 110 + if (ret) 111 111 + pr_err("%s all blocks failed\n", __func__); 112 112 + 113 113 + return ret; 114 114 + } 115 115 + 116 116 + static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len) 117 117 + { 118 118 + u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; 119 119 + int ret; 120 120 + 121 121 + feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK; 122 122 + nand_select_target(chip, 0); 123 123 + ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, 124 124 + feature); 125 125 + nand_deselect_target(chip); 126 126 + if (ret) 127 127 + pr_err("%s all blocks failed\n", __func__); 128 128 + 129 129 + return ret; 130 130 + } 131 131 + 132 132 + static void macronix_nand_block_protection_support(struct nand_chip *chip) 133 133 + { 134 134 + u8 feature[ONFI_SUBFEATURE_PARAM_LEN]; 135 135 + int ret; 136 136 + 137 137 + bitmap_set(chip->parameters.get_feature_list, 138 138 + ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); 139 139 + 140 140 + feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK; 141 141 + nand_select_target(chip, 0); 142 142 + ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION, 143 143 + feature); 144 144 + nand_deselect_target(chip); 145 145 + if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) { 146 146 + if (ret) 147 147 + pr_err("Block protection check failed\n"); 148 148 + 149 149 + bitmap_clear(chip->parameters.get_feature_list, 150 150 + ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); 151 151 + return; 152 152 + } 153 153 + 154 154 + bitmap_set(chip->parameters.set_feature_list, 155 155 + ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1); 156 156 + 157 157 + chip->lock_area = mxic_nand_lock; 158 158 + chip->unlock_area = mxic_nand_unlock; 159 159 + } 160 160 + 161 161 + static int nand_power_down_op(struct nand_chip *chip) 162 162 + { 163 163 + int ret; 164 164 + 165 165 + if (nand_has_exec_op(chip)) { 166 166 + struct nand_op_instr instrs[] = { 167 167 + NAND_OP_CMD(MXIC_CMD_POWER_DOWN, 0), 168 168 + }; 169 169 + 170 170 + struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 171 171 + 172 172 + ret = nand_exec_op(chip, &op); 173 173 + if (ret) 174 174 + return ret; 175 175 + 176 176 + } else { 177 177 + chip->legacy.cmdfunc(chip, MXIC_CMD_POWER_DOWN, -1, -1); 178 178 + } 179 179 + 180 180 + return 0; 181 181 + } 182 182 + 183 183 + static int mxic_nand_suspend(struct nand_chip *chip) 184 184 + { 185 185 + int ret; 186 186 + 187 187 + nand_select_target(chip, 0); 188 188 + ret = nand_power_down_op(chip); 189 189 + if (ret < 0) 190 190 + pr_err("Suspending MXIC NAND chip failed (%d)\n", ret); 191 191 + nand_deselect_target(chip); 192 192 + 193 193 + return ret; 194 194 + } 195 195 + 196 196 + static void mxic_nand_resume(struct nand_chip *chip) 197 197 + { 198 198 + /* 199 199 + * Toggle #CS pin to resume NAND device and don't care 200 200 + * of the others CLE, #WE, #RE pins status. 201 201 + * A NAND controller ensure it is able to assert/de-assert #CS 202 202 + * by sending any byte over the NAND bus. 203 203 + * i.e., 204 204 + * NAND power down command or reset command w/o R/B# status checking. 205 205 + */ 206 206 + nand_select_target(chip, 0); 207 207 + nand_power_down_op(chip); 208 208 + /* The minimum of a recovery time tRDP is 35 us */ 209 209 + usleep_range(35, 100); 210 210 + nand_deselect_target(chip); 211 211 + } 212 212 + 213 213 + static void macronix_nand_deep_power_down_support(struct nand_chip *chip) 214 214 + { 215 215 + int i; 216 216 + static const char * const deep_power_down_dev[] = { 217 217 + "MX30UF1G28AD", 218 218 + "MX30UF2G28AD", 219 219 + "MX30UF4G28AD", 220 220 + }; 221 221 + 222 222 + i = match_string(deep_power_down_dev, ARRAY_SIZE(deep_power_down_dev), 223 223 + chip->parameters.model); 224 224 + if (i < 0) 225 225 + return; 226 226 + 227 227 + chip->suspend = mxic_nand_suspend; 228 228 + chip->resume = mxic_nand_resume; 229 229 + } 230 230 + 182 231 static int macronix_nand_init(struct nand_chip *chip) 183 232 { 184 233 if (nand_is_slc(chip)) ··· 323 98 324 99 macronix_nand_fix_broken_get_timings(chip); 325 100 macronix_nand_onfi_init(chip); 101 101 + macronix_nand_block_protection_support(chip); 102 102 + macronix_nand_deep_power_down_support(chip); 326 103 327 104 return 0; 328 105 }

+56 -2

drivers/mtd/nand/raw/nand_toshiba.c

reviewed

··· 14 14 /* Recommended to rewrite for BENAND */ 15 15 #define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED BIT(3) 16 16 17 17 + /* ECC Status Read Command for BENAND */ 18 18 + #define TOSHIBA_NAND_CMD_ECC_STATUS_READ 0x7A 19 19 + 20 20 + /* ECC Status Mask for BENAND */ 21 21 + #define TOSHIBA_NAND_ECC_STATUS_MASK 0x0F 22 22 + 23 23 + /* Uncorrectable Error for BENAND */ 24 24 + #define TOSHIBA_NAND_ECC_STATUS_UNCORR 0x0F 25 25 + 26 26 + /* Max ECC Steps for BENAND */ 27 27 + #define TOSHIBA_NAND_MAX_ECC_STEPS 8 28 28 + 29 29 + static int toshiba_nand_benand_read_eccstatus_op(struct nand_chip *chip, 30 30 + u8 *buf) 31 31 + { 32 32 + u8 *ecc_status = buf; 33 33 + 34 34 + if (nand_has_exec_op(chip)) { 35 35 + const struct nand_sdr_timings *sdr = 36 36 + nand_get_sdr_timings(&chip->data_interface); 37 37 + struct nand_op_instr instrs[] = { 38 38 + NAND_OP_CMD(TOSHIBA_NAND_CMD_ECC_STATUS_READ, 39 39 + PSEC_TO_NSEC(sdr->tADL_min)), 40 40 + NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0), 41 41 + }; 42 42 + struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 43 43 + 44 44 + return nand_exec_op(chip, &op); 45 45 + } 46 46 + 47 47 + return -ENOTSUPP; 48 48 + } 49 49 + 17 50 static int toshiba_nand_benand_eccstatus(struct nand_chip *chip) 18 51 { 19 52 struct mtd_info *mtd = nand_to_mtd(chip); 20 53 int ret; 21 54 unsigned int max_bitflips = 0; 22 22 - u8 status; 55 55 + u8 status, ecc_status[TOSHIBA_NAND_MAX_ECC_STEPS]; 23 56 24 57 /* Check Status */ 58 58 + ret = toshiba_nand_benand_read_eccstatus_op(chip, ecc_status); 59 59 + if (!ret) { 60 60 + unsigned int i, bitflips = 0; 61 61 + 62 62 + for (i = 0; i < chip->ecc.steps; i++) { 63 63 + bitflips = ecc_status[i] & TOSHIBA_NAND_ECC_STATUS_MASK; 64 64 + if (bitflips == TOSHIBA_NAND_ECC_STATUS_UNCORR) { 65 65 + mtd->ecc_stats.failed++; 66 66 + } else { 67 67 + mtd->ecc_stats.corrected += bitflips; 68 68 + max_bitflips = max(max_bitflips, bitflips); 69 69 + } 70 70 + } 71 71 + 72 72 + return max_bitflips; 73 73 + } 74 74 + 75 75 + /* 76 76 + * Fallback to regular status check if 77 77 + * toshiba_nand_benand_read_eccstatus_op() failed. 78 78 + */ 25 79 ret = nand_status_op(chip, &status); 26 80 if (ret) 27 81 return ret; ··· 162 108 */ 163 109 if (chip->id.len >= 6 && nand_is_slc(chip) && 164 110 (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && 165 165 - !(chip->id.data[4] & 0x80) /* !BENAND */) { 111 111 + !(chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) /* !BENAND */) { 166 112 memorg->oobsize = 32 * memorg->pagesize >> 9; 167 113 mtd->oobsize = memorg->oobsize; 168 114 }

+2 -2

drivers/mtd/nand/raw/nandsim.c

reviewed

··· 2251 2251 switch (bbt) { 2252 2252 case 2: 2253 2253 chip->bbt_options |= NAND_BBT_NO_OOB; 2254 2254 - /* fall through */ 2254 2254 + fallthrough; 2255 2255 case 1: 2256 2256 chip->bbt_options |= NAND_BBT_USE_FLASH; 2257 2257 - /* fall through */ 2257 2257 + fallthrough; 2258 2258 case 0: 2259 2259 break; 2260 2260 default:

+4 -4

drivers/mtd/nand/raw/omap_elm.c

reviewed

··· 455 455 ELM_SYNDROME_FRAGMENT_5 + offset); 456 456 regs->elm_syndrome_fragment_4[i] = elm_read_reg(info, 457 457 ELM_SYNDROME_FRAGMENT_4 + offset); 458 458 - /* fall through */ 458 458 + fallthrough; 459 459 case BCH8_ECC: 460 460 regs->elm_syndrome_fragment_3[i] = elm_read_reg(info, 461 461 ELM_SYNDROME_FRAGMENT_3 + offset); 462 462 regs->elm_syndrome_fragment_2[i] = elm_read_reg(info, 463 463 ELM_SYNDROME_FRAGMENT_2 + offset); 464 464 - /* fall through */ 464 464 + fallthrough; 465 465 case BCH4_ECC: 466 466 regs->elm_syndrome_fragment_1[i] = elm_read_reg(info, 467 467 ELM_SYNDROME_FRAGMENT_1 + offset); ··· 503 503 regs->elm_syndrome_fragment_5[i]); 504 504 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset, 505 505 regs->elm_syndrome_fragment_4[i]); 506 506 - /* fall through */ 506 506 + fallthrough; 507 507 case BCH8_ECC: 508 508 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_3 + offset, 509 509 regs->elm_syndrome_fragment_3[i]); 510 510 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_2 + offset, 511 511 regs->elm_syndrome_fragment_2[i]); 512 512 - /* fall through */ 512 512 + fallthrough; 513 513 case BCH4_ECC: 514 514 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_1 + offset, 515 515 regs->elm_syndrome_fragment_1[i]);

+64 -41

drivers/mtd/nand/raw/qcom_nandc.c

reviewed

··· 2628 2628 .attach_chip = qcom_nand_attach_chip, 2629 2629 }; 2630 2630 2631 2631 + static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) 2632 2632 + { 2633 2633 + if (nandc->props->is_bam) { 2634 2634 + if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) 2635 2635 + dma_unmap_single(nandc->dev, nandc->reg_read_dma, 2636 2636 + MAX_REG_RD * 2637 2637 + sizeof(*nandc->reg_read_buf), 2638 2638 + DMA_FROM_DEVICE); 2639 2639 + 2640 2640 + if (nandc->tx_chan) 2641 2641 + dma_release_channel(nandc->tx_chan); 2642 2642 + 2643 2643 + if (nandc->rx_chan) 2644 2644 + dma_release_channel(nandc->rx_chan); 2645 2645 + 2646 2646 + if (nandc->cmd_chan) 2647 2647 + dma_release_channel(nandc->cmd_chan); 2648 2648 + } else { 2649 2649 + if (nandc->chan) 2650 2650 + dma_release_channel(nandc->chan); 2651 2651 + } 2652 2652 + } 2653 2653 + 2631 2654 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) 2632 2655 { 2633 2656 int ret; ··· 2696 2673 return -EIO; 2697 2674 } 2698 2675 2699 2699 - nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx"); 2700 2700 - if (!nandc->tx_chan) { 2701 2701 - dev_err(nandc->dev, "failed to request tx channel\n"); 2702 2702 - return -ENODEV; 2676 2676 + nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); 2677 2677 + if (IS_ERR(nandc->tx_chan)) { 2678 2678 + ret = PTR_ERR(nandc->tx_chan); 2679 2679 + nandc->tx_chan = NULL; 2680 2680 + if (ret != -EPROBE_DEFER) 2681 2681 + dev_err(nandc->dev, 2682 2682 + "tx DMA channel request failed: %d\n", 2683 2683 + ret); 2684 2684 + goto unalloc; 2703 2685 } 2704 2686 2705 2705 - nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx"); 2706 2706 - if (!nandc->rx_chan) { 2707 2707 - dev_err(nandc->dev, "failed to request rx channel\n"); 2708 2708 - return -ENODEV; 2687 2687 + nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); 2688 2688 + if (IS_ERR(nandc->rx_chan)) { 2689 2689 + ret = PTR_ERR(nandc->rx_chan); 2690 2690 + nandc->rx_chan = NULL; 2691 2691 + if (ret != -EPROBE_DEFER) 2692 2692 + dev_err(nandc->dev, 2693 2693 + "rx DMA channel request failed: %d\n", 2694 2694 + ret); 2695 2695 + goto unalloc; 2709 2696 } 2710 2697 2711 2711 - nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd"); 2712 2712 - if (!nandc->cmd_chan) { 2713 2713 - dev_err(nandc->dev, "failed to request cmd channel\n"); 2714 2714 - return -ENODEV; 2698 2698 + nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); 2699 2699 + if (IS_ERR(nandc->cmd_chan)) { 2700 2700 + ret = PTR_ERR(nandc->cmd_chan); 2701 2701 + nandc->cmd_chan = NULL; 2702 2702 + if (ret != -EPROBE_DEFER) 2703 2703 + dev_err(nandc->dev, 2704 2704 + "cmd DMA channel request failed: %d\n", 2705 2705 + ret); 2706 2706 + goto unalloc; 2715 2707 } 2716 2708 2717 2709 /* ··· 2740 2702 if (!nandc->bam_txn) { 2741 2703 dev_err(nandc->dev, 2742 2704 "failed to allocate bam transaction\n"); 2743 2743 - return -ENOMEM; 2705 2705 + ret = -ENOMEM; 2706 2706 + goto unalloc; 2744 2707 } 2745 2708 } else { 2746 2746 - nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx"); 2747 2747 - if (!nandc->chan) { 2748 2748 - dev_err(nandc->dev, 2749 2749 - "failed to request slave channel\n"); 2750 2750 - return -ENODEV; 2709 2709 + nandc->chan = dma_request_chan(nandc->dev, "rxtx"); 2710 2710 + if (IS_ERR(nandc->chan)) { 2711 2711 + ret = PTR_ERR(nandc->chan); 2712 2712 + nandc->chan = NULL; 2713 2713 + if (ret != -EPROBE_DEFER) 2714 2714 + dev_err(nandc->dev, 2715 2715 + "rxtx DMA channel request failed: %d\n", 2716 2716 + ret); 2717 2717 + return ret; 2751 2718 } 2752 2719 } 2753 2720 ··· 2763 2720 nandc->controller.ops = &qcom_nandc_ops; 2764 2721 2765 2722 return 0; 2766 2766 - } 2767 2767 - 2768 2768 - static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) 2769 2769 - { 2770 2770 - if (nandc->props->is_bam) { 2771 2771 - if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) 2772 2772 - dma_unmap_single(nandc->dev, nandc->reg_read_dma, 2773 2773 - MAX_REG_RD * 2774 2774 - sizeof(*nandc->reg_read_buf), 2775 2775 - DMA_FROM_DEVICE); 2776 2776 - 2777 2777 - if (nandc->tx_chan) 2778 2778 - dma_release_channel(nandc->tx_chan); 2779 2779 - 2780 2780 - if (nandc->rx_chan) 2781 2781 - dma_release_channel(nandc->rx_chan); 2782 2782 - 2783 2783 - if (nandc->cmd_chan) 2784 2784 - dma_release_channel(nandc->cmd_chan); 2785 2785 - } else { 2786 2786 - if (nandc->chan) 2787 2787 - dma_release_channel(nandc->chan); 2788 2788 - } 2723 2723 + unalloc: 2724 2724 + qcom_nandc_unalloc(nandc); 2725 2725 + return ret; 2789 2726 } 2790 2727 2791 2728 /* one time setup of a few nand controller registers */

+37 -7

drivers/mtd/nand/raw/stm32_fmc2_nand.c

reviewed

··· 1606 1606 /* DMA configuration */ 1607 1607 static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2) 1608 1608 { 1609 1609 - int ret; 1609 1609 + int ret = 0; 1610 1610 1611 1611 - fmc2->dma_tx_ch = dma_request_slave_channel(fmc2->dev, "tx"); 1612 1612 - fmc2->dma_rx_ch = dma_request_slave_channel(fmc2->dev, "rx"); 1613 1613 - fmc2->dma_ecc_ch = dma_request_slave_channel(fmc2->dev, "ecc"); 1611 1611 + fmc2->dma_tx_ch = dma_request_chan(fmc2->dev, "tx"); 1612 1612 + if (IS_ERR(fmc2->dma_tx_ch)) { 1613 1613 + ret = PTR_ERR(fmc2->dma_tx_ch); 1614 1614 + if (ret != -ENODEV) 1615 1615 + dev_err(fmc2->dev, 1616 1616 + "failed to request tx DMA channel: %d\n", ret); 1617 1617 + fmc2->dma_tx_ch = NULL; 1618 1618 + goto err_dma; 1619 1619 + } 1614 1620 1615 1615 - if (!fmc2->dma_tx_ch || !fmc2->dma_rx_ch || !fmc2->dma_ecc_ch) { 1616 1616 - dev_warn(fmc2->dev, "DMAs not defined in the device tree, polling mode is used\n"); 1617 1617 - return 0; 1621 1621 + fmc2->dma_rx_ch = dma_request_chan(fmc2->dev, "rx"); 1622 1622 + if (IS_ERR(fmc2->dma_rx_ch)) { 1623 1623 + ret = PTR_ERR(fmc2->dma_rx_ch); 1624 1624 + if (ret != -ENODEV) 1625 1625 + dev_err(fmc2->dev, 1626 1626 + "failed to request rx DMA channel: %d\n", ret); 1627 1627 + fmc2->dma_rx_ch = NULL; 1628 1628 + goto err_dma; 1629 1629 + } 1630 1630 + 1631 1631 + fmc2->dma_ecc_ch = dma_request_chan(fmc2->dev, "ecc"); 1632 1632 + if (IS_ERR(fmc2->dma_ecc_ch)) { 1633 1633 + ret = PTR_ERR(fmc2->dma_ecc_ch); 1634 1634 + if (ret != -ENODEV) 1635 1635 + dev_err(fmc2->dev, 1636 1636 + "failed to request ecc DMA channel: %d\n", ret); 1637 1637 + fmc2->dma_ecc_ch = NULL; 1638 1638 + goto err_dma; 1618 1639 } 1619 1640 1620 1641 ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL); ··· 1656 1635 init_completion(&fmc2->dma_ecc_complete); 1657 1636 1658 1637 return 0; 1638 1638 + 1639 1639 + err_dma: 1640 1640 + if (ret == -ENODEV) { 1641 1641 + dev_warn(fmc2->dev, 1642 1642 + "DMAs not defined in the DT, polling mode is used\n"); 1643 1643 + ret = 0; 1644 1644 + } 1645 1645 + 1646 1646 + return ret; 1659 1647 } 1660 1648 1661 1649 /* NAND callbacks setup */

+11 -6

drivers/mtd/nand/raw/sunxi_nand.c

reviewed

··· 195 195 u32 timing_cfg; 196 196 u32 timing_ctl; 197 197 int nsels; 198 198 - struct sunxi_nand_chip_sel sels[0]; 198 198 + struct sunxi_nand_chip_sel sels[]; 199 199 }; 200 200 201 201 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) ··· 2123 2123 if (ret) 2124 2124 goto out_ahb_reset_reassert; 2125 2125 2126 2126 - nfc->dmac = dma_request_slave_channel(dev, "rxtx"); 2127 2127 - if (nfc->dmac) { 2126 2126 + nfc->dmac = dma_request_chan(dev, "rxtx"); 2127 2127 + if (IS_ERR(nfc->dmac)) { 2128 2128 + ret = PTR_ERR(nfc->dmac); 2129 2129 + if (ret == -EPROBE_DEFER) 2130 2130 + goto out_ahb_reset_reassert; 2131 2131 + 2132 2132 + /* Ignore errors to fall back to PIO mode */ 2133 2133 + dev_warn(dev, "failed to request rxtx DMA channel: %d\n", ret); 2134 2134 + nfc->dmac = NULL; 2135 2135 + } else { 2128 2136 struct dma_slave_config dmac_cfg = { }; 2129 2137 2130 2138 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data; ··· 2146 2138 if (nfc->caps->extra_mbus_conf) 2147 2139 writel(readl(nfc->regs + NFC_REG_CTL) | 2148 2140 NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL); 2149 2149 - 2150 2150 - } else { 2151 2151 - dev_warn(dev, "failed to request rxtx DMA channel\n"); 2152 2141 } 2153 2142 2154 2143 platform_set_drvdata(pdev, nfc);

+71 -33

drivers/mtd/nand/spi/core.c

reviewed

··· 16 16 #include <linux/mtd/spinand.h> 17 17 #include <linux/of.h> 18 18 #include <linux/slab.h> 19 19 + #include <linux/string.h> 19 20 #include <linux/spi/spi.h> 20 21 #include <linux/spi/spi-mem.h> 21 22 ··· 371 370 return status & STATUS_BUSY ? -ETIMEDOUT : 0; 372 371 } 373 372 374 374 - static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) 373 373 + static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, 374 374 + u8 ndummy, u8 *buf) 375 375 { 376 376 - struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, 377 377 - SPINAND_MAX_ID_LEN); 376 376 + struct spi_mem_op op = SPINAND_READID_OP( 377 377 + naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 378 378 int ret; 379 379 380 380 ret = spi_mem_exec_op(spinand->spimem, &op); ··· 570 568 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) 571 569 { 572 570 struct spinand_device *spinand = nand_to_spinand(nand); 571 571 + u8 marker[2] = { }; 573 572 struct nand_page_io_req req = { 574 573 .pos = *pos, 575 575 - .ooblen = 2, 574 574 + .ooblen = sizeof(marker), 576 575 .ooboffs = 0, 577 577 - .oobbuf.in = spinand->oobbuf, 576 576 + .oobbuf.in = marker, 578 577 .mode = MTD_OPS_RAW, 579 578 }; 580 579 581 581 - memset(spinand->oobbuf, 0, 2); 582 580 spinand_select_target(spinand, pos->target); 583 581 spinand_read_page(spinand, &req, false); 584 584 - if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff) 582 582 + if (marker[0] != 0xff || marker[1] != 0xff) 585 583 return true; 586 584 587 585 return false; ··· 605 603 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) 606 604 { 607 605 struct spinand_device *spinand = nand_to_spinand(nand); 606 606 + u8 marker[2] = { }; 608 607 struct nand_page_io_req req = { 609 608 .pos = *pos, 610 609 .ooboffs = 0, 611 611 - .ooblen = 2, 612 612 - .oobbuf.out = spinand->oobbuf, 610 610 + .ooblen = sizeof(marker), 611 611 + .oobbuf.out = marker, 612 612 + .mode = MTD_OPS_RAW, 613 613 }; 614 614 int ret; 615 615 616 616 - /* Erase block before marking it bad. */ 617 616 ret = spinand_select_target(spinand, pos->target); 618 617 if (ret) 619 618 return ret; ··· 623 620 if (ret) 624 621 return ret; 625 622 626 626 - spinand_erase_op(spinand, pos); 627 627 - 628 628 - memset(spinand->oobbuf, 0, 2); 629 623 return spinand_write_page(spinand, &req); 630 624 } 631 625 ··· 762 762 &winbond_spinand_manufacturer, 763 763 }; 764 764 765 765 - static int spinand_manufacturer_detect(struct spinand_device *spinand) 765 765 + static int spinand_manufacturer_match(struct spinand_device *spinand, 766 766 + enum spinand_readid_method rdid_method) 766 767 { 768 768 + u8 *id = spinand->id.data; 767 769 unsigned int i; 768 770 int ret; 769 771 770 772 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { 771 771 - ret = spinand_manufacturers[i]->ops->detect(spinand); 772 772 - if (ret > 0) { 773 773 - spinand->manufacturer = spinand_manufacturers[i]; 774 774 - return 0; 775 775 - } else if (ret < 0) { 776 776 - return ret; 777 777 - } 778 778 - } 773 773 + const struct spinand_manufacturer *manufacturer = 774 774 + spinand_manufacturers[i]; 779 775 776 776 + if (id[0] != manufacturer->id) 777 777 + continue; 778 778 + 779 779 + ret = spinand_match_and_init(spinand, 780 780 + manufacturer->chips, 781 781 + manufacturer->nchips, 782 782 + rdid_method); 783 783 + if (ret < 0) 784 784 + continue; 785 785 + 786 786 + spinand->manufacturer = manufacturer; 787 787 + return 0; 788 788 + } 780 789 return -ENOTSUPP; 790 790 + } 791 791 + 792 792 + static int spinand_id_detect(struct spinand_device *spinand) 793 793 + { 794 794 + u8 *id = spinand->id.data; 795 795 + int ret; 796 796 + 797 797 + ret = spinand_read_id_op(spinand, 0, 0, id); 798 798 + if (ret) 799 799 + return ret; 800 800 + ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); 801 801 + if (!ret) 802 802 + return 0; 803 803 + 804 804 + ret = spinand_read_id_op(spinand, 1, 0, id); 805 805 + if (ret) 806 806 + return ret; 807 807 + ret = spinand_manufacturer_match(spinand, 808 808 + SPINAND_READID_METHOD_OPCODE_ADDR); 809 809 + if (!ret) 810 810 + return 0; 811 811 + 812 812 + ret = spinand_read_id_op(spinand, 0, 1, id); 813 813 + if (ret) 814 814 + return ret; 815 815 + ret = spinand_manufacturer_match(spinand, 816 816 + SPINAND_READID_METHOD_OPCODE_DUMMY); 817 817 + 818 818 + return ret; 781 819 } 782 820 783 821 static int spinand_manufacturer_init(struct spinand_device *spinand) ··· 873 835 * @spinand: SPI NAND object 874 836 * @table: SPI NAND device description table 875 837 * @table_size: size of the device description table 838 838 + * @rdid_method: read id method to match 876 839 * 877 877 - * Should be used by SPI NAND manufacturer drivers when they want to find a 878 878 - * match between a device ID retrieved through the READ_ID command and an 840 840 + * Match between a device ID retrieved through the READ_ID command and an 879 841 * entry in the SPI NAND description table. If a match is found, the spinand 880 842 * object will be initialized with information provided by the matching 881 843 * spinand_info entry. ··· 884 846 */ 885 847 int spinand_match_and_init(struct spinand_device *spinand, 886 848 const struct spinand_info *table, 887 887 - unsigned int table_size, u16 devid) 849 849 + unsigned int table_size, 850 850 + enum spinand_readid_method rdid_method) 888 851 { 852 852 + u8 *id = spinand->id.data; 889 853 struct nand_device *nand = spinand_to_nand(spinand); 890 854 unsigned int i; 891 855 ··· 895 855 const struct spinand_info *info = &table[i]; 896 856 const struct spi_mem_op *op; 897 857 898 898 - if (devid != info->devid) 858 858 + if (rdid_method != info->devid.method) 859 859 + continue; 860 860 + 861 861 + if (memcmp(id + 1, info->devid.id, info->devid.len)) 899 862 continue; 900 863 901 864 nand->memorg = table[i].memorg; 902 865 nand->eccreq = table[i].eccreq; 903 866 spinand->eccinfo = table[i].eccinfo; 904 867 spinand->flags = table[i].flags; 868 868 + spinand->id.len = 1 + table[i].devid.len; 905 869 spinand->select_target = table[i].select_target; 906 870 907 871 op = spinand_select_op_variant(spinand, ··· 942 898 if (ret) 943 899 return ret; 944 900 945 945 - ret = spinand_read_id_op(spinand, spinand->id.data); 946 946 - if (ret) 947 947 - return ret; 948 948 - 949 949 - spinand->id.len = SPINAND_MAX_ID_LEN; 950 950 - 951 951 - ret = spinand_manufacturer_detect(spinand); 901 901 + ret = spinand_id_detect(spinand); 952 902 if (ret) { 953 903 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN, 954 904 spinand->id.data);

+12 -33

drivers/mtd/nand/spi/gigadevice.c

reviewed

··· 195 195 } 196 196 197 197 static const struct spinand_info gigadevice_spinand_table[] = { 198 198 - SPINAND_INFO("GD5F1GQ4xA", 0xF1, 198 198 + SPINAND_INFO("GD5F1GQ4xA", 199 199 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), 199 200 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 200 201 NAND_ECCREQ(8, 512), 201 202 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 205 204 0, 206 205 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 207 206 gd5fxgq4xa_ecc_get_status)), 208 208 - SPINAND_INFO("GD5F2GQ4xA", 0xF2, 207 207 + SPINAND_INFO("GD5F2GQ4xA", 208 208 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), 209 209 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), 210 210 NAND_ECCREQ(8, 512), 211 211 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 215 213 0, 216 214 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 217 215 gd5fxgq4xa_ecc_get_status)), 218 218 - SPINAND_INFO("GD5F4GQ4xA", 0xF4, 216 216 + SPINAND_INFO("GD5F4GQ4xA", 217 217 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), 219 218 NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1), 220 219 NAND_ECCREQ(8, 512), 221 220 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 225 222 0, 226 223 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 227 224 gd5fxgq4xa_ecc_get_status)), 228 228 - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, 225 225 + SPINAND_INFO("GD5F1GQ4UExxG", 226 226 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), 229 227 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 230 228 NAND_ECCREQ(8, 512), 231 229 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 235 231 0, 236 232 SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, 237 233 gd5fxgq4uexxg_ecc_get_status)), 238 238 - SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, 234 234 + SPINAND_INFO("GD5F1GQ4UFxxG", 235 235 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), 239 236 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 240 237 NAND_ECCREQ(8, 512), 241 238 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ··· 247 242 gd5fxgq4ufxxg_ecc_get_status)), 248 243 }; 249 244 250 250 - static int gigadevice_spinand_detect(struct spinand_device *spinand) 251 251 - { 252 252 - u8 *id = spinand->id.data; 253 253 - u16 did; 254 254 - int ret; 255 255 - 256 256 - /* 257 257 - * Earlier GDF5-series devices (A,E) return [0][MID][DID] 258 258 - * Later (F) devices return [MID][DID1][DID2] 259 259 - */ 260 260 - 261 261 - if (id[0] == SPINAND_MFR_GIGADEVICE) 262 262 - did = (id[1] << 8) + id[2]; 263 263 - else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE) 264 264 - did = id[2]; 265 265 - else 266 266 - return 0; 267 267 - 268 268 - ret = spinand_match_and_init(spinand, gigadevice_spinand_table, 269 269 - ARRAY_SIZE(gigadevice_spinand_table), 270 270 - did); 271 271 - if (ret) 272 272 - return ret; 273 273 - 274 274 - return 1; 275 275 - } 276 276 - 277 245 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { 278 278 - .detect = gigadevice_spinand_detect, 279 246 }; 280 247 281 248 const struct spinand_manufacturer gigadevice_spinand_manufacturer = { 282 249 .id = SPINAND_MFR_GIGADEVICE, 283 250 .name = "GigaDevice", 251 251 + .chips = gigadevice_spinand_table, 252 252 + .nchips = ARRAY_SIZE(gigadevice_spinand_table), 284 253 .ops = &gigadevice_spinand_manuf_ops, 285 254 };

+6 -24

drivers/mtd/nand/spi/macronix.c

reviewed

··· 99 99 } 100 100 101 101 static const struct spinand_info macronix_spinand_table[] = { 102 102 - SPINAND_INFO("MX35LF1GE4AB", 0x12, 102 102 + SPINAND_INFO("MX35LF1GE4AB", 103 103 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), 103 104 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 104 105 NAND_ECCREQ(4, 512), 105 106 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 109 108 SPINAND_HAS_QE_BIT, 110 109 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, 111 110 mx35lf1ge4ab_ecc_get_status)), 112 112 - SPINAND_INFO("MX35LF2GE4AB", 0x22, 111 111 + SPINAND_INFO("MX35LF2GE4AB", 112 112 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), 113 113 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), 114 114 NAND_ECCREQ(4, 512), 115 115 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 120 118 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), 121 119 }; 122 120 123 123 - static int macronix_spinand_detect(struct spinand_device *spinand) 124 124 - { 125 125 - u8 *id = spinand->id.data; 126 126 - int ret; 127 127 - 128 128 - /* 129 129 - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in 130 130 - * raw_id is garbage. 131 131 - */ 132 132 - if (id[1] != SPINAND_MFR_MACRONIX) 133 133 - return 0; 134 134 - 135 135 - ret = spinand_match_and_init(spinand, macronix_spinand_table, 136 136 - ARRAY_SIZE(macronix_spinand_table), 137 137 - id[2]); 138 138 - if (ret) 139 139 - return ret; 140 140 - 141 141 - return 1; 142 142 - } 143 143 - 144 121 static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { 145 145 - .detect = macronix_spinand_detect, 146 122 }; 147 123 148 124 const struct spinand_manufacturer macronix_spinand_manufacturer = { 149 125 .id = SPINAND_MFR_MACRONIX, 150 126 .name = "Macronix", 127 127 + .chips = macronix_spinand_table, 128 128 + .nchips = ARRAY_SIZE(macronix_spinand_table), 151 129 .ops = &macronix_spinand_manuf_ops, 152 130 };

+142 -30

drivers/mtd/nand/spi/micron.c

reviewed

··· 18 18 #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) 19 19 #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) 20 20 21 21 + #define MICRON_CFG_CR BIT(0) 22 22 + 23 23 + /* 24 24 + * As per datasheet, die selection is done by the 6th bit of Die 25 25 + * Select Register (Address 0xD0). 26 26 + */ 27 27 + #define MICRON_DIE_SELECT_REG 0xD0 28 28 + 29 29 + #define MICRON_SELECT_DIE(x) ((x) << 6) 30 30 + 21 31 static SPINAND_OP_VARIANTS(read_cache_variants, 22 32 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), 23 33 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ··· 44 34 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), 45 35 SPINAND_PROG_LOAD(false, 0, NULL, 0)); 46 36 47 47 - static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section, 48 48 - struct mtd_oob_region *region) 37 37 + static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section, 38 38 + struct mtd_oob_region *region) 49 39 { 50 40 if (section) 51 41 return -ERANGE; 52 42 53 53 - region->offset = 64; 54 54 - region->length = 64; 43 43 + region->offset = mtd->oobsize / 2; 44 44 + region->length = mtd->oobsize / 2; 55 45 56 46 return 0; 57 47 } 58 48 59 59 - static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section, 60 60 - struct mtd_oob_region *region) 49 49 + static int micron_8_ooblayout_free(struct mtd_info *mtd, int section, 50 50 + struct mtd_oob_region *region) 61 51 { 62 52 if (section) 63 53 return -ERANGE; 64 54 65 55 /* Reserve 2 bytes for the BBM. */ 66 56 region->offset = 2; 67 67 - region->length = 62; 57 57 + region->length = (mtd->oobsize / 2) - 2; 68 58 69 59 return 0; 70 60 } 71 61 72 72 - static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = { 73 73 - .ecc = mt29f2g01abagd_ooblayout_ecc, 74 74 - .free = mt29f2g01abagd_ooblayout_free, 62 62 + static const struct mtd_ooblayout_ops micron_8_ooblayout = { 63 63 + .ecc = micron_8_ooblayout_ecc, 64 64 + .free = micron_8_ooblayout_free, 75 65 }; 76 66 77 77 - static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand, 78 78 - u8 status) 67 67 + static int micron_select_target(struct spinand_device *spinand, 68 68 + unsigned int target) 69 69 + { 70 70 + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, 71 71 + spinand->scratchbuf); 72 72 + 73 73 + if (target > 1) 74 74 + return -EINVAL; 75 75 + 76 76 + *spinand->scratchbuf = MICRON_SELECT_DIE(target); 77 77 + 78 78 + return spi_mem_exec_op(spinand->spimem, &op); 79 79 + } 80 80 + 81 81 + static int micron_8_ecc_get_status(struct spinand_device *spinand, 82 82 + u8 status) 79 83 { 80 84 switch (status & MICRON_STATUS_ECC_MASK) { 81 85 case STATUS_ECC_NO_BITFLIPS: ··· 115 91 } 116 92 117 93 static const struct spinand_info micron_spinand_table[] = { 118 118 - SPINAND_INFO("MT29F2G01ABAGD", 0x24, 94 94 + /* M79A 2Gb 3.3V */ 95 95 + SPINAND_INFO("MT29F2G01ABAGD", 96 96 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), 119 97 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), 120 98 NAND_ECCREQ(8, 512), 121 99 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 122 100 &write_cache_variants, 123 101 &update_cache_variants), 124 102 0, 125 125 - SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout, 126 126 - mt29f2g01abagd_ecc_get_status)), 103 103 + SPINAND_ECCINFO(&micron_8_ooblayout, 104 104 + micron_8_ecc_get_status)), 105 105 + /* M79A 2Gb 1.8V */ 106 106 + SPINAND_INFO("MT29F2G01ABBGD", 107 107 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), 108 108 + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), 109 109 + NAND_ECCREQ(8, 512), 110 110 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 111 111 + &write_cache_variants, 112 112 + &update_cache_variants), 113 113 + 0, 114 114 + SPINAND_ECCINFO(&micron_8_ooblayout, 115 115 + micron_8_ecc_get_status)), 116 116 + /* M78A 1Gb 3.3V */ 117 117 + SPINAND_INFO("MT29F1G01ABAFD", 118 118 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), 119 119 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 120 120 + NAND_ECCREQ(8, 512), 121 121 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 122 122 + &write_cache_variants, 123 123 + &update_cache_variants), 124 124 + 0, 125 125 + SPINAND_ECCINFO(&micron_8_ooblayout, 126 126 + micron_8_ecc_get_status)), 127 127 + /* M78A 1Gb 1.8V */ 128 128 + SPINAND_INFO("MT29F1G01ABAFD", 129 129 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), 130 130 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 131 131 + NAND_ECCREQ(8, 512), 132 132 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 133 133 + &write_cache_variants, 134 134 + &update_cache_variants), 135 135 + 0, 136 136 + SPINAND_ECCINFO(&micron_8_ooblayout, 137 137 + micron_8_ecc_get_status)), 138 138 + /* M79A 4Gb 3.3V */ 139 139 + SPINAND_INFO("MT29F4G01ADAGD", 140 140 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), 141 141 + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), 142 142 + NAND_ECCREQ(8, 512), 143 143 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 144 144 + &write_cache_variants, 145 145 + &update_cache_variants), 146 146 + 0, 147 147 + SPINAND_ECCINFO(&micron_8_ooblayout, 148 148 + micron_8_ecc_get_status), 149 149 + SPINAND_SELECT_TARGET(micron_select_target)), 150 150 + /* M70A 4Gb 3.3V */ 151 151 + SPINAND_INFO("MT29F4G01ABAFD", 152 152 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), 153 153 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 154 154 + NAND_ECCREQ(8, 512), 155 155 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 156 156 + &write_cache_variants, 157 157 + &update_cache_variants), 158 158 + SPINAND_HAS_CR_FEAT_BIT, 159 159 + SPINAND_ECCINFO(&micron_8_ooblayout, 160 160 + micron_8_ecc_get_status)), 161 161 + /* M70A 4Gb 1.8V */ 162 162 + SPINAND_INFO("MT29F4G01ABBFD", 163 163 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), 164 164 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 165 165 + NAND_ECCREQ(8, 512), 166 166 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 167 167 + &write_cache_variants, 168 168 + &update_cache_variants), 169 169 + SPINAND_HAS_CR_FEAT_BIT, 170 170 + SPINAND_ECCINFO(&micron_8_ooblayout, 171 171 + micron_8_ecc_get_status)), 172 172 + /* M70A 8Gb 3.3V */ 173 173 + SPINAND_INFO("MT29F8G01ADAFD", 174 174 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), 175 175 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), 176 176 + NAND_ECCREQ(8, 512), 177 177 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 178 178 + &write_cache_variants, 179 179 + &update_cache_variants), 180 180 + SPINAND_HAS_CR_FEAT_BIT, 181 181 + SPINAND_ECCINFO(&micron_8_ooblayout, 182 182 + micron_8_ecc_get_status), 183 183 + SPINAND_SELECT_TARGET(micron_select_target)), 184 184 + /* M70A 8Gb 1.8V */ 185 185 + SPINAND_INFO("MT29F8G01ADBFD", 186 186 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), 187 187 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), 188 188 + NAND_ECCREQ(8, 512), 189 189 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 190 190 + &write_cache_variants, 191 191 + &update_cache_variants), 192 192 + SPINAND_HAS_CR_FEAT_BIT, 193 193 + SPINAND_ECCINFO(&micron_8_ooblayout, 194 194 + micron_8_ecc_get_status), 195 195 + SPINAND_SELECT_TARGET(micron_select_target)), 127 196 }; 128 197 129 129 - static int micron_spinand_detect(struct spinand_device *spinand) 198 198 + static int micron_spinand_init(struct spinand_device *spinand) 130 199 { 131 131 - u8 *id = spinand->id.data; 132 132 - int ret; 133 133 - 134 200 /* 135 135 - * Micron SPI NAND read ID need a dummy byte, 136 136 - * so the first byte in raw_id is dummy. 201 201 + * M70A device series enable Continuous Read feature at Power-up, 202 202 + * which is not supported. Disable this bit to avoid any possible 203 203 + * failure. 137 204 */ 138 138 - if (id[1] != SPINAND_MFR_MICRON) 139 139 - return 0; 205 205 + if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT) 206 206 + return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0); 140 207 141 141 - ret = spinand_match_and_init(spinand, micron_spinand_table, 142 142 - ARRAY_SIZE(micron_spinand_table), id[2]); 143 143 - if (ret) 144 144 - return ret; 145 145 - 146 146 - return 1; 208 208 + return 0; 147 209 } 148 210 149 211 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { 150 150 - .detect = micron_spinand_detect, 212 212 + .init = micron_spinand_init, 151 213 }; 152 214 153 215 const struct spinand_manufacturer micron_spinand_manufacturer = { 154 216 .id = SPINAND_MFR_MICRON, 155 217 .name = "Micron", 218 218 + .chips = micron_spinand_table, 219 219 + .nchips = ARRAY_SIZE(micron_spinand_table), 156 220 .ops = &micron_spinand_manuf_ops, 157 221 };

+6 -22

drivers/mtd/nand/spi/paragon.c

reviewed

··· 97 97 98 98 99 99 static const struct spinand_info paragon_spinand_table[] = { 100 100 - SPINAND_INFO("PN26G01A", 0xe1, 100 100 + SPINAND_INFO("PN26G01A", 101 101 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1), 101 102 NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1), 102 103 NAND_ECCREQ(8, 512), 103 104 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 107 106 0, 108 107 SPINAND_ECCINFO(&pn26g0xa_ooblayout, 109 108 pn26g0xa_ecc_get_status)), 110 110 - SPINAND_INFO("PN26G02A", 0xe2, 109 109 + SPINAND_INFO("PN26G02A", 110 110 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2), 111 111 NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1), 112 112 NAND_ECCREQ(8, 512), 113 113 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 119 117 pn26g0xa_ecc_get_status)), 120 118 }; 121 119 122 122 - static int paragon_spinand_detect(struct spinand_device *spinand) 123 123 - { 124 124 - u8 *id = spinand->id.data; 125 125 - int ret; 126 126 - 127 127 - /* Read ID returns [0][MID][DID] */ 128 128 - 129 129 - if (id[1] != SPINAND_MFR_PARAGON) 130 130 - return 0; 131 131 - 132 132 - ret = spinand_match_and_init(spinand, paragon_spinand_table, 133 133 - ARRAY_SIZE(paragon_spinand_table), 134 134 - id[2]); 135 135 - if (ret) 136 136 - return ret; 137 137 - 138 138 - return 1; 139 139 - } 140 140 - 141 120 static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = { 142 142 - .detect = paragon_spinand_detect, 143 121 }; 144 122 145 123 const struct spinand_manufacturer paragon_spinand_manufacturer = { 146 124 .id = SPINAND_MFR_PARAGON, 147 125 .name = "Paragon", 126 126 + .chips = paragon_spinand_table, 127 127 + .nchips = ARRAY_SIZE(paragon_spinand_table), 148 128 .ops = &paragon_spinand_manuf_ops, 149 129 };

+145 -63

drivers/mtd/nand/spi/toshiba.c

reviewed

··· 10 10 #include <linux/kernel.h> 11 11 #include <linux/mtd/spinand.h> 12 12 13 13 + /* Kioxia is new name of Toshiba memory. */ 13 14 #define SPINAND_MFR_TOSHIBA 0x98 14 15 #define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) 15 16 ··· 20 19 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), 21 20 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); 22 21 22 22 + static SPINAND_OP_VARIANTS(write_cache_x4_variants, 23 23 + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), 24 24 + SPINAND_PROG_LOAD(true, 0, NULL, 0)); 25 25 + 26 26 + static SPINAND_OP_VARIANTS(update_cache_x4_variants, 27 27 + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), 28 28 + SPINAND_PROG_LOAD(false, 0, NULL, 0)); 29 29 + 30 30 + /** 31 31 + * Backward compatibility for 1st generation Serial NAND devices 32 32 + * which don't support Quad Program Load operation. 33 33 + */ 23 34 static SPINAND_OP_VARIANTS(write_cache_variants, 24 35 SPINAND_PROG_LOAD(true, 0, NULL, 0)); 25 36 26 37 static SPINAND_OP_VARIANTS(update_cache_variants, 27 38 SPINAND_PROG_LOAD(false, 0, NULL, 0)); 28 39 29 29 - static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section, 30 30 - struct mtd_oob_region *region) 40 40 + static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section, 41 41 + struct mtd_oob_region *region) 31 42 { 32 43 if (section > 0) 33 44 return -ERANGE; ··· 50 37 return 0; 51 38 } 52 39 53 53 - static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section, 54 54 - struct mtd_oob_region *region) 40 40 + static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section, 41 41 + struct mtd_oob_region *region) 55 42 { 56 43 if (section > 0) 57 44 return -ERANGE; ··· 63 50 return 0; 64 51 } 65 52 66 66 - static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = { 67 67 - .ecc = tc58cxgxsx_ooblayout_ecc, 68 68 - .free = tc58cxgxsx_ooblayout_free, 53 53 + static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = { 54 54 + .ecc = tx58cxgxsxraix_ooblayout_ecc, 55 55 + .free = tx58cxgxsxraix_ooblayout_free, 69 56 }; 70 57 71 71 - static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, 72 72 - u8 status) 58 58 + static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, 59 59 + u8 status) 73 60 { 74 61 struct nand_device *nand = spinand_to_nand(spinand); 75 62 u8 mbf = 0; ··· 107 94 } 108 95 109 96 static const struct spinand_info toshiba_spinand_table[] = { 110 110 - /* 3.3V 1Gb */ 111 111 - SPINAND_INFO("TC58CVG0S3", 0xC2, 97 97 + /* 3.3V 1Gb (1st generation) */ 98 98 + SPINAND_INFO("TC58CVG0S3HRAIG", 99 99 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), 112 100 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 113 101 NAND_ECCREQ(8, 512), 114 102 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 115 103 &write_cache_variants, 116 104 &update_cache_variants), 117 105 0, 118 118 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 119 119 - tc58cxgxsx_ecc_get_status)), 120 120 - /* 3.3V 2Gb */ 121 121 - SPINAND_INFO("TC58CVG1S3", 0xCB, 106 106 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 107 107 + tx58cxgxsxraix_ecc_get_status)), 108 108 + /* 3.3V 2Gb (1st generation) */ 109 109 + SPINAND_INFO("TC58CVG1S3HRAIG", 110 110 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), 122 111 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 123 112 NAND_ECCREQ(8, 512), 124 113 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 125 114 &write_cache_variants, 126 115 &update_cache_variants), 127 116 0, 128 128 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 129 129 - tc58cxgxsx_ecc_get_status)), 130 130 - /* 3.3V 4Gb */ 131 131 - SPINAND_INFO("TC58CVG2S0", 0xCD, 117 117 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 118 118 + tx58cxgxsxraix_ecc_get_status)), 119 119 + /* 3.3V 4Gb (1st generation) */ 120 120 + SPINAND_INFO("TC58CVG2S0HRAIG", 121 121 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), 132 122 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 133 123 NAND_ECCREQ(8, 512), 134 124 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 135 125 &write_cache_variants, 136 126 &update_cache_variants), 137 127 0, 138 138 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 139 139 - tc58cxgxsx_ecc_get_status)), 140 140 - /* 3.3V 4Gb */ 141 141 - SPINAND_INFO("TC58CVG2S0", 0xED, 142 142 - NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 143 143 - NAND_ECCREQ(8, 512), 144 144 - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 145 145 - &write_cache_variants, 146 146 - &update_cache_variants), 147 147 - 0, 148 148 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 149 149 - tc58cxgxsx_ecc_get_status)), 150 150 - /* 1.8V 1Gb */ 151 151 - SPINAND_INFO("TC58CYG0S3", 0xB2, 128 128 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 129 129 + tx58cxgxsxraix_ecc_get_status)), 130 130 + /* 1.8V 1Gb (1st generation) */ 131 131 + SPINAND_INFO("TC58CYG0S3HRAIG", 132 132 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), 152 133 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 153 134 NAND_ECCREQ(8, 512), 154 135 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 155 136 &write_cache_variants, 156 137 &update_cache_variants), 157 138 0, 158 158 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 159 159 - tc58cxgxsx_ecc_get_status)), 160 160 - /* 1.8V 2Gb */ 161 161 - SPINAND_INFO("TC58CYG1S3", 0xBB, 139 139 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 140 140 + tx58cxgxsxraix_ecc_get_status)), 141 141 + /* 1.8V 2Gb (1st generation) */ 142 142 + SPINAND_INFO("TC58CYG1S3HRAIG", 143 143 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), 162 144 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 163 145 NAND_ECCREQ(8, 512), 164 146 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 165 147 &write_cache_variants, 166 148 &update_cache_variants), 167 149 0, 168 168 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 169 169 - tc58cxgxsx_ecc_get_status)), 170 170 - /* 1.8V 4Gb */ 171 171 - SPINAND_INFO("TC58CYG2S0", 0xBD, 150 150 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 151 151 + tx58cxgxsxraix_ecc_get_status)), 152 152 + /* 1.8V 4Gb (1st generation) */ 153 153 + SPINAND_INFO("TC58CYG2S0HRAIG", 154 154 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), 172 155 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 173 156 NAND_ECCREQ(8, 512), 174 157 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 175 158 &write_cache_variants, 176 159 &update_cache_variants), 177 160 0, 178 178 - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, 179 179 - tc58cxgxsx_ecc_get_status)), 180 180 - }; 181 181 - 182 182 - static int toshiba_spinand_detect(struct spinand_device *spinand) 183 183 - { 184 184 - u8 *id = spinand->id.data; 185 185 - int ret; 161 161 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 162 162 + tx58cxgxsxraix_ecc_get_status)), 186 163 187 164 /* 188 188 - * Toshiba SPI NAND read ID needs a dummy byte, 189 189 - * so the first byte in id is garbage. 165 165 + * 2nd generation serial nand has HOLD_D which is equivalent to 166 166 + * QE_BIT. 190 167 */ 191 191 - if (id[1] != SPINAND_MFR_TOSHIBA) 192 192 - return 0; 193 193 - 194 194 - ret = spinand_match_and_init(spinand, toshiba_spinand_table, 195 195 - ARRAY_SIZE(toshiba_spinand_table), 196 196 - id[2]); 197 197 - if (ret) 198 198 - return ret; 199 199 - 200 200 - return 1; 201 201 - } 168 168 + /* 3.3V 1Gb (2nd generation) */ 169 169 + SPINAND_INFO("TC58CVG0S3HRAIJ", 170 170 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), 171 171 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 172 172 + NAND_ECCREQ(8, 512), 173 173 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 174 174 + &write_cache_x4_variants, 175 175 + &update_cache_x4_variants), 176 176 + SPINAND_HAS_QE_BIT, 177 177 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 178 178 + tx58cxgxsxraix_ecc_get_status)), 179 179 + /* 3.3V 2Gb (2nd generation) */ 180 180 + SPINAND_INFO("TC58CVG1S3HRAIJ", 181 181 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), 182 182 + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 183 183 + NAND_ECCREQ(8, 512), 184 184 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 185 185 + &write_cache_x4_variants, 186 186 + &update_cache_x4_variants), 187 187 + SPINAND_HAS_QE_BIT, 188 188 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 189 189 + tx58cxgxsxraix_ecc_get_status)), 190 190 + /* 3.3V 4Gb (2nd generation) */ 191 191 + SPINAND_INFO("TC58CVG2S0HRAIJ", 192 192 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), 193 193 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 194 194 + NAND_ECCREQ(8, 512), 195 195 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 196 196 + &write_cache_x4_variants, 197 197 + &update_cache_x4_variants), 198 198 + SPINAND_HAS_QE_BIT, 199 199 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 200 200 + tx58cxgxsxraix_ecc_get_status)), 201 201 + /* 3.3V 8Gb (2nd generation) */ 202 202 + SPINAND_INFO("TH58CVG3S0HRAIJ", 203 203 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), 204 204 + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), 205 205 + NAND_ECCREQ(8, 512), 206 206 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 207 207 + &write_cache_x4_variants, 208 208 + &update_cache_x4_variants), 209 209 + SPINAND_HAS_QE_BIT, 210 210 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 211 211 + tx58cxgxsxraix_ecc_get_status)), 212 212 + /* 1.8V 1Gb (2nd generation) */ 213 213 + SPINAND_INFO("TC58CYG0S3HRAIJ", 214 214 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), 215 215 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 216 216 + NAND_ECCREQ(8, 512), 217 217 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 218 218 + &write_cache_x4_variants, 219 219 + &update_cache_x4_variants), 220 220 + SPINAND_HAS_QE_BIT, 221 221 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 222 222 + tx58cxgxsxraix_ecc_get_status)), 223 223 + /* 1.8V 2Gb (2nd generation) */ 224 224 + SPINAND_INFO("TC58CYG1S3HRAIJ", 225 225 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), 226 226 + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 227 227 + NAND_ECCREQ(8, 512), 228 228 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 229 229 + &write_cache_x4_variants, 230 230 + &update_cache_x4_variants), 231 231 + SPINAND_HAS_QE_BIT, 232 232 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 233 233 + tx58cxgxsxraix_ecc_get_status)), 234 234 + /* 1.8V 4Gb (2nd generation) */ 235 235 + SPINAND_INFO("TC58CYG2S0HRAIJ", 236 236 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), 237 237 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 238 238 + NAND_ECCREQ(8, 512), 239 239 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 240 240 + &write_cache_x4_variants, 241 241 + &update_cache_x4_variants), 242 242 + SPINAND_HAS_QE_BIT, 243 243 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 244 244 + tx58cxgxsxraix_ecc_get_status)), 245 245 + /* 1.8V 8Gb (2nd generation) */ 246 246 + SPINAND_INFO("TH58CYG3S0HRAIJ", 247 247 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), 248 248 + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), 249 249 + NAND_ECCREQ(8, 512), 250 250 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 251 251 + &write_cache_x4_variants, 252 252 + &update_cache_x4_variants), 253 253 + SPINAND_HAS_QE_BIT, 254 254 + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, 255 255 + tx58cxgxsxraix_ecc_get_status)), 256 256 + }; 202 257 203 258 static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { 204 204 - .detect = toshiba_spinand_detect, 205 259 }; 206 260 207 261 const struct spinand_manufacturer toshiba_spinand_manufacturer = { 208 262 .id = SPINAND_MFR_TOSHIBA, 209 263 .name = "Toshiba", 264 264 + .chips = toshiba_spinand_table, 265 265 + .nchips = ARRAY_SIZE(toshiba_spinand_table), 210 266 .ops = &toshiba_spinand_manuf_ops, 211 267 };

+6 -28

drivers/mtd/nand/spi/winbond.c

reviewed

··· 75 75 } 76 76 77 77 static const struct spinand_info winbond_spinand_table[] = { 78 78 - SPINAND_INFO("W25M02GV", 0xAB, 78 78 + SPINAND_INFO("W25M02GV", 79 79 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab), 79 80 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2), 80 81 NAND_ECCREQ(1, 512), 81 82 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 85 84 0, 86 85 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), 87 86 SPINAND_SELECT_TARGET(w25m02gv_select_target)), 88 88 - SPINAND_INFO("W25N01GV", 0xAA, 87 87 + SPINAND_INFO("W25N01GV", 88 88 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa), 89 89 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 90 90 NAND_ECCREQ(1, 512), 91 91 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ··· 95 93 0, 96 94 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), 97 95 }; 98 98 - 99 99 - /** 100 100 - * winbond_spinand_detect - initialize device related part in spinand_device 101 101 - * struct if it is a Winbond device. 102 102 - * @spinand: SPI NAND device structure 103 103 - */ 104 104 - static int winbond_spinand_detect(struct spinand_device *spinand) 105 105 - { 106 106 - u8 *id = spinand->id.data; 107 107 - int ret; 108 108 - 109 109 - /* 110 110 - * Winbond SPI NAND read ID need a dummy byte, 111 111 - * so the first byte in raw_id is dummy. 112 112 - */ 113 113 - if (id[1] != SPINAND_MFR_WINBOND) 114 114 - return 0; 115 115 - 116 116 - ret = spinand_match_and_init(spinand, winbond_spinand_table, 117 117 - ARRAY_SIZE(winbond_spinand_table), id[2]); 118 118 - if (ret) 119 119 - return ret; 120 120 - 121 121 - return 1; 122 122 - } 123 96 124 97 static int winbond_spinand_init(struct spinand_device *spinand) 125 98 { ··· 115 138 } 116 139 117 140 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { 118 118 - .detect = winbond_spinand_detect, 119 141 .init = winbond_spinand_init, 120 142 }; 121 143 122 144 const struct spinand_manufacturer winbond_spinand_manufacturer = { 123 145 .id = SPINAND_MFR_WINBOND, 124 146 .name = "Winbond", 147 147 + .chips = winbond_spinand_table, 148 148 + .nchips = ARRAY_SIZE(winbond_spinand_table), 125 149 .ops = &winbond_spinand_manuf_ops, 126 150 };

+1 -74

drivers/mtd/spi-nor/Kconfig

reviewed

··· 24 24 Please note that some tools/drivers/filesystems may not work with 25 25 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). 26 26 27 27 - config SPI_ASPEED_SMC 28 28 - tristate "Aspeed flash controllers in SPI mode" 29 29 - depends on ARCH_ASPEED || COMPILE_TEST 30 30 - depends on HAS_IOMEM && OF 31 31 - help 32 32 - This enables support for the Firmware Memory controller (FMC) 33 33 - in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips, 34 34 - and support for the SPI flash memory controller (SPI) for 35 35 - the host firmware. The implementation only supports SPI NOR. 36 36 - 37 37 - config SPI_CADENCE_QUADSPI 38 38 - tristate "Cadence Quad SPI controller" 39 39 - depends on OF && (ARM || ARM64 || COMPILE_TEST) 40 40 - help 41 41 - Enable support for the Cadence Quad SPI Flash controller. 42 42 - 43 43 - Cadence QSPI is a specialized controller for connecting an SPI 44 44 - Flash over 1/2/4-bit wide bus. Enable this option if you have a 45 45 - device with a Cadence QSPI controller and want to access the 46 46 - Flash as an MTD device. 47 47 - 48 48 - config SPI_HISI_SFC 49 49 - tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)" 50 50 - depends on ARCH_HISI || COMPILE_TEST 51 51 - depends on HAS_IOMEM 52 52 - help 53 53 - This enables support for HiSilicon FMC SPI-NOR flash controller. 54 54 - 55 55 - config SPI_NXP_SPIFI 56 56 - tristate "NXP SPI Flash Interface (SPIFI)" 57 57 - depends on OF && (ARCH_LPC18XX || COMPILE_TEST) 58 58 - depends on HAS_IOMEM 59 59 - help 60 60 - Enable support for the NXP LPC SPI Flash Interface controller. 61 61 - 62 62 - SPIFI is a specialized controller for connecting serial SPI 63 63 - Flash. Enable this option if you have a device with a SPIFI 64 64 - controller and want to access the Flash as a mtd device. 65 65 - 66 66 - config SPI_INTEL_SPI 67 67 - tristate 68 68 - 69 69 - config SPI_INTEL_SPI_PCI 70 70 - tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)" 71 71 - depends on X86 && PCI 72 72 - select SPI_INTEL_SPI 73 73 - help 74 74 - This enables PCI support for the Intel PCH/PCU SPI controller in 75 75 - master mode. This controller is present in modern Intel hardware 76 76 - and is used to hold BIOS and other persistent settings. Using 77 77 - this driver it is possible to upgrade BIOS directly from Linux. 78 78 - 79 79 - Say N here unless you know what you are doing. Overwriting the 80 80 - SPI flash may render the system unbootable. 81 81 - 82 82 - To compile this driver as a module, choose M here: the module 83 83 - will be called intel-spi-pci. 84 84 - 85 85 - config SPI_INTEL_SPI_PLATFORM 86 86 - tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)" 87 87 - depends on X86 88 88 - select SPI_INTEL_SPI 89 89 - help 90 90 - This enables platform support for the Intel PCH/PCU SPI 91 91 - controller in master mode. This controller is present in modern 92 92 - Intel hardware and is used to hold BIOS and other persistent 93 93 - settings. Using this driver it is possible to upgrade BIOS 94 94 - directly from Linux. 95 95 - 96 96 - Say N here unless you know what you are doing. Overwriting the 97 97 - SPI flash may render the system unbootable. 98 98 - 99 99 - To compile this driver as a module, choose M here: the module 100 100 - will be called intel-spi-platform. 27 27 + source "drivers/mtd/spi-nor/controllers/Kconfig" 101 28 102 29 endif # MTD_SPI_NOR

+18 -7

drivers/mtd/spi-nor/Makefile

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + spi-nor-objs := core.o sfdp.o 4 4 + spi-nor-objs += atmel.o 5 5 + spi-nor-objs += catalyst.o 6 6 + spi-nor-objs += eon.o 7 7 + spi-nor-objs += esmt.o 8 8 + spi-nor-objs += everspin.o 9 9 + spi-nor-objs += fujitsu.o 10 10 + spi-nor-objs += gigadevice.o 11 11 + spi-nor-objs += intel.o 12 12 + spi-nor-objs += issi.o 13 13 + spi-nor-objs += macronix.o 14 14 + spi-nor-objs += micron-st.o 15 15 + spi-nor-objs += spansion.o 16 16 + spi-nor-objs += sst.o 17 17 + spi-nor-objs += winbond.o 18 18 + spi-nor-objs += xilinx.o 19 19 + spi-nor-objs += xmc.o 2 20 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o 3 3 - obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o 4 4 - obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o 5 5 - obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o 6 6 - obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o 7 7 - obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o 8 8 - obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o 9 9 - obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o

+2 -2

drivers/mtd/spi-nor/aspeed-smc.c drivers/mtd/spi-nor/controllers/aspeed-smc.c

reviewed

··· 109 109 void __iomem *ahb_base; /* per-chip windows resource */ 110 110 u32 ahb_window_size; /* full mapping window size */ 111 111 112 112 - struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */ 112 112 + struct aspeed_smc_chip *chips[]; /* pointers to attached chips */ 113 113 }; 114 114 115 115 /* ··· 354 354 default: 355 355 WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n", 356 356 nor->addr_width); 357 357 - /* FALLTHROUGH */ 357 357 + fallthrough; 358 358 case 3: 359 359 cmdaddr = addr & 0xFFFFFF; 360 360 cmdaddr |= cmd << 24;

+46

drivers/mtd/spi-nor/atmel.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info atmel_parts[] = { 12 12 + /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 13 13 + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, 14 14 + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, 15 15 + 16 16 + { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, 17 17 + { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 18 18 + { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 19 19 + { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, 20 20 + 21 21 + { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64, 22 22 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 23 23 + 24 24 + { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, 25 25 + { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 26 26 + { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, 27 27 + { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 28 28 + 29 29 + { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 30 30 + }; 31 31 + 32 32 + static void atmel_default_init(struct spi_nor *nor) 33 33 + { 34 34 + nor->flags |= SNOR_F_HAS_LOCK; 35 35 + } 36 36 + 37 37 + static const struct spi_nor_fixups atmel_fixups = { 38 38 + .default_init = atmel_default_init, 39 39 + }; 40 40 + 41 41 + const struct spi_nor_manufacturer spi_nor_atmel = { 42 42 + .name = "atmel", 43 43 + .parts = atmel_parts, 44 44 + .nparts = ARRAY_SIZE(atmel_parts), 45 45 + .fixups = &atmel_fixups, 46 46 + };

drivers/mtd/spi-nor/cadence-quadspi.c drivers/mtd/spi-nor/controllers/cadence-quadspi.c

reviewed

+29

drivers/mtd/spi-nor/catalyst.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info catalyst_parts[] = { 12 12 + /* Catalyst / On Semiconductor -- non-JEDEC */ 13 13 + { "cat25c11", CAT25_INFO(16, 8, 16, 1, 14 14 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 15 15 + { "cat25c03", CAT25_INFO(32, 8, 16, 2, 16 16 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 17 17 + { "cat25c09", CAT25_INFO(128, 8, 32, 2, 18 18 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 19 19 + { "cat25c17", CAT25_INFO(256, 8, 32, 2, 20 20 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 21 21 + { "cat25128", CAT25_INFO(2048, 8, 64, 2, 22 22 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 23 23 + }; 24 24 + 25 25 + const struct spi_nor_manufacturer spi_nor_catalyst = { 26 26 + .name = "catalyst", 27 27 + .parts = catalyst_parts, 28 28 + .nparts = ARRAY_SIZE(catalyst_parts), 29 29 + };

+75

drivers/mtd/spi-nor/controllers/Kconfig

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + config SPI_ASPEED_SMC 3 3 + tristate "Aspeed flash controllers in SPI mode" 4 4 + depends on ARCH_ASPEED || COMPILE_TEST 5 5 + depends on HAS_IOMEM && OF 6 6 + help 7 7 + This enables support for the Firmware Memory controller (FMC) 8 8 + in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips, 9 9 + and support for the SPI flash memory controller (SPI) for 10 10 + the host firmware. The implementation only supports SPI NOR. 11 11 + 12 12 + config SPI_CADENCE_QUADSPI 13 13 + tristate "Cadence Quad SPI controller" 14 14 + depends on OF && (ARM || ARM64 || COMPILE_TEST) 15 15 + help 16 16 + Enable support for the Cadence Quad SPI Flash controller. 17 17 + 18 18 + Cadence QSPI is a specialized controller for connecting an SPI 19 19 + Flash over 1/2/4-bit wide bus. Enable this option if you have a 20 20 + device with a Cadence QSPI controller and want to access the 21 21 + Flash as an MTD device. 22 22 + 23 23 + config SPI_HISI_SFC 24 24 + tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)" 25 25 + depends on ARCH_HISI || COMPILE_TEST 26 26 + depends on HAS_IOMEM 27 27 + help 28 28 + This enables support for HiSilicon FMC SPI-NOR flash controller. 29 29 + 30 30 + config SPI_NXP_SPIFI 31 31 + tristate "NXP SPI Flash Interface (SPIFI)" 32 32 + depends on OF && (ARCH_LPC18XX || COMPILE_TEST) 33 33 + depends on HAS_IOMEM 34 34 + help 35 35 + Enable support for the NXP LPC SPI Flash Interface controller. 36 36 + 37 37 + SPIFI is a specialized controller for connecting serial SPI 38 38 + Flash. Enable this option if you have a device with a SPIFI 39 39 + controller and want to access the Flash as a mtd device. 40 40 + 41 41 + config SPI_INTEL_SPI 42 42 + tristate 43 43 + 44 44 + config SPI_INTEL_SPI_PCI 45 45 + tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)" 46 46 + depends on X86 && PCI 47 47 + select SPI_INTEL_SPI 48 48 + help 49 49 + This enables PCI support for the Intel PCH/PCU SPI controller in 50 50 + master mode. This controller is present in modern Intel hardware 51 51 + and is used to hold BIOS and other persistent settings. Using 52 52 + this driver it is possible to upgrade BIOS directly from Linux. 53 53 + 54 54 + Say N here unless you know what you are doing. Overwriting the 55 55 + SPI flash may render the system unbootable. 56 56 + 57 57 + To compile this driver as a module, choose M here: the module 58 58 + will be called intel-spi-pci. 59 59 + 60 60 + config SPI_INTEL_SPI_PLATFORM 61 61 + tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)" 62 62 + depends on X86 63 63 + select SPI_INTEL_SPI 64 64 + help 65 65 + This enables platform support for the Intel PCH/PCU SPI 66 66 + controller in master mode. This controller is present in modern 67 67 + Intel hardware and is used to hold BIOS and other persistent 68 68 + settings. Using this driver it is possible to upgrade BIOS 69 69 + directly from Linux. 70 70 + 71 71 + Say N here unless you know what you are doing. Overwriting the 72 72 + SPI flash may render the system unbootable. 73 73 + 74 74 + To compile this driver as a module, choose M here: the module 75 75 + will be called intel-spi-platform.

+8

drivers/mtd/spi-nor/controllers/Makefile

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o 3 3 + obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o 4 4 + obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o 5 5 + obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o 6 6 + obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o 7 7 + obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o 8 8 + obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o

+3466

drivers/mtd/spi-nor/core.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 4 + * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 5 + * 6 6 + * Copyright (C) 2005, Intec Automation Inc. 7 7 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 8 + */ 9 9 + 10 10 + #include <linux/err.h> 11 11 + #include <linux/errno.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/device.h> 14 14 + #include <linux/mutex.h> 15 15 + #include <linux/math64.h> 16 16 + #include <linux/sizes.h> 17 17 + #include <linux/slab.h> 18 18 + 19 19 + #include <linux/mtd/mtd.h> 20 20 + #include <linux/of_platform.h> 21 21 + #include <linux/sched/task_stack.h> 22 22 + #include <linux/spi/flash.h> 23 23 + #include <linux/mtd/spi-nor.h> 24 24 + 25 25 + #include "core.h" 26 26 + 27 27 + /* Define max times to check status register before we give up. */ 28 28 + 29 29 + /* 30 30 + * For everything but full-chip erase; probably could be much smaller, but kept 31 31 + * around for safety for now 32 32 + */ 33 33 + #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 34 + 35 35 + /* 36 36 + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 37 37 + * for larger flash 38 38 + */ 39 39 + #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 40 40 + 41 41 + #define SPI_NOR_MAX_ADDR_WIDTH 4 42 42 + 43 43 + /** 44 44 + * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 45 45 + * transfer 46 46 + * @nor: pointer to 'struct spi_nor' 47 47 + * @op: pointer to 'struct spi_mem_op' template for transfer 48 48 + * 49 49 + * If we have to use the bounce buffer, the data field in @op will be updated. 50 50 + * 51 51 + * Return: true if the bounce buffer is needed, false if not 52 52 + */ 53 53 + static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 54 54 + { 55 55 + /* op->data.buf.in occupies the same memory as op->data.buf.out */ 56 56 + if (object_is_on_stack(op->data.buf.in) || 57 57 + !virt_addr_valid(op->data.buf.in)) { 58 58 + if (op->data.nbytes > nor->bouncebuf_size) 59 59 + op->data.nbytes = nor->bouncebuf_size; 60 60 + op->data.buf.in = nor->bouncebuf; 61 61 + return true; 62 62 + } 63 63 + 64 64 + return false; 65 65 + } 66 66 + 67 67 + /** 68 68 + * spi_nor_spimem_exec_op() - execute a memory operation 69 69 + * @nor: pointer to 'struct spi_nor' 70 70 + * @op: pointer to 'struct spi_mem_op' template for transfer 71 71 + * 72 72 + * Return: 0 on success, -error otherwise. 73 73 + */ 74 74 + static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 75 75 + { 76 76 + int error; 77 77 + 78 78 + error = spi_mem_adjust_op_size(nor->spimem, op); 79 79 + if (error) 80 80 + return error; 81 81 + 82 82 + return spi_mem_exec_op(nor->spimem, op); 83 83 + } 84 84 + 85 85 + /** 86 86 + * spi_nor_spimem_read_data() - read data from flash's memory region via 87 87 + * spi-mem 88 88 + * @nor: pointer to 'struct spi_nor' 89 89 + * @from: offset to read from 90 90 + * @len: number of bytes to read 91 91 + * @buf: pointer to dst buffer 92 92 + * 93 93 + * Return: number of bytes read successfully, -errno otherwise 94 94 + */ 95 95 + static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 96 96 + size_t len, u8 *buf) 97 97 + { 98 98 + struct spi_mem_op op = 99 99 + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 100 100 + SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 101 101 + SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 102 102 + SPI_MEM_OP_DATA_IN(len, buf, 1)); 103 103 + bool usebouncebuf; 104 104 + ssize_t nbytes; 105 105 + int error; 106 106 + 107 107 + /* get transfer protocols. */ 108 108 + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 109 109 + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 110 110 + op.dummy.buswidth = op.addr.buswidth; 111 111 + op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 112 112 + 113 113 + /* convert the dummy cycles to the number of bytes */ 114 114 + op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 115 115 + 116 116 + usebouncebuf = spi_nor_spimem_bounce(nor, &op); 117 117 + 118 118 + if (nor->dirmap.rdesc) { 119 119 + nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 120 120 + op.data.nbytes, op.data.buf.in); 121 121 + } else { 122 122 + error = spi_nor_spimem_exec_op(nor, &op); 123 123 + if (error) 124 124 + return error; 125 125 + nbytes = op.data.nbytes; 126 126 + } 127 127 + 128 128 + if (usebouncebuf && nbytes > 0) 129 129 + memcpy(buf, op.data.buf.in, nbytes); 130 130 + 131 131 + return nbytes; 132 132 + } 133 133 + 134 134 + /** 135 135 + * spi_nor_read_data() - read data from flash memory 136 136 + * @nor: pointer to 'struct spi_nor' 137 137 + * @from: offset to read from 138 138 + * @len: number of bytes to read 139 139 + * @buf: pointer to dst buffer 140 140 + * 141 141 + * Return: number of bytes read successfully, -errno otherwise 142 142 + */ 143 143 + ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 144 144 + { 145 145 + if (nor->spimem) 146 146 + return spi_nor_spimem_read_data(nor, from, len, buf); 147 147 + 148 148 + return nor->controller_ops->read(nor, from, len, buf); 149 149 + } 150 150 + 151 151 + /** 152 152 + * spi_nor_spimem_write_data() - write data to flash memory via 153 153 + * spi-mem 154 154 + * @nor: pointer to 'struct spi_nor' 155 155 + * @to: offset to write to 156 156 + * @len: number of bytes to write 157 157 + * @buf: pointer to src buffer 158 158 + * 159 159 + * Return: number of bytes written successfully, -errno otherwise 160 160 + */ 161 161 + static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 162 162 + size_t len, const u8 *buf) 163 163 + { 164 164 + struct spi_mem_op op = 165 165 + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 166 166 + SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 167 167 + SPI_MEM_OP_NO_DUMMY, 168 168 + SPI_MEM_OP_DATA_OUT(len, buf, 1)); 169 169 + ssize_t nbytes; 170 170 + int error; 171 171 + 172 172 + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 173 173 + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 174 174 + op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 175 175 + 176 176 + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 177 177 + op.addr.nbytes = 0; 178 178 + 179 179 + if (spi_nor_spimem_bounce(nor, &op)) 180 180 + memcpy(nor->bouncebuf, buf, op.data.nbytes); 181 181 + 182 182 + if (nor->dirmap.wdesc) { 183 183 + nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 184 184 + op.data.nbytes, op.data.buf.out); 185 185 + } else { 186 186 + error = spi_nor_spimem_exec_op(nor, &op); 187 187 + if (error) 188 188 + return error; 189 189 + nbytes = op.data.nbytes; 190 190 + } 191 191 + 192 192 + return nbytes; 193 193 + } 194 194 + 195 195 + /** 196 196 + * spi_nor_write_data() - write data to flash memory 197 197 + * @nor: pointer to 'struct spi_nor' 198 198 + * @to: offset to write to 199 199 + * @len: number of bytes to write 200 200 + * @buf: pointer to src buffer 201 201 + * 202 202 + * Return: number of bytes written successfully, -errno otherwise 203 203 + */ 204 204 + ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 205 205 + const u8 *buf) 206 206 + { 207 207 + if (nor->spimem) 208 208 + return spi_nor_spimem_write_data(nor, to, len, buf); 209 209 + 210 210 + return nor->controller_ops->write(nor, to, len, buf); 211 211 + } 212 212 + 213 213 + /** 214 214 + * spi_nor_write_enable() - Set write enable latch with Write Enable command. 215 215 + * @nor: pointer to 'struct spi_nor'. 216 216 + * 217 217 + * Return: 0 on success, -errno otherwise. 218 218 + */ 219 219 + int spi_nor_write_enable(struct spi_nor *nor) 220 220 + { 221 221 + int ret; 222 222 + 223 223 + if (nor->spimem) { 224 224 + struct spi_mem_op op = 225 225 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), 226 226 + SPI_MEM_OP_NO_ADDR, 227 227 + SPI_MEM_OP_NO_DUMMY, 228 228 + SPI_MEM_OP_NO_DATA); 229 229 + 230 230 + ret = spi_mem_exec_op(nor->spimem, &op); 231 231 + } else { 232 232 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, 233 233 + NULL, 0); 234 234 + } 235 235 + 236 236 + if (ret) 237 237 + dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 238 238 + 239 239 + return ret; 240 240 + } 241 241 + 242 242 + /** 243 243 + * spi_nor_write_disable() - Send Write Disable instruction to the chip. 244 244 + * @nor: pointer to 'struct spi_nor'. 245 245 + * 246 246 + * Return: 0 on success, -errno otherwise. 247 247 + */ 248 248 + int spi_nor_write_disable(struct spi_nor *nor) 249 249 + { 250 250 + int ret; 251 251 + 252 252 + if (nor->spimem) { 253 253 + struct spi_mem_op op = 254 254 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), 255 255 + SPI_MEM_OP_NO_ADDR, 256 256 + SPI_MEM_OP_NO_DUMMY, 257 257 + SPI_MEM_OP_NO_DATA); 258 258 + 259 259 + ret = spi_mem_exec_op(nor->spimem, &op); 260 260 + } else { 261 261 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, 262 262 + NULL, 0); 263 263 + } 264 264 + 265 265 + if (ret) 266 266 + dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 267 267 + 268 268 + return ret; 269 269 + } 270 270 + 271 271 + /** 272 272 + * spi_nor_read_sr() - Read the Status Register. 273 273 + * @nor: pointer to 'struct spi_nor'. 274 274 + * @sr: pointer to a DMA-able buffer where the value of the 275 275 + * Status Register will be written. 276 276 + * 277 277 + * Return: 0 on success, -errno otherwise. 278 278 + */ 279 279 + static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 280 280 + { 281 281 + int ret; 282 282 + 283 283 + if (nor->spimem) { 284 284 + struct spi_mem_op op = 285 285 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), 286 286 + SPI_MEM_OP_NO_ADDR, 287 287 + SPI_MEM_OP_NO_DUMMY, 288 288 + SPI_MEM_OP_DATA_IN(1, sr, 1)); 289 289 + 290 290 + ret = spi_mem_exec_op(nor->spimem, &op); 291 291 + } else { 292 292 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, 293 293 + sr, 1); 294 294 + } 295 295 + 296 296 + if (ret) 297 297 + dev_dbg(nor->dev, "error %d reading SR\n", ret); 298 298 + 299 299 + return ret; 300 300 + } 301 301 + 302 302 + /** 303 303 + * spi_nor_read_fsr() - Read the Flag Status Register. 304 304 + * @nor: pointer to 'struct spi_nor' 305 305 + * @fsr: pointer to a DMA-able buffer where the value of the 306 306 + * Flag Status Register will be written. 307 307 + * 308 308 + * Return: 0 on success, -errno otherwise. 309 309 + */ 310 310 + static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 311 311 + { 312 312 + int ret; 313 313 + 314 314 + if (nor->spimem) { 315 315 + struct spi_mem_op op = 316 316 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1), 317 317 + SPI_MEM_OP_NO_ADDR, 318 318 + SPI_MEM_OP_NO_DUMMY, 319 319 + SPI_MEM_OP_DATA_IN(1, fsr, 1)); 320 320 + 321 321 + ret = spi_mem_exec_op(nor->spimem, &op); 322 322 + } else { 323 323 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR, 324 324 + fsr, 1); 325 325 + } 326 326 + 327 327 + if (ret) 328 328 + dev_dbg(nor->dev, "error %d reading FSR\n", ret); 329 329 + 330 330 + return ret; 331 331 + } 332 332 + 333 333 + /** 334 334 + * spi_nor_read_cr() - Read the Configuration Register using the 335 335 + * SPINOR_OP_RDCR (35h) command. 336 336 + * @nor: pointer to 'struct spi_nor' 337 337 + * @cr: pointer to a DMA-able buffer where the value of the 338 338 + * Configuration Register will be written. 339 339 + * 340 340 + * Return: 0 on success, -errno otherwise. 341 341 + */ 342 342 + static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 343 343 + { 344 344 + int ret; 345 345 + 346 346 + if (nor->spimem) { 347 347 + struct spi_mem_op op = 348 348 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1), 349 349 + SPI_MEM_OP_NO_ADDR, 350 350 + SPI_MEM_OP_NO_DUMMY, 351 351 + SPI_MEM_OP_DATA_IN(1, cr, 1)); 352 352 + 353 353 + ret = spi_mem_exec_op(nor->spimem, &op); 354 354 + } else { 355 355 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1); 356 356 + } 357 357 + 358 358 + if (ret) 359 359 + dev_dbg(nor->dev, "error %d reading CR\n", ret); 360 360 + 361 361 + return ret; 362 362 + } 363 363 + 364 364 + /** 365 365 + * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. 366 366 + * @nor: pointer to 'struct spi_nor'. 367 367 + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 368 368 + * address mode. 369 369 + * 370 370 + * Return: 0 on success, -errno otherwise. 371 371 + */ 372 372 + int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 373 373 + { 374 374 + int ret; 375 375 + 376 376 + if (nor->spimem) { 377 377 + struct spi_mem_op op = 378 378 + SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? 379 379 + SPINOR_OP_EN4B : 380 380 + SPINOR_OP_EX4B, 381 381 + 1), 382 382 + SPI_MEM_OP_NO_ADDR, 383 383 + SPI_MEM_OP_NO_DUMMY, 384 384 + SPI_MEM_OP_NO_DATA); 385 385 + 386 386 + ret = spi_mem_exec_op(nor->spimem, &op); 387 387 + } else { 388 388 + ret = nor->controller_ops->write_reg(nor, 389 389 + enable ? SPINOR_OP_EN4B : 390 390 + SPINOR_OP_EX4B, 391 391 + NULL, 0); 392 392 + } 393 393 + 394 394 + if (ret) 395 395 + dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 396 396 + 397 397 + return ret; 398 398 + } 399 399 + 400 400 + /** 401 401 + * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion 402 402 + * flashes. 403 403 + * @nor: pointer to 'struct spi_nor'. 404 404 + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 405 405 + * address mode. 406 406 + * 407 407 + * Return: 0 on success, -errno otherwise. 408 408 + */ 409 409 + static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 410 410 + { 411 411 + int ret; 412 412 + 413 413 + nor->bouncebuf[0] = enable << 7; 414 414 + 415 415 + if (nor->spimem) { 416 416 + struct spi_mem_op op = 417 417 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1), 418 418 + SPI_MEM_OP_NO_ADDR, 419 419 + SPI_MEM_OP_NO_DUMMY, 420 420 + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); 421 421 + 422 422 + ret = spi_mem_exec_op(nor->spimem, &op); 423 423 + } else { 424 424 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, 425 425 + nor->bouncebuf, 1); 426 426 + } 427 427 + 428 428 + if (ret) 429 429 + dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 430 430 + 431 431 + return ret; 432 432 + } 433 433 + 434 434 + /** 435 435 + * spi_nor_write_ear() - Write Extended Address Register. 436 436 + * @nor: pointer to 'struct spi_nor'. 437 437 + * @ear: value to write to the Extended Address Register. 438 438 + * 439 439 + * Return: 0 on success, -errno otherwise. 440 440 + */ 441 441 + int spi_nor_write_ear(struct spi_nor *nor, u8 ear) 442 442 + { 443 443 + int ret; 444 444 + 445 445 + nor->bouncebuf[0] = ear; 446 446 + 447 447 + if (nor->spimem) { 448 448 + struct spi_mem_op op = 449 449 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1), 450 450 + SPI_MEM_OP_NO_ADDR, 451 451 + SPI_MEM_OP_NO_DUMMY, 452 452 + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); 453 453 + 454 454 + ret = spi_mem_exec_op(nor->spimem, &op); 455 455 + } else { 456 456 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, 457 457 + nor->bouncebuf, 1); 458 458 + } 459 459 + 460 460 + if (ret) 461 461 + dev_dbg(nor->dev, "error %d writing EAR\n", ret); 462 462 + 463 463 + return ret; 464 464 + } 465 465 + 466 466 + /** 467 467 + * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. 468 468 + * @nor: pointer to 'struct spi_nor'. 469 469 + * @sr: pointer to a DMA-able buffer where the value of the 470 470 + * Status Register will be written. 471 471 + * 472 472 + * Return: 0 on success, -errno otherwise. 473 473 + */ 474 474 + int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) 475 475 + { 476 476 + int ret; 477 477 + 478 478 + if (nor->spimem) { 479 479 + struct spi_mem_op op = 480 480 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1), 481 481 + SPI_MEM_OP_NO_ADDR, 482 482 + SPI_MEM_OP_NO_DUMMY, 483 483 + SPI_MEM_OP_DATA_IN(1, sr, 1)); 484 484 + 485 485 + ret = spi_mem_exec_op(nor->spimem, &op); 486 486 + } else { 487 487 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, 488 488 + sr, 1); 489 489 + } 490 490 + 491 491 + if (ret) 492 492 + dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); 493 493 + 494 494 + return ret; 495 495 + } 496 496 + 497 497 + /** 498 498 + * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if 499 499 + * the flash is ready for new commands. 500 500 + * @nor: pointer to 'struct spi_nor'. 501 501 + * 502 502 + * Return: 0 on success, -errno otherwise. 503 503 + */ 504 504 + static int spi_nor_xsr_ready(struct spi_nor *nor) 505 505 + { 506 506 + int ret; 507 507 + 508 508 + ret = spi_nor_xread_sr(nor, nor->bouncebuf); 509 509 + if (ret) 510 510 + return ret; 511 511 + 512 512 + return !!(nor->bouncebuf[0] & XSR_RDY); 513 513 + } 514 514 + 515 515 + /** 516 516 + * spi_nor_clear_sr() - Clear the Status Register. 517 517 + * @nor: pointer to 'struct spi_nor'. 518 518 + */ 519 519 + static void spi_nor_clear_sr(struct spi_nor *nor) 520 520 + { 521 521 + int ret; 522 522 + 523 523 + if (nor->spimem) { 524 524 + struct spi_mem_op op = 525 525 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1), 526 526 + SPI_MEM_OP_NO_ADDR, 527 527 + SPI_MEM_OP_NO_DUMMY, 528 528 + SPI_MEM_OP_NO_DATA); 529 529 + 530 530 + ret = spi_mem_exec_op(nor->spimem, &op); 531 531 + } else { 532 532 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, 533 533 + NULL, 0); 534 534 + } 535 535 + 536 536 + if (ret) 537 537 + dev_dbg(nor->dev, "error %d clearing SR\n", ret); 538 538 + } 539 539 + 540 540 + /** 541 541 + * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 542 542 + * for new commands. 543 543 + * @nor: pointer to 'struct spi_nor'. 544 544 + * 545 545 + * Return: 0 on success, -errno otherwise. 546 546 + */ 547 547 + static int spi_nor_sr_ready(struct spi_nor *nor) 548 548 + { 549 549 + int ret = spi_nor_read_sr(nor, nor->bouncebuf); 550 550 + 551 551 + if (ret) 552 552 + return ret; 553 553 + 554 554 + if (nor->flags & SNOR_F_USE_CLSR && 555 555 + nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 556 556 + if (nor->bouncebuf[0] & SR_E_ERR) 557 557 + dev_err(nor->dev, "Erase Error occurred\n"); 558 558 + else 559 559 + dev_err(nor->dev, "Programming Error occurred\n"); 560 560 + 561 561 + spi_nor_clear_sr(nor); 562 562 + 563 563 + /* 564 564 + * WEL bit remains set to one when an erase or page program 565 565 + * error occurs. Issue a Write Disable command to protect 566 566 + * against inadvertent writes that can possibly corrupt the 567 567 + * contents of the memory. 568 568 + */ 569 569 + ret = spi_nor_write_disable(nor); 570 570 + if (ret) 571 571 + return ret; 572 572 + 573 573 + return -EIO; 574 574 + } 575 575 + 576 576 + return !(nor->bouncebuf[0] & SR_WIP); 577 577 + } 578 578 + 579 579 + /** 580 580 + * spi_nor_clear_fsr() - Clear the Flag Status Register. 581 581 + * @nor: pointer to 'struct spi_nor'. 582 582 + */ 583 583 + static void spi_nor_clear_fsr(struct spi_nor *nor) 584 584 + { 585 585 + int ret; 586 586 + 587 587 + if (nor->spimem) { 588 588 + struct spi_mem_op op = 589 589 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1), 590 590 + SPI_MEM_OP_NO_ADDR, 591 591 + SPI_MEM_OP_NO_DUMMY, 592 592 + SPI_MEM_OP_NO_DATA); 593 593 + 594 594 + ret = spi_mem_exec_op(nor->spimem, &op); 595 595 + } else { 596 596 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, 597 597 + NULL, 0); 598 598 + } 599 599 + 600 600 + if (ret) 601 601 + dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 602 602 + } 603 603 + 604 604 + /** 605 605 + * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is 606 606 + * ready for new commands. 607 607 + * @nor: pointer to 'struct spi_nor'. 608 608 + * 609 609 + * Return: 0 on success, -errno otherwise. 610 610 + */ 611 611 + static int spi_nor_fsr_ready(struct spi_nor *nor) 612 612 + { 613 613 + int ret = spi_nor_read_fsr(nor, nor->bouncebuf); 614 614 + 615 615 + if (ret) 616 616 + return ret; 617 617 + 618 618 + if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 619 619 + if (nor->bouncebuf[0] & FSR_E_ERR) 620 620 + dev_err(nor->dev, "Erase operation failed.\n"); 621 621 + else 622 622 + dev_err(nor->dev, "Program operation failed.\n"); 623 623 + 624 624 + if (nor->bouncebuf[0] & FSR_PT_ERR) 625 625 + dev_err(nor->dev, 626 626 + "Attempted to modify a protected sector.\n"); 627 627 + 628 628 + spi_nor_clear_fsr(nor); 629 629 + 630 630 + /* 631 631 + * WEL bit remains set to one when an erase or page program 632 632 + * error occurs. Issue a Write Disable command to protect 633 633 + * against inadvertent writes that can possibly corrupt the 634 634 + * contents of the memory. 635 635 + */ 636 636 + ret = spi_nor_write_disable(nor); 637 637 + if (ret) 638 638 + return ret; 639 639 + 640 640 + return -EIO; 641 641 + } 642 642 + 643 643 + return nor->bouncebuf[0] & FSR_READY; 644 644 + } 645 645 + 646 646 + /** 647 647 + * spi_nor_ready() - Query the flash to see if it is ready for new commands. 648 648 + * @nor: pointer to 'struct spi_nor'. 649 649 + * 650 650 + * Return: 0 on success, -errno otherwise. 651 651 + */ 652 652 + static int spi_nor_ready(struct spi_nor *nor) 653 653 + { 654 654 + int sr, fsr; 655 655 + 656 656 + if (nor->flags & SNOR_F_READY_XSR_RDY) 657 657 + sr = spi_nor_xsr_ready(nor); 658 658 + else 659 659 + sr = spi_nor_sr_ready(nor); 660 660 + if (sr < 0) 661 661 + return sr; 662 662 + fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 663 663 + if (fsr < 0) 664 664 + return fsr; 665 665 + return sr && fsr; 666 666 + } 667 667 + 668 668 + /** 669 669 + * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 670 670 + * Status Register until ready, or timeout occurs. 671 671 + * @nor: pointer to "struct spi_nor". 672 672 + * @timeout_jiffies: jiffies to wait until timeout. 673 673 + * 674 674 + * Return: 0 on success, -errno otherwise. 675 675 + */ 676 676 + static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 677 677 + unsigned long timeout_jiffies) 678 678 + { 679 679 + unsigned long deadline; 680 680 + int timeout = 0, ret; 681 681 + 682 682 + deadline = jiffies + timeout_jiffies; 683 683 + 684 684 + while (!timeout) { 685 685 + if (time_after_eq(jiffies, deadline)) 686 686 + timeout = 1; 687 687 + 688 688 + ret = spi_nor_ready(nor); 689 689 + if (ret < 0) 690 690 + return ret; 691 691 + if (ret) 692 692 + return 0; 693 693 + 694 694 + cond_resched(); 695 695 + } 696 696 + 697 697 + dev_dbg(nor->dev, "flash operation timed out\n"); 698 698 + 699 699 + return -ETIMEDOUT; 700 700 + } 701 701 + 702 702 + /** 703 703 + * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 704 704 + * flash to be ready, or timeout occurs. 705 705 + * @nor: pointer to "struct spi_nor". 706 706 + * 707 707 + * Return: 0 on success, -errno otherwise. 708 708 + */ 709 709 + int spi_nor_wait_till_ready(struct spi_nor *nor) 710 710 + { 711 711 + return spi_nor_wait_till_ready_with_timeout(nor, 712 712 + DEFAULT_READY_WAIT_JIFFIES); 713 713 + } 714 714 + 715 715 + /** 716 716 + * spi_nor_write_sr() - Write the Status Register. 717 717 + * @nor: pointer to 'struct spi_nor'. 718 718 + * @sr: pointer to DMA-able buffer to write to the Status Register. 719 719 + * @len: number of bytes to write to the Status Register. 720 720 + * 721 721 + * Return: 0 on success, -errno otherwise. 722 722 + */ 723 723 + static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 724 724 + { 725 725 + int ret; 726 726 + 727 727 + ret = spi_nor_write_enable(nor); 728 728 + if (ret) 729 729 + return ret; 730 730 + 731 731 + if (nor->spimem) { 732 732 + struct spi_mem_op op = 733 733 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), 734 734 + SPI_MEM_OP_NO_ADDR, 735 735 + SPI_MEM_OP_NO_DUMMY, 736 736 + SPI_MEM_OP_DATA_OUT(len, sr, 1)); 737 737 + 738 738 + ret = spi_mem_exec_op(nor->spimem, &op); 739 739 + } else { 740 740 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, 741 741 + sr, len); 742 742 + } 743 743 + 744 744 + if (ret) { 745 745 + dev_dbg(nor->dev, "error %d writing SR\n", ret); 746 746 + return ret; 747 747 + } 748 748 + 749 749 + return spi_nor_wait_till_ready(nor); 750 750 + } 751 751 + 752 752 + /** 753 753 + * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 754 754 + * ensure that the byte written match the received value. 755 755 + * @nor: pointer to a 'struct spi_nor'. 756 756 + * @sr1: byte value to be written to the Status Register. 757 757 + * 758 758 + * Return: 0 on success, -errno otherwise. 759 759 + */ 760 760 + static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 761 761 + { 762 762 + int ret; 763 763 + 764 764 + nor->bouncebuf[0] = sr1; 765 765 + 766 766 + ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 767 767 + if (ret) 768 768 + return ret; 769 769 + 770 770 + ret = spi_nor_read_sr(nor, nor->bouncebuf); 771 771 + if (ret) 772 772 + return ret; 773 773 + 774 774 + if (nor->bouncebuf[0] != sr1) { 775 775 + dev_dbg(nor->dev, "SR1: read back test failed\n"); 776 776 + return -EIO; 777 777 + } 778 778 + 779 779 + return 0; 780 780 + } 781 781 + 782 782 + /** 783 783 + * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 784 784 + * Status Register 2 in one shot. Ensure that the byte written in the Status 785 785 + * Register 1 match the received value, and that the 16-bit Write did not 786 786 + * affect what was already in the Status Register 2. 787 787 + * @nor: pointer to a 'struct spi_nor'. 788 788 + * @sr1: byte value to be written to the Status Register 1. 789 789 + * 790 790 + * Return: 0 on success, -errno otherwise. 791 791 + */ 792 792 + static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 793 793 + { 794 794 + int ret; 795 795 + u8 *sr_cr = nor->bouncebuf; 796 796 + u8 cr_written; 797 797 + 798 798 + /* Make sure we don't overwrite the contents of Status Register 2. */ 799 799 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { 800 800 + ret = spi_nor_read_cr(nor, &sr_cr[1]); 801 801 + if (ret) 802 802 + return ret; 803 803 + } else if (nor->params->quad_enable) { 804 804 + /* 805 805 + * If the Status Register 2 Read command (35h) is not 806 806 + * supported, we should at least be sure we don't 807 807 + * change the value of the SR2 Quad Enable bit. 808 808 + * 809 809 + * We can safely assume that when the Quad Enable method is 810 810 + * set, the value of the QE bit is one, as a consequence of the 811 811 + * nor->params->quad_enable() call. 812 812 + * 813 813 + * We can safely assume that the Quad Enable bit is present in 814 814 + * the Status Register 2 at BIT(1). According to the JESD216 815 815 + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit 816 816 + * Write Status (01h) command is available just for the cases 817 817 + * in which the QE bit is described in SR2 at BIT(1). 818 818 + */ 819 819 + sr_cr[1] = SR2_QUAD_EN_BIT1; 820 820 + } else { 821 821 + sr_cr[1] = 0; 822 822 + } 823 823 + 824 824 + sr_cr[0] = sr1; 825 825 + 826 826 + ret = spi_nor_write_sr(nor, sr_cr, 2); 827 827 + if (ret) 828 828 + return ret; 829 829 + 830 830 + if (nor->flags & SNOR_F_NO_READ_CR) 831 831 + return 0; 832 832 + 833 833 + cr_written = sr_cr[1]; 834 834 + 835 835 + ret = spi_nor_read_cr(nor, &sr_cr[1]); 836 836 + if (ret) 837 837 + return ret; 838 838 + 839 839 + if (cr_written != sr_cr[1]) { 840 840 + dev_dbg(nor->dev, "CR: read back test failed\n"); 841 841 + return -EIO; 842 842 + } 843 843 + 844 844 + return 0; 845 845 + } 846 846 + 847 847 + /** 848 848 + * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 849 849 + * Configuration Register in one shot. Ensure that the byte written in the 850 850 + * Configuration Register match the received value, and that the 16-bit Write 851 851 + * did not affect what was already in the Status Register 1. 852 852 + * @nor: pointer to a 'struct spi_nor'. 853 853 + * @cr: byte value to be written to the Configuration Register. 854 854 + * 855 855 + * Return: 0 on success, -errno otherwise. 856 856 + */ 857 857 + static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 858 858 + { 859 859 + int ret; 860 860 + u8 *sr_cr = nor->bouncebuf; 861 861 + u8 sr_written; 862 862 + 863 863 + /* Keep the current value of the Status Register 1. */ 864 864 + ret = spi_nor_read_sr(nor, sr_cr); 865 865 + if (ret) 866 866 + return ret; 867 867 + 868 868 + sr_cr[1] = cr; 869 869 + 870 870 + ret = spi_nor_write_sr(nor, sr_cr, 2); 871 871 + if (ret) 872 872 + return ret; 873 873 + 874 874 + sr_written = sr_cr[0]; 875 875 + 876 876 + ret = spi_nor_read_sr(nor, sr_cr); 877 877 + if (ret) 878 878 + return ret; 879 879 + 880 880 + if (sr_written != sr_cr[0]) { 881 881 + dev_dbg(nor->dev, "SR: Read back test failed\n"); 882 882 + return -EIO; 883 883 + } 884 884 + 885 885 + if (nor->flags & SNOR_F_NO_READ_CR) 886 886 + return 0; 887 887 + 888 888 + ret = spi_nor_read_cr(nor, &sr_cr[1]); 889 889 + if (ret) 890 890 + return ret; 891 891 + 892 892 + if (cr != sr_cr[1]) { 893 893 + dev_dbg(nor->dev, "CR: read back test failed\n"); 894 894 + return -EIO; 895 895 + } 896 896 + 897 897 + return 0; 898 898 + } 899 899 + 900 900 + /** 901 901 + * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 902 902 + * the byte written match the received value without affecting other bits in the 903 903 + * Status Register 1 and 2. 904 904 + * @nor: pointer to a 'struct spi_nor'. 905 905 + * @sr1: byte value to be written to the Status Register. 906 906 + * 907 907 + * Return: 0 on success, -errno otherwise. 908 908 + */ 909 909 + static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 910 910 + { 911 911 + if (nor->flags & SNOR_F_HAS_16BIT_SR) 912 912 + return spi_nor_write_16bit_sr_and_check(nor, sr1); 913 913 + 914 914 + return spi_nor_write_sr1_and_check(nor, sr1); 915 915 + } 916 916 + 917 917 + /** 918 918 + * spi_nor_write_sr2() - Write the Status Register 2 using the 919 919 + * SPINOR_OP_WRSR2 (3eh) command. 920 920 + * @nor: pointer to 'struct spi_nor'. 921 921 + * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 922 922 + * 923 923 + * Return: 0 on success, -errno otherwise. 924 924 + */ 925 925 + static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 926 926 + { 927 927 + int ret; 928 928 + 929 929 + ret = spi_nor_write_enable(nor); 930 930 + if (ret) 931 931 + return ret; 932 932 + 933 933 + if (nor->spimem) { 934 934 + struct spi_mem_op op = 935 935 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), 936 936 + SPI_MEM_OP_NO_ADDR, 937 937 + SPI_MEM_OP_NO_DUMMY, 938 938 + SPI_MEM_OP_DATA_OUT(1, sr2, 1)); 939 939 + 940 940 + ret = spi_mem_exec_op(nor->spimem, &op); 941 941 + } else { 942 942 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, 943 943 + sr2, 1); 944 944 + } 945 945 + 946 946 + if (ret) { 947 947 + dev_dbg(nor->dev, "error %d writing SR2\n", ret); 948 948 + return ret; 949 949 + } 950 950 + 951 951 + return spi_nor_wait_till_ready(nor); 952 952 + } 953 953 + 954 954 + /** 955 955 + * spi_nor_read_sr2() - Read the Status Register 2 using the 956 956 + * SPINOR_OP_RDSR2 (3fh) command. 957 957 + * @nor: pointer to 'struct spi_nor'. 958 958 + * @sr2: pointer to DMA-able buffer where the value of the 959 959 + * Status Register 2 will be written. 960 960 + * 961 961 + * Return: 0 on success, -errno otherwise. 962 962 + */ 963 963 + static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 964 964 + { 965 965 + int ret; 966 966 + 967 967 + if (nor->spimem) { 968 968 + struct spi_mem_op op = 969 969 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), 970 970 + SPI_MEM_OP_NO_ADDR, 971 971 + SPI_MEM_OP_NO_DUMMY, 972 972 + SPI_MEM_OP_DATA_IN(1, sr2, 1)); 973 973 + 974 974 + ret = spi_mem_exec_op(nor->spimem, &op); 975 975 + } else { 976 976 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, 977 977 + sr2, 1); 978 978 + } 979 979 + 980 980 + if (ret) 981 981 + dev_dbg(nor->dev, "error %d reading SR2\n", ret); 982 982 + 983 983 + return ret; 984 984 + } 985 985 + 986 986 + /** 987 987 + * spi_nor_erase_chip() - Erase the entire flash memory. 988 988 + * @nor: pointer to 'struct spi_nor'. 989 989 + * 990 990 + * Return: 0 on success, -errno otherwise. 991 991 + */ 992 992 + static int spi_nor_erase_chip(struct spi_nor *nor) 993 993 + { 994 994 + int ret; 995 995 + 996 996 + dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 997 997 + 998 998 + if (nor->spimem) { 999 999 + struct spi_mem_op op = 1000 1000 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1), 1001 1001 + SPI_MEM_OP_NO_ADDR, 1002 1002 + SPI_MEM_OP_NO_DUMMY, 1003 1003 + SPI_MEM_OP_NO_DATA); 1004 1004 + 1005 1005 + ret = spi_mem_exec_op(nor->spimem, &op); 1006 1006 + } else { 1007 1007 + ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, 1008 1008 + NULL, 0); 1009 1009 + } 1010 1010 + 1011 1011 + if (ret) 1012 1012 + dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1013 1013 + 1014 1014 + return ret; 1015 1015 + } 1016 1016 + 1017 1017 + static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1018 1018 + { 1019 1019 + size_t i; 1020 1020 + 1021 1021 + for (i = 0; i < size; i++) 1022 1022 + if (table[i][0] == opcode) 1023 1023 + return table[i][1]; 1024 1024 + 1025 1025 + /* No conversion found, keep input op code. */ 1026 1026 + return opcode; 1027 1027 + } 1028 1028 + 1029 1029 + u8 spi_nor_convert_3to4_read(u8 opcode) 1030 1030 + { 1031 1031 + static const u8 spi_nor_3to4_read[][2] = { 1032 1032 + { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1033 1033 + { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1034 1034 + { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1035 1035 + { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1036 1036 + { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1037 1037 + { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1038 1038 + { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1039 1039 + { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1040 1040 + 1041 1041 + { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1042 1042 + { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1043 1043 + { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1044 1044 + }; 1045 1045 + 1046 1046 + return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1047 1047 + ARRAY_SIZE(spi_nor_3to4_read)); 1048 1048 + } 1049 1049 + 1050 1050 + static u8 spi_nor_convert_3to4_program(u8 opcode) 1051 1051 + { 1052 1052 + static const u8 spi_nor_3to4_program[][2] = { 1053 1053 + { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1054 1054 + { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1055 1055 + { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1056 1056 + { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1057 1057 + { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1058 1058 + }; 1059 1059 + 1060 1060 + return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1061 1061 + ARRAY_SIZE(spi_nor_3to4_program)); 1062 1062 + } 1063 1063 + 1064 1064 + static u8 spi_nor_convert_3to4_erase(u8 opcode) 1065 1065 + { 1066 1066 + static const u8 spi_nor_3to4_erase[][2] = { 1067 1067 + { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1068 1068 + { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1069 1069 + { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1070 1070 + }; 1071 1071 + 1072 1072 + return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1073 1073 + ARRAY_SIZE(spi_nor_3to4_erase)); 1074 1074 + } 1075 1075 + 1076 1076 + static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1077 1077 + { 1078 1078 + return !!nor->params->erase_map.uniform_erase_type; 1079 1079 + } 1080 1080 + 1081 1081 + static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1082 1082 + { 1083 1083 + nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1084 1084 + nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1085 1085 + nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1086 1086 + 1087 1087 + if (!spi_nor_has_uniform_erase(nor)) { 1088 1088 + struct spi_nor_erase_map *map = &nor->params->erase_map; 1089 1089 + struct spi_nor_erase_type *erase; 1090 1090 + int i; 1091 1091 + 1092 1092 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1093 1093 + erase = &map->erase_type[i]; 1094 1094 + erase->opcode = 1095 1095 + spi_nor_convert_3to4_erase(erase->opcode); 1096 1096 + } 1097 1097 + } 1098 1098 + } 1099 1099 + 1100 1100 + int spi_nor_lock_and_prep(struct spi_nor *nor) 1101 1101 + { 1102 1102 + int ret = 0; 1103 1103 + 1104 1104 + mutex_lock(&nor->lock); 1105 1105 + 1106 1106 + if (nor->controller_ops && nor->controller_ops->prepare) { 1107 1107 + ret = nor->controller_ops->prepare(nor); 1108 1108 + if (ret) { 1109 1109 + mutex_unlock(&nor->lock); 1110 1110 + return ret; 1111 1111 + } 1112 1112 + } 1113 1113 + return ret; 1114 1114 + } 1115 1115 + 1116 1116 + void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1117 1117 + { 1118 1118 + if (nor->controller_ops && nor->controller_ops->unprepare) 1119 1119 + nor->controller_ops->unprepare(nor); 1120 1120 + mutex_unlock(&nor->lock); 1121 1121 + } 1122 1122 + 1123 1123 + static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1124 1124 + { 1125 1125 + if (!nor->params->convert_addr) 1126 1126 + return addr; 1127 1127 + 1128 1128 + return nor->params->convert_addr(nor, addr); 1129 1129 + } 1130 1130 + 1131 1131 + /* 1132 1132 + * Initiate the erasure of a single sector 1133 1133 + */ 1134 1134 + static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1135 1135 + { 1136 1136 + int i; 1137 1137 + 1138 1138 + addr = spi_nor_convert_addr(nor, addr); 1139 1139 + 1140 1140 + if (nor->spimem) { 1141 1141 + struct spi_mem_op op = 1142 1142 + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), 1143 1143 + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), 1144 1144 + SPI_MEM_OP_NO_DUMMY, 1145 1145 + SPI_MEM_OP_NO_DATA); 1146 1146 + 1147 1147 + return spi_mem_exec_op(nor->spimem, &op); 1148 1148 + } else if (nor->controller_ops->erase) { 1149 1149 + return nor->controller_ops->erase(nor, addr); 1150 1150 + } 1151 1151 + 1152 1152 + /* 1153 1153 + * Default implementation, if driver doesn't have a specialized HW 1154 1154 + * control 1155 1155 + */ 1156 1156 + for (i = nor->addr_width - 1; i >= 0; i--) { 1157 1157 + nor->bouncebuf[i] = addr & 0xff; 1158 1158 + addr >>= 8; 1159 1159 + } 1160 1160 + 1161 1161 + return nor->controller_ops->write_reg(nor, nor->erase_opcode, 1162 1162 + nor->bouncebuf, nor->addr_width); 1163 1163 + } 1164 1164 + 1165 1165 + /** 1166 1166 + * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1167 1167 + * @erase: pointer to a structure that describes a SPI NOR erase type 1168 1168 + * @dividend: dividend value 1169 1169 + * @remainder: pointer to u32 remainder (will be updated) 1170 1170 + * 1171 1171 + * Return: the result of the division 1172 1172 + */ 1173 1173 + static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1174 1174 + u64 dividend, u32 *remainder) 1175 1175 + { 1176 1176 + /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1177 1177 + *remainder = (u32)dividend & erase->size_mask; 1178 1178 + return dividend >> erase->size_shift; 1179 1179 + } 1180 1180 + 1181 1181 + /** 1182 1182 + * spi_nor_find_best_erase_type() - find the best erase type for the given 1183 1183 + * offset in the serial flash memory and the 1184 1184 + * number of bytes to erase. The region in 1185 1185 + * which the address fits is expected to be 1186 1186 + * provided. 1187 1187 + * @map: the erase map of the SPI NOR 1188 1188 + * @region: pointer to a structure that describes a SPI NOR erase region 1189 1189 + * @addr: offset in the serial flash memory 1190 1190 + * @len: number of bytes to erase 1191 1191 + * 1192 1192 + * Return: a pointer to the best fitted erase type, NULL otherwise. 1193 1193 + */ 1194 1194 + static const struct spi_nor_erase_type * 1195 1195 + spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1196 1196 + const struct spi_nor_erase_region *region, 1197 1197 + u64 addr, u32 len) 1198 1198 + { 1199 1199 + const struct spi_nor_erase_type *erase; 1200 1200 + u32 rem; 1201 1201 + int i; 1202 1202 + u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1203 1203 + 1204 1204 + /* 1205 1205 + * Erase types are ordered by size, with the smallest erase type at 1206 1206 + * index 0. 1207 1207 + */ 1208 1208 + for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1209 1209 + /* Does the erase region support the tested erase type? */ 1210 1210 + if (!(erase_mask & BIT(i))) 1211 1211 + continue; 1212 1212 + 1213 1213 + erase = &map->erase_type[i]; 1214 1214 + 1215 1215 + /* Don't erase more than what the user has asked for. */ 1216 1216 + if (erase->size > len) 1217 1217 + continue; 1218 1218 + 1219 1219 + /* Alignment is not mandatory for overlaid regions */ 1220 1220 + if (region->offset & SNOR_OVERLAID_REGION) 1221 1221 + return erase; 1222 1222 + 1223 1223 + spi_nor_div_by_erase_size(erase, addr, &rem); 1224 1224 + if (rem) 1225 1225 + continue; 1226 1226 + else 1227 1227 + return erase; 1228 1228 + } 1229 1229 + 1230 1230 + return NULL; 1231 1231 + } 1232 1232 + 1233 1233 + static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 1234 1234 + { 1235 1235 + return region->offset & SNOR_LAST_REGION; 1236 1236 + } 1237 1237 + 1238 1238 + static u64 spi_nor_region_end(const struct spi_nor_erase_region *region) 1239 1239 + { 1240 1240 + return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 1241 1241 + } 1242 1242 + 1243 1243 + /** 1244 1244 + * spi_nor_region_next() - get the next spi nor region 1245 1245 + * @region: pointer to a structure that describes a SPI NOR erase region 1246 1246 + * 1247 1247 + * Return: the next spi nor region or NULL if last region. 1248 1248 + */ 1249 1249 + struct spi_nor_erase_region * 1250 1250 + spi_nor_region_next(struct spi_nor_erase_region *region) 1251 1251 + { 1252 1252 + if (spi_nor_region_is_last(region)) 1253 1253 + return NULL; 1254 1254 + region++; 1255 1255 + return region; 1256 1256 + } 1257 1257 + 1258 1258 + /** 1259 1259 + * spi_nor_find_erase_region() - find the region of the serial flash memory in 1260 1260 + * which the offset fits 1261 1261 + * @map: the erase map of the SPI NOR 1262 1262 + * @addr: offset in the serial flash memory 1263 1263 + * 1264 1264 + * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1265 1265 + * otherwise. 1266 1266 + */ 1267 1267 + static struct spi_nor_erase_region * 1268 1268 + spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1269 1269 + { 1270 1270 + struct spi_nor_erase_region *region = map->regions; 1271 1271 + u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1272 1272 + u64 region_end = region_start + region->size; 1273 1273 + 1274 1274 + while (addr < region_start || addr >= region_end) { 1275 1275 + region = spi_nor_region_next(region); 1276 1276 + if (!region) 1277 1277 + return ERR_PTR(-EINVAL); 1278 1278 + 1279 1279 + region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1280 1280 + region_end = region_start + region->size; 1281 1281 + } 1282 1282 + 1283 1283 + return region; 1284 1284 + } 1285 1285 + 1286 1286 + /** 1287 1287 + * spi_nor_init_erase_cmd() - initialize an erase command 1288 1288 + * @region: pointer to a structure that describes a SPI NOR erase region 1289 1289 + * @erase: pointer to a structure that describes a SPI NOR erase type 1290 1290 + * 1291 1291 + * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1292 1292 + * otherwise. 1293 1293 + */ 1294 1294 + static struct spi_nor_erase_command * 1295 1295 + spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1296 1296 + const struct spi_nor_erase_type *erase) 1297 1297 + { 1298 1298 + struct spi_nor_erase_command *cmd; 1299 1299 + 1300 1300 + cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1301 1301 + if (!cmd) 1302 1302 + return ERR_PTR(-ENOMEM); 1303 1303 + 1304 1304 + INIT_LIST_HEAD(&cmd->list); 1305 1305 + cmd->opcode = erase->opcode; 1306 1306 + cmd->count = 1; 1307 1307 + 1308 1308 + if (region->offset & SNOR_OVERLAID_REGION) 1309 1309 + cmd->size = region->size; 1310 1310 + else 1311 1311 + cmd->size = erase->size; 1312 1312 + 1313 1313 + return cmd; 1314 1314 + } 1315 1315 + 1316 1316 + /** 1317 1317 + * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1318 1318 + * @erase_list: list of erase commands 1319 1319 + */ 1320 1320 + static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1321 1321 + { 1322 1322 + struct spi_nor_erase_command *cmd, *next; 1323 1323 + 1324 1324 + list_for_each_entry_safe(cmd, next, erase_list, list) { 1325 1325 + list_del(&cmd->list); 1326 1326 + kfree(cmd); 1327 1327 + } 1328 1328 + } 1329 1329 + 1330 1330 + /** 1331 1331 + * spi_nor_init_erase_cmd_list() - initialize erase command list 1332 1332 + * @nor: pointer to a 'struct spi_nor' 1333 1333 + * @erase_list: list of erase commands to be executed once we validate that the 1334 1334 + * erase can be performed 1335 1335 + * @addr: offset in the serial flash memory 1336 1336 + * @len: number of bytes to erase 1337 1337 + * 1338 1338 + * Builds the list of best fitted erase commands and verifies if the erase can 1339 1339 + * be performed. 1340 1340 + * 1341 1341 + * Return: 0 on success, -errno otherwise. 1342 1342 + */ 1343 1343 + static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1344 1344 + struct list_head *erase_list, 1345 1345 + u64 addr, u32 len) 1346 1346 + { 1347 1347 + const struct spi_nor_erase_map *map = &nor->params->erase_map; 1348 1348 + const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1349 1349 + struct spi_nor_erase_region *region; 1350 1350 + struct spi_nor_erase_command *cmd = NULL; 1351 1351 + u64 region_end; 1352 1352 + int ret = -EINVAL; 1353 1353 + 1354 1354 + region = spi_nor_find_erase_region(map, addr); 1355 1355 + if (IS_ERR(region)) 1356 1356 + return PTR_ERR(region); 1357 1357 + 1358 1358 + region_end = spi_nor_region_end(region); 1359 1359 + 1360 1360 + while (len) { 1361 1361 + erase = spi_nor_find_best_erase_type(map, region, addr, len); 1362 1362 + if (!erase) 1363 1363 + goto destroy_erase_cmd_list; 1364 1364 + 1365 1365 + if (prev_erase != erase || 1366 1366 + region->offset & SNOR_OVERLAID_REGION) { 1367 1367 + cmd = spi_nor_init_erase_cmd(region, erase); 1368 1368 + if (IS_ERR(cmd)) { 1369 1369 + ret = PTR_ERR(cmd); 1370 1370 + goto destroy_erase_cmd_list; 1371 1371 + } 1372 1372 + 1373 1373 + list_add_tail(&cmd->list, erase_list); 1374 1374 + } else { 1375 1375 + cmd->count++; 1376 1376 + } 1377 1377 + 1378 1378 + addr += cmd->size; 1379 1379 + len -= cmd->size; 1380 1380 + 1381 1381 + if (len && addr >= region_end) { 1382 1382 + region = spi_nor_region_next(region); 1383 1383 + if (!region) 1384 1384 + goto destroy_erase_cmd_list; 1385 1385 + region_end = spi_nor_region_end(region); 1386 1386 + } 1387 1387 + 1388 1388 + prev_erase = erase; 1389 1389 + } 1390 1390 + 1391 1391 + return 0; 1392 1392 + 1393 1393 + destroy_erase_cmd_list: 1394 1394 + spi_nor_destroy_erase_cmd_list(erase_list); 1395 1395 + return ret; 1396 1396 + } 1397 1397 + 1398 1398 + /** 1399 1399 + * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1400 1400 + * @nor: pointer to a 'struct spi_nor' 1401 1401 + * @addr: offset in the serial flash memory 1402 1402 + * @len: number of bytes to erase 1403 1403 + * 1404 1404 + * Build a list of best fitted erase commands and execute it once we validate 1405 1405 + * that the erase can be performed. 1406 1406 + * 1407 1407 + * Return: 0 on success, -errno otherwise. 1408 1408 + */ 1409 1409 + static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1410 1410 + { 1411 1411 + LIST_HEAD(erase_list); 1412 1412 + struct spi_nor_erase_command *cmd, *next; 1413 1413 + int ret; 1414 1414 + 1415 1415 + ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1416 1416 + if (ret) 1417 1417 + return ret; 1418 1418 + 1419 1419 + list_for_each_entry_safe(cmd, next, &erase_list, list) { 1420 1420 + nor->erase_opcode = cmd->opcode; 1421 1421 + while (cmd->count) { 1422 1422 + ret = spi_nor_write_enable(nor); 1423 1423 + if (ret) 1424 1424 + goto destroy_erase_cmd_list; 1425 1425 + 1426 1426 + ret = spi_nor_erase_sector(nor, addr); 1427 1427 + if (ret) 1428 1428 + goto destroy_erase_cmd_list; 1429 1429 + 1430 1430 + addr += cmd->size; 1431 1431 + cmd->count--; 1432 1432 + 1433 1433 + ret = spi_nor_wait_till_ready(nor); 1434 1434 + if (ret) 1435 1435 + goto destroy_erase_cmd_list; 1436 1436 + } 1437 1437 + list_del(&cmd->list); 1438 1438 + kfree(cmd); 1439 1439 + } 1440 1440 + 1441 1441 + return 0; 1442 1442 + 1443 1443 + destroy_erase_cmd_list: 1444 1444 + spi_nor_destroy_erase_cmd_list(&erase_list); 1445 1445 + return ret; 1446 1446 + } 1447 1447 + 1448 1448 + /* 1449 1449 + * Erase an address range on the nor chip. The address range may extend 1450 1450 + * one or more erase sectors. Return an error is there is a problem erasing. 1451 1451 + */ 1452 1452 + static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1453 1453 + { 1454 1454 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 1455 1455 + u32 addr, len; 1456 1456 + uint32_t rem; 1457 1457 + int ret; 1458 1458 + 1459 1459 + dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1460 1460 + (long long)instr->len); 1461 1461 + 1462 1462 + if (spi_nor_has_uniform_erase(nor)) { 1463 1463 + div_u64_rem(instr->len, mtd->erasesize, &rem); 1464 1464 + if (rem) 1465 1465 + return -EINVAL; 1466 1466 + } 1467 1467 + 1468 1468 + addr = instr->addr; 1469 1469 + len = instr->len; 1470 1470 + 1471 1471 + ret = spi_nor_lock_and_prep(nor); 1472 1472 + if (ret) 1473 1473 + return ret; 1474 1474 + 1475 1475 + /* whole-chip erase? */ 1476 1476 + if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1477 1477 + unsigned long timeout; 1478 1478 + 1479 1479 + ret = spi_nor_write_enable(nor); 1480 1480 + if (ret) 1481 1481 + goto erase_err; 1482 1482 + 1483 1483 + ret = spi_nor_erase_chip(nor); 1484 1484 + if (ret) 1485 1485 + goto erase_err; 1486 1486 + 1487 1487 + /* 1488 1488 + * Scale the timeout linearly with the size of the flash, with 1489 1489 + * a minimum calibrated to an old 2MB flash. We could try to 1490 1490 + * pull these from CFI/SFDP, but these values should be good 1491 1491 + * enough for now. 1492 1492 + */ 1493 1493 + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1494 1494 + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1495 1495 + (unsigned long)(mtd->size / SZ_2M)); 1496 1496 + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1497 1497 + if (ret) 1498 1498 + goto erase_err; 1499 1499 + 1500 1500 + /* REVISIT in some cases we could speed up erasing large regions 1501 1501 + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1502 1502 + * to use "small sector erase", but that's not always optimal. 1503 1503 + */ 1504 1504 + 1505 1505 + /* "sector"-at-a-time erase */ 1506 1506 + } else if (spi_nor_has_uniform_erase(nor)) { 1507 1507 + while (len) { 1508 1508 + ret = spi_nor_write_enable(nor); 1509 1509 + if (ret) 1510 1510 + goto erase_err; 1511 1511 + 1512 1512 + ret = spi_nor_erase_sector(nor, addr); 1513 1513 + if (ret) 1514 1514 + goto erase_err; 1515 1515 + 1516 1516 + addr += mtd->erasesize; 1517 1517 + len -= mtd->erasesize; 1518 1518 + 1519 1519 + ret = spi_nor_wait_till_ready(nor); 1520 1520 + if (ret) 1521 1521 + goto erase_err; 1522 1522 + } 1523 1523 + 1524 1524 + /* erase multiple sectors */ 1525 1525 + } else { 1526 1526 + ret = spi_nor_erase_multi_sectors(nor, addr, len); 1527 1527 + if (ret) 1528 1528 + goto erase_err; 1529 1529 + } 1530 1530 + 1531 1531 + ret = spi_nor_write_disable(nor); 1532 1532 + 1533 1533 + erase_err: 1534 1534 + spi_nor_unlock_and_unprep(nor); 1535 1535 + 1536 1536 + return ret; 1537 1537 + } 1538 1538 + 1539 1539 + static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) 1540 1540 + { 1541 1541 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1542 1542 + 1543 1543 + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) 1544 1544 + return mask | SR_BP3_BIT6; 1545 1545 + 1546 1546 + if (nor->flags & SNOR_F_HAS_4BIT_BP) 1547 1547 + return mask | SR_BP3; 1548 1548 + 1549 1549 + return mask; 1550 1550 + } 1551 1551 + 1552 1552 + static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) 1553 1553 + { 1554 1554 + if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1555 1555 + return SR_TB_BIT6; 1556 1556 + else 1557 1557 + return SR_TB_BIT5; 1558 1558 + } 1559 1559 + 1560 1560 + static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) 1561 1561 + { 1562 1562 + unsigned int bp_slots, bp_slots_needed; 1563 1563 + u8 mask = spi_nor_get_sr_bp_mask(nor); 1564 1564 + 1565 1565 + /* Reserved one for "protect none" and one for "protect all". */ 1566 1566 + bp_slots = (1 << hweight8(mask)) - 2; 1567 1567 + bp_slots_needed = ilog2(nor->info->n_sectors); 1568 1568 + 1569 1569 + if (bp_slots_needed > bp_slots) 1570 1570 + return nor->info->sector_size << 1571 1571 + (bp_slots_needed - bp_slots); 1572 1572 + else 1573 1573 + return nor->info->sector_size; 1574 1574 + } 1575 1575 + 1576 1576 + static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, 1577 1577 + uint64_t *len) 1578 1578 + { 1579 1579 + struct mtd_info *mtd = &nor->mtd; 1580 1580 + u64 min_prot_len; 1581 1581 + u8 mask = spi_nor_get_sr_bp_mask(nor); 1582 1582 + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1583 1583 + u8 bp, val = sr & mask; 1584 1584 + 1585 1585 + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) 1586 1586 + val = (val & ~SR_BP3_BIT6) | SR_BP3; 1587 1587 + 1588 1588 + bp = val >> SR_BP_SHIFT; 1589 1589 + 1590 1590 + if (!bp) { 1591 1591 + /* No protection */ 1592 1592 + *ofs = 0; 1593 1593 + *len = 0; 1594 1594 + return; 1595 1595 + } 1596 1596 + 1597 1597 + min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1598 1598 + *len = min_prot_len << (bp - 1); 1599 1599 + 1600 1600 + if (*len > mtd->size) 1601 1601 + *len = mtd->size; 1602 1602 + 1603 1603 + if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) 1604 1604 + *ofs = 0; 1605 1605 + else 1606 1606 + *ofs = mtd->size - *len; 1607 1607 + } 1608 1608 + 1609 1609 + /* 1610 1610 + * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 1611 1611 + * @locked is false); 0 otherwise 1612 1612 + */ 1613 1613 + static int spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, 1614 1614 + uint64_t len, u8 sr, bool locked) 1615 1615 + { 1616 1616 + loff_t lock_offs; 1617 1617 + uint64_t lock_len; 1618 1618 + 1619 1619 + if (!len) 1620 1620 + return 1; 1621 1621 + 1622 1622 + spi_nor_get_locked_range_sr(nor, sr, &lock_offs, &lock_len); 1623 1623 + 1624 1624 + if (locked) 1625 1625 + /* Requested range is a sub-range of locked range */ 1626 1626 + return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 1627 1627 + else 1628 1628 + /* Requested range does not overlap with locked range */ 1629 1629 + return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 1630 1630 + } 1631 1631 + 1632 1632 + static int spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1633 1633 + u8 sr) 1634 1634 + { 1635 1635 + return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); 1636 1636 + } 1637 1637 + 1638 1638 + static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1639 1639 + u8 sr) 1640 1640 + { 1641 1641 + return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); 1642 1642 + } 1643 1643 + 1644 1644 + /* 1645 1645 + * Lock a region of the flash. Compatible with ST Micro and similar flash. 1646 1646 + * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status 1647 1647 + * register 1648 1648 + * (SR). Does not support these features found in newer SR bitfields: 1649 1649 + * - SEC: sector/block protect - only handle SEC=0 (block protect) 1650 1650 + * - CMP: complement protect - only support CMP=0 (range is not complemented) 1651 1651 + * 1652 1652 + * Support for the following is provided conditionally for some flash: 1653 1653 + * - TB: top/bottom protect 1654 1654 + * 1655 1655 + * Sample table portion for 8MB flash (Winbond w25q64fw): 1656 1656 + * 1657 1657 + * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 1658 1658 + * -------------------------------------------------------------------------- 1659 1659 + * X | X | 0 | 0 | 0 | NONE | NONE 1660 1660 + * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 1661 1661 + * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 1662 1662 + * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 1663 1663 + * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 1664 1664 + * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 1665 1665 + * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 1666 1666 + * X | X | 1 | 1 | 1 | 8 MB | ALL 1667 1667 + * ------|-------|-------|-------|-------|---------------|------------------- 1668 1668 + * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 1669 1669 + * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 1670 1670 + * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 1671 1671 + * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 1672 1672 + * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 1673 1673 + * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 1674 1674 + * 1675 1675 + * Returns negative on errors, 0 on success. 1676 1676 + */ 1677 1677 + static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1678 1678 + { 1679 1679 + struct mtd_info *mtd = &nor->mtd; 1680 1680 + u64 min_prot_len; 1681 1681 + int ret, status_old, status_new; 1682 1682 + u8 mask = spi_nor_get_sr_bp_mask(nor); 1683 1683 + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1684 1684 + u8 pow, val; 1685 1685 + loff_t lock_len; 1686 1686 + bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1687 1687 + bool use_top; 1688 1688 + 1689 1689 + ret = spi_nor_read_sr(nor, nor->bouncebuf); 1690 1690 + if (ret) 1691 1691 + return ret; 1692 1692 + 1693 1693 + status_old = nor->bouncebuf[0]; 1694 1694 + 1695 1695 + /* If nothing in our range is unlocked, we don't need to do anything */ 1696 1696 + if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) 1697 1697 + return 0; 1698 1698 + 1699 1699 + /* If anything below us is unlocked, we can't use 'bottom' protection */ 1700 1700 + if (!spi_nor_is_locked_sr(nor, 0, ofs, status_old)) 1701 1701 + can_be_bottom = false; 1702 1702 + 1703 1703 + /* If anything above us is unlocked, we can't use 'top' protection */ 1704 1704 + if (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 1705 1705 + status_old)) 1706 1706 + can_be_top = false; 1707 1707 + 1708 1708 + if (!can_be_bottom && !can_be_top) 1709 1709 + return -EINVAL; 1710 1710 + 1711 1711 + /* Prefer top, if both are valid */ 1712 1712 + use_top = can_be_top; 1713 1713 + 1714 1714 + /* lock_len: length of region that should end up locked */ 1715 1715 + if (use_top) 1716 1716 + lock_len = mtd->size - ofs; 1717 1717 + else 1718 1718 + lock_len = ofs + len; 1719 1719 + 1720 1720 + if (lock_len == mtd->size) { 1721 1721 + val = mask; 1722 1722 + } else { 1723 1723 + min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1724 1724 + pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 1725 1725 + val = pow << SR_BP_SHIFT; 1726 1726 + 1727 1727 + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 1728 1728 + val = (val & ~SR_BP3) | SR_BP3_BIT6; 1729 1729 + 1730 1730 + if (val & ~mask) 1731 1731 + return -EINVAL; 1732 1732 + 1733 1733 + /* Don't "lock" with no region! */ 1734 1734 + if (!(val & mask)) 1735 1735 + return -EINVAL; 1736 1736 + } 1737 1737 + 1738 1738 + status_new = (status_old & ~mask & ~tb_mask) | val; 1739 1739 + 1740 1740 + /* Disallow further writes if WP pin is asserted */ 1741 1741 + status_new |= SR_SRWD; 1742 1742 + 1743 1743 + if (!use_top) 1744 1744 + status_new |= tb_mask; 1745 1745 + 1746 1746 + /* Don't bother if they're the same */ 1747 1747 + if (status_new == status_old) 1748 1748 + return 0; 1749 1749 + 1750 1750 + /* Only modify protection if it will not unlock other areas */ 1751 1751 + if ((status_new & mask) < (status_old & mask)) 1752 1752 + return -EINVAL; 1753 1753 + 1754 1754 + return spi_nor_write_sr_and_check(nor, status_new); 1755 1755 + } 1756 1756 + 1757 1757 + /* 1758 1758 + * Unlock a region of the flash. See spi_nor_sr_lock() for more info 1759 1759 + * 1760 1760 + * Returns negative on errors, 0 on success. 1761 1761 + */ 1762 1762 + static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1763 1763 + { 1764 1764 + struct mtd_info *mtd = &nor->mtd; 1765 1765 + u64 min_prot_len; 1766 1766 + int ret, status_old, status_new; 1767 1767 + u8 mask = spi_nor_get_sr_bp_mask(nor); 1768 1768 + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1769 1769 + u8 pow, val; 1770 1770 + loff_t lock_len; 1771 1771 + bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1772 1772 + bool use_top; 1773 1773 + 1774 1774 + ret = spi_nor_read_sr(nor, nor->bouncebuf); 1775 1775 + if (ret) 1776 1776 + return ret; 1777 1777 + 1778 1778 + status_old = nor->bouncebuf[0]; 1779 1779 + 1780 1780 + /* If nothing in our range is locked, we don't need to do anything */ 1781 1781 + if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) 1782 1782 + return 0; 1783 1783 + 1784 1784 + /* If anything below us is locked, we can't use 'top' protection */ 1785 1785 + if (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old)) 1786 1786 + can_be_top = false; 1787 1787 + 1788 1788 + /* If anything above us is locked, we can't use 'bottom' protection */ 1789 1789 + if (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 1790 1790 + status_old)) 1791 1791 + can_be_bottom = false; 1792 1792 + 1793 1793 + if (!can_be_bottom && !can_be_top) 1794 1794 + return -EINVAL; 1795 1795 + 1796 1796 + /* Prefer top, if both are valid */ 1797 1797 + use_top = can_be_top; 1798 1798 + 1799 1799 + /* lock_len: length of region that should remain locked */ 1800 1800 + if (use_top) 1801 1801 + lock_len = mtd->size - (ofs + len); 1802 1802 + else 1803 1803 + lock_len = ofs; 1804 1804 + 1805 1805 + if (lock_len == 0) { 1806 1806 + val = 0; /* fully unlocked */ 1807 1807 + } else { 1808 1808 + min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1809 1809 + pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 1810 1810 + val = pow << SR_BP_SHIFT; 1811 1811 + 1812 1812 + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 1813 1813 + val = (val & ~SR_BP3) | SR_BP3_BIT6; 1814 1814 + 1815 1815 + /* Some power-of-two sizes are not supported */ 1816 1816 + if (val & ~mask) 1817 1817 + return -EINVAL; 1818 1818 + } 1819 1819 + 1820 1820 + status_new = (status_old & ~mask & ~tb_mask) | val; 1821 1821 + 1822 1822 + /* Don't protect status register if we're fully unlocked */ 1823 1823 + if (lock_len == 0) 1824 1824 + status_new &= ~SR_SRWD; 1825 1825 + 1826 1826 + if (!use_top) 1827 1827 + status_new |= tb_mask; 1828 1828 + 1829 1829 + /* Don't bother if they're the same */ 1830 1830 + if (status_new == status_old) 1831 1831 + return 0; 1832 1832 + 1833 1833 + /* Only modify protection if it will not lock other areas */ 1834 1834 + if ((status_new & mask) > (status_old & mask)) 1835 1835 + return -EINVAL; 1836 1836 + 1837 1837 + return spi_nor_write_sr_and_check(nor, status_new); 1838 1838 + } 1839 1839 + 1840 1840 + /* 1841 1841 + * Check if a region of the flash is (completely) locked. See spi_nor_sr_lock() 1842 1842 + * for more info. 1843 1843 + * 1844 1844 + * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 1845 1845 + * negative on errors. 1846 1846 + */ 1847 1847 + static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 1848 1848 + { 1849 1849 + int ret; 1850 1850 + 1851 1851 + ret = spi_nor_read_sr(nor, nor->bouncebuf); 1852 1852 + if (ret) 1853 1853 + return ret; 1854 1854 + 1855 1855 + return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); 1856 1856 + } 1857 1857 + 1858 1858 + static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = { 1859 1859 + .lock = spi_nor_sr_lock, 1860 1860 + .unlock = spi_nor_sr_unlock, 1861 1861 + .is_locked = spi_nor_sr_is_locked, 1862 1862 + }; 1863 1863 + 1864 1864 + static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1865 1865 + { 1866 1866 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 1867 1867 + int ret; 1868 1868 + 1869 1869 + ret = spi_nor_lock_and_prep(nor); 1870 1870 + if (ret) 1871 1871 + return ret; 1872 1872 + 1873 1873 + ret = nor->params->locking_ops->lock(nor, ofs, len); 1874 1874 + 1875 1875 + spi_nor_unlock_and_unprep(nor); 1876 1876 + return ret; 1877 1877 + } 1878 1878 + 1879 1879 + static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1880 1880 + { 1881 1881 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 1882 1882 + int ret; 1883 1883 + 1884 1884 + ret = spi_nor_lock_and_prep(nor); 1885 1885 + if (ret) 1886 1886 + return ret; 1887 1887 + 1888 1888 + ret = nor->params->locking_ops->unlock(nor, ofs, len); 1889 1889 + 1890 1890 + spi_nor_unlock_and_unprep(nor); 1891 1891 + return ret; 1892 1892 + } 1893 1893 + 1894 1894 + static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1895 1895 + { 1896 1896 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 1897 1897 + int ret; 1898 1898 + 1899 1899 + ret = spi_nor_lock_and_prep(nor); 1900 1900 + if (ret) 1901 1901 + return ret; 1902 1902 + 1903 1903 + ret = nor->params->locking_ops->is_locked(nor, ofs, len); 1904 1904 + 1905 1905 + spi_nor_unlock_and_unprep(nor); 1906 1906 + return ret; 1907 1907 + } 1908 1908 + 1909 1909 + /** 1910 1910 + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 1911 1911 + * Register 1. 1912 1912 + * @nor: pointer to a 'struct spi_nor' 1913 1913 + * 1914 1914 + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 1915 1915 + * 1916 1916 + * Return: 0 on success, -errno otherwise. 1917 1917 + */ 1918 1918 + int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 1919 1919 + { 1920 1920 + int ret; 1921 1921 + 1922 1922 + ret = spi_nor_read_sr(nor, nor->bouncebuf); 1923 1923 + if (ret) 1924 1924 + return ret; 1925 1925 + 1926 1926 + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 1927 1927 + return 0; 1928 1928 + 1929 1929 + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 1930 1930 + 1931 1931 + return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 1932 1932 + } 1933 1933 + 1934 1934 + /** 1935 1935 + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 1936 1936 + * Register 2. 1937 1937 + * @nor: pointer to a 'struct spi_nor'. 1938 1938 + * 1939 1939 + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 1940 1940 + * 1941 1941 + * Return: 0 on success, -errno otherwise. 1942 1942 + */ 1943 1943 + int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 1944 1944 + { 1945 1945 + int ret; 1946 1946 + 1947 1947 + if (nor->flags & SNOR_F_NO_READ_CR) 1948 1948 + return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 1949 1949 + 1950 1950 + ret = spi_nor_read_cr(nor, nor->bouncebuf); 1951 1951 + if (ret) 1952 1952 + return ret; 1953 1953 + 1954 1954 + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 1955 1955 + return 0; 1956 1956 + 1957 1957 + nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 1958 1958 + 1959 1959 + return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 1960 1960 + } 1961 1961 + 1962 1962 + /** 1963 1963 + * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 1964 1964 + * @nor: pointer to a 'struct spi_nor' 1965 1965 + * 1966 1966 + * Set the Quad Enable (QE) bit in the Status Register 2. 1967 1967 + * 1968 1968 + * This is one of the procedures to set the QE bit described in the SFDP 1969 1969 + * (JESD216 rev B) specification but no manufacturer using this procedure has 1970 1970 + * been identified yet, hence the name of the function. 1971 1971 + * 1972 1972 + * Return: 0 on success, -errno otherwise. 1973 1973 + */ 1974 1974 + int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 1975 1975 + { 1976 1976 + u8 *sr2 = nor->bouncebuf; 1977 1977 + int ret; 1978 1978 + u8 sr2_written; 1979 1979 + 1980 1980 + /* Check current Quad Enable bit value. */ 1981 1981 + ret = spi_nor_read_sr2(nor, sr2); 1982 1982 + if (ret) 1983 1983 + return ret; 1984 1984 + if (*sr2 & SR2_QUAD_EN_BIT7) 1985 1985 + return 0; 1986 1986 + 1987 1987 + /* Update the Quad Enable bit. */ 1988 1988 + *sr2 |= SR2_QUAD_EN_BIT7; 1989 1989 + 1990 1990 + ret = spi_nor_write_sr2(nor, sr2); 1991 1991 + if (ret) 1992 1992 + return ret; 1993 1993 + 1994 1994 + sr2_written = *sr2; 1995 1995 + 1996 1996 + /* Read back and check it. */ 1997 1997 + ret = spi_nor_read_sr2(nor, sr2); 1998 1998 + if (ret) 1999 1999 + return ret; 2000 2000 + 2001 2001 + if (*sr2 != sr2_written) { 2002 2002 + dev_dbg(nor->dev, "SR2: Read back test failed\n"); 2003 2003 + return -EIO; 2004 2004 + } 2005 2005 + 2006 2006 + return 0; 2007 2007 + } 2008 2008 + 2009 2009 + static const struct spi_nor_manufacturer *manufacturers[] = { 2010 2010 + &spi_nor_atmel, 2011 2011 + &spi_nor_catalyst, 2012 2012 + &spi_nor_eon, 2013 2013 + &spi_nor_esmt, 2014 2014 + &spi_nor_everspin, 2015 2015 + &spi_nor_fujitsu, 2016 2016 + &spi_nor_gigadevice, 2017 2017 + &spi_nor_intel, 2018 2018 + &spi_nor_issi, 2019 2019 + &spi_nor_macronix, 2020 2020 + &spi_nor_micron, 2021 2021 + &spi_nor_st, 2022 2022 + &spi_nor_spansion, 2023 2023 + &spi_nor_sst, 2024 2024 + &spi_nor_winbond, 2025 2025 + &spi_nor_xilinx, 2026 2026 + &spi_nor_xmc, 2027 2027 + }; 2028 2028 + 2029 2029 + static const struct flash_info * 2030 2030 + spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts, 2031 2031 + const u8 *id) 2032 2032 + { 2033 2033 + unsigned int i; 2034 2034 + 2035 2035 + for (i = 0; i < nparts; i++) { 2036 2036 + if (parts[i].id_len && 2037 2037 + !memcmp(parts[i].id, id, parts[i].id_len)) 2038 2038 + return &parts[i]; 2039 2039 + } 2040 2040 + 2041 2041 + return NULL; 2042 2042 + } 2043 2043 + 2044 2044 + static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 2045 2045 + { 2046 2046 + const struct flash_info *info; 2047 2047 + u8 *id = nor->bouncebuf; 2048 2048 + unsigned int i; 2049 2049 + int ret; 2050 2050 + 2051 2051 + if (nor->spimem) { 2052 2052 + struct spi_mem_op op = 2053 2053 + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 2054 2054 + SPI_MEM_OP_NO_ADDR, 2055 2055 + SPI_MEM_OP_NO_DUMMY, 2056 2056 + SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); 2057 2057 + 2058 2058 + ret = spi_mem_exec_op(nor->spimem, &op); 2059 2059 + } else { 2060 2060 + ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 2061 2061 + SPI_NOR_MAX_ID_LEN); 2062 2062 + } 2063 2063 + if (ret) { 2064 2064 + dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 2065 2065 + return ERR_PTR(ret); 2066 2066 + } 2067 2067 + 2068 2068 + for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2069 2069 + info = spi_nor_search_part_by_id(manufacturers[i]->parts, 2070 2070 + manufacturers[i]->nparts, 2071 2071 + id); 2072 2072 + if (info) { 2073 2073 + nor->manufacturer = manufacturers[i]; 2074 2074 + return info; 2075 2075 + } 2076 2076 + } 2077 2077 + 2078 2078 + dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2079 2079 + SPI_NOR_MAX_ID_LEN, id); 2080 2080 + return ERR_PTR(-ENODEV); 2081 2081 + } 2082 2082 + 2083 2083 + static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2084 2084 + size_t *retlen, u_char *buf) 2085 2085 + { 2086 2086 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 2087 2087 + ssize_t ret; 2088 2088 + 2089 2089 + dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2090 2090 + 2091 2091 + ret = spi_nor_lock_and_prep(nor); 2092 2092 + if (ret) 2093 2093 + return ret; 2094 2094 + 2095 2095 + while (len) { 2096 2096 + loff_t addr = from; 2097 2097 + 2098 2098 + addr = spi_nor_convert_addr(nor, addr); 2099 2099 + 2100 2100 + ret = spi_nor_read_data(nor, addr, len, buf); 2101 2101 + if (ret == 0) { 2102 2102 + /* We shouldn't see 0-length reads */ 2103 2103 + ret = -EIO; 2104 2104 + goto read_err; 2105 2105 + } 2106 2106 + if (ret < 0) 2107 2107 + goto read_err; 2108 2108 + 2109 2109 + WARN_ON(ret > len); 2110 2110 + *retlen += ret; 2111 2111 + buf += ret; 2112 2112 + from += ret; 2113 2113 + len -= ret; 2114 2114 + } 2115 2115 + ret = 0; 2116 2116 + 2117 2117 + read_err: 2118 2118 + spi_nor_unlock_and_unprep(nor); 2119 2119 + return ret; 2120 2120 + } 2121 2121 + 2122 2122 + /* 2123 2123 + * Write an address range to the nor chip. Data must be written in 2124 2124 + * FLASH_PAGESIZE chunks. The address range may be any size provided 2125 2125 + * it is within the physical boundaries. 2126 2126 + */ 2127 2127 + static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2128 2128 + size_t *retlen, const u_char *buf) 2129 2129 + { 2130 2130 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 2131 2131 + size_t page_offset, page_remain, i; 2132 2132 + ssize_t ret; 2133 2133 + 2134 2134 + dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2135 2135 + 2136 2136 + ret = spi_nor_lock_and_prep(nor); 2137 2137 + if (ret) 2138 2138 + return ret; 2139 2139 + 2140 2140 + for (i = 0; i < len; ) { 2141 2141 + ssize_t written; 2142 2142 + loff_t addr = to + i; 2143 2143 + 2144 2144 + /* 2145 2145 + * If page_size is a power of two, the offset can be quickly 2146 2146 + * calculated with an AND operation. On the other cases we 2147 2147 + * need to do a modulus operation (more expensive). 2148 2148 + * Power of two numbers have only one bit set and we can use 2149 2149 + * the instruction hweight32 to detect if we need to do a 2150 2150 + * modulus (do_div()) or not. 2151 2151 + */ 2152 2152 + if (hweight32(nor->page_size) == 1) { 2153 2153 + page_offset = addr & (nor->page_size - 1); 2154 2154 + } else { 2155 2155 + uint64_t aux = addr; 2156 2156 + 2157 2157 + page_offset = do_div(aux, nor->page_size); 2158 2158 + } 2159 2159 + /* the size of data remaining on the first page */ 2160 2160 + page_remain = min_t(size_t, 2161 2161 + nor->page_size - page_offset, len - i); 2162 2162 + 2163 2163 + addr = spi_nor_convert_addr(nor, addr); 2164 2164 + 2165 2165 + ret = spi_nor_write_enable(nor); 2166 2166 + if (ret) 2167 2167 + goto write_err; 2168 2168 + 2169 2169 + ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 2170 2170 + if (ret < 0) 2171 2171 + goto write_err; 2172 2172 + written = ret; 2173 2173 + 2174 2174 + ret = spi_nor_wait_till_ready(nor); 2175 2175 + if (ret) 2176 2176 + goto write_err; 2177 2177 + *retlen += written; 2178 2178 + i += written; 2179 2179 + } 2180 2180 + 2181 2181 + write_err: 2182 2182 + spi_nor_unlock_and_unprep(nor); 2183 2183 + return ret; 2184 2184 + } 2185 2185 + 2186 2186 + static int spi_nor_check(struct spi_nor *nor) 2187 2187 + { 2188 2188 + if (!nor->dev || 2189 2189 + (!nor->spimem && !nor->controller_ops) || 2190 2190 + (!nor->spimem && nor->controller_ops && 2191 2191 + (!nor->controller_ops->read || 2192 2192 + !nor->controller_ops->write || 2193 2193 + !nor->controller_ops->read_reg || 2194 2194 + !nor->controller_ops->write_reg))) { 2195 2195 + pr_err("spi-nor: please fill all the necessary fields!\n"); 2196 2196 + return -EINVAL; 2197 2197 + } 2198 2198 + 2199 2199 + if (nor->spimem && nor->controller_ops) { 2200 2200 + dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2201 2201 + return -EINVAL; 2202 2202 + } 2203 2203 + 2204 2204 + return 0; 2205 2205 + } 2206 2206 + 2207 2207 + static void 2208 2208 + spi_nor_set_read_settings(struct spi_nor_read_command *read, 2209 2209 + u8 num_mode_clocks, 2210 2210 + u8 num_wait_states, 2211 2211 + u8 opcode, 2212 2212 + enum spi_nor_protocol proto) 2213 2213 + { 2214 2214 + read->num_mode_clocks = num_mode_clocks; 2215 2215 + read->num_wait_states = num_wait_states; 2216 2216 + read->opcode = opcode; 2217 2217 + read->proto = proto; 2218 2218 + } 2219 2219 + 2220 2220 + void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 2221 2221 + enum spi_nor_protocol proto) 2222 2222 + { 2223 2223 + pp->opcode = opcode; 2224 2224 + pp->proto = proto; 2225 2225 + } 2226 2226 + 2227 2227 + static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2228 2228 + { 2229 2229 + size_t i; 2230 2230 + 2231 2231 + for (i = 0; i < size; i++) 2232 2232 + if (table[i][0] == (int)hwcaps) 2233 2233 + return table[i][1]; 2234 2234 + 2235 2235 + return -EINVAL; 2236 2236 + } 2237 2237 + 2238 2238 + int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2239 2239 + { 2240 2240 + static const int hwcaps_read2cmd[][2] = { 2241 2241 + { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2242 2242 + { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2243 2243 + { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2244 2244 + { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2245 2245 + { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2246 2246 + { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2247 2247 + { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2248 2248 + { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2249 2249 + { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2250 2250 + { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2251 2251 + { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2252 2252 + { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2253 2253 + { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2254 2254 + { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2255 2255 + { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2256 2256 + }; 2257 2257 + 2258 2258 + return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2259 2259 + ARRAY_SIZE(hwcaps_read2cmd)); 2260 2260 + } 2261 2261 + 2262 2262 + static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2263 2263 + { 2264 2264 + static const int hwcaps_pp2cmd[][2] = { 2265 2265 + { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2266 2266 + { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2267 2267 + { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2268 2268 + { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2269 2269 + { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2270 2270 + { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2271 2271 + { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2272 2272 + }; 2273 2273 + 2274 2274 + return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2275 2275 + ARRAY_SIZE(hwcaps_pp2cmd)); 2276 2276 + } 2277 2277 + 2278 2278 + /** 2279 2279 + * spi_nor_spimem_check_op - check if the operation is supported 2280 2280 + * by controller 2281 2281 + *@nor: pointer to a 'struct spi_nor' 2282 2282 + *@op: pointer to op template to be checked 2283 2283 + * 2284 2284 + * Returns 0 if operation is supported, -ENOTSUPP otherwise. 2285 2285 + */ 2286 2286 + static int spi_nor_spimem_check_op(struct spi_nor *nor, 2287 2287 + struct spi_mem_op *op) 2288 2288 + { 2289 2289 + /* 2290 2290 + * First test with 4 address bytes. The opcode itself might 2291 2291 + * be a 3B addressing opcode but we don't care, because 2292 2292 + * SPI controller implementation should not check the opcode, 2293 2293 + * but just the sequence. 2294 2294 + */ 2295 2295 + op->addr.nbytes = 4; 2296 2296 + if (!spi_mem_supports_op(nor->spimem, op)) { 2297 2297 + if (nor->mtd.size > SZ_16M) 2298 2298 + return -ENOTSUPP; 2299 2299 + 2300 2300 + /* If flash size <= 16MB, 3 address bytes are sufficient */ 2301 2301 + op->addr.nbytes = 3; 2302 2302 + if (!spi_mem_supports_op(nor->spimem, op)) 2303 2303 + return -ENOTSUPP; 2304 2304 + } 2305 2305 + 2306 2306 + return 0; 2307 2307 + } 2308 2308 + 2309 2309 + /** 2310 2310 + * spi_nor_spimem_check_readop - check if the read op is supported 2311 2311 + * by controller 2312 2312 + *@nor: pointer to a 'struct spi_nor' 2313 2313 + *@read: pointer to op template to be checked 2314 2314 + * 2315 2315 + * Returns 0 if operation is supported, -ENOTSUPP otherwise. 2316 2316 + */ 2317 2317 + static int spi_nor_spimem_check_readop(struct spi_nor *nor, 2318 2318 + const struct spi_nor_read_command *read) 2319 2319 + { 2320 2320 + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1), 2321 2321 + SPI_MEM_OP_ADDR(3, 0, 1), 2322 2322 + SPI_MEM_OP_DUMMY(0, 1), 2323 2323 + SPI_MEM_OP_DATA_IN(0, NULL, 1)); 2324 2324 + 2325 2325 + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto); 2326 2326 + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto); 2327 2327 + op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto); 2328 2328 + op.dummy.buswidth = op.addr.buswidth; 2329 2329 + op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * 2330 2330 + op.dummy.buswidth / 8; 2331 2331 + 2332 2332 + return spi_nor_spimem_check_op(nor, &op); 2333 2333 + } 2334 2334 + 2335 2335 + /** 2336 2336 + * spi_nor_spimem_check_pp - check if the page program op is supported 2337 2337 + * by controller 2338 2338 + *@nor: pointer to a 'struct spi_nor' 2339 2339 + *@pp: pointer to op template to be checked 2340 2340 + * 2341 2341 + * Returns 0 if operation is supported, -ENOTSUPP otherwise. 2342 2342 + */ 2343 2343 + static int spi_nor_spimem_check_pp(struct spi_nor *nor, 2344 2344 + const struct spi_nor_pp_command *pp) 2345 2345 + { 2346 2346 + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1), 2347 2347 + SPI_MEM_OP_ADDR(3, 0, 1), 2348 2348 + SPI_MEM_OP_NO_DUMMY, 2349 2349 + SPI_MEM_OP_DATA_OUT(0, NULL, 1)); 2350 2350 + 2351 2351 + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto); 2352 2352 + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); 2353 2353 + op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); 2354 2354 + 2355 2355 + return spi_nor_spimem_check_op(nor, &op); 2356 2356 + } 2357 2357 + 2358 2358 + /** 2359 2359 + * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 2360 2360 + * based on SPI controller capabilities 2361 2361 + * @nor: pointer to a 'struct spi_nor' 2362 2362 + * @hwcaps: pointer to resulting capabilities after adjusting 2363 2363 + * according to controller and flash's capability 2364 2364 + */ 2365 2365 + static void 2366 2366 + spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 2367 2367 + { 2368 2368 + struct spi_nor_flash_parameter *params = nor->params; 2369 2369 + unsigned int cap; 2370 2370 + 2371 2371 + /* DTR modes are not supported yet, mask them all. */ 2372 2372 + *hwcaps &= ~SNOR_HWCAPS_DTR; 2373 2373 + 2374 2374 + /* X-X-X modes are not supported yet, mask them all. */ 2375 2375 + *hwcaps &= ~SNOR_HWCAPS_X_X_X; 2376 2376 + 2377 2377 + for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 2378 2378 + int rdidx, ppidx; 2379 2379 + 2380 2380 + if (!(*hwcaps & BIT(cap))) 2381 2381 + continue; 2382 2382 + 2383 2383 + rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 2384 2384 + if (rdidx >= 0 && 2385 2385 + spi_nor_spimem_check_readop(nor, &params->reads[rdidx])) 2386 2386 + *hwcaps &= ~BIT(cap); 2387 2387 + 2388 2388 + ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 2389 2389 + if (ppidx < 0) 2390 2390 + continue; 2391 2391 + 2392 2392 + if (spi_nor_spimem_check_pp(nor, 2393 2393 + &params->page_programs[ppidx])) 2394 2394 + *hwcaps &= ~BIT(cap); 2395 2395 + } 2396 2396 + } 2397 2397 + 2398 2398 + /** 2399 2399 + * spi_nor_set_erase_type() - set a SPI NOR erase type 2400 2400 + * @erase: pointer to a structure that describes a SPI NOR erase type 2401 2401 + * @size: the size of the sector/block erased by the erase type 2402 2402 + * @opcode: the SPI command op code to erase the sector/block 2403 2403 + */ 2404 2404 + void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2405 2405 + u8 opcode) 2406 2406 + { 2407 2407 + erase->size = size; 2408 2408 + erase->opcode = opcode; 2409 2409 + /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2410 2410 + erase->size_shift = ffs(erase->size) - 1; 2411 2411 + erase->size_mask = (1 << erase->size_shift) - 1; 2412 2412 + } 2413 2413 + 2414 2414 + /** 2415 2415 + * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2416 2416 + * @map: the erase map of the SPI NOR 2417 2417 + * @erase_mask: bitmask encoding erase types that can erase the entire 2418 2418 + * flash memory 2419 2419 + * @flash_size: the spi nor flash memory size 2420 2420 + */ 2421 2421 + void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2422 2422 + u8 erase_mask, u64 flash_size) 2423 2423 + { 2424 2424 + /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 2425 2425 + map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 2426 2426 + SNOR_LAST_REGION; 2427 2427 + map->uniform_region.size = flash_size; 2428 2428 + map->regions = &map->uniform_region; 2429 2429 + map->uniform_erase_type = erase_mask; 2430 2430 + } 2431 2431 + 2432 2432 + int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2433 2433 + const struct sfdp_parameter_header *bfpt_header, 2434 2434 + const struct sfdp_bfpt *bfpt, 2435 2435 + struct spi_nor_flash_parameter *params) 2436 2436 + { 2437 2437 + int ret; 2438 2438 + 2439 2439 + if (nor->manufacturer && nor->manufacturer->fixups && 2440 2440 + nor->manufacturer->fixups->post_bfpt) { 2441 2441 + ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2442 2442 + bfpt, params); 2443 2443 + if (ret) 2444 2444 + return ret; 2445 2445 + } 2446 2446 + 2447 2447 + if (nor->info->fixups && nor->info->fixups->post_bfpt) 2448 2448 + return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt, 2449 2449 + params); 2450 2450 + 2451 2451 + return 0; 2452 2452 + } 2453 2453 + 2454 2454 + static int spi_nor_select_read(struct spi_nor *nor, 2455 2455 + u32 shared_hwcaps) 2456 2456 + { 2457 2457 + int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2458 2458 + const struct spi_nor_read_command *read; 2459 2459 + 2460 2460 + if (best_match < 0) 2461 2461 + return -EINVAL; 2462 2462 + 2463 2463 + cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2464 2464 + if (cmd < 0) 2465 2465 + return -EINVAL; 2466 2466 + 2467 2467 + read = &nor->params->reads[cmd]; 2468 2468 + nor->read_opcode = read->opcode; 2469 2469 + nor->read_proto = read->proto; 2470 2470 + 2471 2471 + /* 2472 2472 + * In the spi-nor framework, we don't need to make the difference 2473 2473 + * between mode clock cycles and wait state clock cycles. 2474 2474 + * Indeed, the value of the mode clock cycles is used by a QSPI 2475 2475 + * flash memory to know whether it should enter or leave its 0-4-4 2476 2476 + * (Continuous Read / XIP) mode. 2477 2477 + * eXecution In Place is out of the scope of the mtd sub-system. 2478 2478 + * Hence we choose to merge both mode and wait state clock cycles 2479 2479 + * into the so called dummy clock cycles. 2480 2480 + */ 2481 2481 + nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2482 2482 + return 0; 2483 2483 + } 2484 2484 + 2485 2485 + static int spi_nor_select_pp(struct spi_nor *nor, 2486 2486 + u32 shared_hwcaps) 2487 2487 + { 2488 2488 + int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2489 2489 + const struct spi_nor_pp_command *pp; 2490 2490 + 2491 2491 + if (best_match < 0) 2492 2492 + return -EINVAL; 2493 2493 + 2494 2494 + cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2495 2495 + if (cmd < 0) 2496 2496 + return -EINVAL; 2497 2497 + 2498 2498 + pp = &nor->params->page_programs[cmd]; 2499 2499 + nor->program_opcode = pp->opcode; 2500 2500 + nor->write_proto = pp->proto; 2501 2501 + return 0; 2502 2502 + } 2503 2503 + 2504 2504 + /** 2505 2505 + * spi_nor_select_uniform_erase() - select optimum uniform erase type 2506 2506 + * @map: the erase map of the SPI NOR 2507 2507 + * @wanted_size: the erase type size to search for. Contains the value of 2508 2508 + * info->sector_size or of the "small sector" size in case 2509 2509 + * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined. 2510 2510 + * 2511 2511 + * Once the optimum uniform sector erase command is found, disable all the 2512 2512 + * other. 2513 2513 + * 2514 2514 + * Return: pointer to erase type on success, NULL otherwise. 2515 2515 + */ 2516 2516 + static const struct spi_nor_erase_type * 2517 2517 + spi_nor_select_uniform_erase(struct spi_nor_erase_map *map, 2518 2518 + const u32 wanted_size) 2519 2519 + { 2520 2520 + const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2521 2521 + int i; 2522 2522 + u8 uniform_erase_type = map->uniform_erase_type; 2523 2523 + 2524 2524 + for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2525 2525 + if (!(uniform_erase_type & BIT(i))) 2526 2526 + continue; 2527 2527 + 2528 2528 + tested_erase = &map->erase_type[i]; 2529 2529 + 2530 2530 + /* 2531 2531 + * If the current erase size is the one, stop here: 2532 2532 + * we have found the right uniform Sector Erase command. 2533 2533 + */ 2534 2534 + if (tested_erase->size == wanted_size) { 2535 2535 + erase = tested_erase; 2536 2536 + break; 2537 2537 + } 2538 2538 + 2539 2539 + /* 2540 2540 + * Otherwise, the current erase size is still a valid canditate. 2541 2541 + * Select the biggest valid candidate. 2542 2542 + */ 2543 2543 + if (!erase && tested_erase->size) 2544 2544 + erase = tested_erase; 2545 2545 + /* keep iterating to find the wanted_size */ 2546 2546 + } 2547 2547 + 2548 2548 + if (!erase) 2549 2549 + return NULL; 2550 2550 + 2551 2551 + /* Disable all other Sector Erase commands. */ 2552 2552 + map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 2553 2553 + map->uniform_erase_type |= BIT(erase - map->erase_type); 2554 2554 + return erase; 2555 2555 + } 2556 2556 + 2557 2557 + static int spi_nor_select_erase(struct spi_nor *nor) 2558 2558 + { 2559 2559 + struct spi_nor_erase_map *map = &nor->params->erase_map; 2560 2560 + const struct spi_nor_erase_type *erase = NULL; 2561 2561 + struct mtd_info *mtd = &nor->mtd; 2562 2562 + u32 wanted_size = nor->info->sector_size; 2563 2563 + int i; 2564 2564 + 2565 2565 + /* 2566 2566 + * The previous implementation handling Sector Erase commands assumed 2567 2567 + * that the SPI flash memory has an uniform layout then used only one 2568 2568 + * of the supported erase sizes for all Sector Erase commands. 2569 2569 + * So to be backward compatible, the new implementation also tries to 2570 2570 + * manage the SPI flash memory as uniform with a single erase sector 2571 2571 + * size, when possible. 2572 2572 + */ 2573 2573 + #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2574 2574 + /* prefer "small sector" erase if possible */ 2575 2575 + wanted_size = 4096u; 2576 2576 + #endif 2577 2577 + 2578 2578 + if (spi_nor_has_uniform_erase(nor)) { 2579 2579 + erase = spi_nor_select_uniform_erase(map, wanted_size); 2580 2580 + if (!erase) 2581 2581 + return -EINVAL; 2582 2582 + nor->erase_opcode = erase->opcode; 2583 2583 + mtd->erasesize = erase->size; 2584 2584 + return 0; 2585 2585 + } 2586 2586 + 2587 2587 + /* 2588 2588 + * For non-uniform SPI flash memory, set mtd->erasesize to the 2589 2589 + * maximum erase sector size. No need to set nor->erase_opcode. 2590 2590 + */ 2591 2591 + for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2592 2592 + if (map->erase_type[i].size) { 2593 2593 + erase = &map->erase_type[i]; 2594 2594 + break; 2595 2595 + } 2596 2596 + } 2597 2597 + 2598 2598 + if (!erase) 2599 2599 + return -EINVAL; 2600 2600 + 2601 2601 + mtd->erasesize = erase->size; 2602 2602 + return 0; 2603 2603 + } 2604 2604 + 2605 2605 + static int spi_nor_default_setup(struct spi_nor *nor, 2606 2606 + const struct spi_nor_hwcaps *hwcaps) 2607 2607 + { 2608 2608 + struct spi_nor_flash_parameter *params = nor->params; 2609 2609 + u32 ignored_mask, shared_mask; 2610 2610 + int err; 2611 2611 + 2612 2612 + /* 2613 2613 + * Keep only the hardware capabilities supported by both the SPI 2614 2614 + * controller and the SPI flash memory. 2615 2615 + */ 2616 2616 + shared_mask = hwcaps->mask & params->hwcaps.mask; 2617 2617 + 2618 2618 + if (nor->spimem) { 2619 2619 + /* 2620 2620 + * When called from spi_nor_probe(), all caps are set and we 2621 2621 + * need to discard some of them based on what the SPI 2622 2622 + * controller actually supports (using spi_mem_supports_op()). 2623 2623 + */ 2624 2624 + spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2625 2625 + } else { 2626 2626 + /* 2627 2627 + * SPI n-n-n protocols are not supported when the SPI 2628 2628 + * controller directly implements the spi_nor interface. 2629 2629 + * Yet another reason to switch to spi-mem. 2630 2630 + */ 2631 2631 + ignored_mask = SNOR_HWCAPS_X_X_X; 2632 2632 + if (shared_mask & ignored_mask) { 2633 2633 + dev_dbg(nor->dev, 2634 2634 + "SPI n-n-n protocols are not supported.\n"); 2635 2635 + shared_mask &= ~ignored_mask; 2636 2636 + } 2637 2637 + } 2638 2638 + 2639 2639 + /* Select the (Fast) Read command. */ 2640 2640 + err = spi_nor_select_read(nor, shared_mask); 2641 2641 + if (err) { 2642 2642 + dev_dbg(nor->dev, 2643 2643 + "can't select read settings supported by both the SPI controller and memory.\n"); 2644 2644 + return err; 2645 2645 + } 2646 2646 + 2647 2647 + /* Select the Page Program command. */ 2648 2648 + err = spi_nor_select_pp(nor, shared_mask); 2649 2649 + if (err) { 2650 2650 + dev_dbg(nor->dev, 2651 2651 + "can't select write settings supported by both the SPI controller and memory.\n"); 2652 2652 + return err; 2653 2653 + } 2654 2654 + 2655 2655 + /* Select the Sector Erase command. */ 2656 2656 + err = spi_nor_select_erase(nor); 2657 2657 + if (err) { 2658 2658 + dev_dbg(nor->dev, 2659 2659 + "can't select erase settings supported by both the SPI controller and memory.\n"); 2660 2660 + return err; 2661 2661 + } 2662 2662 + 2663 2663 + return 0; 2664 2664 + } 2665 2665 + 2666 2666 + static int spi_nor_setup(struct spi_nor *nor, 2667 2667 + const struct spi_nor_hwcaps *hwcaps) 2668 2668 + { 2669 2669 + if (!nor->params->setup) 2670 2670 + return 0; 2671 2671 + 2672 2672 + return nor->params->setup(nor, hwcaps); 2673 2673 + } 2674 2674 + 2675 2675 + /** 2676 2676 + * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2677 2677 + * settings based on MFR register and ->default_init() hook. 2678 2678 + * @nor: pointer to a 'struct spi-nor'. 2679 2679 + */ 2680 2680 + static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2681 2681 + { 2682 2682 + if (nor->manufacturer && nor->manufacturer->fixups && 2683 2683 + nor->manufacturer->fixups->default_init) 2684 2684 + nor->manufacturer->fixups->default_init(nor); 2685 2685 + 2686 2686 + if (nor->info->fixups && nor->info->fixups->default_init) 2687 2687 + nor->info->fixups->default_init(nor); 2688 2688 + } 2689 2689 + 2690 2690 + /** 2691 2691 + * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings 2692 2692 + * based on JESD216 SFDP standard. 2693 2693 + * @nor: pointer to a 'struct spi-nor'. 2694 2694 + * 2695 2695 + * The method has a roll-back mechanism: in case the SFDP parsing fails, the 2696 2696 + * legacy flash parameters and settings will be restored. 2697 2697 + */ 2698 2698 + static void spi_nor_sfdp_init_params(struct spi_nor *nor) 2699 2699 + { 2700 2700 + struct spi_nor_flash_parameter sfdp_params; 2701 2701 + 2702 2702 + memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 2703 2703 + 2704 2704 + if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2705 2705 + nor->addr_width = 0; 2706 2706 + nor->flags &= ~SNOR_F_4B_OPCODES; 2707 2707 + } else { 2708 2708 + memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 2709 2709 + } 2710 2710 + } 2711 2711 + 2712 2712 + /** 2713 2713 + * spi_nor_info_init_params() - Initialize the flash's parameters and settings 2714 2714 + * based on nor->info data. 2715 2715 + * @nor: pointer to a 'struct spi-nor'. 2716 2716 + */ 2717 2717 + static void spi_nor_info_init_params(struct spi_nor *nor) 2718 2718 + { 2719 2719 + struct spi_nor_flash_parameter *params = nor->params; 2720 2720 + struct spi_nor_erase_map *map = &params->erase_map; 2721 2721 + const struct flash_info *info = nor->info; 2722 2722 + struct device_node *np = spi_nor_get_flash_node(nor); 2723 2723 + u8 i, erase_mask; 2724 2724 + 2725 2725 + /* Initialize legacy flash parameters and settings. */ 2726 2726 + params->quad_enable = spi_nor_sr2_bit1_quad_enable; 2727 2727 + params->set_4byte_addr_mode = spansion_set_4byte_addr_mode; 2728 2728 + params->setup = spi_nor_default_setup; 2729 2729 + /* Default to 16-bit Write Status (01h) Command */ 2730 2730 + nor->flags |= SNOR_F_HAS_16BIT_SR; 2731 2731 + 2732 2732 + /* Set SPI NOR sizes. */ 2733 2733 + params->size = (u64)info->sector_size * info->n_sectors; 2734 2734 + params->page_size = info->page_size; 2735 2735 + 2736 2736 + if (!(info->flags & SPI_NOR_NO_FR)) { 2737 2737 + /* Default to Fast Read for DT and non-DT platform devices. */ 2738 2738 + params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2739 2739 + 2740 2740 + /* Mask out Fast Read if not requested at DT instantiation. */ 2741 2741 + if (np && !of_property_read_bool(np, "m25p,fast-read")) 2742 2742 + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2743 2743 + } 2744 2744 + 2745 2745 + /* (Fast) Read settings. */ 2746 2746 + params->hwcaps.mask |= SNOR_HWCAPS_READ; 2747 2747 + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ], 2748 2748 + 0, 0, SPINOR_OP_READ, 2749 2749 + SNOR_PROTO_1_1_1); 2750 2750 + 2751 2751 + if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 2752 2752 + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST], 2753 2753 + 0, 8, SPINOR_OP_READ_FAST, 2754 2754 + SNOR_PROTO_1_1_1); 2755 2755 + 2756 2756 + if (info->flags & SPI_NOR_DUAL_READ) { 2757 2757 + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2758 2758 + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2], 2759 2759 + 0, 8, SPINOR_OP_READ_1_1_2, 2760 2760 + SNOR_PROTO_1_1_2); 2761 2761 + } 2762 2762 + 2763 2763 + if (info->flags & SPI_NOR_QUAD_READ) { 2764 2764 + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2765 2765 + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4], 2766 2766 + 0, 8, SPINOR_OP_READ_1_1_4, 2767 2767 + SNOR_PROTO_1_1_4); 2768 2768 + } 2769 2769 + 2770 2770 + if (info->flags & SPI_NOR_OCTAL_READ) { 2771 2771 + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2772 2772 + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8], 2773 2773 + 0, 8, SPINOR_OP_READ_1_1_8, 2774 2774 + SNOR_PROTO_1_1_8); 2775 2775 + } 2776 2776 + 2777 2777 + /* Page Program settings. */ 2778 2778 + params->hwcaps.mask |= SNOR_HWCAPS_PP; 2779 2779 + spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP], 2780 2780 + SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2781 2781 + 2782 2782 + /* 2783 2783 + * Sector Erase settings. Sort Erase Types in ascending order, with the 2784 2784 + * smallest erase size starting at BIT(0). 2785 2785 + */ 2786 2786 + erase_mask = 0; 2787 2787 + i = 0; 2788 2788 + if (info->flags & SECT_4K_PMC) { 2789 2789 + erase_mask |= BIT(i); 2790 2790 + spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2791 2791 + SPINOR_OP_BE_4K_PMC); 2792 2792 + i++; 2793 2793 + } else if (info->flags & SECT_4K) { 2794 2794 + erase_mask |= BIT(i); 2795 2795 + spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2796 2796 + SPINOR_OP_BE_4K); 2797 2797 + i++; 2798 2798 + } 2799 2799 + erase_mask |= BIT(i); 2800 2800 + spi_nor_set_erase_type(&map->erase_type[i], info->sector_size, 2801 2801 + SPINOR_OP_SE); 2802 2802 + spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 2803 2803 + } 2804 2804 + 2805 2805 + /** 2806 2806 + * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings 2807 2807 + * after SFDP has been parsed (is also called for SPI NORs that do not 2808 2808 + * support RDSFDP). 2809 2809 + * @nor: pointer to a 'struct spi_nor' 2810 2810 + * 2811 2811 + * Typically used to tweak various parameters that could not be extracted by 2812 2812 + * other means (i.e. when information provided by the SFDP/flash_info tables 2813 2813 + * are incomplete or wrong). 2814 2814 + */ 2815 2815 + static void spi_nor_post_sfdp_fixups(struct spi_nor *nor) 2816 2816 + { 2817 2817 + if (nor->manufacturer && nor->manufacturer->fixups && 2818 2818 + nor->manufacturer->fixups->post_sfdp) 2819 2819 + nor->manufacturer->fixups->post_sfdp(nor); 2820 2820 + 2821 2821 + if (nor->info->fixups && nor->info->fixups->post_sfdp) 2822 2822 + nor->info->fixups->post_sfdp(nor); 2823 2823 + } 2824 2824 + 2825 2825 + /** 2826 2826 + * spi_nor_late_init_params() - Late initialization of default flash parameters. 2827 2827 + * @nor: pointer to a 'struct spi_nor' 2828 2828 + * 2829 2829 + * Used to set default flash parameters and settings when the ->default_init() 2830 2830 + * hook or the SFDP parser let voids. 2831 2831 + */ 2832 2832 + static void spi_nor_late_init_params(struct spi_nor *nor) 2833 2833 + { 2834 2834 + /* 2835 2835 + * NOR protection support. When locking_ops are not provided, we pick 2836 2836 + * the default ones. 2837 2837 + */ 2838 2838 + if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 2839 2839 + nor->params->locking_ops = &spi_nor_sr_locking_ops; 2840 2840 + } 2841 2841 + 2842 2842 + /** 2843 2843 + * spi_nor_init_params() - Initialize the flash's parameters and settings. 2844 2844 + * @nor: pointer to a 'struct spi-nor'. 2845 2845 + * 2846 2846 + * The flash parameters and settings are initialized based on a sequence of 2847 2847 + * calls that are ordered by priority: 2848 2848 + * 2849 2849 + * 1/ Default flash parameters initialization. The initializations are done 2850 2850 + * based on nor->info data: 2851 2851 + * spi_nor_info_init_params() 2852 2852 + * 2853 2853 + * which can be overwritten by: 2854 2854 + * 2/ Manufacturer flash parameters initialization. The initializations are 2855 2855 + * done based on MFR register, or when the decisions can not be done solely 2856 2856 + * based on MFR, by using specific flash_info tweeks, ->default_init(): 2857 2857 + * spi_nor_manufacturer_init_params() 2858 2858 + * 2859 2859 + * which can be overwritten by: 2860 2860 + * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 2861 2861 + * should be more accurate that the above. 2862 2862 + * spi_nor_sfdp_init_params() 2863 2863 + * 2864 2864 + * Please note that there is a ->post_bfpt() fixup hook that can overwrite 2865 2865 + * the flash parameters and settings immediately after parsing the Basic 2866 2866 + * Flash Parameter Table. 2867 2867 + * 2868 2868 + * which can be overwritten by: 2869 2869 + * 4/ Post SFDP flash parameters initialization. Used to tweak various 2870 2870 + * parameters that could not be extracted by other means (i.e. when 2871 2871 + * information provided by the SFDP/flash_info tables are incomplete or 2872 2872 + * wrong). 2873 2873 + * spi_nor_post_sfdp_fixups() 2874 2874 + * 2875 2875 + * 5/ Late default flash parameters initialization, used when the 2876 2876 + * ->default_init() hook or the SFDP parser do not set specific params. 2877 2877 + * spi_nor_late_init_params() 2878 2878 + */ 2879 2879 + static int spi_nor_init_params(struct spi_nor *nor) 2880 2880 + { 2881 2881 + nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 2882 2882 + if (!nor->params) 2883 2883 + return -ENOMEM; 2884 2884 + 2885 2885 + spi_nor_info_init_params(nor); 2886 2886 + 2887 2887 + spi_nor_manufacturer_init_params(nor); 2888 2888 + 2889 2889 + if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2890 2890 + !(nor->info->flags & SPI_NOR_SKIP_SFDP)) 2891 2891 + spi_nor_sfdp_init_params(nor); 2892 2892 + 2893 2893 + spi_nor_post_sfdp_fixups(nor); 2894 2894 + 2895 2895 + spi_nor_late_init_params(nor); 2896 2896 + 2897 2897 + return 0; 2898 2898 + } 2899 2899 + 2900 2900 + /** 2901 2901 + * spi_nor_quad_enable() - enable Quad I/O if needed. 2902 2902 + * @nor: pointer to a 'struct spi_nor' 2903 2903 + * 2904 2904 + * Return: 0 on success, -errno otherwise. 2905 2905 + */ 2906 2906 + static int spi_nor_quad_enable(struct spi_nor *nor) 2907 2907 + { 2908 2908 + if (!nor->params->quad_enable) 2909 2909 + return 0; 2910 2910 + 2911 2911 + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 2912 2912 + spi_nor_get_protocol_width(nor->write_proto) == 4)) 2913 2913 + return 0; 2914 2914 + 2915 2915 + return nor->params->quad_enable(nor); 2916 2916 + } 2917 2917 + 2918 2918 + /** 2919 2919 + * spi_nor_unlock_all() - Unlocks the entire flash memory array. 2920 2920 + * @nor: pointer to a 'struct spi_nor'. 2921 2921 + * 2922 2922 + * Some SPI NOR flashes are write protected by default after a power-on reset 2923 2923 + * cycle, in order to avoid inadvertent writes during power-up. Backward 2924 2924 + * compatibility imposes to unlock the entire flash memory array at power-up 2925 2925 + * by default. 2926 2926 + */ 2927 2927 + static int spi_nor_unlock_all(struct spi_nor *nor) 2928 2928 + { 2929 2929 + if (nor->flags & SNOR_F_HAS_LOCK) 2930 2930 + return spi_nor_unlock(&nor->mtd, 0, nor->params->size); 2931 2931 + 2932 2932 + return 0; 2933 2933 + } 2934 2934 + 2935 2935 + static int spi_nor_init(struct spi_nor *nor) 2936 2936 + { 2937 2937 + int err; 2938 2938 + 2939 2939 + err = spi_nor_quad_enable(nor); 2940 2940 + if (err) { 2941 2941 + dev_dbg(nor->dev, "quad mode not supported\n"); 2942 2942 + return err; 2943 2943 + } 2944 2944 + 2945 2945 + err = spi_nor_unlock_all(nor); 2946 2946 + if (err) { 2947 2947 + dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n"); 2948 2948 + return err; 2949 2949 + } 2950 2950 + 2951 2951 + if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) { 2952 2952 + /* 2953 2953 + * If the RESET# pin isn't hooked up properly, or the system 2954 2954 + * otherwise doesn't perform a reset command in the boot 2955 2955 + * sequence, it's impossible to 100% protect against unexpected 2956 2956 + * reboots (e.g., crashes). Warn the user (or hopefully, system 2957 2957 + * designer) that this is bad. 2958 2958 + */ 2959 2959 + WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 2960 2960 + "enabling reset hack; may not recover from unexpected reboots\n"); 2961 2961 + nor->params->set_4byte_addr_mode(nor, true); 2962 2962 + } 2963 2963 + 2964 2964 + return 0; 2965 2965 + } 2966 2966 + 2967 2967 + /* mtd resume handler */ 2968 2968 + static void spi_nor_resume(struct mtd_info *mtd) 2969 2969 + { 2970 2970 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 2971 2971 + struct device *dev = nor->dev; 2972 2972 + int ret; 2973 2973 + 2974 2974 + /* re-initialize the nor chip */ 2975 2975 + ret = spi_nor_init(nor); 2976 2976 + if (ret) 2977 2977 + dev_err(dev, "resume() failed\n"); 2978 2978 + } 2979 2979 + 2980 2980 + void spi_nor_restore(struct spi_nor *nor) 2981 2981 + { 2982 2982 + /* restore the addressing mode */ 2983 2983 + if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 2984 2984 + nor->flags & SNOR_F_BROKEN_RESET) 2985 2985 + nor->params->set_4byte_addr_mode(nor, false); 2986 2986 + } 2987 2987 + EXPORT_SYMBOL_GPL(spi_nor_restore); 2988 2988 + 2989 2989 + static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 2990 2990 + const char *name) 2991 2991 + { 2992 2992 + unsigned int i, j; 2993 2993 + 2994 2994 + for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2995 2995 + for (j = 0; j < manufacturers[i]->nparts; j++) { 2996 2996 + if (!strcmp(name, manufacturers[i]->parts[j].name)) { 2997 2997 + nor->manufacturer = manufacturers[i]; 2998 2998 + return &manufacturers[i]->parts[j]; 2999 2999 + } 3000 3000 + } 3001 3001 + } 3002 3002 + 3003 3003 + return NULL; 3004 3004 + } 3005 3005 + 3006 3006 + static int spi_nor_set_addr_width(struct spi_nor *nor) 3007 3007 + { 3008 3008 + if (nor->addr_width) { 3009 3009 + /* already configured from SFDP */ 3010 3010 + } else if (nor->info->addr_width) { 3011 3011 + nor->addr_width = nor->info->addr_width; 3012 3012 + } else if (nor->mtd.size > 0x1000000) { 3013 3013 + /* enable 4-byte addressing if the device exceeds 16MiB */ 3014 3014 + nor->addr_width = 4; 3015 3015 + } else { 3016 3016 + nor->addr_width = 3; 3017 3017 + } 3018 3018 + 3019 3019 + if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 3020 3020 + dev_dbg(nor->dev, "address width is too large: %u\n", 3021 3021 + nor->addr_width); 3022 3022 + return -EINVAL; 3023 3023 + } 3024 3024 + 3025 3025 + /* Set 4byte opcodes when possible. */ 3026 3026 + if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES && 3027 3027 + !(nor->flags & SNOR_F_HAS_4BAIT)) 3028 3028 + spi_nor_set_4byte_opcodes(nor); 3029 3029 + 3030 3030 + return 0; 3031 3031 + } 3032 3032 + 3033 3033 + static void spi_nor_debugfs_init(struct spi_nor *nor, 3034 3034 + const struct flash_info *info) 3035 3035 + { 3036 3036 + struct mtd_info *mtd = &nor->mtd; 3037 3037 + 3038 3038 + mtd->dbg.partname = info->name; 3039 3039 + mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN", 3040 3040 + info->id_len, info->id); 3041 3041 + } 3042 3042 + 3043 3043 + static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 3044 3044 + const char *name) 3045 3045 + { 3046 3046 + const struct flash_info *info = NULL; 3047 3047 + 3048 3048 + if (name) 3049 3049 + info = spi_nor_match_id(nor, name); 3050 3050 + /* Try to auto-detect if chip name wasn't specified or not found */ 3051 3051 + if (!info) 3052 3052 + info = spi_nor_read_id(nor); 3053 3053 + if (IS_ERR_OR_NULL(info)) 3054 3054 + return ERR_PTR(-ENOENT); 3055 3055 + 3056 3056 + /* 3057 3057 + * If caller has specified name of flash model that can normally be 3058 3058 + * detected using JEDEC, let's verify it. 3059 3059 + */ 3060 3060 + if (name && info->id_len) { 3061 3061 + const struct flash_info *jinfo; 3062 3062 + 3063 3063 + jinfo = spi_nor_read_id(nor); 3064 3064 + if (IS_ERR(jinfo)) { 3065 3065 + return jinfo; 3066 3066 + } else if (jinfo != info) { 3067 3067 + /* 3068 3068 + * JEDEC knows better, so overwrite platform ID. We 3069 3069 + * can't trust partitions any longer, but we'll let 3070 3070 + * mtd apply them anyway, since some partitions may be 3071 3071 + * marked read-only, and we don't want to lose that 3072 3072 + * information, even if it's not 100% accurate. 3073 3073 + */ 3074 3074 + dev_warn(nor->dev, "found %s, expected %s\n", 3075 3075 + jinfo->name, info->name); 3076 3076 + info = jinfo; 3077 3077 + } 3078 3078 + } 3079 3079 + 3080 3080 + return info; 3081 3081 + } 3082 3082 + 3083 3083 + int spi_nor_scan(struct spi_nor *nor, const char *name, 3084 3084 + const struct spi_nor_hwcaps *hwcaps) 3085 3085 + { 3086 3086 + const struct flash_info *info; 3087 3087 + struct device *dev = nor->dev; 3088 3088 + struct mtd_info *mtd = &nor->mtd; 3089 3089 + struct device_node *np = spi_nor_get_flash_node(nor); 3090 3090 + int ret; 3091 3091 + int i; 3092 3092 + 3093 3093 + ret = spi_nor_check(nor); 3094 3094 + if (ret) 3095 3095 + return ret; 3096 3096 + 3097 3097 + /* Reset SPI protocol for all commands. */ 3098 3098 + nor->reg_proto = SNOR_PROTO_1_1_1; 3099 3099 + nor->read_proto = SNOR_PROTO_1_1_1; 3100 3100 + nor->write_proto = SNOR_PROTO_1_1_1; 3101 3101 + 3102 3102 + /* 3103 3103 + * We need the bounce buffer early to read/write registers when going 3104 3104 + * through the spi-mem layer (buffers have to be DMA-able). 3105 3105 + * For spi-mem drivers, we'll reallocate a new buffer if 3106 3106 + * nor->page_size turns out to be greater than PAGE_SIZE (which 3107 3107 + * shouldn't happen before long since NOR pages are usually less 3108 3108 + * than 1KB) after spi_nor_scan() returns. 3109 3109 + */ 3110 3110 + nor->bouncebuf_size = PAGE_SIZE; 3111 3111 + nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3112 3112 + GFP_KERNEL); 3113 3113 + if (!nor->bouncebuf) 3114 3114 + return -ENOMEM; 3115 3115 + 3116 3116 + info = spi_nor_get_flash_info(nor, name); 3117 3117 + if (IS_ERR(info)) 3118 3118 + return PTR_ERR(info); 3119 3119 + 3120 3120 + nor->info = info; 3121 3121 + 3122 3122 + spi_nor_debugfs_init(nor, info); 3123 3123 + 3124 3124 + mutex_init(&nor->lock); 3125 3125 + 3126 3126 + /* 3127 3127 + * Make sure the XSR_RDY flag is set before calling 3128 3128 + * spi_nor_wait_till_ready(). Xilinx S3AN share MFR 3129 3129 + * with Atmel spi-nor 3130 3130 + */ 3131 3131 + if (info->flags & SPI_NOR_XSR_RDY) 3132 3132 + nor->flags |= SNOR_F_READY_XSR_RDY; 3133 3133 + 3134 3134 + if (info->flags & SPI_NOR_HAS_LOCK) 3135 3135 + nor->flags |= SNOR_F_HAS_LOCK; 3136 3136 + 3137 3137 + mtd->_write = spi_nor_write; 3138 3138 + 3139 3139 + /* Init flash parameters based on flash_info struct and SFDP */ 3140 3140 + ret = spi_nor_init_params(nor); 3141 3141 + if (ret) 3142 3142 + return ret; 3143 3143 + 3144 3144 + if (!mtd->name) 3145 3145 + mtd->name = dev_name(dev); 3146 3146 + mtd->priv = nor; 3147 3147 + mtd->type = MTD_NORFLASH; 3148 3148 + mtd->writesize = 1; 3149 3149 + mtd->flags = MTD_CAP_NORFLASH; 3150 3150 + mtd->size = nor->params->size; 3151 3151 + mtd->_erase = spi_nor_erase; 3152 3152 + mtd->_read = spi_nor_read; 3153 3153 + mtd->_resume = spi_nor_resume; 3154 3154 + 3155 3155 + if (nor->params->locking_ops) { 3156 3156 + mtd->_lock = spi_nor_lock; 3157 3157 + mtd->_unlock = spi_nor_unlock; 3158 3158 + mtd->_is_locked = spi_nor_is_locked; 3159 3159 + } 3160 3160 + 3161 3161 + if (info->flags & USE_FSR) 3162 3162 + nor->flags |= SNOR_F_USE_FSR; 3163 3163 + if (info->flags & SPI_NOR_HAS_TB) { 3164 3164 + nor->flags |= SNOR_F_HAS_SR_TB; 3165 3165 + if (info->flags & SPI_NOR_TB_SR_BIT6) 3166 3166 + nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 3167 3167 + } 3168 3168 + 3169 3169 + if (info->flags & NO_CHIP_ERASE) 3170 3170 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 3171 3171 + if (info->flags & USE_CLSR) 3172 3172 + nor->flags |= SNOR_F_USE_CLSR; 3173 3173 + 3174 3174 + if (info->flags & SPI_NOR_4BIT_BP) { 3175 3175 + nor->flags |= SNOR_F_HAS_4BIT_BP; 3176 3176 + if (info->flags & SPI_NOR_BP3_SR_BIT6) 3177 3177 + nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 3178 3178 + } 3179 3179 + 3180 3180 + if (info->flags & SPI_NOR_NO_ERASE) 3181 3181 + mtd->flags |= MTD_NO_ERASE; 3182 3182 + 3183 3183 + mtd->dev.parent = dev; 3184 3184 + nor->page_size = nor->params->page_size; 3185 3185 + mtd->writebufsize = nor->page_size; 3186 3186 + 3187 3187 + if (of_property_read_bool(np, "broken-flash-reset")) 3188 3188 + nor->flags |= SNOR_F_BROKEN_RESET; 3189 3189 + 3190 3190 + /* 3191 3191 + * Configure the SPI memory: 3192 3192 + * - select op codes for (Fast) Read, Page Program and Sector Erase. 3193 3193 + * - set the number of dummy cycles (mode cycles + wait states). 3194 3194 + * - set the SPI protocols for register and memory accesses. 3195 3195 + */ 3196 3196 + ret = spi_nor_setup(nor, hwcaps); 3197 3197 + if (ret) 3198 3198 + return ret; 3199 3199 + 3200 3200 + if (info->flags & SPI_NOR_4B_OPCODES) 3201 3201 + nor->flags |= SNOR_F_4B_OPCODES; 3202 3202 + 3203 3203 + ret = spi_nor_set_addr_width(nor); 3204 3204 + if (ret) 3205 3205 + return ret; 3206 3206 + 3207 3207 + /* Send all the required SPI flash commands to initialize device */ 3208 3208 + ret = spi_nor_init(nor); 3209 3209 + if (ret) 3210 3210 + return ret; 3211 3211 + 3212 3212 + dev_info(dev, "%s (%lld Kbytes)\n", info->name, 3213 3213 + (long long)mtd->size >> 10); 3214 3214 + 3215 3215 + dev_dbg(dev, 3216 3216 + "mtd .name = %s, .size = 0x%llx (%lldMiB), " 3217 3217 + ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 3218 3218 + mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 3219 3219 + mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 3220 3220 + 3221 3221 + if (mtd->numeraseregions) 3222 3222 + for (i = 0; i < mtd->numeraseregions; i++) 3223 3223 + dev_dbg(dev, 3224 3224 + "mtd.eraseregions[%d] = { .offset = 0x%llx, " 3225 3225 + ".erasesize = 0x%.8x (%uKiB), " 3226 3226 + ".numblocks = %d }\n", 3227 3227 + i, (long long)mtd->eraseregions[i].offset, 3228 3228 + mtd->eraseregions[i].erasesize, 3229 3229 + mtd->eraseregions[i].erasesize / 1024, 3230 3230 + mtd->eraseregions[i].numblocks); 3231 3231 + return 0; 3232 3232 + } 3233 3233 + EXPORT_SYMBOL_GPL(spi_nor_scan); 3234 3234 + 3235 3235 + static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3236 3236 + { 3237 3237 + struct spi_mem_dirmap_info info = { 3238 3238 + .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 3239 3239 + SPI_MEM_OP_ADDR(nor->addr_width, 0, 1), 3240 3240 + SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 3241 3241 + SPI_MEM_OP_DATA_IN(0, NULL, 1)), 3242 3242 + .offset = 0, 3243 3243 + .length = nor->mtd.size, 3244 3244 + }; 3245 3245 + struct spi_mem_op *op = &info.op_tmpl; 3246 3246 + 3247 3247 + /* get transfer protocols. */ 3248 3248 + op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 3249 3249 + op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 3250 3250 + op->dummy.buswidth = op->addr.buswidth; 3251 3251 + op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3252 3252 + 3253 3253 + /* convert the dummy cycles to the number of bytes */ 3254 3254 + op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3255 3255 + 3256 3256 + nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3257 3257 + &info); 3258 3258 + return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3259 3259 + } 3260 3260 + 3261 3261 + static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3262 3262 + { 3263 3263 + struct spi_mem_dirmap_info info = { 3264 3264 + .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 3265 3265 + SPI_MEM_OP_ADDR(nor->addr_width, 0, 1), 3266 3266 + SPI_MEM_OP_NO_DUMMY, 3267 3267 + SPI_MEM_OP_DATA_OUT(0, NULL, 1)), 3268 3268 + .offset = 0, 3269 3269 + .length = nor->mtd.size, 3270 3270 + }; 3271 3271 + struct spi_mem_op *op = &info.op_tmpl; 3272 3272 + 3273 3273 + /* get transfer protocols. */ 3274 3274 + op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 3275 3275 + op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 3276 3276 + op->dummy.buswidth = op->addr.buswidth; 3277 3277 + op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3278 3278 + 3279 3279 + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3280 3280 + op->addr.nbytes = 0; 3281 3281 + 3282 3282 + nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3283 3283 + &info); 3284 3284 + return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3285 3285 + } 3286 3286 + 3287 3287 + static int spi_nor_probe(struct spi_mem *spimem) 3288 3288 + { 3289 3289 + struct spi_device *spi = spimem->spi; 3290 3290 + struct flash_platform_data *data = dev_get_platdata(&spi->dev); 3291 3291 + struct spi_nor *nor; 3292 3292 + /* 3293 3293 + * Enable all caps by default. The core will mask them after 3294 3294 + * checking what's really supported using spi_mem_supports_op(). 3295 3295 + */ 3296 3296 + const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3297 3297 + char *flash_name; 3298 3298 + int ret; 3299 3299 + 3300 3300 + nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 3301 3301 + if (!nor) 3302 3302 + return -ENOMEM; 3303 3303 + 3304 3304 + nor->spimem = spimem; 3305 3305 + nor->dev = &spi->dev; 3306 3306 + spi_nor_set_flash_node(nor, spi->dev.of_node); 3307 3307 + 3308 3308 + spi_mem_set_drvdata(spimem, nor); 3309 3309 + 3310 3310 + if (data && data->name) 3311 3311 + nor->mtd.name = data->name; 3312 3312 + 3313 3313 + if (!nor->mtd.name) 3314 3314 + nor->mtd.name = spi_mem_get_name(spimem); 3315 3315 + 3316 3316 + /* 3317 3317 + * For some (historical?) reason many platforms provide two different 3318 3318 + * names in flash_platform_data: "name" and "type". Quite often name is 3319 3319 + * set to "m25p80" and then "type" provides a real chip name. 3320 3320 + * If that's the case, respect "type" and ignore a "name". 3321 3321 + */ 3322 3322 + if (data && data->type) 3323 3323 + flash_name = data->type; 3324 3324 + else if (!strcmp(spi->modalias, "spi-nor")) 3325 3325 + flash_name = NULL; /* auto-detect */ 3326 3326 + else 3327 3327 + flash_name = spi->modalias; 3328 3328 + 3329 3329 + ret = spi_nor_scan(nor, flash_name, &hwcaps); 3330 3330 + if (ret) 3331 3331 + return ret; 3332 3332 + 3333 3333 + /* 3334 3334 + * None of the existing parts have > 512B pages, but let's play safe 3335 3335 + * and add this logic so that if anyone ever adds support for such 3336 3336 + * a NOR we don't end up with buffer overflows. 3337 3337 + */ 3338 3338 + if (nor->page_size > PAGE_SIZE) { 3339 3339 + nor->bouncebuf_size = nor->page_size; 3340 3340 + devm_kfree(nor->dev, nor->bouncebuf); 3341 3341 + nor->bouncebuf = devm_kmalloc(nor->dev, 3342 3342 + nor->bouncebuf_size, 3343 3343 + GFP_KERNEL); 3344 3344 + if (!nor->bouncebuf) 3345 3345 + return -ENOMEM; 3346 3346 + } 3347 3347 + 3348 3348 + ret = spi_nor_create_read_dirmap(nor); 3349 3349 + if (ret) 3350 3350 + return ret; 3351 3351 + 3352 3352 + ret = spi_nor_create_write_dirmap(nor); 3353 3353 + if (ret) 3354 3354 + return ret; 3355 3355 + 3356 3356 + return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3357 3357 + data ? data->nr_parts : 0); 3358 3358 + } 3359 3359 + 3360 3360 + static int spi_nor_remove(struct spi_mem *spimem) 3361 3361 + { 3362 3362 + struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3363 3363 + 3364 3364 + spi_nor_restore(nor); 3365 3365 + 3366 3366 + /* Clean up MTD stuff. */ 3367 3367 + return mtd_device_unregister(&nor->mtd); 3368 3368 + } 3369 3369 + 3370 3370 + static void spi_nor_shutdown(struct spi_mem *spimem) 3371 3371 + { 3372 3372 + struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3373 3373 + 3374 3374 + spi_nor_restore(nor); 3375 3375 + } 3376 3376 + 3377 3377 + /* 3378 3378 + * Do NOT add to this array without reading the following: 3379 3379 + * 3380 3380 + * Historically, many flash devices are bound to this driver by their name. But 3381 3381 + * since most of these flash are compatible to some extent, and their 3382 3382 + * differences can often be differentiated by the JEDEC read-ID command, we 3383 3383 + * encourage new users to add support to the spi-nor library, and simply bind 3384 3384 + * against a generic string here (e.g., "jedec,spi-nor"). 3385 3385 + * 3386 3386 + * Many flash names are kept here in this list (as well as in spi-nor.c) to 3387 3387 + * keep them available as module aliases for existing platforms. 3388 3388 + */ 3389 3389 + static const struct spi_device_id spi_nor_dev_ids[] = { 3390 3390 + /* 3391 3391 + * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3392 3392 + * hack around the fact that the SPI core does not provide uevent 3393 3393 + * matching for .of_match_table 3394 3394 + */ 3395 3395 + {"spi-nor"}, 3396 3396 + 3397 3397 + /* 3398 3398 + * Entries not used in DTs that should be safe to drop after replacing 3399 3399 + * them with "spi-nor" in platform data. 3400 3400 + */ 3401 3401 + {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3402 3402 + 3403 3403 + /* 3404 3404 + * Entries that were used in DTs without "jedec,spi-nor" fallback and 3405 3405 + * should be kept for backward compatibility. 3406 3406 + */ 3407 3407 + {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3408 3408 + {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3409 3409 + {"mx25l25635e"},{"mx66l51235l"}, 3410 3410 + {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3411 3411 + {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3412 3412 + {"s25fl064k"}, 3413 3413 + {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3414 3414 + {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3415 3415 + {"m25p64"}, {"m25p128"}, 3416 3416 + {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3417 3417 + {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3418 3418 + 3419 3419 + /* Flashes that can't be detected using JEDEC */ 3420 3420 + {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3421 3421 + {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3422 3422 + {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3423 3423 + 3424 3424 + /* Everspin MRAMs (non-JEDEC) */ 3425 3425 + { "mr25h128" }, /* 128 Kib, 40 MHz */ 3426 3426 + { "mr25h256" }, /* 256 Kib, 40 MHz */ 3427 3427 + { "mr25h10" }, /* 1 Mib, 40 MHz */ 3428 3428 + { "mr25h40" }, /* 4 Mib, 40 MHz */ 3429 3429 + 3430 3430 + { }, 3431 3431 + }; 3432 3432 + MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3433 3433 + 3434 3434 + static const struct of_device_id spi_nor_of_table[] = { 3435 3435 + /* 3436 3436 + * Generic compatibility for SPI NOR that can be identified by the 3437 3437 + * JEDEC READ ID opcode (0x9F). Use this, if possible. 3438 3438 + */ 3439 3439 + { .compatible = "jedec,spi-nor" }, 3440 3440 + { /* sentinel */ }, 3441 3441 + }; 3442 3442 + MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3443 3443 + 3444 3444 + /* 3445 3445 + * REVISIT: many of these chips have deep power-down modes, which 3446 3446 + * should clearly be entered on suspend() to minimize power use. 3447 3447 + * And also when they're otherwise idle... 3448 3448 + */ 3449 3449 + static struct spi_mem_driver spi_nor_driver = { 3450 3450 + .spidrv = { 3451 3451 + .driver = { 3452 3452 + .name = "spi-nor", 3453 3453 + .of_match_table = spi_nor_of_table, 3454 3454 + }, 3455 3455 + .id_table = spi_nor_dev_ids, 3456 3456 + }, 3457 3457 + .probe = spi_nor_probe, 3458 3458 + .remove = spi_nor_remove, 3459 3459 + .shutdown = spi_nor_shutdown, 3460 3460 + }; 3461 3461 + module_spi_mem_driver(spi_nor_driver); 3462 3462 + 3463 3463 + MODULE_LICENSE("GPL v2"); 3464 3464 + MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3465 3465 + MODULE_AUTHOR("Mike Lavender"); 3466 3466 + MODULE_DESCRIPTION("framework for SPI NOR");

+441

drivers/mtd/spi-nor/core.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H 8 8 + #define __LINUX_MTD_SPI_NOR_INTERNAL_H 9 9 + 10 10 + #include "sfdp.h" 11 11 + 12 12 + #define SPI_NOR_MAX_ID_LEN 6 13 13 + 14 14 + enum spi_nor_option_flags { 15 15 + SNOR_F_USE_FSR = BIT(0), 16 16 + SNOR_F_HAS_SR_TB = BIT(1), 17 17 + SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 18 18 + SNOR_F_READY_XSR_RDY = BIT(3), 19 19 + SNOR_F_USE_CLSR = BIT(4), 20 20 + SNOR_F_BROKEN_RESET = BIT(5), 21 21 + SNOR_F_4B_OPCODES = BIT(6), 22 22 + SNOR_F_HAS_4BAIT = BIT(7), 23 23 + SNOR_F_HAS_LOCK = BIT(8), 24 24 + SNOR_F_HAS_16BIT_SR = BIT(9), 25 25 + SNOR_F_NO_READ_CR = BIT(10), 26 26 + SNOR_F_HAS_SR_TB_BIT6 = BIT(11), 27 27 + SNOR_F_HAS_4BIT_BP = BIT(12), 28 28 + SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), 29 29 + }; 30 30 + 31 31 + struct spi_nor_read_command { 32 32 + u8 num_mode_clocks; 33 33 + u8 num_wait_states; 34 34 + u8 opcode; 35 35 + enum spi_nor_protocol proto; 36 36 + }; 37 37 + 38 38 + struct spi_nor_pp_command { 39 39 + u8 opcode; 40 40 + enum spi_nor_protocol proto; 41 41 + }; 42 42 + 43 43 + enum spi_nor_read_command_index { 44 44 + SNOR_CMD_READ, 45 45 + SNOR_CMD_READ_FAST, 46 46 + SNOR_CMD_READ_1_1_1_DTR, 47 47 + 48 48 + /* Dual SPI */ 49 49 + SNOR_CMD_READ_1_1_2, 50 50 + SNOR_CMD_READ_1_2_2, 51 51 + SNOR_CMD_READ_2_2_2, 52 52 + SNOR_CMD_READ_1_2_2_DTR, 53 53 + 54 54 + /* Quad SPI */ 55 55 + SNOR_CMD_READ_1_1_4, 56 56 + SNOR_CMD_READ_1_4_4, 57 57 + SNOR_CMD_READ_4_4_4, 58 58 + SNOR_CMD_READ_1_4_4_DTR, 59 59 + 60 60 + /* Octal SPI */ 61 61 + SNOR_CMD_READ_1_1_8, 62 62 + SNOR_CMD_READ_1_8_8, 63 63 + SNOR_CMD_READ_8_8_8, 64 64 + SNOR_CMD_READ_1_8_8_DTR, 65 65 + 66 66 + SNOR_CMD_READ_MAX 67 67 + }; 68 68 + 69 69 + enum spi_nor_pp_command_index { 70 70 + SNOR_CMD_PP, 71 71 + 72 72 + /* Quad SPI */ 73 73 + SNOR_CMD_PP_1_1_4, 74 74 + SNOR_CMD_PP_1_4_4, 75 75 + SNOR_CMD_PP_4_4_4, 76 76 + 77 77 + /* Octal SPI */ 78 78 + SNOR_CMD_PP_1_1_8, 79 79 + SNOR_CMD_PP_1_8_8, 80 80 + SNOR_CMD_PP_8_8_8, 81 81 + 82 82 + SNOR_CMD_PP_MAX 83 83 + }; 84 84 + 85 85 + /** 86 86 + * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type 87 87 + * @size: the size of the sector/block erased by the erase type. 88 88 + * JEDEC JESD216B imposes erase sizes to be a power of 2. 89 89 + * @size_shift: @size is a power of 2, the shift is stored in 90 90 + * @size_shift. 91 91 + * @size_mask: the size mask based on @size_shift. 92 92 + * @opcode: the SPI command op code to erase the sector/block. 93 93 + * @idx: Erase Type index as sorted in the Basic Flash Parameter 94 94 + * Table. It will be used to synchronize the supported 95 95 + * Erase Types with the ones identified in the SFDP 96 96 + * optional tables. 97 97 + */ 98 98 + struct spi_nor_erase_type { 99 99 + u32 size; 100 100 + u32 size_shift; 101 101 + u32 size_mask; 102 102 + u8 opcode; 103 103 + u8 idx; 104 104 + }; 105 105 + 106 106 + /** 107 107 + * struct spi_nor_erase_command - Used for non-uniform erases 108 108 + * The structure is used to describe a list of erase commands to be executed 109 109 + * once we validate that the erase can be performed. The elements in the list 110 110 + * are run-length encoded. 111 111 + * @list: for inclusion into the list of erase commands. 112 112 + * @count: how many times the same erase command should be 113 113 + * consecutively used. 114 114 + * @size: the size of the sector/block erased by the command. 115 115 + * @opcode: the SPI command op code to erase the sector/block. 116 116 + */ 117 117 + struct spi_nor_erase_command { 118 118 + struct list_head list; 119 119 + u32 count; 120 120 + u32 size; 121 121 + u8 opcode; 122 122 + }; 123 123 + 124 124 + /** 125 125 + * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region 126 126 + * @offset: the offset in the data array of erase region start. 127 127 + * LSB bits are used as a bitmask encoding flags to 128 128 + * determine if this region is overlaid, if this region is 129 129 + * the last in the SPI NOR flash memory and to indicate 130 130 + * all the supported erase commands inside this region. 131 131 + * The erase types are sorted in ascending order with the 132 132 + * smallest Erase Type size being at BIT(0). 133 133 + * @size: the size of the region in bytes. 134 134 + */ 135 135 + struct spi_nor_erase_region { 136 136 + u64 offset; 137 137 + u64 size; 138 138 + }; 139 139 + 140 140 + #define SNOR_ERASE_TYPE_MAX 4 141 141 + #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) 142 142 + 143 143 + #define SNOR_LAST_REGION BIT(4) 144 144 + #define SNOR_OVERLAID_REGION BIT(5) 145 145 + 146 146 + #define SNOR_ERASE_FLAGS_MAX 6 147 147 + #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) 148 148 + 149 149 + /** 150 150 + * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map 151 151 + * @regions: array of erase regions. The regions are consecutive in 152 152 + * address space. Walking through the regions is done 153 153 + * incrementally. 154 154 + * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform 155 155 + * sector size (legacy implementation). 156 156 + * @erase_type: an array of erase types shared by all the regions. 157 157 + * The erase types are sorted in ascending order, with the 158 158 + * smallest Erase Type size being the first member in the 159 159 + * erase_type array. 160 160 + * @uniform_erase_type: bitmask encoding erase types that can erase the 161 161 + * entire memory. This member is completed at init by 162 162 + * uniform and non-uniform SPI NOR flash memories if they 163 163 + * support at least one erase type that can erase the 164 164 + * entire memory. 165 165 + */ 166 166 + struct spi_nor_erase_map { 167 167 + struct spi_nor_erase_region *regions; 168 168 + struct spi_nor_erase_region uniform_region; 169 169 + struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; 170 170 + u8 uniform_erase_type; 171 171 + }; 172 172 + 173 173 + /** 174 174 + * struct spi_nor_locking_ops - SPI NOR locking methods 175 175 + * @lock: lock a region of the SPI NOR. 176 176 + * @unlock: unlock a region of the SPI NOR. 177 177 + * @is_locked: check if a region of the SPI NOR is completely locked 178 178 + */ 179 179 + struct spi_nor_locking_ops { 180 180 + int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 181 181 + int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 182 182 + int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 183 183 + }; 184 184 + 185 185 + /** 186 186 + * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. 187 187 + * Includes legacy flash parameters and settings that can be overwritten 188 188 + * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 189 189 + * Serial Flash Discoverable Parameters (SFDP) tables. 190 190 + * 191 191 + * @size: the flash memory density in bytes. 192 192 + * @page_size: the page size of the SPI NOR flash memory. 193 193 + * @hwcaps: describes the read and page program hardware 194 194 + * capabilities. 195 195 + * @reads: read capabilities ordered by priority: the higher index 196 196 + * in the array, the higher priority. 197 197 + * @page_programs: page program capabilities ordered by priority: the 198 198 + * higher index in the array, the higher priority. 199 199 + * @erase_map: the erase map parsed from the SFDP Sector Map Parameter 200 200 + * Table. 201 201 + * @quad_enable: enables SPI NOR quad mode. 202 202 + * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. 203 203 + * @convert_addr: converts an absolute address into something the flash 204 204 + * will understand. Particularly useful when pagesize is 205 205 + * not a power-of-2. 206 206 + * @setup: configures the SPI NOR memory. Useful for SPI NOR 207 207 + * flashes that have peculiarities to the SPI NOR standard 208 208 + * e.g. different opcodes, specific address calculation, 209 209 + * page size, etc. 210 210 + * @locking_ops: SPI NOR locking methods. 211 211 + */ 212 212 + struct spi_nor_flash_parameter { 213 213 + u64 size; 214 214 + u32 page_size; 215 215 + 216 216 + struct spi_nor_hwcaps hwcaps; 217 217 + struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 218 218 + struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 219 219 + 220 220 + struct spi_nor_erase_map erase_map; 221 221 + 222 222 + int (*quad_enable)(struct spi_nor *nor); 223 223 + int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); 224 224 + u32 (*convert_addr)(struct spi_nor *nor, u32 addr); 225 225 + int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); 226 226 + 227 227 + const struct spi_nor_locking_ops *locking_ops; 228 228 + }; 229 229 + 230 230 + /** 231 231 + * struct spi_nor_fixups - SPI NOR fixup hooks 232 232 + * @default_init: called after default flash parameters init. Used to tweak 233 233 + * flash parameters when information provided by the flash_info 234 234 + * table is incomplete or wrong. 235 235 + * @post_bfpt: called after the BFPT table has been parsed 236 236 + * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs 237 237 + * that do not support RDSFDP). Typically used to tweak various 238 238 + * parameters that could not be extracted by other means (i.e. 239 239 + * when information provided by the SFDP/flash_info tables are 240 240 + * incomplete or wrong). 241 241 + * 242 242 + * Those hooks can be used to tweak the SPI NOR configuration when the SFDP 243 243 + * table is broken or not available. 244 244 + */ 245 245 + struct spi_nor_fixups { 246 246 + void (*default_init)(struct spi_nor *nor); 247 247 + int (*post_bfpt)(struct spi_nor *nor, 248 248 + const struct sfdp_parameter_header *bfpt_header, 249 249 + const struct sfdp_bfpt *bfpt, 250 250 + struct spi_nor_flash_parameter *params); 251 251 + void (*post_sfdp)(struct spi_nor *nor); 252 252 + }; 253 253 + 254 254 + struct flash_info { 255 255 + char *name; 256 256 + 257 257 + /* 258 258 + * This array stores the ID bytes. 259 259 + * The first three bytes are the JEDIC ID. 260 260 + * JEDEC ID zero means "no ID" (mostly older chips). 261 261 + */ 262 262 + u8 id[SPI_NOR_MAX_ID_LEN]; 263 263 + u8 id_len; 264 264 + 265 265 + /* The size listed here is what works with SPINOR_OP_SE, which isn't 266 266 + * necessarily called a "sector" by the vendor. 267 267 + */ 268 268 + unsigned sector_size; 269 269 + u16 n_sectors; 270 270 + 271 271 + u16 page_size; 272 272 + u16 addr_width; 273 273 + 274 274 + u32 flags; 275 275 + #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 276 276 + #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 277 277 + #define SST_WRITE BIT(2) /* use SST byte programming */ 278 278 + #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 279 279 + #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 280 280 + #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 281 281 + #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 282 282 + #define USE_FSR BIT(7) /* use flag status register */ 283 283 + #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 284 284 + #define SPI_NOR_HAS_TB BIT(9) /* 285 285 + * Flash SR has Top/Bottom (TB) protect 286 286 + * bit. Must be used with 287 287 + * SPI_NOR_HAS_LOCK. 288 288 + */ 289 289 + #define SPI_NOR_XSR_RDY BIT(10) /* 290 290 + * S3AN flashes have specific opcode to 291 291 + * read the status register. 292 292 + */ 293 293 + #define SPI_NOR_4B_OPCODES BIT(11) /* 294 294 + * Use dedicated 4byte address op codes 295 295 + * to support memory size above 128Mib. 296 296 + */ 297 297 + #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 298 298 + #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 299 299 + #define USE_CLSR BIT(14) /* use CLSR command */ 300 300 + #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ 301 301 + #define SPI_NOR_TB_SR_BIT6 BIT(16) /* 302 302 + * Top/Bottom (TB) is bit 6 of 303 303 + * status register. Must be used with 304 304 + * SPI_NOR_HAS_TB. 305 305 + */ 306 306 + #define SPI_NOR_4BIT_BP BIT(17) /* 307 307 + * Flash SR has 4 bit fields (BP0-3) 308 308 + * for block protection. 309 309 + */ 310 310 + #define SPI_NOR_BP3_SR_BIT6 BIT(18) /* 311 311 + * BP3 is bit 6 of status register. 312 312 + * Must be used with SPI_NOR_4BIT_BP. 313 313 + */ 314 314 + 315 315 + /* Part specific fixup hooks. */ 316 316 + const struct spi_nor_fixups *fixups; 317 317 + }; 318 318 + 319 319 + /* Used when the "_ext_id" is two bytes at most */ 320 320 + #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 321 321 + .id = { \ 322 322 + ((_jedec_id) >> 16) & 0xff, \ 323 323 + ((_jedec_id) >> 8) & 0xff, \ 324 324 + (_jedec_id) & 0xff, \ 325 325 + ((_ext_id) >> 8) & 0xff, \ 326 326 + (_ext_id) & 0xff, \ 327 327 + }, \ 328 328 + .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 329 329 + .sector_size = (_sector_size), \ 330 330 + .n_sectors = (_n_sectors), \ 331 331 + .page_size = 256, \ 332 332 + .flags = (_flags), 333 333 + 334 334 + #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 335 335 + .id = { \ 336 336 + ((_jedec_id) >> 16) & 0xff, \ 337 337 + ((_jedec_id) >> 8) & 0xff, \ 338 338 + (_jedec_id) & 0xff, \ 339 339 + ((_ext_id) >> 16) & 0xff, \ 340 340 + ((_ext_id) >> 8) & 0xff, \ 341 341 + (_ext_id) & 0xff, \ 342 342 + }, \ 343 343 + .id_len = 6, \ 344 344 + .sector_size = (_sector_size), \ 345 345 + .n_sectors = (_n_sectors), \ 346 346 + .page_size = 256, \ 347 347 + .flags = (_flags), 348 348 + 349 349 + #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ 350 350 + .sector_size = (_sector_size), \ 351 351 + .n_sectors = (_n_sectors), \ 352 352 + .page_size = (_page_size), \ 353 353 + .addr_width = (_addr_width), \ 354 354 + .flags = (_flags), 355 355 + 356 356 + #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 357 357 + .id = { \ 358 358 + ((_jedec_id) >> 16) & 0xff, \ 359 359 + ((_jedec_id) >> 8) & 0xff, \ 360 360 + (_jedec_id) & 0xff \ 361 361 + }, \ 362 362 + .id_len = 3, \ 363 363 + .sector_size = (8*_page_size), \ 364 364 + .n_sectors = (_n_sectors), \ 365 365 + .page_size = _page_size, \ 366 366 + .addr_width = 3, \ 367 367 + .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY, 368 368 + 369 369 + /** 370 370 + * struct spi_nor_manufacturer - SPI NOR manufacturer object 371 371 + * @name: manufacturer name 372 372 + * @parts: array of parts supported by this manufacturer 373 373 + * @nparts: number of entries in the parts array 374 374 + * @fixups: hooks called at various points in time during spi_nor_scan() 375 375 + */ 376 376 + struct spi_nor_manufacturer { 377 377 + const char *name; 378 378 + const struct flash_info *parts; 379 379 + unsigned int nparts; 380 380 + const struct spi_nor_fixups *fixups; 381 381 + }; 382 382 + 383 383 + /* Manufacturer drivers. */ 384 384 + extern const struct spi_nor_manufacturer spi_nor_atmel; 385 385 + extern const struct spi_nor_manufacturer spi_nor_catalyst; 386 386 + extern const struct spi_nor_manufacturer spi_nor_eon; 387 387 + extern const struct spi_nor_manufacturer spi_nor_esmt; 388 388 + extern const struct spi_nor_manufacturer spi_nor_everspin; 389 389 + extern const struct spi_nor_manufacturer spi_nor_fujitsu; 390 390 + extern const struct spi_nor_manufacturer spi_nor_gigadevice; 391 391 + extern const struct spi_nor_manufacturer spi_nor_intel; 392 392 + extern const struct spi_nor_manufacturer spi_nor_issi; 393 393 + extern const struct spi_nor_manufacturer spi_nor_macronix; 394 394 + extern const struct spi_nor_manufacturer spi_nor_micron; 395 395 + extern const struct spi_nor_manufacturer spi_nor_st; 396 396 + extern const struct spi_nor_manufacturer spi_nor_spansion; 397 397 + extern const struct spi_nor_manufacturer spi_nor_sst; 398 398 + extern const struct spi_nor_manufacturer spi_nor_winbond; 399 399 + extern const struct spi_nor_manufacturer spi_nor_xilinx; 400 400 + extern const struct spi_nor_manufacturer spi_nor_xmc; 401 401 + 402 402 + int spi_nor_write_enable(struct spi_nor *nor); 403 403 + int spi_nor_write_disable(struct spi_nor *nor); 404 404 + int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); 405 405 + int spi_nor_write_ear(struct spi_nor *nor, u8 ear); 406 406 + int spi_nor_wait_till_ready(struct spi_nor *nor); 407 407 + int spi_nor_lock_and_prep(struct spi_nor *nor); 408 408 + void spi_nor_unlock_and_unprep(struct spi_nor *nor); 409 409 + int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); 410 410 + int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); 411 411 + int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); 412 412 + 413 413 + int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); 414 414 + ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 415 415 + u8 *buf); 416 416 + ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 417 417 + const u8 *buf); 418 418 + 419 419 + int spi_nor_hwcaps_read2cmd(u32 hwcaps); 420 420 + u8 spi_nor_convert_3to4_read(u8 opcode); 421 421 + void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 422 422 + enum spi_nor_protocol proto); 423 423 + 424 424 + void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 425 425 + u8 opcode); 426 426 + struct spi_nor_erase_region * 427 427 + spi_nor_region_next(struct spi_nor_erase_region *region); 428 428 + void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 429 429 + u8 erase_mask, u64 flash_size); 430 430 + 431 431 + int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 432 432 + const struct sfdp_parameter_header *bfpt_header, 433 433 + const struct sfdp_bfpt *bfpt, 434 434 + struct spi_nor_flash_parameter *params); 435 435 + 436 436 + static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd) 437 437 + { 438 438 + return mtd->priv; 439 439 + } 440 440 + 441 441 + #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */

+34

drivers/mtd/spi-nor/eon.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info eon_parts[] = { 12 12 + /* EON -- en25xxx */ 13 13 + { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, 14 14 + { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, 15 15 + { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 16 16 + { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, 17 17 + { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 18 18 + { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, 19 19 + SECT_4K | SPI_NOR_DUAL_READ) }, 20 20 + { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32, 21 21 + SECT_4K | SPI_NOR_DUAL_READ) }, 22 22 + { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) }, 23 23 + { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128, 24 24 + SECT_4K | SPI_NOR_DUAL_READ) }, 25 25 + { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, 26 26 + { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, 27 27 + { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 28 28 + }; 29 29 + 30 30 + const struct spi_nor_manufacturer spi_nor_eon = { 31 31 + .name = "eon", 32 32 + .parts = eon_parts, 33 33 + .nparts = ARRAY_SIZE(eon_parts), 34 34 + };

+25

drivers/mtd/spi-nor/esmt.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info esmt_parts[] = { 12 12 + /* ESMT */ 13 13 + { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, 14 14 + SECT_4K | SPI_NOR_HAS_LOCK) }, 15 15 + { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, 16 16 + SECT_4K | SPI_NOR_HAS_LOCK) }, 17 17 + { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, 18 18 + SECT_4K | SPI_NOR_HAS_LOCK) }, 19 19 + }; 20 20 + 21 21 + const struct spi_nor_manufacturer spi_nor_esmt = { 22 22 + .name = "esmt", 23 23 + .parts = esmt_parts, 24 24 + .nparts = ARRAY_SIZE(esmt_parts), 25 25 + };

+27

drivers/mtd/spi-nor/everspin.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info everspin_parts[] = { 12 12 + /* Everspin */ 13 13 + { "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2, 14 14 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 15 15 + { "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2, 16 16 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 17 17 + { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, 18 18 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 19 19 + { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, 20 20 + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 21 21 + }; 22 22 + 23 23 + const struct spi_nor_manufacturer spi_nor_everspin = { 24 24 + .name = "everspin", 25 25 + .parts = everspin_parts, 26 26 + .nparts = ARRAY_SIZE(everspin_parts), 27 27 + };

+20

drivers/mtd/spi-nor/fujitsu.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info fujitsu_parts[] = { 12 12 + /* Fujitsu */ 13 13 + { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, 14 14 + }; 15 15 + 16 16 + const struct spi_nor_manufacturer spi_nor_fujitsu = { 17 17 + .name = "fujitsu", 18 18 + .parts = fujitsu_parts, 19 19 + .nparts = ARRAY_SIZE(fujitsu_parts), 20 20 + };

+59

drivers/mtd/spi-nor/gigadevice.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static void gd25q256_default_init(struct spi_nor *nor) 12 12 + { 13 13 + /* 14 14 + * Some manufacturer like GigaDevice may use different 15 15 + * bit to set QE on different memories, so the MFR can't 16 16 + * indicate the quad_enable method for this case, we need 17 17 + * to set it in the default_init fixup hook. 18 18 + */ 19 19 + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; 20 20 + } 21 21 + 22 22 + static struct spi_nor_fixups gd25q256_fixups = { 23 23 + .default_init = gd25q256_default_init, 24 24 + }; 25 25 + 26 26 + static const struct flash_info gigadevice_parts[] = { 27 27 + { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 28 28 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 29 29 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 30 30 + { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 31 31 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 32 32 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 33 33 + { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 34 34 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 35 35 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 36 36 + { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 37 37 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 38 38 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 39 39 + { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, 40 40 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 41 41 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 42 42 + { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256, 43 43 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 44 44 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 45 45 + { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, 46 46 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 47 47 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 48 48 + { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, 49 49 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 50 50 + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 51 51 + SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) 52 52 + .fixups = &gd25q256_fixups }, 53 53 + }; 54 54 + 55 55 + const struct spi_nor_manufacturer spi_nor_gigadevice = { 56 56 + .name = "gigadevice", 57 57 + .parts = gigadevice_parts, 58 58 + .nparts = ARRAY_SIZE(gigadevice_parts), 59 59 + };

drivers/mtd/spi-nor/hisi-sfc.c drivers/mtd/spi-nor/controllers/hisi-sfc.c

reviewed

drivers/mtd/spi-nor/intel-spi-pci.c drivers/mtd/spi-nor/controllers/intel-spi-pci.c

reviewed

drivers/mtd/spi-nor/intel-spi-platform.c drivers/mtd/spi-nor/controllers/intel-spi-platform.c

reviewed

drivers/mtd/spi-nor/intel-spi.c drivers/mtd/spi-nor/controllers/intel-spi.c

reviewed

drivers/mtd/spi-nor/intel-spi.h drivers/mtd/spi-nor/controllers/intel-spi.h

reviewed

+32

drivers/mtd/spi-nor/intel.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info intel_parts[] = { 12 12 + /* Intel/Numonyx -- xxxs33b */ 13 13 + { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, 14 14 + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, 15 15 + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, 16 16 + }; 17 17 + 18 18 + static void intel_default_init(struct spi_nor *nor) 19 19 + { 20 20 + nor->flags |= SNOR_F_HAS_LOCK; 21 21 + } 22 22 + 23 23 + static const struct spi_nor_fixups intel_fixups = { 24 24 + .default_init = intel_default_init, 25 25 + }; 26 26 + 27 27 + const struct spi_nor_manufacturer spi_nor_intel = { 28 28 + .name = "intel", 29 29 + .parts = intel_parts, 30 30 + .nparts = ARRAY_SIZE(intel_parts), 31 31 + .fixups = &intel_fixups, 32 32 + };

+83

drivers/mtd/spi-nor/issi.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static int 12 12 + is25lp256_post_bfpt_fixups(struct spi_nor *nor, 13 13 + const struct sfdp_parameter_header *bfpt_header, 14 14 + const struct sfdp_bfpt *bfpt, 15 15 + struct spi_nor_flash_parameter *params) 16 16 + { 17 17 + /* 18 18 + * IS25LP256 supports 4B opcodes, but the BFPT advertises a 19 19 + * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width. 20 20 + * Overwrite the address width advertised by the BFPT. 21 21 + */ 22 22 + if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) == 23 23 + BFPT_DWORD1_ADDRESS_BYTES_3_ONLY) 24 24 + nor->addr_width = 4; 25 25 + 26 26 + return 0; 27 27 + } 28 28 + 29 29 + static struct spi_nor_fixups is25lp256_fixups = { 30 30 + .post_bfpt = is25lp256_post_bfpt_fixups, 31 31 + }; 32 32 + 33 33 + static const struct flash_info issi_parts[] = { 34 34 + /* ISSI */ 35 35 + { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, 36 36 + { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8, 37 37 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 38 38 + { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32, 39 39 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 40 40 + { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16, 41 41 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 42 42 + { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 43 43 + SECT_4K | SPI_NOR_DUAL_READ) }, 44 44 + { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 45 45 + SECT_4K | SPI_NOR_DUAL_READ) }, 46 46 + { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256, 47 47 + SECT_4K | SPI_NOR_DUAL_READ) }, 48 48 + { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512, 49 49 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 50 50 + SPI_NOR_4B_OPCODES) 51 51 + .fixups = &is25lp256_fixups }, 52 52 + { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64, 53 53 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 54 54 + { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128, 55 55 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 56 56 + { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, 57 57 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 58 58 + { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512, 59 59 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 60 60 + SPI_NOR_4B_OPCODES) 61 61 + .fixups = &is25lp256_fixups }, 62 62 + 63 63 + /* PMC */ 64 64 + { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, 65 65 + { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, 66 66 + { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, 67 67 + }; 68 68 + 69 69 + static void issi_default_init(struct spi_nor *nor) 70 70 + { 71 71 + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; 72 72 + } 73 73 + 74 74 + static const struct spi_nor_fixups issi_fixups = { 75 75 + .default_init = issi_default_init, 76 76 + }; 77 77 + 78 78 + const struct spi_nor_manufacturer spi_nor_issi = { 79 79 + .name = "issi", 80 80 + .parts = issi_parts, 81 81 + .nparts = ARRAY_SIZE(issi_parts), 82 82 + .fixups = &issi_fixups, 83 83 + };

+98

drivers/mtd/spi-nor/macronix.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static int 12 12 + mx25l25635_post_bfpt_fixups(struct spi_nor *nor, 13 13 + const struct sfdp_parameter_header *bfpt_header, 14 14 + const struct sfdp_bfpt *bfpt, 15 15 + struct spi_nor_flash_parameter *params) 16 16 + { 17 17 + /* 18 18 + * MX25L25635F supports 4B opcodes but MX25L25635E does not. 19 19 + * Unfortunately, Macronix has re-used the same JEDEC ID for both 20 20 + * variants which prevents us from defining a new entry in the parts 21 21 + * table. 22 22 + * We need a way to differentiate MX25L25635E and MX25L25635F, and it 23 23 + * seems that the F version advertises support for Fast Read 4-4-4 in 24 24 + * its BFPT table. 25 25 + */ 26 26 + if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4) 27 27 + nor->flags |= SNOR_F_4B_OPCODES; 28 28 + 29 29 + return 0; 30 30 + } 31 31 + 32 32 + static struct spi_nor_fixups mx25l25635_fixups = { 33 33 + .post_bfpt = mx25l25635_post_bfpt_fixups, 34 34 + }; 35 35 + 36 36 + static const struct flash_info macronix_parts[] = { 37 37 + /* Macronix */ 38 38 + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, 39 39 + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 40 40 + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 41 41 + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 42 42 + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 43 43 + { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 44 44 + { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, 45 45 + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 46 46 + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 47 47 + { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 48 48 + SECT_4K | SPI_NOR_DUAL_READ | 49 49 + SPI_NOR_QUAD_READ) }, 50 50 + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, 51 51 + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, 52 52 + { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 53 53 + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 54 54 + { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 55 55 + { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64, 56 56 + SECT_4K | SPI_NOR_DUAL_READ | 57 57 + SPI_NOR_QUAD_READ) }, 58 58 + { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256, 59 59 + SECT_4K | SPI_NOR_DUAL_READ | 60 60 + SPI_NOR_QUAD_READ) }, 61 61 + { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 62 62 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 63 63 + .fixups = &mx25l25635_fixups }, 64 64 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, 65 65 + SECT_4K | SPI_NOR_4B_OPCODES) }, 66 66 + { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16, 67 67 + SECT_4K | SPI_NOR_DUAL_READ | 68 68 + SPI_NOR_QUAD_READ) }, 69 69 + { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 70 70 + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 71 71 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 72 72 + SPI_NOR_4B_OPCODES) }, 73 73 + { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, 74 74 + SECT_4K | SPI_NOR_DUAL_READ | 75 75 + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 76 76 + { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, 77 77 + SECT_4K | SPI_NOR_DUAL_READ | 78 78 + SPI_NOR_QUAD_READ) }, 79 79 + { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, 80 80 + SPI_NOR_QUAD_READ) }, 81 81 + }; 82 82 + 83 83 + static void macronix_default_init(struct spi_nor *nor) 84 84 + { 85 85 + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; 86 86 + nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode; 87 87 + } 88 88 + 89 89 + static const struct spi_nor_fixups macronix_fixups = { 90 90 + .default_init = macronix_default_init, 91 91 + }; 92 92 + 93 93 + const struct spi_nor_manufacturer spi_nor_macronix = { 94 94 + .name = "macronix", 95 95 + .parts = macronix_parts, 96 96 + .nparts = ARRAY_SIZE(macronix_parts), 97 97 + .fixups = &macronix_fixups, 98 98 + };

+157

drivers/mtd/spi-nor/micron-st.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info micron_parts[] = { 12 12 + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, 13 13 + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | 14 14 + SPI_NOR_4B_OPCODES) }, 15 15 + { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, 16 16 + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | 17 17 + SPI_NOR_4B_OPCODES) }, 18 18 + }; 19 19 + 20 20 + static const struct flash_info st_parts[] = { 21 21 + { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, 22 22 + SECT_4K | SPI_NOR_QUAD_READ) }, 23 23 + { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 24 24 + SPI_NOR_QUAD_READ) }, 25 25 + { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, 26 26 + SPI_NOR_QUAD_READ) }, 27 27 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 28 28 + SECT_4K | SPI_NOR_QUAD_READ) }, 29 29 + { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, 30 30 + SECT_4K | SPI_NOR_QUAD_READ) }, 31 31 + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 32 32 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 33 33 + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 34 34 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 35 35 + { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, 36 36 + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 37 37 + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 38 38 + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | 39 39 + USE_FSR | SPI_NOR_DUAL_READ | 40 40 + SPI_NOR_QUAD_READ) }, 41 41 + { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, 42 42 + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 43 43 + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 44 44 + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, 45 45 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 46 46 + { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, 47 47 + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 48 48 + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 49 49 + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, 50 50 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 51 51 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 52 52 + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, 53 53 + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024, 54 54 + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 55 55 + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 56 56 + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, 57 57 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 58 58 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 59 59 + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, 60 60 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, 61 61 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 62 62 + NO_CHIP_ERASE) }, 63 63 + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, 64 64 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 65 65 + NO_CHIP_ERASE) }, 66 66 + { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096, 67 67 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 68 68 + NO_CHIP_ERASE) }, 69 69 + { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, 70 70 + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 71 71 + NO_CHIP_ERASE) }, 72 72 + 73 73 + { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, 74 74 + { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 75 75 + { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 76 76 + { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 77 77 + { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 78 78 + { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 79 79 + { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 80 80 + { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 81 81 + { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 82 82 + 83 83 + { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, 84 84 + { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, 85 85 + { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, 86 86 + { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, 87 87 + { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, 88 88 + { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, 89 89 + { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, 90 90 + { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, 91 91 + { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, 92 92 + 93 93 + { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, 94 94 + { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, 95 95 + { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, 96 96 + 97 97 + { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, 98 98 + { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, 99 99 + { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 100 100 + 101 101 + { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, 102 102 + { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, 103 103 + { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, 104 104 + { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, 105 105 + { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 106 106 + { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, 107 107 + }; 108 108 + 109 109 + /** 110 110 + * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron 111 111 + * flashes. 112 112 + * @nor: pointer to 'struct spi_nor'. 113 113 + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 114 114 + * address mode. 115 115 + * 116 116 + * Return: 0 on success, -errno otherwise. 117 117 + */ 118 118 + static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 119 119 + { 120 120 + int ret; 121 121 + 122 122 + ret = spi_nor_write_enable(nor); 123 123 + if (ret) 124 124 + return ret; 125 125 + 126 126 + ret = spi_nor_set_4byte_addr_mode(nor, enable); 127 127 + if (ret) 128 128 + return ret; 129 129 + 130 130 + return spi_nor_write_disable(nor); 131 131 + } 132 132 + 133 133 + static void micron_st_default_init(struct spi_nor *nor) 134 134 + { 135 135 + nor->flags |= SNOR_F_HAS_LOCK; 136 136 + nor->flags &= ~SNOR_F_HAS_16BIT_SR; 137 137 + nor->params->quad_enable = NULL; 138 138 + nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode; 139 139 + } 140 140 + 141 141 + static const struct spi_nor_fixups micron_st_fixups = { 142 142 + .default_init = micron_st_default_init, 143 143 + }; 144 144 + 145 145 + const struct spi_nor_manufacturer spi_nor_micron = { 146 146 + .name = "micron", 147 147 + .parts = micron_parts, 148 148 + .nparts = ARRAY_SIZE(micron_parts), 149 149 + .fixups = &micron_st_fixups, 150 150 + }; 151 151 + 152 152 + const struct spi_nor_manufacturer spi_nor_st = { 153 153 + .name = "st", 154 154 + .parts = st_parts, 155 155 + .nparts = ARRAY_SIZE(st_parts), 156 156 + .fixups = &micron_st_fixups, 157 157 + };

drivers/mtd/spi-nor/nxp-spifi.c drivers/mtd/spi-nor/controllers/nxp-spifi.c

reviewed

+1204

drivers/mtd/spi-nor/sfdp.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/slab.h> 8 8 + #include <linux/sort.h> 9 9 + #include <linux/mtd/spi-nor.h> 10 10 + 11 11 + #include "core.h" 12 12 + 13 13 + #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 14 14 + #define SFDP_PARAM_HEADER_PTP(p) \ 15 15 + (((p)->parameter_table_pointer[2] << 16) | \ 16 16 + ((p)->parameter_table_pointer[1] << 8) | \ 17 17 + ((p)->parameter_table_pointer[0] << 0)) 18 18 + 19 19 + #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 20 20 + #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 21 21 + #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */ 22 22 + 23 23 + #define SFDP_SIGNATURE 0x50444653U 24 24 + #define SFDP_JESD216_MAJOR 1 25 25 + #define SFDP_JESD216_MINOR 0 26 26 + #define SFDP_JESD216A_MINOR 5 27 27 + #define SFDP_JESD216B_MINOR 6 28 28 + 29 29 + struct sfdp_header { 30 30 + u32 signature; /* Ox50444653U <=> "SFDP" */ 31 31 + u8 minor; 32 32 + u8 major; 33 33 + u8 nph; /* 0-base number of parameter headers */ 34 34 + u8 unused; 35 35 + 36 36 + /* Basic Flash Parameter Table. */ 37 37 + struct sfdp_parameter_header bfpt_header; 38 38 + }; 39 39 + 40 40 + /* Fast Read settings. */ 41 41 + struct sfdp_bfpt_read { 42 42 + /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 43 43 + u32 hwcaps; 44 44 + 45 45 + /* 46 46 + * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 47 47 + * whether the Fast Read x-y-z command is supported. 48 48 + */ 49 49 + u32 supported_dword; 50 50 + u32 supported_bit; 51 51 + 52 52 + /* 53 53 + * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 54 54 + * encodes the op code, the number of mode clocks and the number of wait 55 55 + * states to be used by Fast Read x-y-z command. 56 56 + */ 57 57 + u32 settings_dword; 58 58 + u32 settings_shift; 59 59 + 60 60 + /* The SPI protocol for this Fast Read x-y-z command. */ 61 61 + enum spi_nor_protocol proto; 62 62 + }; 63 63 + 64 64 + struct sfdp_bfpt_erase { 65 65 + /* 66 66 + * The half-word at offset <shift> in DWORD <dwoard> encodes the 67 67 + * op code and erase sector size to be used by Sector Erase commands. 68 68 + */ 69 69 + u32 dword; 70 70 + u32 shift; 71 71 + }; 72 72 + 73 73 + #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22) 74 74 + #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22) 75 75 + #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22) 76 76 + #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22) 77 77 + #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22) 78 78 + 79 79 + #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16) 80 80 + #define SMPT_CMD_READ_DUMMY_SHIFT 16 81 81 + #define SMPT_CMD_READ_DUMMY(_cmd) \ 82 82 + (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT) 83 83 + #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL 84 84 + 85 85 + #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24) 86 86 + #define SMPT_CMD_READ_DATA_SHIFT 24 87 87 + #define SMPT_CMD_READ_DATA(_cmd) \ 88 88 + (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT) 89 89 + 90 90 + #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8) 91 91 + #define SMPT_CMD_OPCODE_SHIFT 8 92 92 + #define SMPT_CMD_OPCODE(_cmd) \ 93 93 + (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT) 94 94 + 95 95 + #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16) 96 96 + #define SMPT_MAP_REGION_COUNT_SHIFT 16 97 97 + #define SMPT_MAP_REGION_COUNT(_header) \ 98 98 + ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \ 99 99 + SMPT_MAP_REGION_COUNT_SHIFT) + 1) 100 100 + 101 101 + #define SMPT_MAP_ID_MASK GENMASK(15, 8) 102 102 + #define SMPT_MAP_ID_SHIFT 8 103 103 + #define SMPT_MAP_ID(_header) \ 104 104 + (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT) 105 105 + 106 106 + #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8) 107 107 + #define SMPT_MAP_REGION_SIZE_SHIFT 8 108 108 + #define SMPT_MAP_REGION_SIZE(_region) \ 109 109 + (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \ 110 110 + SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256) 111 111 + 112 112 + #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0) 113 113 + #define SMPT_MAP_REGION_ERASE_TYPE(_region) \ 114 114 + ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK) 115 115 + 116 116 + #define SMPT_DESC_TYPE_MAP BIT(1) 117 117 + #define SMPT_DESC_END BIT(0) 118 118 + 119 119 + #define SFDP_4BAIT_DWORD_MAX 2 120 120 + 121 121 + struct sfdp_4bait { 122 122 + /* The hardware capability. */ 123 123 + u32 hwcaps; 124 124 + 125 125 + /* 126 126 + * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether 127 127 + * the associated 4-byte address op code is supported. 128 128 + */ 129 129 + u32 supported_bit; 130 130 + }; 131 131 + 132 132 + /** 133 133 + * spi_nor_read_raw() - raw read of serial flash memory. read_opcode, 134 134 + * addr_width and read_dummy members of the struct spi_nor 135 135 + * should be previously 136 136 + * set. 137 137 + * @nor: pointer to a 'struct spi_nor' 138 138 + * @addr: offset in the serial flash memory 139 139 + * @len: number of bytes to read 140 140 + * @buf: buffer where the data is copied into (dma-safe memory) 141 141 + * 142 142 + * Return: 0 on success, -errno otherwise. 143 143 + */ 144 144 + static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf) 145 145 + { 146 146 + ssize_t ret; 147 147 + 148 148 + while (len) { 149 149 + ret = spi_nor_read_data(nor, addr, len, buf); 150 150 + if (ret < 0) 151 151 + return ret; 152 152 + if (!ret || ret > len) 153 153 + return -EIO; 154 154 + 155 155 + buf += ret; 156 156 + addr += ret; 157 157 + len -= ret; 158 158 + } 159 159 + return 0; 160 160 + } 161 161 + 162 162 + /** 163 163 + * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 164 164 + * @nor: pointer to a 'struct spi_nor' 165 165 + * @addr: offset in the SFDP area to start reading data from 166 166 + * @len: number of bytes to read 167 167 + * @buf: buffer where the SFDP data are copied into (dma-safe memory) 168 168 + * 169 169 + * Whatever the actual numbers of bytes for address and dummy cycles are 170 170 + * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 171 171 + * followed by a 3-byte address and 8 dummy clock cycles. 172 172 + * 173 173 + * Return: 0 on success, -errno otherwise. 174 174 + */ 175 175 + static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 176 176 + size_t len, void *buf) 177 177 + { 178 178 + u8 addr_width, read_opcode, read_dummy; 179 179 + int ret; 180 180 + 181 181 + read_opcode = nor->read_opcode; 182 182 + addr_width = nor->addr_width; 183 183 + read_dummy = nor->read_dummy; 184 184 + 185 185 + nor->read_opcode = SPINOR_OP_RDSFDP; 186 186 + nor->addr_width = 3; 187 187 + nor->read_dummy = 8; 188 188 + 189 189 + ret = spi_nor_read_raw(nor, addr, len, buf); 190 190 + 191 191 + nor->read_opcode = read_opcode; 192 192 + nor->addr_width = addr_width; 193 193 + nor->read_dummy = read_dummy; 194 194 + 195 195 + return ret; 196 196 + } 197 197 + 198 198 + /** 199 199 + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. 200 200 + * @nor: pointer to a 'struct spi_nor' 201 201 + * @addr: offset in the SFDP area to start reading data from 202 202 + * @len: number of bytes to read 203 203 + * @buf: buffer where the SFDP data are copied into 204 204 + * 205 205 + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not 206 206 + * guaranteed to be dma-safe. 207 207 + * 208 208 + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() 209 209 + * otherwise. 210 210 + */ 211 211 + static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, 212 212 + size_t len, void *buf) 213 213 + { 214 214 + void *dma_safe_buf; 215 215 + int ret; 216 216 + 217 217 + dma_safe_buf = kmalloc(len, GFP_KERNEL); 218 218 + if (!dma_safe_buf) 219 219 + return -ENOMEM; 220 220 + 221 221 + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); 222 222 + memcpy(buf, dma_safe_buf, len); 223 223 + kfree(dma_safe_buf); 224 224 + 225 225 + return ret; 226 226 + } 227 227 + 228 228 + static void 229 229 + spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 230 230 + u16 half, 231 231 + enum spi_nor_protocol proto) 232 232 + { 233 233 + read->num_mode_clocks = (half >> 5) & 0x07; 234 234 + read->num_wait_states = (half >> 0) & 0x1f; 235 235 + read->opcode = (half >> 8) & 0xff; 236 236 + read->proto = proto; 237 237 + } 238 238 + 239 239 + static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 240 240 + /* Fast Read 1-1-2 */ 241 241 + { 242 242 + SNOR_HWCAPS_READ_1_1_2, 243 243 + BFPT_DWORD(1), BIT(16), /* Supported bit */ 244 244 + BFPT_DWORD(4), 0, /* Settings */ 245 245 + SNOR_PROTO_1_1_2, 246 246 + }, 247 247 + 248 248 + /* Fast Read 1-2-2 */ 249 249 + { 250 250 + SNOR_HWCAPS_READ_1_2_2, 251 251 + BFPT_DWORD(1), BIT(20), /* Supported bit */ 252 252 + BFPT_DWORD(4), 16, /* Settings */ 253 253 + SNOR_PROTO_1_2_2, 254 254 + }, 255 255 + 256 256 + /* Fast Read 2-2-2 */ 257 257 + { 258 258 + SNOR_HWCAPS_READ_2_2_2, 259 259 + BFPT_DWORD(5), BIT(0), /* Supported bit */ 260 260 + BFPT_DWORD(6), 16, /* Settings */ 261 261 + SNOR_PROTO_2_2_2, 262 262 + }, 263 263 + 264 264 + /* Fast Read 1-1-4 */ 265 265 + { 266 266 + SNOR_HWCAPS_READ_1_1_4, 267 267 + BFPT_DWORD(1), BIT(22), /* Supported bit */ 268 268 + BFPT_DWORD(3), 16, /* Settings */ 269 269 + SNOR_PROTO_1_1_4, 270 270 + }, 271 271 + 272 272 + /* Fast Read 1-4-4 */ 273 273 + { 274 274 + SNOR_HWCAPS_READ_1_4_4, 275 275 + BFPT_DWORD(1), BIT(21), /* Supported bit */ 276 276 + BFPT_DWORD(3), 0, /* Settings */ 277 277 + SNOR_PROTO_1_4_4, 278 278 + }, 279 279 + 280 280 + /* Fast Read 4-4-4 */ 281 281 + { 282 282 + SNOR_HWCAPS_READ_4_4_4, 283 283 + BFPT_DWORD(5), BIT(4), /* Supported bit */ 284 284 + BFPT_DWORD(7), 16, /* Settings */ 285 285 + SNOR_PROTO_4_4_4, 286 286 + }, 287 287 + }; 288 288 + 289 289 + static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 290 290 + /* Erase Type 1 in DWORD8 bits[15:0] */ 291 291 + {BFPT_DWORD(8), 0}, 292 292 + 293 293 + /* Erase Type 2 in DWORD8 bits[31:16] */ 294 294 + {BFPT_DWORD(8), 16}, 295 295 + 296 296 + /* Erase Type 3 in DWORD9 bits[15:0] */ 297 297 + {BFPT_DWORD(9), 0}, 298 298 + 299 299 + /* Erase Type 4 in DWORD9 bits[31:16] */ 300 300 + {BFPT_DWORD(9), 16}, 301 301 + }; 302 302 + 303 303 + /** 304 304 + * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT 305 305 + * @erase: pointer to a structure that describes a SPI NOR erase type 306 306 + * @size: the size of the sector/block erased by the erase type 307 307 + * @opcode: the SPI command op code to erase the sector/block 308 308 + * @i: erase type index as sorted in the Basic Flash Parameter Table 309 309 + * 310 310 + * The supported Erase Types will be sorted at init in ascending order, with 311 311 + * the smallest Erase Type size being the first member in the erase_type array 312 312 + * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in 313 313 + * the Basic Flash Parameter Table since it will be used later on to 314 314 + * synchronize with the supported Erase Types defined in SFDP optional tables. 315 315 + */ 316 316 + static void 317 317 + spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase, 318 318 + u32 size, u8 opcode, u8 i) 319 319 + { 320 320 + erase->idx = i; 321 321 + spi_nor_set_erase_type(erase, size, opcode); 322 322 + } 323 323 + 324 324 + /** 325 325 + * spi_nor_map_cmp_erase_type() - compare the map's erase types by size 326 326 + * @l: member in the left half of the map's erase_type array 327 327 + * @r: member in the right half of the map's erase_type array 328 328 + * 329 329 + * Comparison function used in the sort() call to sort in ascending order the 330 330 + * map's erase types, the smallest erase type size being the first member in the 331 331 + * sorted erase_type array. 332 332 + * 333 333 + * Return: the result of @l->size - @r->size 334 334 + */ 335 335 + static int spi_nor_map_cmp_erase_type(const void *l, const void *r) 336 336 + { 337 337 + const struct spi_nor_erase_type *left = l, *right = r; 338 338 + 339 339 + return left->size - right->size; 340 340 + } 341 341 + 342 342 + /** 343 343 + * spi_nor_sort_erase_mask() - sort erase mask 344 344 + * @map: the erase map of the SPI NOR 345 345 + * @erase_mask: the erase type mask to be sorted 346 346 + * 347 347 + * Replicate the sort done for the map's erase types in BFPT: sort the erase 348 348 + * mask in ascending order with the smallest erase type size starting from 349 349 + * BIT(0) in the sorted erase mask. 350 350 + * 351 351 + * Return: sorted erase mask. 352 352 + */ 353 353 + static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask) 354 354 + { 355 355 + struct spi_nor_erase_type *erase_type = map->erase_type; 356 356 + int i; 357 357 + u8 sorted_erase_mask = 0; 358 358 + 359 359 + if (!erase_mask) 360 360 + return 0; 361 361 + 362 362 + /* Replicate the sort done for the map's erase types. */ 363 363 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) 364 364 + if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx)) 365 365 + sorted_erase_mask |= BIT(i); 366 366 + 367 367 + return sorted_erase_mask; 368 368 + } 369 369 + 370 370 + /** 371 371 + * spi_nor_regions_sort_erase_types() - sort erase types in each region 372 372 + * @map: the erase map of the SPI NOR 373 373 + * 374 374 + * Function assumes that the erase types defined in the erase map are already 375 375 + * sorted in ascending order, with the smallest erase type size being the first 376 376 + * member in the erase_type array. It replicates the sort done for the map's 377 377 + * erase types. Each region's erase bitmask will indicate which erase types are 378 378 + * supported from the sorted erase types defined in the erase map. 379 379 + * Sort the all region's erase type at init in order to speed up the process of 380 380 + * finding the best erase command at runtime. 381 381 + */ 382 382 + static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map) 383 383 + { 384 384 + struct spi_nor_erase_region *region = map->regions; 385 385 + u8 region_erase_mask, sorted_erase_mask; 386 386 + 387 387 + while (region) { 388 388 + region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 389 389 + 390 390 + sorted_erase_mask = spi_nor_sort_erase_mask(map, 391 391 + region_erase_mask); 392 392 + 393 393 + /* Overwrite erase mask. */ 394 394 + region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) | 395 395 + sorted_erase_mask; 396 396 + 397 397 + region = spi_nor_region_next(region); 398 398 + } 399 399 + } 400 400 + 401 401 + /** 402 402 + * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 403 403 + * @nor: pointer to a 'struct spi_nor' 404 404 + * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 405 405 + * the Basic Flash Parameter Table length and version 406 406 + * @params: pointer to the 'struct spi_nor_flash_parameter' to be 407 407 + * filled 408 408 + * 409 409 + * The Basic Flash Parameter Table is the main and only mandatory table as 410 410 + * defined by the SFDP (JESD216) specification. 411 411 + * It provides us with the total size (memory density) of the data array and 412 412 + * the number of address bytes for Fast Read, Page Program and Sector Erase 413 413 + * commands. 414 414 + * For Fast READ commands, it also gives the number of mode clock cycles and 415 415 + * wait states (regrouped in the number of dummy clock cycles) for each 416 416 + * supported instruction op code. 417 417 + * For Page Program, the page size is now available since JESD216 rev A, however 418 418 + * the supported instruction op codes are still not provided. 419 419 + * For Sector Erase commands, this table stores the supported instruction op 420 420 + * codes and the associated sector sizes. 421 421 + * Finally, the Quad Enable Requirements (QER) are also available since JESD216 422 422 + * rev A. The QER bits encode the manufacturer dependent procedure to be 423 423 + * executed to set the Quad Enable (QE) bit in some internal register of the 424 424 + * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 425 425 + * sending any Quad SPI command to the memory. Actually, setting the QE bit 426 426 + * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 427 427 + * and IO3 hence enabling 4 (Quad) I/O lines. 428 428 + * 429 429 + * Return: 0 on success, -errno otherwise. 430 430 + */ 431 431 + static int spi_nor_parse_bfpt(struct spi_nor *nor, 432 432 + const struct sfdp_parameter_header *bfpt_header, 433 433 + struct spi_nor_flash_parameter *params) 434 434 + { 435 435 + struct spi_nor_erase_map *map = &params->erase_map; 436 436 + struct spi_nor_erase_type *erase_type = map->erase_type; 437 437 + struct sfdp_bfpt bfpt; 438 438 + size_t len; 439 439 + int i, cmd, err; 440 440 + u32 addr; 441 441 + u16 half; 442 442 + u8 erase_mask; 443 443 + 444 444 + /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 445 445 + if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 446 446 + return -EINVAL; 447 447 + 448 448 + /* Read the Basic Flash Parameter Table. */ 449 449 + len = min_t(size_t, sizeof(bfpt), 450 450 + bfpt_header->length * sizeof(u32)); 451 451 + addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 452 452 + memset(&bfpt, 0, sizeof(bfpt)); 453 453 + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); 454 454 + if (err < 0) 455 455 + return err; 456 456 + 457 457 + /* Fix endianness of the BFPT DWORDs. */ 458 458 + le32_to_cpu_array(bfpt.dwords, BFPT_DWORD_MAX); 459 459 + 460 460 + /* Number of address bytes. */ 461 461 + switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 462 462 + case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 463 463 + nor->addr_width = 3; 464 464 + break; 465 465 + 466 466 + case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 467 467 + nor->addr_width = 4; 468 468 + break; 469 469 + 470 470 + default: 471 471 + break; 472 472 + } 473 473 + 474 474 + /* Flash Memory Density (in bits). */ 475 475 + params->size = bfpt.dwords[BFPT_DWORD(2)]; 476 476 + if (params->size & BIT(31)) { 477 477 + params->size &= ~BIT(31); 478 478 + 479 479 + /* 480 480 + * Prevent overflows on params->size. Anyway, a NOR of 2^64 481 481 + * bits is unlikely to exist so this error probably means 482 482 + * the BFPT we are reading is corrupted/wrong. 483 483 + */ 484 484 + if (params->size > 63) 485 485 + return -EINVAL; 486 486 + 487 487 + params->size = 1ULL << params->size; 488 488 + } else { 489 489 + params->size++; 490 490 + } 491 491 + params->size >>= 3; /* Convert to bytes. */ 492 492 + 493 493 + /* Fast Read settings. */ 494 494 + for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 495 495 + const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 496 496 + struct spi_nor_read_command *read; 497 497 + 498 498 + if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 499 499 + params->hwcaps.mask &= ~rd->hwcaps; 500 500 + continue; 501 501 + } 502 502 + 503 503 + params->hwcaps.mask |= rd->hwcaps; 504 504 + cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 505 505 + read = &params->reads[cmd]; 506 506 + half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 507 507 + spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 508 508 + } 509 509 + 510 510 + /* 511 511 + * Sector Erase settings. Reinitialize the uniform erase map using the 512 512 + * Erase Types defined in the bfpt table. 513 513 + */ 514 514 + erase_mask = 0; 515 515 + memset(&params->erase_map, 0, sizeof(params->erase_map)); 516 516 + for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 517 517 + const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 518 518 + u32 erasesize; 519 519 + u8 opcode; 520 520 + 521 521 + half = bfpt.dwords[er->dword] >> er->shift; 522 522 + erasesize = half & 0xff; 523 523 + 524 524 + /* erasesize == 0 means this Erase Type is not supported. */ 525 525 + if (!erasesize) 526 526 + continue; 527 527 + 528 528 + erasesize = 1U << erasesize; 529 529 + opcode = (half >> 8) & 0xff; 530 530 + erase_mask |= BIT(i); 531 531 + spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize, 532 532 + opcode, i); 533 533 + } 534 534 + spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 535 535 + /* 536 536 + * Sort all the map's Erase Types in ascending order with the smallest 537 537 + * erase size being the first member in the erase_type array. 538 538 + */ 539 539 + sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]), 540 540 + spi_nor_map_cmp_erase_type, NULL); 541 541 + /* 542 542 + * Sort the erase types in the uniform region in order to update the 543 543 + * uniform_erase_type bitmask. The bitmask will be used later on when 544 544 + * selecting the uniform erase. 545 545 + */ 546 546 + spi_nor_regions_sort_erase_types(map); 547 547 + map->uniform_erase_type = map->uniform_region.offset & 548 548 + SNOR_ERASE_TYPE_MASK; 549 549 + 550 550 + /* Stop here if not JESD216 rev A or later. */ 551 551 + if (bfpt_header->length < BFPT_DWORD_MAX) 552 552 + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, 553 553 + params); 554 554 + 555 555 + /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 556 556 + params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 557 557 + params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 558 558 + params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 559 559 + params->page_size = 1U << params->page_size; 560 560 + 561 561 + /* Quad Enable Requirements. */ 562 562 + switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 563 563 + case BFPT_DWORD15_QER_NONE: 564 564 + params->quad_enable = NULL; 565 565 + break; 566 566 + 567 567 + case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 568 568 + /* 569 569 + * Writing only one byte to the Status Register has the 570 570 + * side-effect of clearing Status Register 2. 571 571 + */ 572 572 + case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 573 573 + /* 574 574 + * Read Configuration Register (35h) instruction is not 575 575 + * supported. 576 576 + */ 577 577 + nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; 578 578 + params->quad_enable = spi_nor_sr2_bit1_quad_enable; 579 579 + break; 580 580 + 581 581 + case BFPT_DWORD15_QER_SR1_BIT6: 582 582 + nor->flags &= ~SNOR_F_HAS_16BIT_SR; 583 583 + params->quad_enable = spi_nor_sr1_bit6_quad_enable; 584 584 + break; 585 585 + 586 586 + case BFPT_DWORD15_QER_SR2_BIT7: 587 587 + nor->flags &= ~SNOR_F_HAS_16BIT_SR; 588 588 + params->quad_enable = spi_nor_sr2_bit7_quad_enable; 589 589 + break; 590 590 + 591 591 + case BFPT_DWORD15_QER_SR2_BIT1: 592 592 + /* 593 593 + * JESD216 rev B or later does not specify if writing only one 594 594 + * byte to the Status Register clears or not the Status 595 595 + * Register 2, so let's be cautious and keep the default 596 596 + * assumption of a 16-bit Write Status (01h) command. 597 597 + */ 598 598 + nor->flags |= SNOR_F_HAS_16BIT_SR; 599 599 + 600 600 + params->quad_enable = spi_nor_sr2_bit1_quad_enable; 601 601 + break; 602 602 + 603 603 + default: 604 604 + return -EINVAL; 605 605 + } 606 606 + 607 607 + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); 608 608 + } 609 609 + 610 610 + /** 611 611 + * spi_nor_smpt_addr_width() - return the address width used in the 612 612 + * configuration detection command. 613 613 + * @nor: pointer to a 'struct spi_nor' 614 614 + * @settings: configuration detection command descriptor, dword1 615 615 + */ 616 616 + static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings) 617 617 + { 618 618 + switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) { 619 619 + case SMPT_CMD_ADDRESS_LEN_0: 620 620 + return 0; 621 621 + case SMPT_CMD_ADDRESS_LEN_3: 622 622 + return 3; 623 623 + case SMPT_CMD_ADDRESS_LEN_4: 624 624 + return 4; 625 625 + case SMPT_CMD_ADDRESS_LEN_USE_CURRENT: 626 626 + default: 627 627 + return nor->addr_width; 628 628 + } 629 629 + } 630 630 + 631 631 + /** 632 632 + * spi_nor_smpt_read_dummy() - return the configuration detection command read 633 633 + * latency, in clock cycles. 634 634 + * @nor: pointer to a 'struct spi_nor' 635 635 + * @settings: configuration detection command descriptor, dword1 636 636 + * 637 637 + * Return: the number of dummy cycles for an SMPT read 638 638 + */ 639 639 + static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings) 640 640 + { 641 641 + u8 read_dummy = SMPT_CMD_READ_DUMMY(settings); 642 642 + 643 643 + if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE) 644 644 + return nor->read_dummy; 645 645 + return read_dummy; 646 646 + } 647 647 + 648 648 + /** 649 649 + * spi_nor_get_map_in_use() - get the configuration map in use 650 650 + * @nor: pointer to a 'struct spi_nor' 651 651 + * @smpt: pointer to the sector map parameter table 652 652 + * @smpt_len: sector map parameter table length 653 653 + * 654 654 + * Return: pointer to the map in use, ERR_PTR(-errno) otherwise. 655 655 + */ 656 656 + static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt, 657 657 + u8 smpt_len) 658 658 + { 659 659 + const u32 *ret; 660 660 + u8 *buf; 661 661 + u32 addr; 662 662 + int err; 663 663 + u8 i; 664 664 + u8 addr_width, read_opcode, read_dummy; 665 665 + u8 read_data_mask, map_id; 666 666 + 667 667 + /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */ 668 668 + buf = kmalloc(sizeof(*buf), GFP_KERNEL); 669 669 + if (!buf) 670 670 + return ERR_PTR(-ENOMEM); 671 671 + 672 672 + addr_width = nor->addr_width; 673 673 + read_dummy = nor->read_dummy; 674 674 + read_opcode = nor->read_opcode; 675 675 + 676 676 + map_id = 0; 677 677 + /* Determine if there are any optional Detection Command Descriptors */ 678 678 + for (i = 0; i < smpt_len; i += 2) { 679 679 + if (smpt[i] & SMPT_DESC_TYPE_MAP) 680 680 + break; 681 681 + 682 682 + read_data_mask = SMPT_CMD_READ_DATA(smpt[i]); 683 683 + nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]); 684 684 + nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]); 685 685 + nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]); 686 686 + addr = smpt[i + 1]; 687 687 + 688 688 + err = spi_nor_read_raw(nor, addr, 1, buf); 689 689 + if (err) { 690 690 + ret = ERR_PTR(err); 691 691 + goto out; 692 692 + } 693 693 + 694 694 + /* 695 695 + * Build an index value that is used to select the Sector Map 696 696 + * Configuration that is currently in use. 697 697 + */ 698 698 + map_id = map_id << 1 | !!(*buf & read_data_mask); 699 699 + } 700 700 + 701 701 + /* 702 702 + * If command descriptors are provided, they always precede map 703 703 + * descriptors in the table. There is no need to start the iteration 704 704 + * over smpt array all over again. 705 705 + * 706 706 + * Find the matching configuration map. 707 707 + */ 708 708 + ret = ERR_PTR(-EINVAL); 709 709 + while (i < smpt_len) { 710 710 + if (SMPT_MAP_ID(smpt[i]) == map_id) { 711 711 + ret = smpt + i; 712 712 + break; 713 713 + } 714 714 + 715 715 + /* 716 716 + * If there are no more configuration map descriptors and no 717 717 + * configuration ID matched the configuration identifier, the 718 718 + * sector address map is unknown. 719 719 + */ 720 720 + if (smpt[i] & SMPT_DESC_END) 721 721 + break; 722 722 + 723 723 + /* increment the table index to the next map */ 724 724 + i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1; 725 725 + } 726 726 + 727 727 + /* fall through */ 728 728 + out: 729 729 + kfree(buf); 730 730 + nor->addr_width = addr_width; 731 731 + nor->read_dummy = read_dummy; 732 732 + nor->read_opcode = read_opcode; 733 733 + return ret; 734 734 + } 735 735 + 736 736 + static void spi_nor_region_mark_end(struct spi_nor_erase_region *region) 737 737 + { 738 738 + region->offset |= SNOR_LAST_REGION; 739 739 + } 740 740 + 741 741 + static void spi_nor_region_mark_overlay(struct spi_nor_erase_region *region) 742 742 + { 743 743 + region->offset |= SNOR_OVERLAID_REGION; 744 744 + } 745 745 + 746 746 + /** 747 747 + * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid 748 748 + * @region: pointer to a structure that describes a SPI NOR erase region 749 749 + * @erase: pointer to a structure that describes a SPI NOR erase type 750 750 + * @erase_type: erase type bitmask 751 751 + */ 752 752 + static void 753 753 + spi_nor_region_check_overlay(struct spi_nor_erase_region *region, 754 754 + const struct spi_nor_erase_type *erase, 755 755 + const u8 erase_type) 756 756 + { 757 757 + int i; 758 758 + 759 759 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 760 760 + if (!(erase_type & BIT(i))) 761 761 + continue; 762 762 + if (region->size & erase[i].size_mask) { 763 763 + spi_nor_region_mark_overlay(region); 764 764 + return; 765 765 + } 766 766 + } 767 767 + } 768 768 + 769 769 + /** 770 770 + * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map 771 771 + * @nor: pointer to a 'struct spi_nor' 772 772 + * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is 773 773 + * used for storing SFDP parsed data 774 774 + * @smpt: pointer to the sector map parameter table 775 775 + * 776 776 + * Return: 0 on success, -errno otherwise. 777 777 + */ 778 778 + static int 779 779 + spi_nor_init_non_uniform_erase_map(struct spi_nor *nor, 780 780 + struct spi_nor_flash_parameter *params, 781 781 + const u32 *smpt) 782 782 + { 783 783 + struct spi_nor_erase_map *map = &params->erase_map; 784 784 + struct spi_nor_erase_type *erase = map->erase_type; 785 785 + struct spi_nor_erase_region *region; 786 786 + u64 offset; 787 787 + u32 region_count; 788 788 + int i, j; 789 789 + u8 uniform_erase_type, save_uniform_erase_type; 790 790 + u8 erase_type, regions_erase_type; 791 791 + 792 792 + region_count = SMPT_MAP_REGION_COUNT(*smpt); 793 793 + /* 794 794 + * The regions will be freed when the driver detaches from the 795 795 + * device. 796 796 + */ 797 797 + region = devm_kcalloc(nor->dev, region_count, sizeof(*region), 798 798 + GFP_KERNEL); 799 799 + if (!region) 800 800 + return -ENOMEM; 801 801 + map->regions = region; 802 802 + 803 803 + uniform_erase_type = 0xff; 804 804 + regions_erase_type = 0; 805 805 + offset = 0; 806 806 + /* Populate regions. */ 807 807 + for (i = 0; i < region_count; i++) { 808 808 + j = i + 1; /* index for the region dword */ 809 809 + region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]); 810 810 + erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]); 811 811 + region[i].offset = offset | erase_type; 812 812 + 813 813 + spi_nor_region_check_overlay(&region[i], erase, erase_type); 814 814 + 815 815 + /* 816 816 + * Save the erase types that are supported in all regions and 817 817 + * can erase the entire flash memory. 818 818 + */ 819 819 + uniform_erase_type &= erase_type; 820 820 + 821 821 + /* 822 822 + * regions_erase_type mask will indicate all the erase types 823 823 + * supported in this configuration map. 824 824 + */ 825 825 + regions_erase_type |= erase_type; 826 826 + 827 827 + offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) + 828 828 + region[i].size; 829 829 + } 830 830 + 831 831 + save_uniform_erase_type = map->uniform_erase_type; 832 832 + map->uniform_erase_type = spi_nor_sort_erase_mask(map, 833 833 + uniform_erase_type); 834 834 + 835 835 + if (!regions_erase_type) { 836 836 + /* 837 837 + * Roll back to the previous uniform_erase_type mask, SMPT is 838 838 + * broken. 839 839 + */ 840 840 + map->uniform_erase_type = save_uniform_erase_type; 841 841 + return -EINVAL; 842 842 + } 843 843 + 844 844 + /* 845 845 + * BFPT advertises all the erase types supported by all the possible 846 846 + * map configurations. Mask out the erase types that are not supported 847 847 + * by the current map configuration. 848 848 + */ 849 849 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) 850 850 + if (!(regions_erase_type & BIT(erase[i].idx))) 851 851 + spi_nor_set_erase_type(&erase[i], 0, 0xFF); 852 852 + 853 853 + spi_nor_region_mark_end(&region[i - 1]); 854 854 + 855 855 + return 0; 856 856 + } 857 857 + 858 858 + /** 859 859 + * spi_nor_parse_smpt() - parse Sector Map Parameter Table 860 860 + * @nor: pointer to a 'struct spi_nor' 861 861 + * @smpt_header: sector map parameter table header 862 862 + * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' 863 863 + * that is used for storing SFDP parsed data 864 864 + * 865 865 + * This table is optional, but when available, we parse it to identify the 866 866 + * location and size of sectors within the main data array of the flash memory 867 867 + * device and to identify which Erase Types are supported by each sector. 868 868 + * 869 869 + * Return: 0 on success, -errno otherwise. 870 870 + */ 871 871 + static int spi_nor_parse_smpt(struct spi_nor *nor, 872 872 + const struct sfdp_parameter_header *smpt_header, 873 873 + struct spi_nor_flash_parameter *params) 874 874 + { 875 875 + const u32 *sector_map; 876 876 + u32 *smpt; 877 877 + size_t len; 878 878 + u32 addr; 879 879 + int ret; 880 880 + 881 881 + /* Read the Sector Map Parameter Table. */ 882 882 + len = smpt_header->length * sizeof(*smpt); 883 883 + smpt = kmalloc(len, GFP_KERNEL); 884 884 + if (!smpt) 885 885 + return -ENOMEM; 886 886 + 887 887 + addr = SFDP_PARAM_HEADER_PTP(smpt_header); 888 888 + ret = spi_nor_read_sfdp(nor, addr, len, smpt); 889 889 + if (ret) 890 890 + goto out; 891 891 + 892 892 + /* Fix endianness of the SMPT DWORDs. */ 893 893 + le32_to_cpu_array(smpt, smpt_header->length); 894 894 + 895 895 + sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length); 896 896 + if (IS_ERR(sector_map)) { 897 897 + ret = PTR_ERR(sector_map); 898 898 + goto out; 899 899 + } 900 900 + 901 901 + ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map); 902 902 + if (ret) 903 903 + goto out; 904 904 + 905 905 + spi_nor_regions_sort_erase_types(&params->erase_map); 906 906 + /* fall through */ 907 907 + out: 908 908 + kfree(smpt); 909 909 + return ret; 910 910 + } 911 911 + 912 912 + /** 913 913 + * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table 914 914 + * @nor: pointer to a 'struct spi_nor'. 915 915 + * @param_header: pointer to the 'struct sfdp_parameter_header' describing 916 916 + * the 4-Byte Address Instruction Table length and version. 917 917 + * @params: pointer to the 'struct spi_nor_flash_parameter' to be. 918 918 + * 919 919 + * Return: 0 on success, -errno otherwise. 920 920 + */ 921 921 + static int spi_nor_parse_4bait(struct spi_nor *nor, 922 922 + const struct sfdp_parameter_header *param_header, 923 923 + struct spi_nor_flash_parameter *params) 924 924 + { 925 925 + static const struct sfdp_4bait reads[] = { 926 926 + { SNOR_HWCAPS_READ, BIT(0) }, 927 927 + { SNOR_HWCAPS_READ_FAST, BIT(1) }, 928 928 + { SNOR_HWCAPS_READ_1_1_2, BIT(2) }, 929 929 + { SNOR_HWCAPS_READ_1_2_2, BIT(3) }, 930 930 + { SNOR_HWCAPS_READ_1_1_4, BIT(4) }, 931 931 + { SNOR_HWCAPS_READ_1_4_4, BIT(5) }, 932 932 + { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) }, 933 933 + { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) }, 934 934 + { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) }, 935 935 + }; 936 936 + static const struct sfdp_4bait programs[] = { 937 937 + { SNOR_HWCAPS_PP, BIT(6) }, 938 938 + { SNOR_HWCAPS_PP_1_1_4, BIT(7) }, 939 939 + { SNOR_HWCAPS_PP_1_4_4, BIT(8) }, 940 940 + }; 941 941 + static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = { 942 942 + { 0u /* not used */, BIT(9) }, 943 943 + { 0u /* not used */, BIT(10) }, 944 944 + { 0u /* not used */, BIT(11) }, 945 945 + { 0u /* not used */, BIT(12) }, 946 946 + }; 947 947 + struct spi_nor_pp_command *params_pp = params->page_programs; 948 948 + struct spi_nor_erase_map *map = &params->erase_map; 949 949 + struct spi_nor_erase_type *erase_type = map->erase_type; 950 950 + u32 *dwords; 951 951 + size_t len; 952 952 + u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask; 953 953 + int i, ret; 954 954 + 955 955 + if (param_header->major != SFDP_JESD216_MAJOR || 956 956 + param_header->length < SFDP_4BAIT_DWORD_MAX) 957 957 + return -EINVAL; 958 958 + 959 959 + /* Read the 4-byte Address Instruction Table. */ 960 960 + len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX; 961 961 + 962 962 + /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */ 963 963 + dwords = kmalloc(len, GFP_KERNEL); 964 964 + if (!dwords) 965 965 + return -ENOMEM; 966 966 + 967 967 + addr = SFDP_PARAM_HEADER_PTP(param_header); 968 968 + ret = spi_nor_read_sfdp(nor, addr, len, dwords); 969 969 + if (ret) 970 970 + goto out; 971 971 + 972 972 + /* Fix endianness of the 4BAIT DWORDs. */ 973 973 + le32_to_cpu_array(dwords, SFDP_4BAIT_DWORD_MAX); 974 974 + 975 975 + /* 976 976 + * Compute the subset of (Fast) Read commands for which the 4-byte 977 977 + * version is supported. 978 978 + */ 979 979 + discard_hwcaps = 0; 980 980 + read_hwcaps = 0; 981 981 + for (i = 0; i < ARRAY_SIZE(reads); i++) { 982 982 + const struct sfdp_4bait *read = &reads[i]; 983 983 + 984 984 + discard_hwcaps |= read->hwcaps; 985 985 + if ((params->hwcaps.mask & read->hwcaps) && 986 986 + (dwords[0] & read->supported_bit)) 987 987 + read_hwcaps |= read->hwcaps; 988 988 + } 989 989 + 990 990 + /* 991 991 + * Compute the subset of Page Program commands for which the 4-byte 992 992 + * version is supported. 993 993 + */ 994 994 + pp_hwcaps = 0; 995 995 + for (i = 0; i < ARRAY_SIZE(programs); i++) { 996 996 + const struct sfdp_4bait *program = &programs[i]; 997 997 + 998 998 + /* 999 999 + * The 4 Byte Address Instruction (Optional) Table is the only 1000 1000 + * SFDP table that indicates support for Page Program Commands. 1001 1001 + * Bypass the params->hwcaps.mask and consider 4BAIT the biggest 1002 1002 + * authority for specifying Page Program support. 1003 1003 + */ 1004 1004 + discard_hwcaps |= program->hwcaps; 1005 1005 + if (dwords[0] & program->supported_bit) 1006 1006 + pp_hwcaps |= program->hwcaps; 1007 1007 + } 1008 1008 + 1009 1009 + /* 1010 1010 + * Compute the subset of Sector Erase commands for which the 4-byte 1011 1011 + * version is supported. 1012 1012 + */ 1013 1013 + erase_mask = 0; 1014 1014 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1015 1015 + const struct sfdp_4bait *erase = &erases[i]; 1016 1016 + 1017 1017 + if (dwords[0] & erase->supported_bit) 1018 1018 + erase_mask |= BIT(i); 1019 1019 + } 1020 1020 + 1021 1021 + /* Replicate the sort done for the map's erase types in BFPT. */ 1022 1022 + erase_mask = spi_nor_sort_erase_mask(map, erase_mask); 1023 1023 + 1024 1024 + /* 1025 1025 + * We need at least one 4-byte op code per read, program and erase 1026 1026 + * operation; the .read(), .write() and .erase() hooks share the 1027 1027 + * nor->addr_width value. 1028 1028 + */ 1029 1029 + if (!read_hwcaps || !pp_hwcaps || !erase_mask) 1030 1030 + goto out; 1031 1031 + 1032 1032 + /* 1033 1033 + * Discard all operations from the 4-byte instruction set which are 1034 1034 + * not supported by this memory. 1035 1035 + */ 1036 1036 + params->hwcaps.mask &= ~discard_hwcaps; 1037 1037 + params->hwcaps.mask |= (read_hwcaps | pp_hwcaps); 1038 1038 + 1039 1039 + /* Use the 4-byte address instruction set. */ 1040 1040 + for (i = 0; i < SNOR_CMD_READ_MAX; i++) { 1041 1041 + struct spi_nor_read_command *read_cmd = &params->reads[i]; 1042 1042 + 1043 1043 + read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode); 1044 1044 + } 1045 1045 + 1046 1046 + /* 4BAIT is the only SFDP table that indicates page program support. */ 1047 1047 + if (pp_hwcaps & SNOR_HWCAPS_PP) 1048 1048 + spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP], 1049 1049 + SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 1050 1050 + if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4) 1051 1051 + spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_1_4], 1052 1052 + SPINOR_OP_PP_1_1_4_4B, 1053 1053 + SNOR_PROTO_1_1_4); 1054 1054 + if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4) 1055 1055 + spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_4_4], 1056 1056 + SPINOR_OP_PP_1_4_4_4B, 1057 1057 + SNOR_PROTO_1_4_4); 1058 1058 + 1059 1059 + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1060 1060 + if (erase_mask & BIT(i)) 1061 1061 + erase_type[i].opcode = (dwords[1] >> 1062 1062 + erase_type[i].idx * 8) & 0xFF; 1063 1063 + else 1064 1064 + spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF); 1065 1065 + } 1066 1066 + 1067 1067 + /* 1068 1068 + * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes() 1069 1069 + * later because we already did the conversion to 4byte opcodes. Also, 1070 1070 + * this latest function implements a legacy quirk for the erase size of 1071 1071 + * Spansion memory. However this quirk is no longer needed with new 1072 1072 + * SFDP compliant memories. 1073 1073 + */ 1074 1074 + nor->addr_width = 4; 1075 1075 + nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT; 1076 1076 + 1077 1077 + /* fall through */ 1078 1078 + out: 1079 1079 + kfree(dwords); 1080 1080 + return ret; 1081 1081 + } 1082 1082 + 1083 1083 + /** 1084 1084 + * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 1085 1085 + * @nor: pointer to a 'struct spi_nor' 1086 1086 + * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1087 1087 + * filled 1088 1088 + * 1089 1089 + * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 1090 1090 + * specification. This is a standard which tends to supported by almost all 1091 1091 + * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 1092 1092 + * runtime the main parameters needed to perform basic SPI flash operations such 1093 1093 + * as Fast Read, Page Program or Sector Erase commands. 1094 1094 + * 1095 1095 + * Return: 0 on success, -errno otherwise. 1096 1096 + */ 1097 1097 + int spi_nor_parse_sfdp(struct spi_nor *nor, 1098 1098 + struct spi_nor_flash_parameter *params) 1099 1099 + { 1100 1100 + const struct sfdp_parameter_header *param_header, *bfpt_header; 1101 1101 + struct sfdp_parameter_header *param_headers = NULL; 1102 1102 + struct sfdp_header header; 1103 1103 + struct device *dev = nor->dev; 1104 1104 + size_t psize; 1105 1105 + int i, err; 1106 1106 + 1107 1107 + /* Get the SFDP header. */ 1108 1108 + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); 1109 1109 + if (err < 0) 1110 1110 + return err; 1111 1111 + 1112 1112 + /* Check the SFDP header version. */ 1113 1113 + if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 1114 1114 + header.major != SFDP_JESD216_MAJOR) 1115 1115 + return -EINVAL; 1116 1116 + 1117 1117 + /* 1118 1118 + * Verify that the first and only mandatory parameter header is a 1119 1119 + * Basic Flash Parameter Table header as specified in JESD216. 1120 1120 + */ 1121 1121 + bfpt_header = &header.bfpt_header; 1122 1122 + if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 1123 1123 + bfpt_header->major != SFDP_JESD216_MAJOR) 1124 1124 + return -EINVAL; 1125 1125 + 1126 1126 + /* 1127 1127 + * Allocate memory then read all parameter headers with a single 1128 1128 + * Read SFDP command. These parameter headers will actually be parsed 1129 1129 + * twice: a first time to get the latest revision of the basic flash 1130 1130 + * parameter table, then a second time to handle the supported optional 1131 1131 + * tables. 1132 1132 + * Hence we read the parameter headers once for all to reduce the 1133 1133 + * processing time. Also we use kmalloc() instead of devm_kmalloc() 1134 1134 + * because we don't need to keep these parameter headers: the allocated 1135 1135 + * memory is always released with kfree() before exiting this function. 1136 1136 + */ 1137 1137 + if (header.nph) { 1138 1138 + psize = header.nph * sizeof(*param_headers); 1139 1139 + 1140 1140 + param_headers = kmalloc(psize, GFP_KERNEL); 1141 1141 + if (!param_headers) 1142 1142 + return -ENOMEM; 1143 1143 + 1144 1144 + err = spi_nor_read_sfdp(nor, sizeof(header), 1145 1145 + psize, param_headers); 1146 1146 + if (err < 0) { 1147 1147 + dev_dbg(dev, "failed to read SFDP parameter headers\n"); 1148 1148 + goto exit; 1149 1149 + } 1150 1150 + } 1151 1151 + 1152 1152 + /* 1153 1153 + * Check other parameter headers to get the latest revision of 1154 1154 + * the basic flash parameter table. 1155 1155 + */ 1156 1156 + for (i = 0; i < header.nph; i++) { 1157 1157 + param_header = &param_headers[i]; 1158 1158 + 1159 1159 + if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 1160 1160 + param_header->major == SFDP_JESD216_MAJOR && 1161 1161 + (param_header->minor > bfpt_header->minor || 1162 1162 + (param_header->minor == bfpt_header->minor && 1163 1163 + param_header->length > bfpt_header->length))) 1164 1164 + bfpt_header = param_header; 1165 1165 + } 1166 1166 + 1167 1167 + err = spi_nor_parse_bfpt(nor, bfpt_header, params); 1168 1168 + if (err) 1169 1169 + goto exit; 1170 1170 + 1171 1171 + /* Parse optional parameter tables. */ 1172 1172 + for (i = 0; i < header.nph; i++) { 1173 1173 + param_header = &param_headers[i]; 1174 1174 + 1175 1175 + switch (SFDP_PARAM_HEADER_ID(param_header)) { 1176 1176 + case SFDP_SECTOR_MAP_ID: 1177 1177 + err = spi_nor_parse_smpt(nor, param_header, params); 1178 1178 + break; 1179 1179 + 1180 1180 + case SFDP_4BAIT_ID: 1181 1181 + err = spi_nor_parse_4bait(nor, param_header, params); 1182 1182 + break; 1183 1183 + 1184 1184 + default: 1185 1185 + break; 1186 1186 + } 1187 1187 + 1188 1188 + if (err) { 1189 1189 + dev_warn(dev, "Failed to parse optional parameter table: %04x\n", 1190 1190 + SFDP_PARAM_HEADER_ID(param_header)); 1191 1191 + /* 1192 1192 + * Let's not drop all information we extracted so far 1193 1193 + * if optional table parsers fail. In case of failing, 1194 1194 + * each optional parser is responsible to roll back to 1195 1195 + * the previously known spi_nor data. 1196 1196 + */ 1197 1197 + err = 0; 1198 1198 + } 1199 1199 + } 1200 1200 + 1201 1201 + exit: 1202 1202 + kfree(param_headers); 1203 1203 + return err; 1204 1204 + }

+98

drivers/mtd/spi-nor/sfdp.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #ifndef __LINUX_MTD_SFDP_H 8 8 + #define __LINUX_MTD_SFDP_H 9 9 + 10 10 + /* Basic Flash Parameter Table */ 11 11 + 12 12 + /* 13 13 + * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 14 14 + * They are indexed from 1 but C arrays are indexed from 0. 15 15 + */ 16 16 + #define BFPT_DWORD(i) ((i) - 1) 17 17 + #define BFPT_DWORD_MAX 16 18 18 + 19 19 + struct sfdp_bfpt { 20 20 + u32 dwords[BFPT_DWORD_MAX]; 21 21 + }; 22 22 + 23 23 + /* The first version of JESD216 defined only 9 DWORDs. */ 24 24 + #define BFPT_DWORD_MAX_JESD216 9 25 25 + 26 26 + /* 1st DWORD. */ 27 27 + #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 28 28 + #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 29 29 + #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 30 30 + #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 31 31 + #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 32 32 + #define BFPT_DWORD1_DTR BIT(19) 33 33 + #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 34 34 + #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 35 35 + #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 36 36 + 37 37 + /* 5th DWORD. */ 38 38 + #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 39 39 + #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 40 40 + 41 41 + /* 11th DWORD. */ 42 42 + #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 43 43 + #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 44 44 + 45 45 + /* 15th DWORD. */ 46 46 + 47 47 + /* 48 48 + * (from JESD216 rev B) 49 49 + * Quad Enable Requirements (QER): 50 50 + * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 51 51 + * reads based on instruction. DQ3/HOLD# functions are hold during 52 52 + * instruction phase. 53 53 + * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 54 54 + * two data bytes where bit 1 of the second byte is one. 55 55 + * [...] 56 56 + * Writing only one byte to the status register has the side-effect of 57 57 + * clearing status register 2, including the QE bit. The 100b code is 58 58 + * used if writing one byte to the status register does not modify 59 59 + * status register 2. 60 60 + * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 61 61 + * one data byte where bit 6 is one. 62 62 + * [...] 63 63 + * - 011b: QE is bit 7 of status register 2. It is set via Write status 64 64 + * register 2 instruction 3Eh with one data byte where bit 7 is one. 65 65 + * [...] 66 66 + * The status register 2 is read using instruction 3Fh. 67 67 + * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 68 68 + * two data bytes where bit 1 of the second byte is one. 69 69 + * [...] 70 70 + * In contrast to the 001b code, writing one byte to the status 71 71 + * register does not modify status register 2. 72 72 + * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 73 73 + * Read Status instruction 05h. Status register2 is read using 74 74 + * instruction 35h. QE is set via Write Status instruction 01h with 75 75 + * two data bytes where bit 1 of the second byte is one. 76 76 + * [...] 77 77 + */ 78 78 + #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 79 79 + #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 80 80 + #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 81 81 + #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 82 82 + #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 83 83 + #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 84 84 + #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 85 85 + 86 86 + struct sfdp_parameter_header { 87 87 + u8 id_lsb; 88 88 + u8 minor; 89 89 + u8 major; 90 90 + u8 length; /* in double words */ 91 91 + u8 parameter_table_pointer[3]; /* byte address */ 92 92 + u8 id_msb; 93 93 + }; 94 94 + 95 95 + int spi_nor_parse_sfdp(struct spi_nor *nor, 96 96 + struct spi_nor_flash_parameter *params); 97 97 + 98 98 + #endif /* __LINUX_MTD_SFDP_H */

+95

drivers/mtd/spi-nor/spansion.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info spansion_parts[] = { 12 12 + /* Spansion/Cypress -- single (large) sector size only, at least 13 13 + * for the chips listed here (without boot sectors). 14 14 + */ 15 15 + { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 16 16 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 17 17 + { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 18 18 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 19 19 + { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, 20 20 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 21 21 + USE_CLSR) }, 22 22 + { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, 23 23 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 24 24 + USE_CLSR) }, 25 25 + { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 26 26 + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 27 27 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 28 28 + USE_CLSR) }, 29 29 + { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, 30 30 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 31 31 + SPI_NOR_HAS_LOCK | USE_CLSR) }, 32 32 + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, 33 33 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 34 34 + USE_CLSR) }, 35 35 + { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, 36 36 + { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 37 37 + { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 38 38 + { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 39 39 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 40 40 + USE_CLSR) }, 41 41 + { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 42 42 + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 43 43 + USE_CLSR) }, 44 44 + { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, 45 45 + { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 46 46 + { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 47 47 + { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 48 48 + { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 49 49 + { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, 50 50 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 51 51 + { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, 52 52 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 53 53 + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, 54 54 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 55 55 + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 56 56 + { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, 57 57 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 58 58 + { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, 59 59 + { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 60 60 + { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, 61 61 + SECT_4K | SPI_NOR_DUAL_READ) }, 62 62 + { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, 63 63 + SECT_4K | SPI_NOR_DUAL_READ) }, 64 64 + { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, 65 65 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 66 66 + SPI_NOR_4B_OPCODES) }, 67 67 + { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, 68 68 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 69 69 + SPI_NOR_4B_OPCODES) }, 70 70 + { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, 71 71 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 72 72 + SPI_NOR_4B_OPCODES) }, 73 73 + }; 74 74 + 75 75 + static void spansion_post_sfdp_fixups(struct spi_nor *nor) 76 76 + { 77 77 + if (nor->params->size <= SZ_16M) 78 78 + return; 79 79 + 80 80 + nor->flags |= SNOR_F_4B_OPCODES; 81 81 + /* No small sector erase for 4-byte command set */ 82 82 + nor->erase_opcode = SPINOR_OP_SE; 83 83 + nor->mtd.erasesize = nor->info->sector_size; 84 84 + } 85 85 + 86 86 + static const struct spi_nor_fixups spansion_fixups = { 87 87 + .post_sfdp = spansion_post_sfdp_fixups, 88 88 + }; 89 89 + 90 90 + const struct spi_nor_manufacturer spi_nor_spansion = { 91 91 + .name = "spansion", 92 92 + .parts = spansion_parts, 93 93 + .nparts = ARRAY_SIZE(spansion_parts), 94 94 + .fixups = &spansion_fixups, 95 95 + };

-5434

drivers/mtd/spi-nor/spi-nor.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 2 2 - /* 3 3 - * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 4 - * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 5 - * 6 6 - * Copyright (C) 2005, Intec Automation Inc. 7 7 - * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 8 - */ 9 9 - 10 10 - #include <linux/err.h> 11 11 - #include <linux/errno.h> 12 12 - #include <linux/module.h> 13 13 - #include <linux/device.h> 14 14 - #include <linux/mutex.h> 15 15 - #include <linux/math64.h> 16 16 - #include <linux/sizes.h> 17 17 - #include <linux/slab.h> 18 18 - #include <linux/sort.h> 19 19 - 20 20 - #include <linux/mtd/mtd.h> 21 21 - #include <linux/of_platform.h> 22 22 - #include <linux/sched/task_stack.h> 23 23 - #include <linux/spi/flash.h> 24 24 - #include <linux/mtd/spi-nor.h> 25 25 - 26 26 - /* Define max times to check status register before we give up. */ 27 27 - 28 28 - /* 29 29 - * For everything but full-chip erase; probably could be much smaller, but kept 30 30 - * around for safety for now 31 31 - */ 32 32 - #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 33 33 - 34 34 - /* 35 35 - * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 36 36 - * for larger flash 37 37 - */ 38 38 - #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 39 39 - 40 40 - #define SPI_NOR_MAX_ID_LEN 6 41 41 - #define SPI_NOR_MAX_ADDR_WIDTH 4 42 42 - 43 43 - struct sfdp_parameter_header { 44 44 - u8 id_lsb; 45 45 - u8 minor; 46 46 - u8 major; 47 47 - u8 length; /* in double words */ 48 48 - u8 parameter_table_pointer[3]; /* byte address */ 49 49 - u8 id_msb; 50 50 - }; 51 51 - 52 52 - #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 53 53 - #define SFDP_PARAM_HEADER_PTP(p) \ 54 54 - (((p)->parameter_table_pointer[2] << 16) | \ 55 55 - ((p)->parameter_table_pointer[1] << 8) | \ 56 56 - ((p)->parameter_table_pointer[0] << 0)) 57 57 - 58 58 - #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 59 59 - #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 60 60 - #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */ 61 61 - 62 62 - #define SFDP_SIGNATURE 0x50444653U 63 63 - #define SFDP_JESD216_MAJOR 1 64 64 - #define SFDP_JESD216_MINOR 0 65 65 - #define SFDP_JESD216A_MINOR 5 66 66 - #define SFDP_JESD216B_MINOR 6 67 67 - 68 68 - struct sfdp_header { 69 69 - u32 signature; /* Ox50444653U <=> "SFDP" */ 70 70 - u8 minor; 71 71 - u8 major; 72 72 - u8 nph; /* 0-base number of parameter headers */ 73 73 - u8 unused; 74 74 - 75 75 - /* Basic Flash Parameter Table. */ 76 76 - struct sfdp_parameter_header bfpt_header; 77 77 - }; 78 78 - 79 79 - /* Basic Flash Parameter Table */ 80 80 - 81 81 - /* 82 82 - * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 83 83 - * They are indexed from 1 but C arrays are indexed from 0. 84 84 - */ 85 85 - #define BFPT_DWORD(i) ((i) - 1) 86 86 - #define BFPT_DWORD_MAX 16 87 87 - 88 88 - /* The first version of JESD216 defined only 9 DWORDs. */ 89 89 - #define BFPT_DWORD_MAX_JESD216 9 90 90 - 91 91 - /* 1st DWORD. */ 92 92 - #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 93 93 - #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 94 94 - #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 95 95 - #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 96 96 - #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 97 97 - #define BFPT_DWORD1_DTR BIT(19) 98 98 - #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 99 99 - #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 100 100 - #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 101 101 - 102 102 - /* 5th DWORD. */ 103 103 - #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 104 104 - #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 105 105 - 106 106 - /* 11th DWORD. */ 107 107 - #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 108 108 - #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 109 109 - 110 110 - /* 15th DWORD. */ 111 111 - 112 112 - /* 113 113 - * (from JESD216 rev B) 114 114 - * Quad Enable Requirements (QER): 115 115 - * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 116 116 - * reads based on instruction. DQ3/HOLD# functions are hold during 117 117 - * instruction phase. 118 118 - * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 119 119 - * two data bytes where bit 1 of the second byte is one. 120 120 - * [...] 121 121 - * Writing only one byte to the status register has the side-effect of 122 122 - * clearing status register 2, including the QE bit. The 100b code is 123 123 - * used if writing one byte to the status register does not modify 124 124 - * status register 2. 125 125 - * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 126 126 - * one data byte where bit 6 is one. 127 127 - * [...] 128 128 - * - 011b: QE is bit 7 of status register 2. It is set via Write status 129 129 - * register 2 instruction 3Eh with one data byte where bit 7 is one. 130 130 - * [...] 131 131 - * The status register 2 is read using instruction 3Fh. 132 132 - * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 133 133 - * two data bytes where bit 1 of the second byte is one. 134 134 - * [...] 135 135 - * In contrast to the 001b code, writing one byte to the status 136 136 - * register does not modify status register 2. 137 137 - * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 138 138 - * Read Status instruction 05h. Status register2 is read using 139 139 - * instruction 35h. QE is set via Write Status instruction 01h with 140 140 - * two data bytes where bit 1 of the second byte is one. 141 141 - * [...] 142 142 - */ 143 143 - #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 144 144 - #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 145 145 - #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 146 146 - #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 147 147 - #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 148 148 - #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 149 149 - #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 150 150 - 151 151 - struct sfdp_bfpt { 152 152 - u32 dwords[BFPT_DWORD_MAX]; 153 153 - }; 154 154 - 155 155 - /** 156 156 - * struct spi_nor_fixups - SPI NOR fixup hooks 157 157 - * @default_init: called after default flash parameters init. Used to tweak 158 158 - * flash parameters when information provided by the flash_info 159 159 - * table is incomplete or wrong. 160 160 - * @post_bfpt: called after the BFPT table has been parsed 161 161 - * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs 162 162 - * that do not support RDSFDP). Typically used to tweak various 163 163 - * parameters that could not be extracted by other means (i.e. 164 164 - * when information provided by the SFDP/flash_info tables are 165 165 - * incomplete or wrong). 166 166 - * 167 167 - * Those hooks can be used to tweak the SPI NOR configuration when the SFDP 168 168 - * table is broken or not available. 169 169 - */ 170 170 - struct spi_nor_fixups { 171 171 - void (*default_init)(struct spi_nor *nor); 172 172 - int (*post_bfpt)(struct spi_nor *nor, 173 173 - const struct sfdp_parameter_header *bfpt_header, 174 174 - const struct sfdp_bfpt *bfpt, 175 175 - struct spi_nor_flash_parameter *params); 176 176 - void (*post_sfdp)(struct spi_nor *nor); 177 177 - }; 178 178 - 179 179 - struct flash_info { 180 180 - char *name; 181 181 - 182 182 - /* 183 183 - * This array stores the ID bytes. 184 184 - * The first three bytes are the JEDIC ID. 185 185 - * JEDEC ID zero means "no ID" (mostly older chips). 186 186 - */ 187 187 - u8 id[SPI_NOR_MAX_ID_LEN]; 188 188 - u8 id_len; 189 189 - 190 190 - /* The size listed here is what works with SPINOR_OP_SE, which isn't 191 191 - * necessarily called a "sector" by the vendor. 192 192 - */ 193 193 - unsigned sector_size; 194 194 - u16 n_sectors; 195 195 - 196 196 - u16 page_size; 197 197 - u16 addr_width; 198 198 - 199 199 - u32 flags; 200 200 - #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 201 201 - #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 202 202 - #define SST_WRITE BIT(2) /* use SST byte programming */ 203 203 - #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 204 204 - #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 205 205 - #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 206 206 - #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 207 207 - #define USE_FSR BIT(7) /* use flag status register */ 208 208 - #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 209 209 - #define SPI_NOR_HAS_TB BIT(9) /* 210 210 - * Flash SR has Top/Bottom (TB) protect 211 211 - * bit. Must be used with 212 212 - * SPI_NOR_HAS_LOCK. 213 213 - */ 214 214 - #define SPI_NOR_XSR_RDY BIT(10) /* 215 215 - * S3AN flashes have specific opcode to 216 216 - * read the status register. 217 217 - * Flags SPI_NOR_XSR_RDY and SPI_S3AN 218 218 - * use the same bit as one implies the 219 219 - * other, but we will get rid of 220 220 - * SPI_S3AN soon. 221 221 - */ 222 222 - #define SPI_S3AN BIT(10) /* 223 223 - * Xilinx Spartan 3AN In-System Flash 224 224 - * (MFR cannot be used for probing 225 225 - * because it has the same value as 226 226 - * ATMEL flashes) 227 227 - */ 228 228 - #define SPI_NOR_4B_OPCODES BIT(11) /* 229 229 - * Use dedicated 4byte address op codes 230 230 - * to support memory size above 128Mib. 231 231 - */ 232 232 - #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 233 233 - #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 234 234 - #define USE_CLSR BIT(14) /* use CLSR command */ 235 235 - #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ 236 236 - #define SPI_NOR_TB_SR_BIT6 BIT(16) /* 237 237 - * Top/Bottom (TB) is bit 6 of 238 238 - * status register. Must be used with 239 239 - * SPI_NOR_HAS_TB. 240 240 - */ 241 241 - 242 242 - /* Part specific fixup hooks. */ 243 243 - const struct spi_nor_fixups *fixups; 244 244 - }; 245 245 - 246 246 - #define JEDEC_MFR(info) ((info)->id[0]) 247 247 - 248 248 - /** 249 249 - * spi_nor_spimem_xfer_data() - helper function to read/write data to 250 250 - * flash's memory region 251 251 - * @nor: pointer to 'struct spi_nor' 252 252 - * @op: pointer to 'struct spi_mem_op' template for transfer 253 253 - * 254 254 - * Return: number of bytes transferred on success, -errno otherwise 255 255 - */ 256 256 - static ssize_t spi_nor_spimem_xfer_data(struct spi_nor *nor, 257 257 - struct spi_mem_op *op) 258 258 - { 259 259 - bool usebouncebuf = false; 260 260 - void *rdbuf = NULL; 261 261 - const void *buf; 262 262 - int ret; 263 263 - 264 264 - if (op->data.dir == SPI_MEM_DATA_IN) 265 265 - buf = op->data.buf.in; 266 266 - else 267 267 - buf = op->data.buf.out; 268 268 - 269 269 - if (object_is_on_stack(buf) || !virt_addr_valid(buf)) 270 270 - usebouncebuf = true; 271 271 - 272 272 - if (usebouncebuf) { 273 273 - if (op->data.nbytes > nor->bouncebuf_size) 274 274 - op->data.nbytes = nor->bouncebuf_size; 275 275 - 276 276 - if (op->data.dir == SPI_MEM_DATA_IN) { 277 277 - rdbuf = op->data.buf.in; 278 278 - op->data.buf.in = nor->bouncebuf; 279 279 - } else { 280 280 - op->data.buf.out = nor->bouncebuf; 281 281 - memcpy(nor->bouncebuf, buf, 282 282 - op->data.nbytes); 283 283 - } 284 284 - } 285 285 - 286 286 - ret = spi_mem_adjust_op_size(nor->spimem, op); 287 287 - if (ret) 288 288 - return ret; 289 289 - 290 290 - ret = spi_mem_exec_op(nor->spimem, op); 291 291 - if (ret) 292 292 - return ret; 293 293 - 294 294 - if (usebouncebuf && op->data.dir == SPI_MEM_DATA_IN) 295 295 - memcpy(rdbuf, nor->bouncebuf, op->data.nbytes); 296 296 - 297 297 - return op->data.nbytes; 298 298 - } 299 299 - 300 300 - /** 301 301 - * spi_nor_spimem_read_data() - read data from flash's memory region via 302 302 - * spi-mem 303 303 - * @nor: pointer to 'struct spi_nor' 304 304 - * @from: offset to read from 305 305 - * @len: number of bytes to read 306 306 - * @buf: pointer to dst buffer 307 307 - * 308 308 - * Return: number of bytes read successfully, -errno otherwise 309 309 - */ 310 310 - static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 311 311 - size_t len, u8 *buf) 312 312 - { 313 313 - struct spi_mem_op op = 314 314 - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 315 315 - SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 316 316 - SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 317 317 - SPI_MEM_OP_DATA_IN(len, buf, 1)); 318 318 - 319 319 - /* get transfer protocols. */ 320 320 - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 321 321 - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 322 322 - op.dummy.buswidth = op.addr.buswidth; 323 323 - op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 324 324 - 325 325 - /* convert the dummy cycles to the number of bytes */ 326 326 - op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 327 327 - 328 328 - return spi_nor_spimem_xfer_data(nor, &op); 329 329 - } 330 330 - 331 331 - /** 332 332 - * spi_nor_read_data() - read data from flash memory 333 333 - * @nor: pointer to 'struct spi_nor' 334 334 - * @from: offset to read from 335 335 - * @len: number of bytes to read 336 336 - * @buf: pointer to dst buffer 337 337 - * 338 338 - * Return: number of bytes read successfully, -errno otherwise 339 339 - */ 340 340 - static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 341 341 - u8 *buf) 342 342 - { 343 343 - if (nor->spimem) 344 344 - return spi_nor_spimem_read_data(nor, from, len, buf); 345 345 - 346 346 - return nor->controller_ops->read(nor, from, len, buf); 347 347 - } 348 348 - 349 349 - /** 350 350 - * spi_nor_spimem_write_data() - write data to flash memory via 351 351 - * spi-mem 352 352 - * @nor: pointer to 'struct spi_nor' 353 353 - * @to: offset to write to 354 354 - * @len: number of bytes to write 355 355 - * @buf: pointer to src buffer 356 356 - * 357 357 - * Return: number of bytes written successfully, -errno otherwise 358 358 - */ 359 359 - static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 360 360 - size_t len, const u8 *buf) 361 361 - { 362 362 - struct spi_mem_op op = 363 363 - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 364 364 - SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 365 365 - SPI_MEM_OP_NO_DUMMY, 366 366 - SPI_MEM_OP_DATA_OUT(len, buf, 1)); 367 367 - 368 368 - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 369 369 - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 370 370 - op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 371 371 - 372 372 - if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 373 373 - op.addr.nbytes = 0; 374 374 - 375 375 - return spi_nor_spimem_xfer_data(nor, &op); 376 376 - } 377 377 - 378 378 - /** 379 379 - * spi_nor_write_data() - write data to flash memory 380 380 - * @nor: pointer to 'struct spi_nor' 381 381 - * @to: offset to write to 382 382 - * @len: number of bytes to write 383 383 - * @buf: pointer to src buffer 384 384 - * 385 385 - * Return: number of bytes written successfully, -errno otherwise 386 386 - */ 387 387 - static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 388 388 - const u8 *buf) 389 389 - { 390 390 - if (nor->spimem) 391 391 - return spi_nor_spimem_write_data(nor, to, len, buf); 392 392 - 393 393 - return nor->controller_ops->write(nor, to, len, buf); 394 394 - } 395 395 - 396 396 - /** 397 397 - * spi_nor_write_enable() - Set write enable latch with Write Enable command. 398 398 - * @nor: pointer to 'struct spi_nor'. 399 399 - * 400 400 - * Return: 0 on success, -errno otherwise. 401 401 - */ 402 402 - static int spi_nor_write_enable(struct spi_nor *nor) 403 403 - { 404 404 - int ret; 405 405 - 406 406 - if (nor->spimem) { 407 407 - struct spi_mem_op op = 408 408 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), 409 409 - SPI_MEM_OP_NO_ADDR, 410 410 - SPI_MEM_OP_NO_DUMMY, 411 411 - SPI_MEM_OP_NO_DATA); 412 412 - 413 413 - ret = spi_mem_exec_op(nor->spimem, &op); 414 414 - } else { 415 415 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, 416 416 - NULL, 0); 417 417 - } 418 418 - 419 419 - if (ret) 420 420 - dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 421 421 - 422 422 - return ret; 423 423 - } 424 424 - 425 425 - /** 426 426 - * spi_nor_write_disable() - Send Write Disable instruction to the chip. 427 427 - * @nor: pointer to 'struct spi_nor'. 428 428 - * 429 429 - * Return: 0 on success, -errno otherwise. 430 430 - */ 431 431 - static int spi_nor_write_disable(struct spi_nor *nor) 432 432 - { 433 433 - int ret; 434 434 - 435 435 - if (nor->spimem) { 436 436 - struct spi_mem_op op = 437 437 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), 438 438 - SPI_MEM_OP_NO_ADDR, 439 439 - SPI_MEM_OP_NO_DUMMY, 440 440 - SPI_MEM_OP_NO_DATA); 441 441 - 442 442 - ret = spi_mem_exec_op(nor->spimem, &op); 443 443 - } else { 444 444 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, 445 445 - NULL, 0); 446 446 - } 447 447 - 448 448 - if (ret) 449 449 - dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 450 450 - 451 451 - return ret; 452 452 - } 453 453 - 454 454 - /** 455 455 - * spi_nor_read_sr() - Read the Status Register. 456 456 - * @nor: pointer to 'struct spi_nor'. 457 457 - * @sr: pointer to a DMA-able buffer where the value of the 458 458 - * Status Register will be written. 459 459 - * 460 460 - * Return: 0 on success, -errno otherwise. 461 461 - */ 462 462 - static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 463 463 - { 464 464 - int ret; 465 465 - 466 466 - if (nor->spimem) { 467 467 - struct spi_mem_op op = 468 468 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), 469 469 - SPI_MEM_OP_NO_ADDR, 470 470 - SPI_MEM_OP_NO_DUMMY, 471 471 - SPI_MEM_OP_DATA_IN(1, sr, 1)); 472 472 - 473 473 - ret = spi_mem_exec_op(nor->spimem, &op); 474 474 - } else { 475 475 - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, 476 476 - sr, 1); 477 477 - } 478 478 - 479 479 - if (ret) 480 480 - dev_dbg(nor->dev, "error %d reading SR\n", ret); 481 481 - 482 482 - return ret; 483 483 - } 484 484 - 485 485 - /** 486 486 - * spi_nor_read_fsr() - Read the Flag Status Register. 487 487 - * @nor: pointer to 'struct spi_nor' 488 488 - * @fsr: pointer to a DMA-able buffer where the value of the 489 489 - * Flag Status Register will be written. 490 490 - * 491 491 - * Return: 0 on success, -errno otherwise. 492 492 - */ 493 493 - static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 494 494 - { 495 495 - int ret; 496 496 - 497 497 - if (nor->spimem) { 498 498 - struct spi_mem_op op = 499 499 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1), 500 500 - SPI_MEM_OP_NO_ADDR, 501 501 - SPI_MEM_OP_NO_DUMMY, 502 502 - SPI_MEM_OP_DATA_IN(1, fsr, 1)); 503 503 - 504 504 - ret = spi_mem_exec_op(nor->spimem, &op); 505 505 - } else { 506 506 - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR, 507 507 - fsr, 1); 508 508 - } 509 509 - 510 510 - if (ret) 511 511 - dev_dbg(nor->dev, "error %d reading FSR\n", ret); 512 512 - 513 513 - return ret; 514 514 - } 515 515 - 516 516 - /** 517 517 - * spi_nor_read_cr() - Read the Configuration Register using the 518 518 - * SPINOR_OP_RDCR (35h) command. 519 519 - * @nor: pointer to 'struct spi_nor' 520 520 - * @cr: pointer to a DMA-able buffer where the value of the 521 521 - * Configuration Register will be written. 522 522 - * 523 523 - * Return: 0 on success, -errno otherwise. 524 524 - */ 525 525 - static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 526 526 - { 527 527 - int ret; 528 528 - 529 529 - if (nor->spimem) { 530 530 - struct spi_mem_op op = 531 531 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1), 532 532 - SPI_MEM_OP_NO_ADDR, 533 533 - SPI_MEM_OP_NO_DUMMY, 534 534 - SPI_MEM_OP_DATA_IN(1, cr, 1)); 535 535 - 536 536 - ret = spi_mem_exec_op(nor->spimem, &op); 537 537 - } else { 538 538 - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1); 539 539 - } 540 540 - 541 541 - if (ret) 542 542 - dev_dbg(nor->dev, "error %d reading CR\n", ret); 543 543 - 544 544 - return ret; 545 545 - } 546 546 - 547 547 - /** 548 548 - * macronix_set_4byte() - Set 4-byte address mode for Macronix flashes. 549 549 - * @nor: pointer to 'struct spi_nor'. 550 550 - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 551 551 - * address mode. 552 552 - * 553 553 - * Return: 0 on success, -errno otherwise. 554 554 - */ 555 555 - static int macronix_set_4byte(struct spi_nor *nor, bool enable) 556 556 - { 557 557 - int ret; 558 558 - 559 559 - if (nor->spimem) { 560 560 - struct spi_mem_op op = 561 561 - SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? 562 562 - SPINOR_OP_EN4B : 563 563 - SPINOR_OP_EX4B, 564 564 - 1), 565 565 - SPI_MEM_OP_NO_ADDR, 566 566 - SPI_MEM_OP_NO_DUMMY, 567 567 - SPI_MEM_OP_NO_DATA); 568 568 - 569 569 - ret = spi_mem_exec_op(nor->spimem, &op); 570 570 - } else { 571 571 - ret = nor->controller_ops->write_reg(nor, 572 572 - enable ? SPINOR_OP_EN4B : 573 573 - SPINOR_OP_EX4B, 574 574 - NULL, 0); 575 575 - } 576 576 - 577 577 - if (ret) 578 578 - dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 579 579 - 580 580 - return ret; 581 581 - } 582 582 - 583 583 - /** 584 584 - * st_micron_set_4byte() - Set 4-byte address mode for ST and Micron flashes. 585 585 - * @nor: pointer to 'struct spi_nor'. 586 586 - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 587 587 - * address mode. 588 588 - * 589 589 - * Return: 0 on success, -errno otherwise. 590 590 - */ 591 591 - static int st_micron_set_4byte(struct spi_nor *nor, bool enable) 592 592 - { 593 593 - int ret; 594 594 - 595 595 - ret = spi_nor_write_enable(nor); 596 596 - if (ret) 597 597 - return ret; 598 598 - 599 599 - ret = macronix_set_4byte(nor, enable); 600 600 - if (ret) 601 601 - return ret; 602 602 - 603 603 - return spi_nor_write_disable(nor); 604 604 - } 605 605 - 606 606 - /** 607 607 - * spansion_set_4byte() - Set 4-byte address mode for Spansion flashes. 608 608 - * @nor: pointer to 'struct spi_nor'. 609 609 - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 610 610 - * address mode. 611 611 - * 612 612 - * Return: 0 on success, -errno otherwise. 613 613 - */ 614 614 - static int spansion_set_4byte(struct spi_nor *nor, bool enable) 615 615 - { 616 616 - int ret; 617 617 - 618 618 - nor->bouncebuf[0] = enable << 7; 619 619 - 620 620 - if (nor->spimem) { 621 621 - struct spi_mem_op op = 622 622 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1), 623 623 - SPI_MEM_OP_NO_ADDR, 624 624 - SPI_MEM_OP_NO_DUMMY, 625 625 - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); 626 626 - 627 627 - ret = spi_mem_exec_op(nor->spimem, &op); 628 628 - } else { 629 629 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, 630 630 - nor->bouncebuf, 1); 631 631 - } 632 632 - 633 633 - if (ret) 634 634 - dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 635 635 - 636 636 - return ret; 637 637 - } 638 638 - 639 639 - /** 640 640 - * spi_nor_write_ear() - Write Extended Address Register. 641 641 - * @nor: pointer to 'struct spi_nor'. 642 642 - * @ear: value to write to the Extended Address Register. 643 643 - * 644 644 - * Return: 0 on success, -errno otherwise. 645 645 - */ 646 646 - static int spi_nor_write_ear(struct spi_nor *nor, u8 ear) 647 647 - { 648 648 - int ret; 649 649 - 650 650 - nor->bouncebuf[0] = ear; 651 651 - 652 652 - if (nor->spimem) { 653 653 - struct spi_mem_op op = 654 654 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1), 655 655 - SPI_MEM_OP_NO_ADDR, 656 656 - SPI_MEM_OP_NO_DUMMY, 657 657 - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); 658 658 - 659 659 - ret = spi_mem_exec_op(nor->spimem, &op); 660 660 - } else { 661 661 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, 662 662 - nor->bouncebuf, 1); 663 663 - } 664 664 - 665 665 - if (ret) 666 666 - dev_dbg(nor->dev, "error %d writing EAR\n", ret); 667 667 - 668 668 - return ret; 669 669 - } 670 670 - 671 671 - /** 672 672 - * winbond_set_4byte() - Set 4-byte address mode for Winbond flashes. 673 673 - * @nor: pointer to 'struct spi_nor'. 674 674 - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 675 675 - * address mode. 676 676 - * 677 677 - * Return: 0 on success, -errno otherwise. 678 678 - */ 679 679 - static int winbond_set_4byte(struct spi_nor *nor, bool enable) 680 680 - { 681 681 - int ret; 682 682 - 683 683 - ret = macronix_set_4byte(nor, enable); 684 684 - if (ret || enable) 685 685 - return ret; 686 686 - 687 687 - /* 688 688 - * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address 689 689 - * Register to be set to 1, so all 3-byte-address reads come from the 690 690 - * second 16M. We must clear the register to enable normal behavior. 691 691 - */ 692 692 - ret = spi_nor_write_enable(nor); 693 693 - if (ret) 694 694 - return ret; 695 695 - 696 696 - ret = spi_nor_write_ear(nor, 0); 697 697 - if (ret) 698 698 - return ret; 699 699 - 700 700 - return spi_nor_write_disable(nor); 701 701 - } 702 702 - 703 703 - /** 704 704 - * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. 705 705 - * @nor: pointer to 'struct spi_nor'. 706 706 - * @sr: pointer to a DMA-able buffer where the value of the 707 707 - * Status Register will be written. 708 708 - * 709 709 - * Return: 0 on success, -errno otherwise. 710 710 - */ 711 711 - static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) 712 712 - { 713 713 - int ret; 714 714 - 715 715 - if (nor->spimem) { 716 716 - struct spi_mem_op op = 717 717 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1), 718 718 - SPI_MEM_OP_NO_ADDR, 719 719 - SPI_MEM_OP_NO_DUMMY, 720 720 - SPI_MEM_OP_DATA_IN(1, sr, 1)); 721 721 - 722 722 - ret = spi_mem_exec_op(nor->spimem, &op); 723 723 - } else { 724 724 - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, 725 725 - sr, 1); 726 726 - } 727 727 - 728 728 - if (ret) 729 729 - dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); 730 730 - 731 731 - return ret; 732 732 - } 733 733 - 734 734 - /** 735 735 - * s3an_sr_ready() - Query the Status Register of the S3AN flash to see if the 736 736 - * flash is ready for new commands. 737 737 - * @nor: pointer to 'struct spi_nor'. 738 738 - * 739 739 - * Return: 0 on success, -errno otherwise. 740 740 - */ 741 741 - static int s3an_sr_ready(struct spi_nor *nor) 742 742 - { 743 743 - int ret; 744 744 - 745 745 - ret = spi_nor_xread_sr(nor, nor->bouncebuf); 746 746 - if (ret) 747 747 - return ret; 748 748 - 749 749 - return !!(nor->bouncebuf[0] & XSR_RDY); 750 750 - } 751 751 - 752 752 - /** 753 753 - * spi_nor_clear_sr() - Clear the Status Register. 754 754 - * @nor: pointer to 'struct spi_nor'. 755 755 - */ 756 756 - static void spi_nor_clear_sr(struct spi_nor *nor) 757 757 - { 758 758 - int ret; 759 759 - 760 760 - if (nor->spimem) { 761 761 - struct spi_mem_op op = 762 762 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1), 763 763 - SPI_MEM_OP_NO_ADDR, 764 764 - SPI_MEM_OP_NO_DUMMY, 765 765 - SPI_MEM_OP_NO_DATA); 766 766 - 767 767 - ret = spi_mem_exec_op(nor->spimem, &op); 768 768 - } else { 769 769 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, 770 770 - NULL, 0); 771 771 - } 772 772 - 773 773 - if (ret) 774 774 - dev_dbg(nor->dev, "error %d clearing SR\n", ret); 775 775 - } 776 776 - 777 777 - /** 778 778 - * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 779 779 - * for new commands. 780 780 - * @nor: pointer to 'struct spi_nor'. 781 781 - * 782 782 - * Return: 0 on success, -errno otherwise. 783 783 - */ 784 784 - static int spi_nor_sr_ready(struct spi_nor *nor) 785 785 - { 786 786 - int ret = spi_nor_read_sr(nor, nor->bouncebuf); 787 787 - 788 788 - if (ret) 789 789 - return ret; 790 790 - 791 791 - if (nor->flags & SNOR_F_USE_CLSR && 792 792 - nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 793 793 - if (nor->bouncebuf[0] & SR_E_ERR) 794 794 - dev_err(nor->dev, "Erase Error occurred\n"); 795 795 - else 796 796 - dev_err(nor->dev, "Programming Error occurred\n"); 797 797 - 798 798 - spi_nor_clear_sr(nor); 799 799 - return -EIO; 800 800 - } 801 801 - 802 802 - return !(nor->bouncebuf[0] & SR_WIP); 803 803 - } 804 804 - 805 805 - /** 806 806 - * spi_nor_clear_fsr() - Clear the Flag Status Register. 807 807 - * @nor: pointer to 'struct spi_nor'. 808 808 - */ 809 809 - static void spi_nor_clear_fsr(struct spi_nor *nor) 810 810 - { 811 811 - int ret; 812 812 - 813 813 - if (nor->spimem) { 814 814 - struct spi_mem_op op = 815 815 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1), 816 816 - SPI_MEM_OP_NO_ADDR, 817 817 - SPI_MEM_OP_NO_DUMMY, 818 818 - SPI_MEM_OP_NO_DATA); 819 819 - 820 820 - ret = spi_mem_exec_op(nor->spimem, &op); 821 821 - } else { 822 822 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, 823 823 - NULL, 0); 824 824 - } 825 825 - 826 826 - if (ret) 827 827 - dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 828 828 - } 829 829 - 830 830 - /** 831 831 - * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is 832 832 - * ready for new commands. 833 833 - * @nor: pointer to 'struct spi_nor'. 834 834 - * 835 835 - * Return: 0 on success, -errno otherwise. 836 836 - */ 837 837 - static int spi_nor_fsr_ready(struct spi_nor *nor) 838 838 - { 839 839 - int ret = spi_nor_read_fsr(nor, nor->bouncebuf); 840 840 - 841 841 - if (ret) 842 842 - return ret; 843 843 - 844 844 - if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 845 845 - if (nor->bouncebuf[0] & FSR_E_ERR) 846 846 - dev_err(nor->dev, "Erase operation failed.\n"); 847 847 - else 848 848 - dev_err(nor->dev, "Program operation failed.\n"); 849 849 - 850 850 - if (nor->bouncebuf[0] & FSR_PT_ERR) 851 851 - dev_err(nor->dev, 852 852 - "Attempted to modify a protected sector.\n"); 853 853 - 854 854 - spi_nor_clear_fsr(nor); 855 855 - return -EIO; 856 856 - } 857 857 - 858 858 - return nor->bouncebuf[0] & FSR_READY; 859 859 - } 860 860 - 861 861 - /** 862 862 - * spi_nor_ready() - Query the flash to see if it is ready for new commands. 863 863 - * @nor: pointer to 'struct spi_nor'. 864 864 - * 865 865 - * Return: 0 on success, -errno otherwise. 866 866 - */ 867 867 - static int spi_nor_ready(struct spi_nor *nor) 868 868 - { 869 869 - int sr, fsr; 870 870 - 871 871 - if (nor->flags & SNOR_F_READY_XSR_RDY) 872 872 - sr = s3an_sr_ready(nor); 873 873 - else 874 874 - sr = spi_nor_sr_ready(nor); 875 875 - if (sr < 0) 876 876 - return sr; 877 877 - fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 878 878 - if (fsr < 0) 879 879 - return fsr; 880 880 - return sr && fsr; 881 881 - } 882 882 - 883 883 - /** 884 884 - * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 885 885 - * Status Register until ready, or timeout occurs. 886 886 - * @nor: pointer to "struct spi_nor". 887 887 - * @timeout_jiffies: jiffies to wait until timeout. 888 888 - * 889 889 - * Return: 0 on success, -errno otherwise. 890 890 - */ 891 891 - static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 892 892 - unsigned long timeout_jiffies) 893 893 - { 894 894 - unsigned long deadline; 895 895 - int timeout = 0, ret; 896 896 - 897 897 - deadline = jiffies + timeout_jiffies; 898 898 - 899 899 - while (!timeout) { 900 900 - if (time_after_eq(jiffies, deadline)) 901 901 - timeout = 1; 902 902 - 903 903 - ret = spi_nor_ready(nor); 904 904 - if (ret < 0) 905 905 - return ret; 906 906 - if (ret) 907 907 - return 0; 908 908 - 909 909 - cond_resched(); 910 910 - } 911 911 - 912 912 - dev_dbg(nor->dev, "flash operation timed out\n"); 913 913 - 914 914 - return -ETIMEDOUT; 915 915 - } 916 916 - 917 917 - /** 918 918 - * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 919 919 - * flash to be ready, or timeout occurs. 920 920 - * @nor: pointer to "struct spi_nor". 921 921 - * 922 922 - * Return: 0 on success, -errno otherwise. 923 923 - */ 924 924 - static int spi_nor_wait_till_ready(struct spi_nor *nor) 925 925 - { 926 926 - return spi_nor_wait_till_ready_with_timeout(nor, 927 927 - DEFAULT_READY_WAIT_JIFFIES); 928 928 - } 929 929 - 930 930 - /** 931 931 - * spi_nor_write_sr() - Write the Status Register. 932 932 - * @nor: pointer to 'struct spi_nor'. 933 933 - * @sr: pointer to DMA-able buffer to write to the Status Register. 934 934 - * @len: number of bytes to write to the Status Register. 935 935 - * 936 936 - * Return: 0 on success, -errno otherwise. 937 937 - */ 938 938 - static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 939 939 - { 940 940 - int ret; 941 941 - 942 942 - ret = spi_nor_write_enable(nor); 943 943 - if (ret) 944 944 - return ret; 945 945 - 946 946 - if (nor->spimem) { 947 947 - struct spi_mem_op op = 948 948 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), 949 949 - SPI_MEM_OP_NO_ADDR, 950 950 - SPI_MEM_OP_NO_DUMMY, 951 951 - SPI_MEM_OP_DATA_OUT(len, sr, 1)); 952 952 - 953 953 - ret = spi_mem_exec_op(nor->spimem, &op); 954 954 - } else { 955 955 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, 956 956 - sr, len); 957 957 - } 958 958 - 959 959 - if (ret) { 960 960 - dev_dbg(nor->dev, "error %d writing SR\n", ret); 961 961 - return ret; 962 962 - } 963 963 - 964 964 - return spi_nor_wait_till_ready(nor); 965 965 - } 966 966 - 967 967 - /** 968 968 - * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 969 969 - * ensure that the byte written match the received value. 970 970 - * @nor: pointer to a 'struct spi_nor'. 971 971 - * @sr1: byte value to be written to the Status Register. 972 972 - * 973 973 - * Return: 0 on success, -errno otherwise. 974 974 - */ 975 975 - static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 976 976 - { 977 977 - int ret; 978 978 - 979 979 - nor->bouncebuf[0] = sr1; 980 980 - 981 981 - ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 982 982 - if (ret) 983 983 - return ret; 984 984 - 985 985 - ret = spi_nor_read_sr(nor, nor->bouncebuf); 986 986 - if (ret) 987 987 - return ret; 988 988 - 989 989 - if (nor->bouncebuf[0] != sr1) { 990 990 - dev_dbg(nor->dev, "SR1: read back test failed\n"); 991 991 - return -EIO; 992 992 - } 993 993 - 994 994 - return 0; 995 995 - } 996 996 - 997 997 - /** 998 998 - * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 999 999 - * Status Register 2 in one shot. Ensure that the byte written in the Status 1000 1000 - * Register 1 match the received value, and that the 16-bit Write did not 1001 1001 - * affect what was already in the Status Register 2. 1002 1002 - * @nor: pointer to a 'struct spi_nor'. 1003 1003 - * @sr1: byte value to be written to the Status Register 1. 1004 1004 - * 1005 1005 - * Return: 0 on success, -errno otherwise. 1006 1006 - */ 1007 1007 - static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 1008 1008 - { 1009 1009 - int ret; 1010 1010 - u8 *sr_cr = nor->bouncebuf; 1011 1011 - u8 cr_written; 1012 1012 - 1013 1013 - /* Make sure we don't overwrite the contents of Status Register 2. */ 1014 1014 - if (!(nor->flags & SNOR_F_NO_READ_CR)) { 1015 1015 - ret = spi_nor_read_cr(nor, &sr_cr[1]); 1016 1016 - if (ret) 1017 1017 - return ret; 1018 1018 - } else if (nor->params.quad_enable) { 1019 1019 - /* 1020 1020 - * If the Status Register 2 Read command (35h) is not 1021 1021 - * supported, we should at least be sure we don't 1022 1022 - * change the value of the SR2 Quad Enable bit. 1023 1023 - * 1024 1024 - * We can safely assume that when the Quad Enable method is 1025 1025 - * set, the value of the QE bit is one, as a consequence of the 1026 1026 - * nor->params.quad_enable() call. 1027 1027 - * 1028 1028 - * We can safely assume that the Quad Enable bit is present in 1029 1029 - * the Status Register 2 at BIT(1). According to the JESD216 1030 1030 - * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit 1031 1031 - * Write Status (01h) command is available just for the cases 1032 1032 - * in which the QE bit is described in SR2 at BIT(1). 1033 1033 - */ 1034 1034 - sr_cr[1] = SR2_QUAD_EN_BIT1; 1035 1035 - } else { 1036 1036 - sr_cr[1] = 0; 1037 1037 - } 1038 1038 - 1039 1039 - sr_cr[0] = sr1; 1040 1040 - 1041 1041 - ret = spi_nor_write_sr(nor, sr_cr, 2); 1042 1042 - if (ret) 1043 1043 - return ret; 1044 1044 - 1045 1045 - if (nor->flags & SNOR_F_NO_READ_CR) 1046 1046 - return 0; 1047 1047 - 1048 1048 - cr_written = sr_cr[1]; 1049 1049 - 1050 1050 - ret = spi_nor_read_cr(nor, &sr_cr[1]); 1051 1051 - if (ret) 1052 1052 - return ret; 1053 1053 - 1054 1054 - if (cr_written != sr_cr[1]) { 1055 1055 - dev_dbg(nor->dev, "CR: read back test failed\n"); 1056 1056 - return -EIO; 1057 1057 - } 1058 1058 - 1059 1059 - return 0; 1060 1060 - } 1061 1061 - 1062 1062 - /** 1063 1063 - * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 1064 1064 - * Configuration Register in one shot. Ensure that the byte written in the 1065 1065 - * Configuration Register match the received value, and that the 16-bit Write 1066 1066 - * did not affect what was already in the Status Register 1. 1067 1067 - * @nor: pointer to a 'struct spi_nor'. 1068 1068 - * @cr: byte value to be written to the Configuration Register. 1069 1069 - * 1070 1070 - * Return: 0 on success, -errno otherwise. 1071 1071 - */ 1072 1072 - static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 1073 1073 - { 1074 1074 - int ret; 1075 1075 - u8 *sr_cr = nor->bouncebuf; 1076 1076 - u8 sr_written; 1077 1077 - 1078 1078 - /* Keep the current value of the Status Register 1. */ 1079 1079 - ret = spi_nor_read_sr(nor, sr_cr); 1080 1080 - if (ret) 1081 1081 - return ret; 1082 1082 - 1083 1083 - sr_cr[1] = cr; 1084 1084 - 1085 1085 - ret = spi_nor_write_sr(nor, sr_cr, 2); 1086 1086 - if (ret) 1087 1087 - return ret; 1088 1088 - 1089 1089 - sr_written = sr_cr[0]; 1090 1090 - 1091 1091 - ret = spi_nor_read_sr(nor, sr_cr); 1092 1092 - if (ret) 1093 1093 - return ret; 1094 1094 - 1095 1095 - if (sr_written != sr_cr[0]) { 1096 1096 - dev_dbg(nor->dev, "SR: Read back test failed\n"); 1097 1097 - return -EIO; 1098 1098 - } 1099 1099 - 1100 1100 - if (nor->flags & SNOR_F_NO_READ_CR) 1101 1101 - return 0; 1102 1102 - 1103 1103 - ret = spi_nor_read_cr(nor, &sr_cr[1]); 1104 1104 - if (ret) 1105 1105 - return ret; 1106 1106 - 1107 1107 - if (cr != sr_cr[1]) { 1108 1108 - dev_dbg(nor->dev, "CR: read back test failed\n"); 1109 1109 - return -EIO; 1110 1110 - } 1111 1111 - 1112 1112 - return 0; 1113 1113 - } 1114 1114 - 1115 1115 - /** 1116 1116 - * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 1117 1117 - * the byte written match the received value without affecting other bits in the 1118 1118 - * Status Register 1 and 2. 1119 1119 - * @nor: pointer to a 'struct spi_nor'. 1120 1120 - * @sr1: byte value to be written to the Status Register. 1121 1121 - * 1122 1122 - * Return: 0 on success, -errno otherwise. 1123 1123 - */ 1124 1124 - static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 1125 1125 - { 1126 1126 - if (nor->flags & SNOR_F_HAS_16BIT_SR) 1127 1127 - return spi_nor_write_16bit_sr_and_check(nor, sr1); 1128 1128 - 1129 1129 - return spi_nor_write_sr1_and_check(nor, sr1); 1130 1130 - } 1131 1131 - 1132 1132 - /** 1133 1133 - * spi_nor_write_sr2() - Write the Status Register 2 using the 1134 1134 - * SPINOR_OP_WRSR2 (3eh) command. 1135 1135 - * @nor: pointer to 'struct spi_nor'. 1136 1136 - * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 1137 1137 - * 1138 1138 - * Return: 0 on success, -errno otherwise. 1139 1139 - */ 1140 1140 - static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 1141 1141 - { 1142 1142 - int ret; 1143 1143 - 1144 1144 - ret = spi_nor_write_enable(nor); 1145 1145 - if (ret) 1146 1146 - return ret; 1147 1147 - 1148 1148 - if (nor->spimem) { 1149 1149 - struct spi_mem_op op = 1150 1150 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), 1151 1151 - SPI_MEM_OP_NO_ADDR, 1152 1152 - SPI_MEM_OP_NO_DUMMY, 1153 1153 - SPI_MEM_OP_DATA_OUT(1, sr2, 1)); 1154 1154 - 1155 1155 - ret = spi_mem_exec_op(nor->spimem, &op); 1156 1156 - } else { 1157 1157 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, 1158 1158 - sr2, 1); 1159 1159 - } 1160 1160 - 1161 1161 - if (ret) { 1162 1162 - dev_dbg(nor->dev, "error %d writing SR2\n", ret); 1163 1163 - return ret; 1164 1164 - } 1165 1165 - 1166 1166 - return spi_nor_wait_till_ready(nor); 1167 1167 - } 1168 1168 - 1169 1169 - /** 1170 1170 - * spi_nor_read_sr2() - Read the Status Register 2 using the 1171 1171 - * SPINOR_OP_RDSR2 (3fh) command. 1172 1172 - * @nor: pointer to 'struct spi_nor'. 1173 1173 - * @sr2: pointer to DMA-able buffer where the value of the 1174 1174 - * Status Register 2 will be written. 1175 1175 - * 1176 1176 - * Return: 0 on success, -errno otherwise. 1177 1177 - */ 1178 1178 - static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 1179 1179 - { 1180 1180 - int ret; 1181 1181 - 1182 1182 - if (nor->spimem) { 1183 1183 - struct spi_mem_op op = 1184 1184 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), 1185 1185 - SPI_MEM_OP_NO_ADDR, 1186 1186 - SPI_MEM_OP_NO_DUMMY, 1187 1187 - SPI_MEM_OP_DATA_IN(1, sr2, 1)); 1188 1188 - 1189 1189 - ret = spi_mem_exec_op(nor->spimem, &op); 1190 1190 - } else { 1191 1191 - ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, 1192 1192 - sr2, 1); 1193 1193 - } 1194 1194 - 1195 1195 - if (ret) 1196 1196 - dev_dbg(nor->dev, "error %d reading SR2\n", ret); 1197 1197 - 1198 1198 - return ret; 1199 1199 - } 1200 1200 - 1201 1201 - /** 1202 1202 - * spi_nor_erase_chip() - Erase the entire flash memory. 1203 1203 - * @nor: pointer to 'struct spi_nor'. 1204 1204 - * 1205 1205 - * Return: 0 on success, -errno otherwise. 1206 1206 - */ 1207 1207 - static int spi_nor_erase_chip(struct spi_nor *nor) 1208 1208 - { 1209 1209 - int ret; 1210 1210 - 1211 1211 - dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 1212 1212 - 1213 1213 - if (nor->spimem) { 1214 1214 - struct spi_mem_op op = 1215 1215 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1), 1216 1216 - SPI_MEM_OP_NO_ADDR, 1217 1217 - SPI_MEM_OP_NO_DUMMY, 1218 1218 - SPI_MEM_OP_NO_DATA); 1219 1219 - 1220 1220 - ret = spi_mem_exec_op(nor->spimem, &op); 1221 1221 - } else { 1222 1222 - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, 1223 1223 - NULL, 0); 1224 1224 - } 1225 1225 - 1226 1226 - if (ret) 1227 1227 - dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1228 1228 - 1229 1229 - return ret; 1230 1230 - } 1231 1231 - 1232 1232 - static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 1233 1233 - { 1234 1234 - return mtd->priv; 1235 1235 - } 1236 1236 - 1237 1237 - static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1238 1238 - { 1239 1239 - size_t i; 1240 1240 - 1241 1241 - for (i = 0; i < size; i++) 1242 1242 - if (table[i][0] == opcode) 1243 1243 - return table[i][1]; 1244 1244 - 1245 1245 - /* No conversion found, keep input op code. */ 1246 1246 - return opcode; 1247 1247 - } 1248 1248 - 1249 1249 - static u8 spi_nor_convert_3to4_read(u8 opcode) 1250 1250 - { 1251 1251 - static const u8 spi_nor_3to4_read[][2] = { 1252 1252 - { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1253 1253 - { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1254 1254 - { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1255 1255 - { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1256 1256 - { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1257 1257 - { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1258 1258 - { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1259 1259 - { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1260 1260 - 1261 1261 - { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1262 1262 - { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1263 1263 - { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1264 1264 - }; 1265 1265 - 1266 1266 - return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1267 1267 - ARRAY_SIZE(spi_nor_3to4_read)); 1268 1268 - } 1269 1269 - 1270 1270 - static u8 spi_nor_convert_3to4_program(u8 opcode) 1271 1271 - { 1272 1272 - static const u8 spi_nor_3to4_program[][2] = { 1273 1273 - { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1274 1274 - { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1275 1275 - { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1276 1276 - { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1277 1277 - { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1278 1278 - }; 1279 1279 - 1280 1280 - return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1281 1281 - ARRAY_SIZE(spi_nor_3to4_program)); 1282 1282 - } 1283 1283 - 1284 1284 - static u8 spi_nor_convert_3to4_erase(u8 opcode) 1285 1285 - { 1286 1286 - static const u8 spi_nor_3to4_erase[][2] = { 1287 1287 - { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1288 1288 - { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1289 1289 - { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1290 1290 - }; 1291 1291 - 1292 1292 - return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1293 1293 - ARRAY_SIZE(spi_nor_3to4_erase)); 1294 1294 - } 1295 1295 - 1296 1296 - static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1297 1297 - { 1298 1298 - nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1299 1299 - nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1300 1300 - nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1301 1301 - 1302 1302 - if (!spi_nor_has_uniform_erase(nor)) { 1303 1303 - struct spi_nor_erase_map *map = &nor->params.erase_map; 1304 1304 - struct spi_nor_erase_type *erase; 1305 1305 - int i; 1306 1306 - 1307 1307 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1308 1308 - erase = &map->erase_type[i]; 1309 1309 - erase->opcode = 1310 1310 - spi_nor_convert_3to4_erase(erase->opcode); 1311 1311 - } 1312 1312 - } 1313 1313 - } 1314 1314 - 1315 1315 - static int spi_nor_lock_and_prep(struct spi_nor *nor) 1316 1316 - { 1317 1317 - int ret = 0; 1318 1318 - 1319 1319 - mutex_lock(&nor->lock); 1320 1320 - 1321 1321 - if (nor->controller_ops && nor->controller_ops->prepare) { 1322 1322 - ret = nor->controller_ops->prepare(nor); 1323 1323 - if (ret) { 1324 1324 - mutex_unlock(&nor->lock); 1325 1325 - return ret; 1326 1326 - } 1327 1327 - } 1328 1328 - return ret; 1329 1329 - } 1330 1330 - 1331 1331 - static void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1332 1332 - { 1333 1333 - if (nor->controller_ops && nor->controller_ops->unprepare) 1334 1334 - nor->controller_ops->unprepare(nor); 1335 1335 - mutex_unlock(&nor->lock); 1336 1336 - } 1337 1337 - 1338 1338 - /* 1339 1339 - * This code converts an address to the Default Address Mode, that has non 1340 1340 - * power of two page sizes. We must support this mode because it is the default 1341 1341 - * mode supported by Xilinx tools, it can access the whole flash area and 1342 1342 - * changing over to the Power-of-two mode is irreversible and corrupts the 1343 1343 - * original data. 1344 1344 - * Addr can safely be unsigned int, the biggest S3AN device is smaller than 1345 1345 - * 4 MiB. 1346 1346 - */ 1347 1347 - static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr) 1348 1348 - { 1349 1349 - u32 offset, page; 1350 1350 - 1351 1351 - offset = addr % nor->page_size; 1352 1352 - page = addr / nor->page_size; 1353 1353 - page <<= (nor->page_size > 512) ? 10 : 9; 1354 1354 - 1355 1355 - return page | offset; 1356 1356 - } 1357 1357 - 1358 1358 - static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1359 1359 - { 1360 1360 - if (!nor->params.convert_addr) 1361 1361 - return addr; 1362 1362 - 1363 1363 - return nor->params.convert_addr(nor, addr); 1364 1364 - } 1365 1365 - 1366 1366 - /* 1367 1367 - * Initiate the erasure of a single sector 1368 1368 - */ 1369 1369 - static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1370 1370 - { 1371 1371 - int i; 1372 1372 - 1373 1373 - addr = spi_nor_convert_addr(nor, addr); 1374 1374 - 1375 1375 - if (nor->spimem) { 1376 1376 - struct spi_mem_op op = 1377 1377 - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), 1378 1378 - SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), 1379 1379 - SPI_MEM_OP_NO_DUMMY, 1380 1380 - SPI_MEM_OP_NO_DATA); 1381 1381 - 1382 1382 - return spi_mem_exec_op(nor->spimem, &op); 1383 1383 - } else if (nor->controller_ops->erase) { 1384 1384 - return nor->controller_ops->erase(nor, addr); 1385 1385 - } 1386 1386 - 1387 1387 - /* 1388 1388 - * Default implementation, if driver doesn't have a specialized HW 1389 1389 - * control 1390 1390 - */ 1391 1391 - for (i = nor->addr_width - 1; i >= 0; i--) { 1392 1392 - nor->bouncebuf[i] = addr & 0xff; 1393 1393 - addr >>= 8; 1394 1394 - } 1395 1395 - 1396 1396 - return nor->controller_ops->write_reg(nor, nor->erase_opcode, 1397 1397 - nor->bouncebuf, nor->addr_width); 1398 1398 - } 1399 1399 - 1400 1400 - /** 1401 1401 - * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1402 1402 - * @erase: pointer to a structure that describes a SPI NOR erase type 1403 1403 - * @dividend: dividend value 1404 1404 - * @remainder: pointer to u32 remainder (will be updated) 1405 1405 - * 1406 1406 - * Return: the result of the division 1407 1407 - */ 1408 1408 - static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1409 1409 - u64 dividend, u32 *remainder) 1410 1410 - { 1411 1411 - /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1412 1412 - *remainder = (u32)dividend & erase->size_mask; 1413 1413 - return dividend >> erase->size_shift; 1414 1414 - } 1415 1415 - 1416 1416 - /** 1417 1417 - * spi_nor_find_best_erase_type() - find the best erase type for the given 1418 1418 - * offset in the serial flash memory and the 1419 1419 - * number of bytes to erase. The region in 1420 1420 - * which the address fits is expected to be 1421 1421 - * provided. 1422 1422 - * @map: the erase map of the SPI NOR 1423 1423 - * @region: pointer to a structure that describes a SPI NOR erase region 1424 1424 - * @addr: offset in the serial flash memory 1425 1425 - * @len: number of bytes to erase 1426 1426 - * 1427 1427 - * Return: a pointer to the best fitted erase type, NULL otherwise. 1428 1428 - */ 1429 1429 - static const struct spi_nor_erase_type * 1430 1430 - spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1431 1431 - const struct spi_nor_erase_region *region, 1432 1432 - u64 addr, u32 len) 1433 1433 - { 1434 1434 - const struct spi_nor_erase_type *erase; 1435 1435 - u32 rem; 1436 1436 - int i; 1437 1437 - u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1438 1438 - 1439 1439 - /* 1440 1440 - * Erase types are ordered by size, with the smallest erase type at 1441 1441 - * index 0. 1442 1442 - */ 1443 1443 - for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1444 1444 - /* Does the erase region support the tested erase type? */ 1445 1445 - if (!(erase_mask & BIT(i))) 1446 1446 - continue; 1447 1447 - 1448 1448 - erase = &map->erase_type[i]; 1449 1449 - 1450 1450 - /* Don't erase more than what the user has asked for. */ 1451 1451 - if (erase->size > len) 1452 1452 - continue; 1453 1453 - 1454 1454 - /* Alignment is not mandatory for overlaid regions */ 1455 1455 - if (region->offset & SNOR_OVERLAID_REGION) 1456 1456 - return erase; 1457 1457 - 1458 1458 - spi_nor_div_by_erase_size(erase, addr, &rem); 1459 1459 - if (rem) 1460 1460 - continue; 1461 1461 - else 1462 1462 - return erase; 1463 1463 - } 1464 1464 - 1465 1465 - return NULL; 1466 1466 - } 1467 1467 - 1468 1468 - /** 1469 1469 - * spi_nor_region_next() - get the next spi nor region 1470 1470 - * @region: pointer to a structure that describes a SPI NOR erase region 1471 1471 - * 1472 1472 - * Return: the next spi nor region or NULL if last region. 1473 1473 - */ 1474 1474 - static struct spi_nor_erase_region * 1475 1475 - spi_nor_region_next(struct spi_nor_erase_region *region) 1476 1476 - { 1477 1477 - if (spi_nor_region_is_last(region)) 1478 1478 - return NULL; 1479 1479 - region++; 1480 1480 - return region; 1481 1481 - } 1482 1482 - 1483 1483 - /** 1484 1484 - * spi_nor_find_erase_region() - find the region of the serial flash memory in 1485 1485 - * which the offset fits 1486 1486 - * @map: the erase map of the SPI NOR 1487 1487 - * @addr: offset in the serial flash memory 1488 1488 - * 1489 1489 - * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1490 1490 - * otherwise. 1491 1491 - */ 1492 1492 - static struct spi_nor_erase_region * 1493 1493 - spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1494 1494 - { 1495 1495 - struct spi_nor_erase_region *region = map->regions; 1496 1496 - u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1497 1497 - u64 region_end = region_start + region->size; 1498 1498 - 1499 1499 - while (addr < region_start || addr >= region_end) { 1500 1500 - region = spi_nor_region_next(region); 1501 1501 - if (!region) 1502 1502 - return ERR_PTR(-EINVAL); 1503 1503 - 1504 1504 - region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1505 1505 - region_end = region_start + region->size; 1506 1506 - } 1507 1507 - 1508 1508 - return region; 1509 1509 - } 1510 1510 - 1511 1511 - /** 1512 1512 - * spi_nor_init_erase_cmd() - initialize an erase command 1513 1513 - * @region: pointer to a structure that describes a SPI NOR erase region 1514 1514 - * @erase: pointer to a structure that describes a SPI NOR erase type 1515 1515 - * 1516 1516 - * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1517 1517 - * otherwise. 1518 1518 - */ 1519 1519 - static struct spi_nor_erase_command * 1520 1520 - spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1521 1521 - const struct spi_nor_erase_type *erase) 1522 1522 - { 1523 1523 - struct spi_nor_erase_command *cmd; 1524 1524 - 1525 1525 - cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1526 1526 - if (!cmd) 1527 1527 - return ERR_PTR(-ENOMEM); 1528 1528 - 1529 1529 - INIT_LIST_HEAD(&cmd->list); 1530 1530 - cmd->opcode = erase->opcode; 1531 1531 - cmd->count = 1; 1532 1532 - 1533 1533 - if (region->offset & SNOR_OVERLAID_REGION) 1534 1534 - cmd->size = region->size; 1535 1535 - else 1536 1536 - cmd->size = erase->size; 1537 1537 - 1538 1538 - return cmd; 1539 1539 - } 1540 1540 - 1541 1541 - /** 1542 1542 - * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1543 1543 - * @erase_list: list of erase commands 1544 1544 - */ 1545 1545 - static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1546 1546 - { 1547 1547 - struct spi_nor_erase_command *cmd, *next; 1548 1548 - 1549 1549 - list_for_each_entry_safe(cmd, next, erase_list, list) { 1550 1550 - list_del(&cmd->list); 1551 1551 - kfree(cmd); 1552 1552 - } 1553 1553 - } 1554 1554 - 1555 1555 - /** 1556 1556 - * spi_nor_init_erase_cmd_list() - initialize erase command list 1557 1557 - * @nor: pointer to a 'struct spi_nor' 1558 1558 - * @erase_list: list of erase commands to be executed once we validate that the 1559 1559 - * erase can be performed 1560 1560 - * @addr: offset in the serial flash memory 1561 1561 - * @len: number of bytes to erase 1562 1562 - * 1563 1563 - * Builds the list of best fitted erase commands and verifies if the erase can 1564 1564 - * be performed. 1565 1565 - * 1566 1566 - * Return: 0 on success, -errno otherwise. 1567 1567 - */ 1568 1568 - static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1569 1569 - struct list_head *erase_list, 1570 1570 - u64 addr, u32 len) 1571 1571 - { 1572 1572 - const struct spi_nor_erase_map *map = &nor->params.erase_map; 1573 1573 - const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1574 1574 - struct spi_nor_erase_region *region; 1575 1575 - struct spi_nor_erase_command *cmd = NULL; 1576 1576 - u64 region_end; 1577 1577 - int ret = -EINVAL; 1578 1578 - 1579 1579 - region = spi_nor_find_erase_region(map, addr); 1580 1580 - if (IS_ERR(region)) 1581 1581 - return PTR_ERR(region); 1582 1582 - 1583 1583 - region_end = spi_nor_region_end(region); 1584 1584 - 1585 1585 - while (len) { 1586 1586 - erase = spi_nor_find_best_erase_type(map, region, addr, len); 1587 1587 - if (!erase) 1588 1588 - goto destroy_erase_cmd_list; 1589 1589 - 1590 1590 - if (prev_erase != erase || 1591 1591 - region->offset & SNOR_OVERLAID_REGION) { 1592 1592 - cmd = spi_nor_init_erase_cmd(region, erase); 1593 1593 - if (IS_ERR(cmd)) { 1594 1594 - ret = PTR_ERR(cmd); 1595 1595 - goto destroy_erase_cmd_list; 1596 1596 - } 1597 1597 - 1598 1598 - list_add_tail(&cmd->list, erase_list); 1599 1599 - } else { 1600 1600 - cmd->count++; 1601 1601 - } 1602 1602 - 1603 1603 - addr += cmd->size; 1604 1604 - len -= cmd->size; 1605 1605 - 1606 1606 - if (len && addr >= region_end) { 1607 1607 - region = spi_nor_region_next(region); 1608 1608 - if (!region) 1609 1609 - goto destroy_erase_cmd_list; 1610 1610 - region_end = spi_nor_region_end(region); 1611 1611 - } 1612 1612 - 1613 1613 - prev_erase = erase; 1614 1614 - } 1615 1615 - 1616 1616 - return 0; 1617 1617 - 1618 1618 - destroy_erase_cmd_list: 1619 1619 - spi_nor_destroy_erase_cmd_list(erase_list); 1620 1620 - return ret; 1621 1621 - } 1622 1622 - 1623 1623 - /** 1624 1624 - * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1625 1625 - * @nor: pointer to a 'struct spi_nor' 1626 1626 - * @addr: offset in the serial flash memory 1627 1627 - * @len: number of bytes to erase 1628 1628 - * 1629 1629 - * Build a list of best fitted erase commands and execute it once we validate 1630 1630 - * that the erase can be performed. 1631 1631 - * 1632 1632 - * Return: 0 on success, -errno otherwise. 1633 1633 - */ 1634 1634 - static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1635 1635 - { 1636 1636 - LIST_HEAD(erase_list); 1637 1637 - struct spi_nor_erase_command *cmd, *next; 1638 1638 - int ret; 1639 1639 - 1640 1640 - ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1641 1641 - if (ret) 1642 1642 - return ret; 1643 1643 - 1644 1644 - list_for_each_entry_safe(cmd, next, &erase_list, list) { 1645 1645 - nor->erase_opcode = cmd->opcode; 1646 1646 - while (cmd->count) { 1647 1647 - ret = spi_nor_write_enable(nor); 1648 1648 - if (ret) 1649 1649 - goto destroy_erase_cmd_list; 1650 1650 - 1651 1651 - ret = spi_nor_erase_sector(nor, addr); 1652 1652 - if (ret) 1653 1653 - goto destroy_erase_cmd_list; 1654 1654 - 1655 1655 - addr += cmd->size; 1656 1656 - cmd->count--; 1657 1657 - 1658 1658 - ret = spi_nor_wait_till_ready(nor); 1659 1659 - if (ret) 1660 1660 - goto destroy_erase_cmd_list; 1661 1661 - } 1662 1662 - list_del(&cmd->list); 1663 1663 - kfree(cmd); 1664 1664 - } 1665 1665 - 1666 1666 - return 0; 1667 1667 - 1668 1668 - destroy_erase_cmd_list: 1669 1669 - spi_nor_destroy_erase_cmd_list(&erase_list); 1670 1670 - return ret; 1671 1671 - } 1672 1672 - 1673 1673 - /* 1674 1674 - * Erase an address range on the nor chip. The address range may extend 1675 1675 - * one or more erase sectors. Return an error is there is a problem erasing. 1676 1676 - */ 1677 1677 - static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1678 1678 - { 1679 1679 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 1680 1680 - u32 addr, len; 1681 1681 - uint32_t rem; 1682 1682 - int ret; 1683 1683 - 1684 1684 - dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1685 1685 - (long long)instr->len); 1686 1686 - 1687 1687 - if (spi_nor_has_uniform_erase(nor)) { 1688 1688 - div_u64_rem(instr->len, mtd->erasesize, &rem); 1689 1689 - if (rem) 1690 1690 - return -EINVAL; 1691 1691 - } 1692 1692 - 1693 1693 - addr = instr->addr; 1694 1694 - len = instr->len; 1695 1695 - 1696 1696 - ret = spi_nor_lock_and_prep(nor); 1697 1697 - if (ret) 1698 1698 - return ret; 1699 1699 - 1700 1700 - /* whole-chip erase? */ 1701 1701 - if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1702 1702 - unsigned long timeout; 1703 1703 - 1704 1704 - ret = spi_nor_write_enable(nor); 1705 1705 - if (ret) 1706 1706 - goto erase_err; 1707 1707 - 1708 1708 - ret = spi_nor_erase_chip(nor); 1709 1709 - if (ret) 1710 1710 - goto erase_err; 1711 1711 - 1712 1712 - /* 1713 1713 - * Scale the timeout linearly with the size of the flash, with 1714 1714 - * a minimum calibrated to an old 2MB flash. We could try to 1715 1715 - * pull these from CFI/SFDP, but these values should be good 1716 1716 - * enough for now. 1717 1717 - */ 1718 1718 - timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1719 1719 - CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1720 1720 - (unsigned long)(mtd->size / SZ_2M)); 1721 1721 - ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1722 1722 - if (ret) 1723 1723 - goto erase_err; 1724 1724 - 1725 1725 - /* REVISIT in some cases we could speed up erasing large regions 1726 1726 - * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1727 1727 - * to use "small sector erase", but that's not always optimal. 1728 1728 - */ 1729 1729 - 1730 1730 - /* "sector"-at-a-time erase */ 1731 1731 - } else if (spi_nor_has_uniform_erase(nor)) { 1732 1732 - while (len) { 1733 1733 - ret = spi_nor_write_enable(nor); 1734 1734 - if (ret) 1735 1735 - goto erase_err; 1736 1736 - 1737 1737 - ret = spi_nor_erase_sector(nor, addr); 1738 1738 - if (ret) 1739 1739 - goto erase_err; 1740 1740 - 1741 1741 - addr += mtd->erasesize; 1742 1742 - len -= mtd->erasesize; 1743 1743 - 1744 1744 - ret = spi_nor_wait_till_ready(nor); 1745 1745 - if (ret) 1746 1746 - goto erase_err; 1747 1747 - } 1748 1748 - 1749 1749 - /* erase multiple sectors */ 1750 1750 - } else { 1751 1751 - ret = spi_nor_erase_multi_sectors(nor, addr, len); 1752 1752 - if (ret) 1753 1753 - goto erase_err; 1754 1754 - } 1755 1755 - 1756 1756 - ret = spi_nor_write_disable(nor); 1757 1757 - 1758 1758 - erase_err: 1759 1759 - spi_nor_unlock_and_unprep(nor); 1760 1760 - 1761 1761 - return ret; 1762 1762 - } 1763 1763 - 1764 1764 - static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 1765 1765 - uint64_t *len) 1766 1766 - { 1767 1767 - struct mtd_info *mtd = &nor->mtd; 1768 1768 - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1769 1769 - u8 tb_mask = SR_TB_BIT5; 1770 1770 - int shift = ffs(mask) - 1; 1771 1771 - int pow; 1772 1772 - 1773 1773 - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1774 1774 - tb_mask = SR_TB_BIT6; 1775 1775 - 1776 1776 - if (!(sr & mask)) { 1777 1777 - /* No protection */ 1778 1778 - *ofs = 0; 1779 1779 - *len = 0; 1780 1780 - } else { 1781 1781 - pow = ((sr & mask) ^ mask) >> shift; 1782 1782 - *len = mtd->size >> pow; 1783 1783 - if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) 1784 1784 - *ofs = 0; 1785 1785 - else 1786 1786 - *ofs = mtd->size - *len; 1787 1787 - } 1788 1788 - } 1789 1789 - 1790 1790 - /* 1791 1791 - * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 1792 1792 - * @locked is false); 0 otherwise 1793 1793 - */ 1794 1794 - static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1795 1795 - u8 sr, bool locked) 1796 1796 - { 1797 1797 - loff_t lock_offs; 1798 1798 - uint64_t lock_len; 1799 1799 - 1800 1800 - if (!len) 1801 1801 - return 1; 1802 1802 - 1803 1803 - stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 1804 1804 - 1805 1805 - if (locked) 1806 1806 - /* Requested range is a sub-range of locked range */ 1807 1807 - return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 1808 1808 - else 1809 1809 - /* Requested range does not overlap with locked range */ 1810 1810 - return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 1811 1811 - } 1812 1812 - 1813 1813 - static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1814 1814 - u8 sr) 1815 1815 - { 1816 1816 - return stm_check_lock_status_sr(nor, ofs, len, sr, true); 1817 1817 - } 1818 1818 - 1819 1819 - static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1820 1820 - u8 sr) 1821 1821 - { 1822 1822 - return stm_check_lock_status_sr(nor, ofs, len, sr, false); 1823 1823 - } 1824 1824 - 1825 1825 - /* 1826 1826 - * Lock a region of the flash. Compatible with ST Micro and similar flash. 1827 1827 - * Supports the block protection bits BP{0,1,2} in the status register 1828 1828 - * (SR). Does not support these features found in newer SR bitfields: 1829 1829 - * - SEC: sector/block protect - only handle SEC=0 (block protect) 1830 1830 - * - CMP: complement protect - only support CMP=0 (range is not complemented) 1831 1831 - * 1832 1832 - * Support for the following is provided conditionally for some flash: 1833 1833 - * - TB: top/bottom protect 1834 1834 - * 1835 1835 - * Sample table portion for 8MB flash (Winbond w25q64fw): 1836 1836 - * 1837 1837 - * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 1838 1838 - * -------------------------------------------------------------------------- 1839 1839 - * X | X | 0 | 0 | 0 | NONE | NONE 1840 1840 - * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 1841 1841 - * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 1842 1842 - * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 1843 1843 - * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 1844 1844 - * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 1845 1845 - * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 1846 1846 - * X | X | 1 | 1 | 1 | 8 MB | ALL 1847 1847 - * ------|-------|-------|-------|-------|---------------|------------------- 1848 1848 - * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 1849 1849 - * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 1850 1850 - * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 1851 1851 - * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 1852 1852 - * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 1853 1853 - * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 1854 1854 - * 1855 1855 - * Returns negative on errors, 0 on success. 1856 1856 - */ 1857 1857 - static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1858 1858 - { 1859 1859 - struct mtd_info *mtd = &nor->mtd; 1860 1860 - int ret, status_old, status_new; 1861 1861 - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1862 1862 - u8 tb_mask = SR_TB_BIT5; 1863 1863 - u8 shift = ffs(mask) - 1, pow, val; 1864 1864 - loff_t lock_len; 1865 1865 - bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1866 1866 - bool use_top; 1867 1867 - 1868 1868 - ret = spi_nor_read_sr(nor, nor->bouncebuf); 1869 1869 - if (ret) 1870 1870 - return ret; 1871 1871 - 1872 1872 - status_old = nor->bouncebuf[0]; 1873 1873 - 1874 1874 - /* If nothing in our range is unlocked, we don't need to do anything */ 1875 1875 - if (stm_is_locked_sr(nor, ofs, len, status_old)) 1876 1876 - return 0; 1877 1877 - 1878 1878 - /* If anything below us is unlocked, we can't use 'bottom' protection */ 1879 1879 - if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 1880 1880 - can_be_bottom = false; 1881 1881 - 1882 1882 - /* If anything above us is unlocked, we can't use 'top' protection */ 1883 1883 - if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 1884 1884 - status_old)) 1885 1885 - can_be_top = false; 1886 1886 - 1887 1887 - if (!can_be_bottom && !can_be_top) 1888 1888 - return -EINVAL; 1889 1889 - 1890 1890 - /* Prefer top, if both are valid */ 1891 1891 - use_top = can_be_top; 1892 1892 - 1893 1893 - /* lock_len: length of region that should end up locked */ 1894 1894 - if (use_top) 1895 1895 - lock_len = mtd->size - ofs; 1896 1896 - else 1897 1897 - lock_len = ofs + len; 1898 1898 - 1899 1899 - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1900 1900 - tb_mask = SR_TB_BIT6; 1901 1901 - 1902 1902 - /* 1903 1903 - * Need smallest pow such that: 1904 1904 - * 1905 1905 - * 1 / (2^pow) <= (len / size) 1906 1906 - * 1907 1907 - * so (assuming power-of-2 size) we do: 1908 1908 - * 1909 1909 - * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 1910 1910 - */ 1911 1911 - pow = ilog2(mtd->size) - ilog2(lock_len); 1912 1912 - val = mask - (pow << shift); 1913 1913 - if (val & ~mask) 1914 1914 - return -EINVAL; 1915 1915 - /* Don't "lock" with no region! */ 1916 1916 - if (!(val & mask)) 1917 1917 - return -EINVAL; 1918 1918 - 1919 1919 - status_new = (status_old & ~mask & ~tb_mask) | val; 1920 1920 - 1921 1921 - /* Disallow further writes if WP pin is asserted */ 1922 1922 - status_new |= SR_SRWD; 1923 1923 - 1924 1924 - if (!use_top) 1925 1925 - status_new |= tb_mask; 1926 1926 - 1927 1927 - /* Don't bother if they're the same */ 1928 1928 - if (status_new == status_old) 1929 1929 - return 0; 1930 1930 - 1931 1931 - /* Only modify protection if it will not unlock other areas */ 1932 1932 - if ((status_new & mask) < (status_old & mask)) 1933 1933 - return -EINVAL; 1934 1934 - 1935 1935 - return spi_nor_write_sr_and_check(nor, status_new); 1936 1936 - } 1937 1937 - 1938 1938 - /* 1939 1939 - * Unlock a region of the flash. See stm_lock() for more info 1940 1940 - * 1941 1941 - * Returns negative on errors, 0 on success. 1942 1942 - */ 1943 1943 - static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1944 1944 - { 1945 1945 - struct mtd_info *mtd = &nor->mtd; 1946 1946 - int ret, status_old, status_new; 1947 1947 - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1948 1948 - u8 tb_mask = SR_TB_BIT5; 1949 1949 - u8 shift = ffs(mask) - 1, pow, val; 1950 1950 - loff_t lock_len; 1951 1951 - bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1952 1952 - bool use_top; 1953 1953 - 1954 1954 - ret = spi_nor_read_sr(nor, nor->bouncebuf); 1955 1955 - if (ret) 1956 1956 - return ret; 1957 1957 - 1958 1958 - status_old = nor->bouncebuf[0]; 1959 1959 - 1960 1960 - /* If nothing in our range is locked, we don't need to do anything */ 1961 1961 - if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 1962 1962 - return 0; 1963 1963 - 1964 1964 - /* If anything below us is locked, we can't use 'top' protection */ 1965 1965 - if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 1966 1966 - can_be_top = false; 1967 1967 - 1968 1968 - /* If anything above us is locked, we can't use 'bottom' protection */ 1969 1969 - if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 1970 1970 - status_old)) 1971 1971 - can_be_bottom = false; 1972 1972 - 1973 1973 - if (!can_be_bottom && !can_be_top) 1974 1974 - return -EINVAL; 1975 1975 - 1976 1976 - /* Prefer top, if both are valid */ 1977 1977 - use_top = can_be_top; 1978 1978 - 1979 1979 - /* lock_len: length of region that should remain locked */ 1980 1980 - if (use_top) 1981 1981 - lock_len = mtd->size - (ofs + len); 1982 1982 - else 1983 1983 - lock_len = ofs; 1984 1984 - 1985 1985 - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1986 1986 - tb_mask = SR_TB_BIT6; 1987 1987 - /* 1988 1988 - * Need largest pow such that: 1989 1989 - * 1990 1990 - * 1 / (2^pow) >= (len / size) 1991 1991 - * 1992 1992 - * so (assuming power-of-2 size) we do: 1993 1993 - * 1994 1994 - * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 1995 1995 - */ 1996 1996 - pow = ilog2(mtd->size) - order_base_2(lock_len); 1997 1997 - if (lock_len == 0) { 1998 1998 - val = 0; /* fully unlocked */ 1999 1999 - } else { 2000 2000 - val = mask - (pow << shift); 2001 2001 - /* Some power-of-two sizes are not supported */ 2002 2002 - if (val & ~mask) 2003 2003 - return -EINVAL; 2004 2004 - } 2005 2005 - 2006 2006 - status_new = (status_old & ~mask & ~tb_mask) | val; 2007 2007 - 2008 2008 - /* Don't protect status register if we're fully unlocked */ 2009 2009 - if (lock_len == 0) 2010 2010 - status_new &= ~SR_SRWD; 2011 2011 - 2012 2012 - if (!use_top) 2013 2013 - status_new |= tb_mask; 2014 2014 - 2015 2015 - /* Don't bother if they're the same */ 2016 2016 - if (status_new == status_old) 2017 2017 - return 0; 2018 2018 - 2019 2019 - /* Only modify protection if it will not lock other areas */ 2020 2020 - if ((status_new & mask) > (status_old & mask)) 2021 2021 - return -EINVAL; 2022 2022 - 2023 2023 - return spi_nor_write_sr_and_check(nor, status_new); 2024 2024 - } 2025 2025 - 2026 2026 - /* 2027 2027 - * Check if a region of the flash is (completely) locked. See stm_lock() for 2028 2028 - * more info. 2029 2029 - * 2030 2030 - * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 2031 2031 - * negative on errors. 2032 2032 - */ 2033 2033 - static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 2034 2034 - { 2035 2035 - int ret; 2036 2036 - 2037 2037 - ret = spi_nor_read_sr(nor, nor->bouncebuf); 2038 2038 - if (ret) 2039 2039 - return ret; 2040 2040 - 2041 2041 - return stm_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); 2042 2042 - } 2043 2043 - 2044 2044 - static const struct spi_nor_locking_ops stm_locking_ops = { 2045 2045 - .lock = stm_lock, 2046 2046 - .unlock = stm_unlock, 2047 2047 - .is_locked = stm_is_locked, 2048 2048 - }; 2049 2049 - 2050 2050 - static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2051 2051 - { 2052 2052 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2053 2053 - int ret; 2054 2054 - 2055 2055 - ret = spi_nor_lock_and_prep(nor); 2056 2056 - if (ret) 2057 2057 - return ret; 2058 2058 - 2059 2059 - ret = nor->params.locking_ops->lock(nor, ofs, len); 2060 2060 - 2061 2061 - spi_nor_unlock_and_unprep(nor); 2062 2062 - return ret; 2063 2063 - } 2064 2064 - 2065 2065 - static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2066 2066 - { 2067 2067 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2068 2068 - int ret; 2069 2069 - 2070 2070 - ret = spi_nor_lock_and_prep(nor); 2071 2071 - if (ret) 2072 2072 - return ret; 2073 2073 - 2074 2074 - ret = nor->params.locking_ops->unlock(nor, ofs, len); 2075 2075 - 2076 2076 - spi_nor_unlock_and_unprep(nor); 2077 2077 - return ret; 2078 2078 - } 2079 2079 - 2080 2080 - static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2081 2081 - { 2082 2082 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2083 2083 - int ret; 2084 2084 - 2085 2085 - ret = spi_nor_lock_and_prep(nor); 2086 2086 - if (ret) 2087 2087 - return ret; 2088 2088 - 2089 2089 - ret = nor->params.locking_ops->is_locked(nor, ofs, len); 2090 2090 - 2091 2091 - spi_nor_unlock_and_unprep(nor); 2092 2092 - return ret; 2093 2093 - } 2094 2094 - 2095 2095 - /** 2096 2096 - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 2097 2097 - * Register 1. 2098 2098 - * @nor: pointer to a 'struct spi_nor' 2099 2099 - * 2100 2100 - * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 2101 2101 - * 2102 2102 - * Return: 0 on success, -errno otherwise. 2103 2103 - */ 2104 2104 - static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 2105 2105 - { 2106 2106 - int ret; 2107 2107 - 2108 2108 - ret = spi_nor_read_sr(nor, nor->bouncebuf); 2109 2109 - if (ret) 2110 2110 - return ret; 2111 2111 - 2112 2112 - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 2113 2113 - return 0; 2114 2114 - 2115 2115 - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 2116 2116 - 2117 2117 - return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 2118 2118 - } 2119 2119 - 2120 2120 - /** 2121 2121 - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 2122 2122 - * Register 2. 2123 2123 - * @nor: pointer to a 'struct spi_nor'. 2124 2124 - * 2125 2125 - * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 2126 2126 - * 2127 2127 - * Return: 0 on success, -errno otherwise. 2128 2128 - */ 2129 2129 - static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 2130 2130 - { 2131 2131 - int ret; 2132 2132 - 2133 2133 - if (nor->flags & SNOR_F_NO_READ_CR) 2134 2134 - return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 2135 2135 - 2136 2136 - ret = spi_nor_read_cr(nor, nor->bouncebuf); 2137 2137 - if (ret) 2138 2138 - return ret; 2139 2139 - 2140 2140 - if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 2141 2141 - return 0; 2142 2142 - 2143 2143 - nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 2144 2144 - 2145 2145 - return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 2146 2146 - } 2147 2147 - 2148 2148 - /** 2149 2149 - * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 2150 2150 - * @nor: pointer to a 'struct spi_nor' 2151 2151 - * 2152 2152 - * Set the Quad Enable (QE) bit in the Status Register 2. 2153 2153 - * 2154 2154 - * This is one of the procedures to set the QE bit described in the SFDP 2155 2155 - * (JESD216 rev B) specification but no manufacturer using this procedure has 2156 2156 - * been identified yet, hence the name of the function. 2157 2157 - * 2158 2158 - * Return: 0 on success, -errno otherwise. 2159 2159 - */ 2160 2160 - static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 2161 2161 - { 2162 2162 - u8 *sr2 = nor->bouncebuf; 2163 2163 - int ret; 2164 2164 - u8 sr2_written; 2165 2165 - 2166 2166 - /* Check current Quad Enable bit value. */ 2167 2167 - ret = spi_nor_read_sr2(nor, sr2); 2168 2168 - if (ret) 2169 2169 - return ret; 2170 2170 - if (*sr2 & SR2_QUAD_EN_BIT7) 2171 2171 - return 0; 2172 2172 - 2173 2173 - /* Update the Quad Enable bit. */ 2174 2174 - *sr2 |= SR2_QUAD_EN_BIT7; 2175 2175 - 2176 2176 - ret = spi_nor_write_sr2(nor, sr2); 2177 2177 - if (ret) 2178 2178 - return ret; 2179 2179 - 2180 2180 - sr2_written = *sr2; 2181 2181 - 2182 2182 - /* Read back and check it. */ 2183 2183 - ret = spi_nor_read_sr2(nor, sr2); 2184 2184 - if (ret) 2185 2185 - return ret; 2186 2186 - 2187 2187 - if (*sr2 != sr2_written) { 2188 2188 - dev_dbg(nor->dev, "SR2: Read back test failed\n"); 2189 2189 - return -EIO; 2190 2190 - } 2191 2191 - 2192 2192 - return 0; 2193 2193 - } 2194 2194 - 2195 2195 - /* Used when the "_ext_id" is two bytes at most */ 2196 2196 - #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 2197 2197 - .id = { \ 2198 2198 - ((_jedec_id) >> 16) & 0xff, \ 2199 2199 - ((_jedec_id) >> 8) & 0xff, \ 2200 2200 - (_jedec_id) & 0xff, \ 2201 2201 - ((_ext_id) >> 8) & 0xff, \ 2202 2202 - (_ext_id) & 0xff, \ 2203 2203 - }, \ 2204 2204 - .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 2205 2205 - .sector_size = (_sector_size), \ 2206 2206 - .n_sectors = (_n_sectors), \ 2207 2207 - .page_size = 256, \ 2208 2208 - .flags = (_flags), 2209 2209 - 2210 2210 - #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 2211 2211 - .id = { \ 2212 2212 - ((_jedec_id) >> 16) & 0xff, \ 2213 2213 - ((_jedec_id) >> 8) & 0xff, \ 2214 2214 - (_jedec_id) & 0xff, \ 2215 2215 - ((_ext_id) >> 16) & 0xff, \ 2216 2216 - ((_ext_id) >> 8) & 0xff, \ 2217 2217 - (_ext_id) & 0xff, \ 2218 2218 - }, \ 2219 2219 - .id_len = 6, \ 2220 2220 - .sector_size = (_sector_size), \ 2221 2221 - .n_sectors = (_n_sectors), \ 2222 2222 - .page_size = 256, \ 2223 2223 - .flags = (_flags), 2224 2224 - 2225 2225 - #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ 2226 2226 - .sector_size = (_sector_size), \ 2227 2227 - .n_sectors = (_n_sectors), \ 2228 2228 - .page_size = (_page_size), \ 2229 2229 - .addr_width = (_addr_width), \ 2230 2230 - .flags = (_flags), 2231 2231 - 2232 2232 - #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 2233 2233 - .id = { \ 2234 2234 - ((_jedec_id) >> 16) & 0xff, \ 2235 2235 - ((_jedec_id) >> 8) & 0xff, \ 2236 2236 - (_jedec_id) & 0xff \ 2237 2237 - }, \ 2238 2238 - .id_len = 3, \ 2239 2239 - .sector_size = (8*_page_size), \ 2240 2240 - .n_sectors = (_n_sectors), \ 2241 2241 - .page_size = _page_size, \ 2242 2242 - .addr_width = 3, \ 2243 2243 - .flags = SPI_NOR_NO_FR | SPI_S3AN, 2244 2244 - 2245 2245 - static int 2246 2246 - is25lp256_post_bfpt_fixups(struct spi_nor *nor, 2247 2247 - const struct sfdp_parameter_header *bfpt_header, 2248 2248 - const struct sfdp_bfpt *bfpt, 2249 2249 - struct spi_nor_flash_parameter *params) 2250 2250 - { 2251 2251 - /* 2252 2252 - * IS25LP256 supports 4B opcodes, but the BFPT advertises a 2253 2253 - * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width. 2254 2254 - * Overwrite the address width advertised by the BFPT. 2255 2255 - */ 2256 2256 - if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) == 2257 2257 - BFPT_DWORD1_ADDRESS_BYTES_3_ONLY) 2258 2258 - nor->addr_width = 4; 2259 2259 - 2260 2260 - return 0; 2261 2261 - } 2262 2262 - 2263 2263 - static struct spi_nor_fixups is25lp256_fixups = { 2264 2264 - .post_bfpt = is25lp256_post_bfpt_fixups, 2265 2265 - }; 2266 2266 - 2267 2267 - static int 2268 2268 - mx25l25635_post_bfpt_fixups(struct spi_nor *nor, 2269 2269 - const struct sfdp_parameter_header *bfpt_header, 2270 2270 - const struct sfdp_bfpt *bfpt, 2271 2271 - struct spi_nor_flash_parameter *params) 2272 2272 - { 2273 2273 - /* 2274 2274 - * MX25L25635F supports 4B opcodes but MX25L25635E does not. 2275 2275 - * Unfortunately, Macronix has re-used the same JEDEC ID for both 2276 2276 - * variants which prevents us from defining a new entry in the parts 2277 2277 - * table. 2278 2278 - * We need a way to differentiate MX25L25635E and MX25L25635F, and it 2279 2279 - * seems that the F version advertises support for Fast Read 4-4-4 in 2280 2280 - * its BFPT table. 2281 2281 - */ 2282 2282 - if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4) 2283 2283 - nor->flags |= SNOR_F_4B_OPCODES; 2284 2284 - 2285 2285 - return 0; 2286 2286 - } 2287 2287 - 2288 2288 - static struct spi_nor_fixups mx25l25635_fixups = { 2289 2289 - .post_bfpt = mx25l25635_post_bfpt_fixups, 2290 2290 - }; 2291 2291 - 2292 2292 - static void gd25q256_default_init(struct spi_nor *nor) 2293 2293 - { 2294 2294 - /* 2295 2295 - * Some manufacturer like GigaDevice may use different 2296 2296 - * bit to set QE on different memories, so the MFR can't 2297 2297 - * indicate the quad_enable method for this case, we need 2298 2298 - * to set it in the default_init fixup hook. 2299 2299 - */ 2300 2300 - nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; 2301 2301 - } 2302 2302 - 2303 2303 - static struct spi_nor_fixups gd25q256_fixups = { 2304 2304 - .default_init = gd25q256_default_init, 2305 2305 - }; 2306 2306 - 2307 2307 - /* NOTE: double check command sets and memory organization when you add 2308 2308 - * more nor chips. This current list focusses on newer chips, which 2309 2309 - * have been converging on command sets which including JEDEC ID. 2310 2310 - * 2311 2311 - * All newly added entries should describe *hardware* and should use SECT_4K 2312 2312 - * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 2313 2313 - * scenarios excluding small sectors there is config option that can be 2314 2314 - * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. 2315 2315 - * For historical (and compatibility) reasons (before we got above config) some 2316 2316 - * old entries may be missing 4K flag. 2317 2317 - */ 2318 2318 - static const struct flash_info spi_nor_ids[] = { 2319 2319 - /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 2320 2320 - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, 2321 2321 - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, 2322 2322 - 2323 2323 - { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, 2324 2324 - { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 2325 2325 - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 2326 2326 - { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, 2327 2327 - 2328 2328 - { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64, 2329 2329 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2330 2330 - 2331 2331 - { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, 2332 2332 - { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 2333 2333 - { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, 2334 2334 - { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 2335 2335 - 2336 2336 - { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 2337 2337 - 2338 2338 - /* EON -- en25xxx */ 2339 2339 - { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, 2340 2340 - { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, 2341 2341 - { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 2342 2342 - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, 2343 2343 - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 2344 2344 - { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, 2345 2345 - SECT_4K | SPI_NOR_DUAL_READ) }, 2346 2346 - { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32, 2347 2347 - SECT_4K | SPI_NOR_DUAL_READ) }, 2348 2348 - { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) }, 2349 2349 - { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128, 2350 2350 - SECT_4K | SPI_NOR_DUAL_READ) }, 2351 2351 - { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, 2352 2352 - { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, 2353 2353 - { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 2354 2354 - 2355 2355 - /* ESMT */ 2356 2356 - { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, 2357 2357 - { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, 2358 2358 - { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) }, 2359 2359 - 2360 2360 - /* Everspin */ 2361 2361 - { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2362 2362 - { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2363 2363 - { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2364 2364 - { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2365 2365 - 2366 2366 - /* Fujitsu */ 2367 2367 - { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, 2368 2368 - 2369 2369 - /* GigaDevice */ 2370 2370 - { 2371 2371 - "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 2372 2372 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2373 2373 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2374 2374 - }, 2375 2375 - { 2376 2376 - "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 2377 2377 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2378 2378 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2379 2379 - }, 2380 2380 - { 2381 2381 - "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 2382 2382 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2383 2383 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2384 2384 - }, 2385 2385 - { 2386 2386 - "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 2387 2387 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2388 2388 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2389 2389 - }, 2390 2390 - { 2391 2391 - "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, 2392 2392 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2393 2393 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2394 2394 - }, 2395 2395 - { 2396 2396 - "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256, 2397 2397 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2398 2398 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2399 2399 - }, 2400 2400 - { 2401 2401 - "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, 2402 2402 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2403 2403 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2404 2404 - }, 2405 2405 - { 2406 2406 - "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, 2407 2407 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2408 2408 - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 2409 2409 - SPI_NOR_TB_SR_BIT6) 2410 2410 - .fixups = &gd25q256_fixups, 2411 2411 - }, 2412 2412 - 2413 2413 - /* Intel/Numonyx -- xxxs33b */ 2414 2414 - { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, 2415 2415 - { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, 2416 2416 - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, 2417 2417 - 2418 2418 - /* ISSI */ 2419 2419 - { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, 2420 2420 - { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8, 2421 2421 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2422 2422 - { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32, 2423 2423 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2424 2424 - { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16, 2425 2425 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2426 2426 - { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 2427 2427 - SECT_4K | SPI_NOR_DUAL_READ) }, 2428 2428 - { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 2429 2429 - SECT_4K | SPI_NOR_DUAL_READ) }, 2430 2430 - { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256, 2431 2431 - SECT_4K | SPI_NOR_DUAL_READ) }, 2432 2432 - { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512, 2433 2433 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2434 2434 - SPI_NOR_4B_OPCODES) 2435 2435 - .fixups = &is25lp256_fixups }, 2436 2436 - { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64, 2437 2437 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2438 2438 - { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128, 2439 2439 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2440 2440 - { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, 2441 2441 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2442 2442 - { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512, 2443 2443 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2444 2444 - SPI_NOR_4B_OPCODES) 2445 2445 - .fixups = &is25lp256_fixups }, 2446 2446 - 2447 2447 - /* Macronix */ 2448 2448 - { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, 2449 2449 - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 2450 2450 - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 2451 2451 - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 2452 2452 - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 2453 2453 - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 2454 2454 - { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, 2455 2455 - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 2456 2456 - { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 2457 2457 - { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 2458 2458 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2459 2459 - { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, 2460 2460 - { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, 2461 2461 - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 2462 2462 - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 2463 2463 - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 2464 2464 - { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64, 2465 2465 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2466 2466 - { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256, 2467 2467 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2468 2468 - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 2469 2469 - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 2470 2470 - .fixups = &mx25l25635_fixups }, 2471 2471 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 2472 2472 - { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16, 2473 2473 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2474 2474 - { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 2475 2475 - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2476 2476 - { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2477 2477 - { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2478 2478 - { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, 2479 2479 - 2480 2480 - /* Micron <--> ST Micro */ 2481 2481 - { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 2482 2482 - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 2483 2483 - { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 2484 2484 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 2485 2485 - { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 2486 2486 - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | 2487 2487 - USE_FSR | SPI_NOR_QUAD_READ) }, 2488 2488 - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | 2489 2489 - USE_FSR | SPI_NOR_QUAD_READ) }, 2490 2490 - { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, 2491 2491 - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 2492 2492 - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2493 2493 - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | 2494 2494 - USE_FSR | SPI_NOR_DUAL_READ | 2495 2495 - SPI_NOR_QUAD_READ) }, 2496 2496 - { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, 2497 2497 - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 2498 2498 - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2499 2499 - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | 2500 2500 - USE_FSR | SPI_NOR_QUAD_READ) }, 2501 2501 - { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, 2502 2502 - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 2503 2503 - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2504 2504 - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 2505 2505 - { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024, 2506 2506 - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | 2507 2507 - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2508 2508 - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | 2509 2509 - USE_FSR | SPI_NOR_QUAD_READ) }, 2510 2510 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 2511 2511 - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 2512 2512 - { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096, 2513 2513 - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | 2514 2514 - NO_CHIP_ERASE) }, 2515 2515 - { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 2516 2516 - 2517 2517 - /* Micron */ 2518 2518 - { 2519 2519 - "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, 2520 2520 - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | 2521 2521 - SPI_NOR_4B_OPCODES) 2522 2522 - }, 2523 2523 - { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, 2524 2524 - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | 2525 2525 - SPI_NOR_4B_OPCODES) }, 2526 2526 - 2527 2527 - /* PMC */ 2528 2528 - { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, 2529 2529 - { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, 2530 2530 - { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, 2531 2531 - 2532 2532 - /* Spansion/Cypress -- single (large) sector size only, at least 2533 2533 - * for the chips listed here (without boot sectors). 2534 2534 - */ 2535 2535 - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2536 2536 - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2537 2537 - { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, 2538 2538 - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2539 2539 - { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, 2540 2540 - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2541 2541 - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 2542 2542 - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2543 2543 - { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, 2544 2544 - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2545 2545 - SPI_NOR_HAS_LOCK | USE_CLSR) }, 2546 2546 - { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2547 2547 - { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, 2548 2548 - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 2549 2549 - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 2550 2550 - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2551 2551 - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 2552 2552 - { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, 2553 2553 - { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 2554 2554 - { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 2555 2555 - { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 2556 2556 - { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 2557 2557 - { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2558 2558 - { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2559 2559 - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2560 2560 - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 2561 2561 - { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2562 2562 - { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, 2563 2563 - { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 2564 2564 - { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, 2565 2565 - { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 2566 2566 - { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2567 2567 - { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2568 2568 - { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2569 2569 - 2570 2570 - /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 2571 2571 - { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 2572 2572 - { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 2573 2573 - { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 2574 2574 - { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 2575 2575 - { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 2576 2576 - { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 2577 2577 - { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 2578 2578 - { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 2579 2579 - { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, 2580 2580 - { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, 2581 2581 - { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 2582 2582 - { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 2583 2583 - { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K | 2584 2584 - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2585 2585 - { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, SECT_4K | 2586 2586 - SPI_NOR_DUAL_READ) }, 2587 2587 - { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2588 2588 - 2589 2589 - /* ST Microelectronics -- newer production may have feature updates */ 2590 2590 - { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, 2591 2591 - { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 2592 2592 - { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 2593 2593 - { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 2594 2594 - { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 2595 2595 - { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 2596 2596 - { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 2597 2597 - { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 2598 2598 - { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 2599 2599 - 2600 2600 - { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, 2601 2601 - { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, 2602 2602 - { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, 2603 2603 - { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, 2604 2604 - { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, 2605 2605 - { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, 2606 2606 - { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, 2607 2607 - { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, 2608 2608 - { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, 2609 2609 - 2610 2610 - { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, 2611 2611 - { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, 2612 2612 - { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, 2613 2613 - 2614 2614 - { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, 2615 2615 - { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, 2616 2616 - { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 2617 2617 - 2618 2618 - { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, 2619 2619 - { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, 2620 2620 - { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, 2621 2621 - { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, 2622 2622 - { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 2623 2623 - { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, 2624 2624 - 2625 2625 - /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 2626 2626 - { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 2627 2627 - { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 2628 2628 - { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 2629 2629 - { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 2630 2630 - { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 2631 2631 - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 2632 2632 - { 2633 2633 - "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 2634 2634 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2635 2635 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2636 2636 - }, 2637 2637 - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 2638 2638 - { 2639 2639 - "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32, 2640 2640 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2641 2641 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2642 2642 - }, 2643 2643 - { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 2644 2644 - { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 2645 2645 - { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 2646 2646 - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 2647 2647 - { 2648 2648 - "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 2649 2649 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2650 2650 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2651 2651 - }, 2652 2652 - { 2653 2653 - "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 2654 2654 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2655 2655 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2656 2656 - }, 2657 2657 - { 2658 2658 - "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, 2659 2659 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2660 2660 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2661 2661 - }, 2662 2662 - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 2663 2663 - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 2664 2664 - { 2665 2665 - "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 2666 2666 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2667 2667 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2668 2668 - }, 2669 2669 - { 2670 2670 - "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 2671 2671 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2672 2672 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2673 2673 - }, 2674 2674 - { 2675 2675 - "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256, 2676 2676 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2677 2677 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 2678 2678 - }, 2679 2679 - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 2680 2680 - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 2681 2681 - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 2682 2682 - { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, 2683 2683 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 2684 2684 - SPI_NOR_4B_OPCODES) }, 2685 2685 - { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512, 2686 2686 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2687 2687 - { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, 2688 2688 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2689 2689 - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 2690 2690 - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 2691 2691 - 2692 2692 - /* Catalyst / On Semiconductor -- non-JEDEC */ 2693 2693 - { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2694 2694 - { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2695 2695 - { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2696 2696 - { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2697 2697 - { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, 2698 2698 - 2699 2699 - /* Xilinx S3AN Internal Flash */ 2700 2700 - { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, 2701 2701 - { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, 2702 2702 - { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, 2703 2703 - { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, 2704 2704 - { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, 2705 2705 - 2706 2706 - /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 2707 2707 - { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2708 2708 - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 2709 2709 - { }, 2710 2710 - }; 2711 2711 - 2712 2712 - static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 2713 2713 - { 2714 2714 - int tmp; 2715 2715 - u8 *id = nor->bouncebuf; 2716 2716 - const struct flash_info *info; 2717 2717 - 2718 2718 - if (nor->spimem) { 2719 2719 - struct spi_mem_op op = 2720 2720 - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 2721 2721 - SPI_MEM_OP_NO_ADDR, 2722 2722 - SPI_MEM_OP_NO_DUMMY, 2723 2723 - SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); 2724 2724 - 2725 2725 - tmp = spi_mem_exec_op(nor->spimem, &op); 2726 2726 - } else { 2727 2727 - tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 2728 2728 - SPI_NOR_MAX_ID_LEN); 2729 2729 - } 2730 2730 - if (tmp) { 2731 2731 - dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 2732 2732 - return ERR_PTR(tmp); 2733 2733 - } 2734 2734 - 2735 2735 - for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { 2736 2736 - info = &spi_nor_ids[tmp]; 2737 2737 - if (info->id_len) { 2738 2738 - if (!memcmp(info->id, id, info->id_len)) 2739 2739 - return &spi_nor_ids[tmp]; 2740 2740 - } 2741 2741 - } 2742 2742 - dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2743 2743 - SPI_NOR_MAX_ID_LEN, id); 2744 2744 - return ERR_PTR(-ENODEV); 2745 2745 - } 2746 2746 - 2747 2747 - static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2748 2748 - size_t *retlen, u_char *buf) 2749 2749 - { 2750 2750 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2751 2751 - ssize_t ret; 2752 2752 - 2753 2753 - dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2754 2754 - 2755 2755 - ret = spi_nor_lock_and_prep(nor); 2756 2756 - if (ret) 2757 2757 - return ret; 2758 2758 - 2759 2759 - while (len) { 2760 2760 - loff_t addr = from; 2761 2761 - 2762 2762 - addr = spi_nor_convert_addr(nor, addr); 2763 2763 - 2764 2764 - ret = spi_nor_read_data(nor, addr, len, buf); 2765 2765 - if (ret == 0) { 2766 2766 - /* We shouldn't see 0-length reads */ 2767 2767 - ret = -EIO; 2768 2768 - goto read_err; 2769 2769 - } 2770 2770 - if (ret < 0) 2771 2771 - goto read_err; 2772 2772 - 2773 2773 - WARN_ON(ret > len); 2774 2774 - *retlen += ret; 2775 2775 - buf += ret; 2776 2776 - from += ret; 2777 2777 - len -= ret; 2778 2778 - } 2779 2779 - ret = 0; 2780 2780 - 2781 2781 - read_err: 2782 2782 - spi_nor_unlock_and_unprep(nor); 2783 2783 - return ret; 2784 2784 - } 2785 2785 - 2786 2786 - static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 2787 2787 - size_t *retlen, const u_char *buf) 2788 2788 - { 2789 2789 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2790 2790 - size_t actual = 0; 2791 2791 - int ret; 2792 2792 - 2793 2793 - dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2794 2794 - 2795 2795 - ret = spi_nor_lock_and_prep(nor); 2796 2796 - if (ret) 2797 2797 - return ret; 2798 2798 - 2799 2799 - ret = spi_nor_write_enable(nor); 2800 2800 - if (ret) 2801 2801 - goto out; 2802 2802 - 2803 2803 - nor->sst_write_second = false; 2804 2804 - 2805 2805 - /* Start write from odd address. */ 2806 2806 - if (to % 2) { 2807 2807 - nor->program_opcode = SPINOR_OP_BP; 2808 2808 - 2809 2809 - /* write one byte. */ 2810 2810 - ret = spi_nor_write_data(nor, to, 1, buf); 2811 2811 - if (ret < 0) 2812 2812 - goto out; 2813 2813 - WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret); 2814 2814 - ret = spi_nor_wait_till_ready(nor); 2815 2815 - if (ret) 2816 2816 - goto out; 2817 2817 - 2818 2818 - to++; 2819 2819 - actual++; 2820 2820 - } 2821 2821 - 2822 2822 - /* Write out most of the data here. */ 2823 2823 - for (; actual < len - 1; actual += 2) { 2824 2824 - nor->program_opcode = SPINOR_OP_AAI_WP; 2825 2825 - 2826 2826 - /* write two bytes. */ 2827 2827 - ret = spi_nor_write_data(nor, to, 2, buf + actual); 2828 2828 - if (ret < 0) 2829 2829 - goto out; 2830 2830 - WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret); 2831 2831 - ret = spi_nor_wait_till_ready(nor); 2832 2832 - if (ret) 2833 2833 - goto out; 2834 2834 - to += 2; 2835 2835 - nor->sst_write_second = true; 2836 2836 - } 2837 2837 - nor->sst_write_second = false; 2838 2838 - 2839 2839 - ret = spi_nor_write_disable(nor); 2840 2840 - if (ret) 2841 2841 - goto out; 2842 2842 - 2843 2843 - ret = spi_nor_wait_till_ready(nor); 2844 2844 - if (ret) 2845 2845 - goto out; 2846 2846 - 2847 2847 - /* Write out trailing byte if it exists. */ 2848 2848 - if (actual != len) { 2849 2849 - ret = spi_nor_write_enable(nor); 2850 2850 - if (ret) 2851 2851 - goto out; 2852 2852 - 2853 2853 - nor->program_opcode = SPINOR_OP_BP; 2854 2854 - ret = spi_nor_write_data(nor, to, 1, buf + actual); 2855 2855 - if (ret < 0) 2856 2856 - goto out; 2857 2857 - WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret); 2858 2858 - ret = spi_nor_wait_till_ready(nor); 2859 2859 - if (ret) 2860 2860 - goto out; 2861 2861 - 2862 2862 - actual += 1; 2863 2863 - 2864 2864 - ret = spi_nor_write_disable(nor); 2865 2865 - } 2866 2866 - out: 2867 2867 - *retlen += actual; 2868 2868 - spi_nor_unlock_and_unprep(nor); 2869 2869 - return ret; 2870 2870 - } 2871 2871 - 2872 2872 - /* 2873 2873 - * Write an address range to the nor chip. Data must be written in 2874 2874 - * FLASH_PAGESIZE chunks. The address range may be any size provided 2875 2875 - * it is within the physical boundaries. 2876 2876 - */ 2877 2877 - static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2878 2878 - size_t *retlen, const u_char *buf) 2879 2879 - { 2880 2880 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 2881 2881 - size_t page_offset, page_remain, i; 2882 2882 - ssize_t ret; 2883 2883 - 2884 2884 - dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2885 2885 - 2886 2886 - ret = spi_nor_lock_and_prep(nor); 2887 2887 - if (ret) 2888 2888 - return ret; 2889 2889 - 2890 2890 - for (i = 0; i < len; ) { 2891 2891 - ssize_t written; 2892 2892 - loff_t addr = to + i; 2893 2893 - 2894 2894 - /* 2895 2895 - * If page_size is a power of two, the offset can be quickly 2896 2896 - * calculated with an AND operation. On the other cases we 2897 2897 - * need to do a modulus operation (more expensive). 2898 2898 - * Power of two numbers have only one bit set and we can use 2899 2899 - * the instruction hweight32 to detect if we need to do a 2900 2900 - * modulus (do_div()) or not. 2901 2901 - */ 2902 2902 - if (hweight32(nor->page_size) == 1) { 2903 2903 - page_offset = addr & (nor->page_size - 1); 2904 2904 - } else { 2905 2905 - uint64_t aux = addr; 2906 2906 - 2907 2907 - page_offset = do_div(aux, nor->page_size); 2908 2908 - } 2909 2909 - /* the size of data remaining on the first page */ 2910 2910 - page_remain = min_t(size_t, 2911 2911 - nor->page_size - page_offset, len - i); 2912 2912 - 2913 2913 - addr = spi_nor_convert_addr(nor, addr); 2914 2914 - 2915 2915 - ret = spi_nor_write_enable(nor); 2916 2916 - if (ret) 2917 2917 - goto write_err; 2918 2918 - 2919 2919 - ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 2920 2920 - if (ret < 0) 2921 2921 - goto write_err; 2922 2922 - written = ret; 2923 2923 - 2924 2924 - ret = spi_nor_wait_till_ready(nor); 2925 2925 - if (ret) 2926 2926 - goto write_err; 2927 2927 - *retlen += written; 2928 2928 - i += written; 2929 2929 - } 2930 2930 - 2931 2931 - write_err: 2932 2932 - spi_nor_unlock_and_unprep(nor); 2933 2933 - return ret; 2934 2934 - } 2935 2935 - 2936 2936 - static int spi_nor_check(struct spi_nor *nor) 2937 2937 - { 2938 2938 - if (!nor->dev || 2939 2939 - (!nor->spimem && !nor->controller_ops) || 2940 2940 - (!nor->spimem && nor->controller_ops && 2941 2941 - (!nor->controller_ops->read || 2942 2942 - !nor->controller_ops->write || 2943 2943 - !nor->controller_ops->read_reg || 2944 2944 - !nor->controller_ops->write_reg))) { 2945 2945 - pr_err("spi-nor: please fill all the necessary fields!\n"); 2946 2946 - return -EINVAL; 2947 2947 - } 2948 2948 - 2949 2949 - if (nor->spimem && nor->controller_ops) { 2950 2950 - dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2951 2951 - return -EINVAL; 2952 2952 - } 2953 2953 - 2954 2954 - return 0; 2955 2955 - } 2956 2956 - 2957 2957 - static int s3an_nor_setup(struct spi_nor *nor, 2958 2958 - const struct spi_nor_hwcaps *hwcaps) 2959 2959 - { 2960 2960 - int ret; 2961 2961 - 2962 2962 - ret = spi_nor_xread_sr(nor, nor->bouncebuf); 2963 2963 - if (ret) 2964 2964 - return ret; 2965 2965 - 2966 2966 - nor->erase_opcode = SPINOR_OP_XSE; 2967 2967 - nor->program_opcode = SPINOR_OP_XPP; 2968 2968 - nor->read_opcode = SPINOR_OP_READ; 2969 2969 - nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2970 2970 - 2971 2971 - /* 2972 2972 - * This flashes have a page size of 264 or 528 bytes (known as 2973 2973 - * Default addressing mode). It can be changed to a more standard 2974 2974 - * Power of two mode where the page size is 256/512. This comes 2975 2975 - * with a price: there is 3% less of space, the data is corrupted 2976 2976 - * and the page size cannot be changed back to default addressing 2977 2977 - * mode. 2978 2978 - * 2979 2979 - * The current addressing mode can be read from the XRDSR register 2980 2980 - * and should not be changed, because is a destructive operation. 2981 2981 - */ 2982 2982 - if (nor->bouncebuf[0] & XSR_PAGESIZE) { 2983 2983 - /* Flash in Power of 2 mode */ 2984 2984 - nor->page_size = (nor->page_size == 264) ? 256 : 512; 2985 2985 - nor->mtd.writebufsize = nor->page_size; 2986 2986 - nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors; 2987 2987 - nor->mtd.erasesize = 8 * nor->page_size; 2988 2988 - } else { 2989 2989 - /* Flash in Default addressing mode */ 2990 2990 - nor->params.convert_addr = s3an_convert_addr; 2991 2991 - nor->mtd.erasesize = nor->info->sector_size; 2992 2992 - } 2993 2993 - 2994 2994 - return 0; 2995 2995 - } 2996 2996 - 2997 2997 - static void 2998 2998 - spi_nor_set_read_settings(struct spi_nor_read_command *read, 2999 2999 - u8 num_mode_clocks, 3000 3000 - u8 num_wait_states, 3001 3001 - u8 opcode, 3002 3002 - enum spi_nor_protocol proto) 3003 3003 - { 3004 3004 - read->num_mode_clocks = num_mode_clocks; 3005 3005 - read->num_wait_states = num_wait_states; 3006 3006 - read->opcode = opcode; 3007 3007 - read->proto = proto; 3008 3008 - } 3009 3009 - 3010 3010 - static void 3011 3011 - spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 3012 3012 - u8 opcode, 3013 3013 - enum spi_nor_protocol proto) 3014 3014 - { 3015 3015 - pp->opcode = opcode; 3016 3016 - pp->proto = proto; 3017 3017 - } 3018 3018 - 3019 3019 - static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 3020 3020 - { 3021 3021 - size_t i; 3022 3022 - 3023 3023 - for (i = 0; i < size; i++) 3024 3024 - if (table[i][0] == (int)hwcaps) 3025 3025 - return table[i][1]; 3026 3026 - 3027 3027 - return -EINVAL; 3028 3028 - } 3029 3029 - 3030 3030 - static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 3031 3031 - { 3032 3032 - static const int hwcaps_read2cmd[][2] = { 3033 3033 - { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 3034 3034 - { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 3035 3035 - { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 3036 3036 - { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 3037 3037 - { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 3038 3038 - { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 3039 3039 - { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 3040 3040 - { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 3041 3041 - { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 3042 3042 - { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 3043 3043 - { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 3044 3044 - { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 3045 3045 - { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 3046 3046 - { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 3047 3047 - { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 3048 3048 - }; 3049 3049 - 3050 3050 - return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 3051 3051 - ARRAY_SIZE(hwcaps_read2cmd)); 3052 3052 - } 3053 3053 - 3054 3054 - static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 3055 3055 - { 3056 3056 - static const int hwcaps_pp2cmd[][2] = { 3057 3057 - { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 3058 3058 - { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 3059 3059 - { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 3060 3060 - { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 3061 3061 - { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 3062 3062 - { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 3063 3063 - { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 3064 3064 - }; 3065 3065 - 3066 3066 - return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 3067 3067 - ARRAY_SIZE(hwcaps_pp2cmd)); 3068 3068 - } 3069 3069 - 3070 3070 - /* 3071 3071 - * Serial Flash Discoverable Parameters (SFDP) parsing. 3072 3072 - */ 3073 3073 - 3074 3074 - /** 3075 3075 - * spi_nor_read_raw() - raw read of serial flash memory. read_opcode, 3076 3076 - * addr_width and read_dummy members of the struct spi_nor 3077 3077 - * should be previously 3078 3078 - * set. 3079 3079 - * @nor: pointer to a 'struct spi_nor' 3080 3080 - * @addr: offset in the serial flash memory 3081 3081 - * @len: number of bytes to read 3082 3082 - * @buf: buffer where the data is copied into (dma-safe memory) 3083 3083 - * 3084 3084 - * Return: 0 on success, -errno otherwise. 3085 3085 - */ 3086 3086 - static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf) 3087 3087 - { 3088 3088 - ssize_t ret; 3089 3089 - 3090 3090 - while (len) { 3091 3091 - ret = spi_nor_read_data(nor, addr, len, buf); 3092 3092 - if (ret < 0) 3093 3093 - return ret; 3094 3094 - if (!ret || ret > len) 3095 3095 - return -EIO; 3096 3096 - 3097 3097 - buf += ret; 3098 3098 - addr += ret; 3099 3099 - len -= ret; 3100 3100 - } 3101 3101 - return 0; 3102 3102 - } 3103 3103 - 3104 3104 - /** 3105 3105 - * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 3106 3106 - * @nor: pointer to a 'struct spi_nor' 3107 3107 - * @addr: offset in the SFDP area to start reading data from 3108 3108 - * @len: number of bytes to read 3109 3109 - * @buf: buffer where the SFDP data are copied into (dma-safe memory) 3110 3110 - * 3111 3111 - * Whatever the actual numbers of bytes for address and dummy cycles are 3112 3112 - * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 3113 3113 - * followed by a 3-byte address and 8 dummy clock cycles. 3114 3114 - * 3115 3115 - * Return: 0 on success, -errno otherwise. 3116 3116 - */ 3117 3117 - static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 3118 3118 - size_t len, void *buf) 3119 3119 - { 3120 3120 - u8 addr_width, read_opcode, read_dummy; 3121 3121 - int ret; 3122 3122 - 3123 3123 - read_opcode = nor->read_opcode; 3124 3124 - addr_width = nor->addr_width; 3125 3125 - read_dummy = nor->read_dummy; 3126 3126 - 3127 3127 - nor->read_opcode = SPINOR_OP_RDSFDP; 3128 3128 - nor->addr_width = 3; 3129 3129 - nor->read_dummy = 8; 3130 3130 - 3131 3131 - ret = spi_nor_read_raw(nor, addr, len, buf); 3132 3132 - 3133 3133 - nor->read_opcode = read_opcode; 3134 3134 - nor->addr_width = addr_width; 3135 3135 - nor->read_dummy = read_dummy; 3136 3136 - 3137 3137 - return ret; 3138 3138 - } 3139 3139 - 3140 3140 - /** 3141 3141 - * spi_nor_spimem_check_op - check if the operation is supported 3142 3142 - * by controller 3143 3143 - *@nor: pointer to a 'struct spi_nor' 3144 3144 - *@op: pointer to op template to be checked 3145 3145 - * 3146 3146 - * Returns 0 if operation is supported, -ENOTSUPP otherwise. 3147 3147 - */ 3148 3148 - static int spi_nor_spimem_check_op(struct spi_nor *nor, 3149 3149 - struct spi_mem_op *op) 3150 3150 - { 3151 3151 - /* 3152 3152 - * First test with 4 address bytes. The opcode itself might 3153 3153 - * be a 3B addressing opcode but we don't care, because 3154 3154 - * SPI controller implementation should not check the opcode, 3155 3155 - * but just the sequence. 3156 3156 - */ 3157 3157 - op->addr.nbytes = 4; 3158 3158 - if (!spi_mem_supports_op(nor->spimem, op)) { 3159 3159 - if (nor->mtd.size > SZ_16M) 3160 3160 - return -ENOTSUPP; 3161 3161 - 3162 3162 - /* If flash size <= 16MB, 3 address bytes are sufficient */ 3163 3163 - op->addr.nbytes = 3; 3164 3164 - if (!spi_mem_supports_op(nor->spimem, op)) 3165 3165 - return -ENOTSUPP; 3166 3166 - } 3167 3167 - 3168 3168 - return 0; 3169 3169 - } 3170 3170 - 3171 3171 - /** 3172 3172 - * spi_nor_spimem_check_readop - check if the read op is supported 3173 3173 - * by controller 3174 3174 - *@nor: pointer to a 'struct spi_nor' 3175 3175 - *@read: pointer to op template to be checked 3176 3176 - * 3177 3177 - * Returns 0 if operation is supported, -ENOTSUPP otherwise. 3178 3178 - */ 3179 3179 - static int spi_nor_spimem_check_readop(struct spi_nor *nor, 3180 3180 - const struct spi_nor_read_command *read) 3181 3181 - { 3182 3182 - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1), 3183 3183 - SPI_MEM_OP_ADDR(3, 0, 1), 3184 3184 - SPI_MEM_OP_DUMMY(0, 1), 3185 3185 - SPI_MEM_OP_DATA_IN(0, NULL, 1)); 3186 3186 - 3187 3187 - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto); 3188 3188 - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto); 3189 3189 - op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto); 3190 3190 - op.dummy.buswidth = op.addr.buswidth; 3191 3191 - op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * 3192 3192 - op.dummy.buswidth / 8; 3193 3193 - 3194 3194 - return spi_nor_spimem_check_op(nor, &op); 3195 3195 - } 3196 3196 - 3197 3197 - /** 3198 3198 - * spi_nor_spimem_check_pp - check if the page program op is supported 3199 3199 - * by controller 3200 3200 - *@nor: pointer to a 'struct spi_nor' 3201 3201 - *@pp: pointer to op template to be checked 3202 3202 - * 3203 3203 - * Returns 0 if operation is supported, -ENOTSUPP otherwise. 3204 3204 - */ 3205 3205 - static int spi_nor_spimem_check_pp(struct spi_nor *nor, 3206 3206 - const struct spi_nor_pp_command *pp) 3207 3207 - { 3208 3208 - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1), 3209 3209 - SPI_MEM_OP_ADDR(3, 0, 1), 3210 3210 - SPI_MEM_OP_NO_DUMMY, 3211 3211 - SPI_MEM_OP_DATA_OUT(0, NULL, 1)); 3212 3212 - 3213 3213 - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto); 3214 3214 - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); 3215 3215 - op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); 3216 3216 - 3217 3217 - return spi_nor_spimem_check_op(nor, &op); 3218 3218 - } 3219 3219 - 3220 3220 - /** 3221 3221 - * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 3222 3222 - * based on SPI controller capabilities 3223 3223 - * @nor: pointer to a 'struct spi_nor' 3224 3224 - * @hwcaps: pointer to resulting capabilities after adjusting 3225 3225 - * according to controller and flash's capability 3226 3226 - */ 3227 3227 - static void 3228 3228 - spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 3229 3229 - { 3230 3230 - struct spi_nor_flash_parameter *params = &nor->params; 3231 3231 - unsigned int cap; 3232 3232 - 3233 3233 - /* DTR modes are not supported yet, mask them all. */ 3234 3234 - *hwcaps &= ~SNOR_HWCAPS_DTR; 3235 3235 - 3236 3236 - /* X-X-X modes are not supported yet, mask them all. */ 3237 3237 - *hwcaps &= ~SNOR_HWCAPS_X_X_X; 3238 3238 - 3239 3239 - for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 3240 3240 - int rdidx, ppidx; 3241 3241 - 3242 3242 - if (!(*hwcaps & BIT(cap))) 3243 3243 - continue; 3244 3244 - 3245 3245 - rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 3246 3246 - if (rdidx >= 0 && 3247 3247 - spi_nor_spimem_check_readop(nor, &params->reads[rdidx])) 3248 3248 - *hwcaps &= ~BIT(cap); 3249 3249 - 3250 3250 - ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 3251 3251 - if (ppidx < 0) 3252 3252 - continue; 3253 3253 - 3254 3254 - if (spi_nor_spimem_check_pp(nor, 3255 3255 - &params->page_programs[ppidx])) 3256 3256 - *hwcaps &= ~BIT(cap); 3257 3257 - } 3258 3258 - } 3259 3259 - 3260 3260 - /** 3261 3261 - * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. 3262 3262 - * @nor: pointer to a 'struct spi_nor' 3263 3263 - * @addr: offset in the SFDP area to start reading data from 3264 3264 - * @len: number of bytes to read 3265 3265 - * @buf: buffer where the SFDP data are copied into 3266 3266 - * 3267 3267 - * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not 3268 3268 - * guaranteed to be dma-safe. 3269 3269 - * 3270 3270 - * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() 3271 3271 - * otherwise. 3272 3272 - */ 3273 3273 - static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, 3274 3274 - size_t len, void *buf) 3275 3275 - { 3276 3276 - void *dma_safe_buf; 3277 3277 - int ret; 3278 3278 - 3279 3279 - dma_safe_buf = kmalloc(len, GFP_KERNEL); 3280 3280 - if (!dma_safe_buf) 3281 3281 - return -ENOMEM; 3282 3282 - 3283 3283 - ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); 3284 3284 - memcpy(buf, dma_safe_buf, len); 3285 3285 - kfree(dma_safe_buf); 3286 3286 - 3287 3287 - return ret; 3288 3288 - } 3289 3289 - 3290 3290 - /* Fast Read settings. */ 3291 3291 - 3292 3292 - static void 3293 3293 - spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 3294 3294 - u16 half, 3295 3295 - enum spi_nor_protocol proto) 3296 3296 - { 3297 3297 - read->num_mode_clocks = (half >> 5) & 0x07; 3298 3298 - read->num_wait_states = (half >> 0) & 0x1f; 3299 3299 - read->opcode = (half >> 8) & 0xff; 3300 3300 - read->proto = proto; 3301 3301 - } 3302 3302 - 3303 3303 - struct sfdp_bfpt_read { 3304 3304 - /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 3305 3305 - u32 hwcaps; 3306 3306 - 3307 3307 - /* 3308 3308 - * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 3309 3309 - * whether the Fast Read x-y-z command is supported. 3310 3310 - */ 3311 3311 - u32 supported_dword; 3312 3312 - u32 supported_bit; 3313 3313 - 3314 3314 - /* 3315 3315 - * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 3316 3316 - * encodes the op code, the number of mode clocks and the number of wait 3317 3317 - * states to be used by Fast Read x-y-z command. 3318 3318 - */ 3319 3319 - u32 settings_dword; 3320 3320 - u32 settings_shift; 3321 3321 - 3322 3322 - /* The SPI protocol for this Fast Read x-y-z command. */ 3323 3323 - enum spi_nor_protocol proto; 3324 3324 - }; 3325 3325 - 3326 3326 - static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 3327 3327 - /* Fast Read 1-1-2 */ 3328 3328 - { 3329 3329 - SNOR_HWCAPS_READ_1_1_2, 3330 3330 - BFPT_DWORD(1), BIT(16), /* Supported bit */ 3331 3331 - BFPT_DWORD(4), 0, /* Settings */ 3332 3332 - SNOR_PROTO_1_1_2, 3333 3333 - }, 3334 3334 - 3335 3335 - /* Fast Read 1-2-2 */ 3336 3336 - { 3337 3337 - SNOR_HWCAPS_READ_1_2_2, 3338 3338 - BFPT_DWORD(1), BIT(20), /* Supported bit */ 3339 3339 - BFPT_DWORD(4), 16, /* Settings */ 3340 3340 - SNOR_PROTO_1_2_2, 3341 3341 - }, 3342 3342 - 3343 3343 - /* Fast Read 2-2-2 */ 3344 3344 - { 3345 3345 - SNOR_HWCAPS_READ_2_2_2, 3346 3346 - BFPT_DWORD(5), BIT(0), /* Supported bit */ 3347 3347 - BFPT_DWORD(6), 16, /* Settings */ 3348 3348 - SNOR_PROTO_2_2_2, 3349 3349 - }, 3350 3350 - 3351 3351 - /* Fast Read 1-1-4 */ 3352 3352 - { 3353 3353 - SNOR_HWCAPS_READ_1_1_4, 3354 3354 - BFPT_DWORD(1), BIT(22), /* Supported bit */ 3355 3355 - BFPT_DWORD(3), 16, /* Settings */ 3356 3356 - SNOR_PROTO_1_1_4, 3357 3357 - }, 3358 3358 - 3359 3359 - /* Fast Read 1-4-4 */ 3360 3360 - { 3361 3361 - SNOR_HWCAPS_READ_1_4_4, 3362 3362 - BFPT_DWORD(1), BIT(21), /* Supported bit */ 3363 3363 - BFPT_DWORD(3), 0, /* Settings */ 3364 3364 - SNOR_PROTO_1_4_4, 3365 3365 - }, 3366 3366 - 3367 3367 - /* Fast Read 4-4-4 */ 3368 3368 - { 3369 3369 - SNOR_HWCAPS_READ_4_4_4, 3370 3370 - BFPT_DWORD(5), BIT(4), /* Supported bit */ 3371 3371 - BFPT_DWORD(7), 16, /* Settings */ 3372 3372 - SNOR_PROTO_4_4_4, 3373 3373 - }, 3374 3374 - }; 3375 3375 - 3376 3376 - struct sfdp_bfpt_erase { 3377 3377 - /* 3378 3378 - * The half-word at offset <shift> in DWORD <dwoard> encodes the 3379 3379 - * op code and erase sector size to be used by Sector Erase commands. 3380 3380 - */ 3381 3381 - u32 dword; 3382 3382 - u32 shift; 3383 3383 - }; 3384 3384 - 3385 3385 - static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 3386 3386 - /* Erase Type 1 in DWORD8 bits[15:0] */ 3387 3387 - {BFPT_DWORD(8), 0}, 3388 3388 - 3389 3389 - /* Erase Type 2 in DWORD8 bits[31:16] */ 3390 3390 - {BFPT_DWORD(8), 16}, 3391 3391 - 3392 3392 - /* Erase Type 3 in DWORD9 bits[15:0] */ 3393 3393 - {BFPT_DWORD(9), 0}, 3394 3394 - 3395 3395 - /* Erase Type 4 in DWORD9 bits[31:16] */ 3396 3396 - {BFPT_DWORD(9), 16}, 3397 3397 - }; 3398 3398 - 3399 3399 - /** 3400 3400 - * spi_nor_set_erase_type() - set a SPI NOR erase type 3401 3401 - * @erase: pointer to a structure that describes a SPI NOR erase type 3402 3402 - * @size: the size of the sector/block erased by the erase type 3403 3403 - * @opcode: the SPI command op code to erase the sector/block 3404 3404 - */ 3405 3405 - static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, 3406 3406 - u32 size, u8 opcode) 3407 3407 - { 3408 3408 - erase->size = size; 3409 3409 - erase->opcode = opcode; 3410 3410 - /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 3411 3411 - erase->size_shift = ffs(erase->size) - 1; 3412 3412 - erase->size_mask = (1 << erase->size_shift) - 1; 3413 3413 - } 3414 3414 - 3415 3415 - /** 3416 3416 - * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT 3417 3417 - * @erase: pointer to a structure that describes a SPI NOR erase type 3418 3418 - * @size: the size of the sector/block erased by the erase type 3419 3419 - * @opcode: the SPI command op code to erase the sector/block 3420 3420 - * @i: erase type index as sorted in the Basic Flash Parameter Table 3421 3421 - * 3422 3422 - * The supported Erase Types will be sorted at init in ascending order, with 3423 3423 - * the smallest Erase Type size being the first member in the erase_type array 3424 3424 - * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in 3425 3425 - * the Basic Flash Parameter Table since it will be used later on to 3426 3426 - * synchronize with the supported Erase Types defined in SFDP optional tables. 3427 3427 - */ 3428 3428 - static void 3429 3429 - spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase, 3430 3430 - u32 size, u8 opcode, u8 i) 3431 3431 - { 3432 3432 - erase->idx = i; 3433 3433 - spi_nor_set_erase_type(erase, size, opcode); 3434 3434 - } 3435 3435 - 3436 3436 - /** 3437 3437 - * spi_nor_map_cmp_erase_type() - compare the map's erase types by size 3438 3438 - * @l: member in the left half of the map's erase_type array 3439 3439 - * @r: member in the right half of the map's erase_type array 3440 3440 - * 3441 3441 - * Comparison function used in the sort() call to sort in ascending order the 3442 3442 - * map's erase types, the smallest erase type size being the first member in the 3443 3443 - * sorted erase_type array. 3444 3444 - * 3445 3445 - * Return: the result of @l->size - @r->size 3446 3446 - */ 3447 3447 - static int spi_nor_map_cmp_erase_type(const void *l, const void *r) 3448 3448 - { 3449 3449 - const struct spi_nor_erase_type *left = l, *right = r; 3450 3450 - 3451 3451 - return left->size - right->size; 3452 3452 - } 3453 3453 - 3454 3454 - /** 3455 3455 - * spi_nor_sort_erase_mask() - sort erase mask 3456 3456 - * @map: the erase map of the SPI NOR 3457 3457 - * @erase_mask: the erase type mask to be sorted 3458 3458 - * 3459 3459 - * Replicate the sort done for the map's erase types in BFPT: sort the erase 3460 3460 - * mask in ascending order with the smallest erase type size starting from 3461 3461 - * BIT(0) in the sorted erase mask. 3462 3462 - * 3463 3463 - * Return: sorted erase mask. 3464 3464 - */ 3465 3465 - static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask) 3466 3466 - { 3467 3467 - struct spi_nor_erase_type *erase_type = map->erase_type; 3468 3468 - int i; 3469 3469 - u8 sorted_erase_mask = 0; 3470 3470 - 3471 3471 - if (!erase_mask) 3472 3472 - return 0; 3473 3473 - 3474 3474 - /* Replicate the sort done for the map's erase types. */ 3475 3475 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) 3476 3476 - if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx)) 3477 3477 - sorted_erase_mask |= BIT(i); 3478 3478 - 3479 3479 - return sorted_erase_mask; 3480 3480 - } 3481 3481 - 3482 3482 - /** 3483 3483 - * spi_nor_regions_sort_erase_types() - sort erase types in each region 3484 3484 - * @map: the erase map of the SPI NOR 3485 3485 - * 3486 3486 - * Function assumes that the erase types defined in the erase map are already 3487 3487 - * sorted in ascending order, with the smallest erase type size being the first 3488 3488 - * member in the erase_type array. It replicates the sort done for the map's 3489 3489 - * erase types. Each region's erase bitmask will indicate which erase types are 3490 3490 - * supported from the sorted erase types defined in the erase map. 3491 3491 - * Sort the all region's erase type at init in order to speed up the process of 3492 3492 - * finding the best erase command at runtime. 3493 3493 - */ 3494 3494 - static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map) 3495 3495 - { 3496 3496 - struct spi_nor_erase_region *region = map->regions; 3497 3497 - u8 region_erase_mask, sorted_erase_mask; 3498 3498 - 3499 3499 - while (region) { 3500 3500 - region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 3501 3501 - 3502 3502 - sorted_erase_mask = spi_nor_sort_erase_mask(map, 3503 3503 - region_erase_mask); 3504 3504 - 3505 3505 - /* Overwrite erase mask. */ 3506 3506 - region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) | 3507 3507 - sorted_erase_mask; 3508 3508 - 3509 3509 - region = spi_nor_region_next(region); 3510 3510 - } 3511 3511 - } 3512 3512 - 3513 3513 - /** 3514 3514 - * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 3515 3515 - * @map: the erase map of the SPI NOR 3516 3516 - * @erase_mask: bitmask encoding erase types that can erase the entire 3517 3517 - * flash memory 3518 3518 - * @flash_size: the spi nor flash memory size 3519 3519 - */ 3520 3520 - static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 3521 3521 - u8 erase_mask, u64 flash_size) 3522 3522 - { 3523 3523 - /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 3524 3524 - map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 3525 3525 - SNOR_LAST_REGION; 3526 3526 - map->uniform_region.size = flash_size; 3527 3527 - map->regions = &map->uniform_region; 3528 3528 - map->uniform_erase_type = erase_mask; 3529 3529 - } 3530 3530 - 3531 3531 - static int 3532 3532 - spi_nor_post_bfpt_fixups(struct spi_nor *nor, 3533 3533 - const struct sfdp_parameter_header *bfpt_header, 3534 3534 - const struct sfdp_bfpt *bfpt, 3535 3535 - struct spi_nor_flash_parameter *params) 3536 3536 - { 3537 3537 - if (nor->info->fixups && nor->info->fixups->post_bfpt) 3538 3538 - return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt, 3539 3539 - params); 3540 3540 - 3541 3541 - return 0; 3542 3542 - } 3543 3543 - 3544 3544 - /** 3545 3545 - * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 3546 3546 - * @nor: pointer to a 'struct spi_nor' 3547 3547 - * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 3548 3548 - * the Basic Flash Parameter Table length and version 3549 3549 - * @params: pointer to the 'struct spi_nor_flash_parameter' to be 3550 3550 - * filled 3551 3551 - * 3552 3552 - * The Basic Flash Parameter Table is the main and only mandatory table as 3553 3553 - * defined by the SFDP (JESD216) specification. 3554 3554 - * It provides us with the total size (memory density) of the data array and 3555 3555 - * the number of address bytes for Fast Read, Page Program and Sector Erase 3556 3556 - * commands. 3557 3557 - * For Fast READ commands, it also gives the number of mode clock cycles and 3558 3558 - * wait states (regrouped in the number of dummy clock cycles) for each 3559 3559 - * supported instruction op code. 3560 3560 - * For Page Program, the page size is now available since JESD216 rev A, however 3561 3561 - * the supported instruction op codes are still not provided. 3562 3562 - * For Sector Erase commands, this table stores the supported instruction op 3563 3563 - * codes and the associated sector sizes. 3564 3564 - * Finally, the Quad Enable Requirements (QER) are also available since JESD216 3565 3565 - * rev A. The QER bits encode the manufacturer dependent procedure to be 3566 3566 - * executed to set the Quad Enable (QE) bit in some internal register of the 3567 3567 - * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 3568 3568 - * sending any Quad SPI command to the memory. Actually, setting the QE bit 3569 3569 - * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 3570 3570 - * and IO3 hence enabling 4 (Quad) I/O lines. 3571 3571 - * 3572 3572 - * Return: 0 on success, -errno otherwise. 3573 3573 - */ 3574 3574 - static int spi_nor_parse_bfpt(struct spi_nor *nor, 3575 3575 - const struct sfdp_parameter_header *bfpt_header, 3576 3576 - struct spi_nor_flash_parameter *params) 3577 3577 - { 3578 3578 - struct spi_nor_erase_map *map = &params->erase_map; 3579 3579 - struct spi_nor_erase_type *erase_type = map->erase_type; 3580 3580 - struct sfdp_bfpt bfpt; 3581 3581 - size_t len; 3582 3582 - int i, cmd, err; 3583 3583 - u32 addr; 3584 3584 - u16 half; 3585 3585 - u8 erase_mask; 3586 3586 - 3587 3587 - /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 3588 3588 - if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 3589 3589 - return -EINVAL; 3590 3590 - 3591 3591 - /* Read the Basic Flash Parameter Table. */ 3592 3592 - len = min_t(size_t, sizeof(bfpt), 3593 3593 - bfpt_header->length * sizeof(u32)); 3594 3594 - addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 3595 3595 - memset(&bfpt, 0, sizeof(bfpt)); 3596 3596 - err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); 3597 3597 - if (err < 0) 3598 3598 - return err; 3599 3599 - 3600 3600 - /* Fix endianness of the BFPT DWORDs. */ 3601 3601 - for (i = 0; i < BFPT_DWORD_MAX; i++) 3602 3602 - bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 3603 3603 - 3604 3604 - /* Number of address bytes. */ 3605 3605 - switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 3606 3606 - case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 3607 3607 - nor->addr_width = 3; 3608 3608 - break; 3609 3609 - 3610 3610 - case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 3611 3611 - nor->addr_width = 4; 3612 3612 - break; 3613 3613 - 3614 3614 - default: 3615 3615 - break; 3616 3616 - } 3617 3617 - 3618 3618 - /* Flash Memory Density (in bits). */ 3619 3619 - params->size = bfpt.dwords[BFPT_DWORD(2)]; 3620 3620 - if (params->size & BIT(31)) { 3621 3621 - params->size &= ~BIT(31); 3622 3622 - 3623 3623 - /* 3624 3624 - * Prevent overflows on params->size. Anyway, a NOR of 2^64 3625 3625 - * bits is unlikely to exist so this error probably means 3626 3626 - * the BFPT we are reading is corrupted/wrong. 3627 3627 - */ 3628 3628 - if (params->size > 63) 3629 3629 - return -EINVAL; 3630 3630 - 3631 3631 - params->size = 1ULL << params->size; 3632 3632 - } else { 3633 3633 - params->size++; 3634 3634 - } 3635 3635 - params->size >>= 3; /* Convert to bytes. */ 3636 3636 - 3637 3637 - /* Fast Read settings. */ 3638 3638 - for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 3639 3639 - const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 3640 3640 - struct spi_nor_read_command *read; 3641 3641 - 3642 3642 - if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 3643 3643 - params->hwcaps.mask &= ~rd->hwcaps; 3644 3644 - continue; 3645 3645 - } 3646 3646 - 3647 3647 - params->hwcaps.mask |= rd->hwcaps; 3648 3648 - cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 3649 3649 - read = &params->reads[cmd]; 3650 3650 - half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 3651 3651 - spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 3652 3652 - } 3653 3653 - 3654 3654 - /* 3655 3655 - * Sector Erase settings. Reinitialize the uniform erase map using the 3656 3656 - * Erase Types defined in the bfpt table. 3657 3657 - */ 3658 3658 - erase_mask = 0; 3659 3659 - memset(&params->erase_map, 0, sizeof(params->erase_map)); 3660 3660 - for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 3661 3661 - const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 3662 3662 - u32 erasesize; 3663 3663 - u8 opcode; 3664 3664 - 3665 3665 - half = bfpt.dwords[er->dword] >> er->shift; 3666 3666 - erasesize = half & 0xff; 3667 3667 - 3668 3668 - /* erasesize == 0 means this Erase Type is not supported. */ 3669 3669 - if (!erasesize) 3670 3670 - continue; 3671 3671 - 3672 3672 - erasesize = 1U << erasesize; 3673 3673 - opcode = (half >> 8) & 0xff; 3674 3674 - erase_mask |= BIT(i); 3675 3675 - spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize, 3676 3676 - opcode, i); 3677 3677 - } 3678 3678 - spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 3679 3679 - /* 3680 3680 - * Sort all the map's Erase Types in ascending order with the smallest 3681 3681 - * erase size being the first member in the erase_type array. 3682 3682 - */ 3683 3683 - sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]), 3684 3684 - spi_nor_map_cmp_erase_type, NULL); 3685 3685 - /* 3686 3686 - * Sort the erase types in the uniform region in order to update the 3687 3687 - * uniform_erase_type bitmask. The bitmask will be used later on when 3688 3688 - * selecting the uniform erase. 3689 3689 - */ 3690 3690 - spi_nor_regions_sort_erase_types(map); 3691 3691 - map->uniform_erase_type = map->uniform_region.offset & 3692 3692 - SNOR_ERASE_TYPE_MASK; 3693 3693 - 3694 3694 - /* Stop here if not JESD216 rev A or later. */ 3695 3695 - if (bfpt_header->length < BFPT_DWORD_MAX) 3696 3696 - return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, 3697 3697 - params); 3698 3698 - 3699 3699 - /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 3700 3700 - params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 3701 3701 - params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 3702 3702 - params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 3703 3703 - params->page_size = 1U << params->page_size; 3704 3704 - 3705 3705 - /* Quad Enable Requirements. */ 3706 3706 - switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 3707 3707 - case BFPT_DWORD15_QER_NONE: 3708 3708 - params->quad_enable = NULL; 3709 3709 - break; 3710 3710 - 3711 3711 - case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 3712 3712 - /* 3713 3713 - * Writing only one byte to the Status Register has the 3714 3714 - * side-effect of clearing Status Register 2. 3715 3715 - */ 3716 3716 - case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 3717 3717 - /* 3718 3718 - * Read Configuration Register (35h) instruction is not 3719 3719 - * supported. 3720 3720 - */ 3721 3721 - nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; 3722 3722 - params->quad_enable = spi_nor_sr2_bit1_quad_enable; 3723 3723 - break; 3724 3724 - 3725 3725 - case BFPT_DWORD15_QER_SR1_BIT6: 3726 3726 - nor->flags &= ~SNOR_F_HAS_16BIT_SR; 3727 3727 - params->quad_enable = spi_nor_sr1_bit6_quad_enable; 3728 3728 - break; 3729 3729 - 3730 3730 - case BFPT_DWORD15_QER_SR2_BIT7: 3731 3731 - nor->flags &= ~SNOR_F_HAS_16BIT_SR; 3732 3732 - params->quad_enable = spi_nor_sr2_bit7_quad_enable; 3733 3733 - break; 3734 3734 - 3735 3735 - case BFPT_DWORD15_QER_SR2_BIT1: 3736 3736 - /* 3737 3737 - * JESD216 rev B or later does not specify if writing only one 3738 3738 - * byte to the Status Register clears or not the Status 3739 3739 - * Register 2, so let's be cautious and keep the default 3740 3740 - * assumption of a 16-bit Write Status (01h) command. 3741 3741 - */ 3742 3742 - nor->flags |= SNOR_F_HAS_16BIT_SR; 3743 3743 - 3744 3744 - params->quad_enable = spi_nor_sr2_bit1_quad_enable; 3745 3745 - break; 3746 3746 - 3747 3747 - default: 3748 3748 - return -EINVAL; 3749 3749 - } 3750 3750 - 3751 3751 - return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); 3752 3752 - } 3753 3753 - 3754 3754 - #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22) 3755 3755 - #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22) 3756 3756 - #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22) 3757 3757 - #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22) 3758 3758 - #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22) 3759 3759 - 3760 3760 - #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16) 3761 3761 - #define SMPT_CMD_READ_DUMMY_SHIFT 16 3762 3762 - #define SMPT_CMD_READ_DUMMY(_cmd) \ 3763 3763 - (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT) 3764 3764 - #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL 3765 3765 - 3766 3766 - #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24) 3767 3767 - #define SMPT_CMD_READ_DATA_SHIFT 24 3768 3768 - #define SMPT_CMD_READ_DATA(_cmd) \ 3769 3769 - (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT) 3770 3770 - 3771 3771 - #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8) 3772 3772 - #define SMPT_CMD_OPCODE_SHIFT 8 3773 3773 - #define SMPT_CMD_OPCODE(_cmd) \ 3774 3774 - (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT) 3775 3775 - 3776 3776 - #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16) 3777 3777 - #define SMPT_MAP_REGION_COUNT_SHIFT 16 3778 3778 - #define SMPT_MAP_REGION_COUNT(_header) \ 3779 3779 - ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \ 3780 3780 - SMPT_MAP_REGION_COUNT_SHIFT) + 1) 3781 3781 - 3782 3782 - #define SMPT_MAP_ID_MASK GENMASK(15, 8) 3783 3783 - #define SMPT_MAP_ID_SHIFT 8 3784 3784 - #define SMPT_MAP_ID(_header) \ 3785 3785 - (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT) 3786 3786 - 3787 3787 - #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8) 3788 3788 - #define SMPT_MAP_REGION_SIZE_SHIFT 8 3789 3789 - #define SMPT_MAP_REGION_SIZE(_region) \ 3790 3790 - (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \ 3791 3791 - SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256) 3792 3792 - 3793 3793 - #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0) 3794 3794 - #define SMPT_MAP_REGION_ERASE_TYPE(_region) \ 3795 3795 - ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK) 3796 3796 - 3797 3797 - #define SMPT_DESC_TYPE_MAP BIT(1) 3798 3798 - #define SMPT_DESC_END BIT(0) 3799 3799 - 3800 3800 - /** 3801 3801 - * spi_nor_smpt_addr_width() - return the address width used in the 3802 3802 - * configuration detection command. 3803 3803 - * @nor: pointer to a 'struct spi_nor' 3804 3804 - * @settings: configuration detection command descriptor, dword1 3805 3805 - */ 3806 3806 - static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings) 3807 3807 - { 3808 3808 - switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) { 3809 3809 - case SMPT_CMD_ADDRESS_LEN_0: 3810 3810 - return 0; 3811 3811 - case SMPT_CMD_ADDRESS_LEN_3: 3812 3812 - return 3; 3813 3813 - case SMPT_CMD_ADDRESS_LEN_4: 3814 3814 - return 4; 3815 3815 - case SMPT_CMD_ADDRESS_LEN_USE_CURRENT: 3816 3816 - /* fall through */ 3817 3817 - default: 3818 3818 - return nor->addr_width; 3819 3819 - } 3820 3820 - } 3821 3821 - 3822 3822 - /** 3823 3823 - * spi_nor_smpt_read_dummy() - return the configuration detection command read 3824 3824 - * latency, in clock cycles. 3825 3825 - * @nor: pointer to a 'struct spi_nor' 3826 3826 - * @settings: configuration detection command descriptor, dword1 3827 3827 - * 3828 3828 - * Return: the number of dummy cycles for an SMPT read 3829 3829 - */ 3830 3830 - static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings) 3831 3831 - { 3832 3832 - u8 read_dummy = SMPT_CMD_READ_DUMMY(settings); 3833 3833 - 3834 3834 - if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE) 3835 3835 - return nor->read_dummy; 3836 3836 - return read_dummy; 3837 3837 - } 3838 3838 - 3839 3839 - /** 3840 3840 - * spi_nor_get_map_in_use() - get the configuration map in use 3841 3841 - * @nor: pointer to a 'struct spi_nor' 3842 3842 - * @smpt: pointer to the sector map parameter table 3843 3843 - * @smpt_len: sector map parameter table length 3844 3844 - * 3845 3845 - * Return: pointer to the map in use, ERR_PTR(-errno) otherwise. 3846 3846 - */ 3847 3847 - static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt, 3848 3848 - u8 smpt_len) 3849 3849 - { 3850 3850 - const u32 *ret; 3851 3851 - u8 *buf; 3852 3852 - u32 addr; 3853 3853 - int err; 3854 3854 - u8 i; 3855 3855 - u8 addr_width, read_opcode, read_dummy; 3856 3856 - u8 read_data_mask, map_id; 3857 3857 - 3858 3858 - /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */ 3859 3859 - buf = kmalloc(sizeof(*buf), GFP_KERNEL); 3860 3860 - if (!buf) 3861 3861 - return ERR_PTR(-ENOMEM); 3862 3862 - 3863 3863 - addr_width = nor->addr_width; 3864 3864 - read_dummy = nor->read_dummy; 3865 3865 - read_opcode = nor->read_opcode; 3866 3866 - 3867 3867 - map_id = 0; 3868 3868 - /* Determine if there are any optional Detection Command Descriptors */ 3869 3869 - for (i = 0; i < smpt_len; i += 2) { 3870 3870 - if (smpt[i] & SMPT_DESC_TYPE_MAP) 3871 3871 - break; 3872 3872 - 3873 3873 - read_data_mask = SMPT_CMD_READ_DATA(smpt[i]); 3874 3874 - nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]); 3875 3875 - nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]); 3876 3876 - nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]); 3877 3877 - addr = smpt[i + 1]; 3878 3878 - 3879 3879 - err = spi_nor_read_raw(nor, addr, 1, buf); 3880 3880 - if (err) { 3881 3881 - ret = ERR_PTR(err); 3882 3882 - goto out; 3883 3883 - } 3884 3884 - 3885 3885 - /* 3886 3886 - * Build an index value that is used to select the Sector Map 3887 3887 - * Configuration that is currently in use. 3888 3888 - */ 3889 3889 - map_id = map_id << 1 | !!(*buf & read_data_mask); 3890 3890 - } 3891 3891 - 3892 3892 - /* 3893 3893 - * If command descriptors are provided, they always precede map 3894 3894 - * descriptors in the table. There is no need to start the iteration 3895 3895 - * over smpt array all over again. 3896 3896 - * 3897 3897 - * Find the matching configuration map. 3898 3898 - */ 3899 3899 - ret = ERR_PTR(-EINVAL); 3900 3900 - while (i < smpt_len) { 3901 3901 - if (SMPT_MAP_ID(smpt[i]) == map_id) { 3902 3902 - ret = smpt + i; 3903 3903 - break; 3904 3904 - } 3905 3905 - 3906 3906 - /* 3907 3907 - * If there are no more configuration map descriptors and no 3908 3908 - * configuration ID matched the configuration identifier, the 3909 3909 - * sector address map is unknown. 3910 3910 - */ 3911 3911 - if (smpt[i] & SMPT_DESC_END) 3912 3912 - break; 3913 3913 - 3914 3914 - /* increment the table index to the next map */ 3915 3915 - i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1; 3916 3916 - } 3917 3917 - 3918 3918 - /* fall through */ 3919 3919 - out: 3920 3920 - kfree(buf); 3921 3921 - nor->addr_width = addr_width; 3922 3922 - nor->read_dummy = read_dummy; 3923 3923 - nor->read_opcode = read_opcode; 3924 3924 - return ret; 3925 3925 - } 3926 3926 - 3927 3927 - /** 3928 3928 - * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid 3929 3929 - * @region: pointer to a structure that describes a SPI NOR erase region 3930 3930 - * @erase: pointer to a structure that describes a SPI NOR erase type 3931 3931 - * @erase_type: erase type bitmask 3932 3932 - */ 3933 3933 - static void 3934 3934 - spi_nor_region_check_overlay(struct spi_nor_erase_region *region, 3935 3935 - const struct spi_nor_erase_type *erase, 3936 3936 - const u8 erase_type) 3937 3937 - { 3938 3938 - int i; 3939 3939 - 3940 3940 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 3941 3941 - if (!(erase_type & BIT(i))) 3942 3942 - continue; 3943 3943 - if (region->size & erase[i].size_mask) { 3944 3944 - spi_nor_region_mark_overlay(region); 3945 3945 - return; 3946 3946 - } 3947 3947 - } 3948 3948 - } 3949 3949 - 3950 3950 - /** 3951 3951 - * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map 3952 3952 - * @nor: pointer to a 'struct spi_nor' 3953 3953 - * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is 3954 3954 - * used for storing SFDP parsed data 3955 3955 - * @smpt: pointer to the sector map parameter table 3956 3956 - * 3957 3957 - * Return: 0 on success, -errno otherwise. 3958 3958 - */ 3959 3959 - static int 3960 3960 - spi_nor_init_non_uniform_erase_map(struct spi_nor *nor, 3961 3961 - struct spi_nor_flash_parameter *params, 3962 3962 - const u32 *smpt) 3963 3963 - { 3964 3964 - struct spi_nor_erase_map *map = &params->erase_map; 3965 3965 - struct spi_nor_erase_type *erase = map->erase_type; 3966 3966 - struct spi_nor_erase_region *region; 3967 3967 - u64 offset; 3968 3968 - u32 region_count; 3969 3969 - int i, j; 3970 3970 - u8 uniform_erase_type, save_uniform_erase_type; 3971 3971 - u8 erase_type, regions_erase_type; 3972 3972 - 3973 3973 - region_count = SMPT_MAP_REGION_COUNT(*smpt); 3974 3974 - /* 3975 3975 - * The regions will be freed when the driver detaches from the 3976 3976 - * device. 3977 3977 - */ 3978 3978 - region = devm_kcalloc(nor->dev, region_count, sizeof(*region), 3979 3979 - GFP_KERNEL); 3980 3980 - if (!region) 3981 3981 - return -ENOMEM; 3982 3982 - map->regions = region; 3983 3983 - 3984 3984 - uniform_erase_type = 0xff; 3985 3985 - regions_erase_type = 0; 3986 3986 - offset = 0; 3987 3987 - /* Populate regions. */ 3988 3988 - for (i = 0; i < region_count; i++) { 3989 3989 - j = i + 1; /* index for the region dword */ 3990 3990 - region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]); 3991 3991 - erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]); 3992 3992 - region[i].offset = offset | erase_type; 3993 3993 - 3994 3994 - spi_nor_region_check_overlay(&region[i], erase, erase_type); 3995 3995 - 3996 3996 - /* 3997 3997 - * Save the erase types that are supported in all regions and 3998 3998 - * can erase the entire flash memory. 3999 3999 - */ 4000 4000 - uniform_erase_type &= erase_type; 4001 4001 - 4002 4002 - /* 4003 4003 - * regions_erase_type mask will indicate all the erase types 4004 4004 - * supported in this configuration map. 4005 4005 - */ 4006 4006 - regions_erase_type |= erase_type; 4007 4007 - 4008 4008 - offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) + 4009 4009 - region[i].size; 4010 4010 - } 4011 4011 - 4012 4012 - save_uniform_erase_type = map->uniform_erase_type; 4013 4013 - map->uniform_erase_type = spi_nor_sort_erase_mask(map, 4014 4014 - uniform_erase_type); 4015 4015 - 4016 4016 - if (!regions_erase_type) { 4017 4017 - /* 4018 4018 - * Roll back to the previous uniform_erase_type mask, SMPT is 4019 4019 - * broken. 4020 4020 - */ 4021 4021 - map->uniform_erase_type = save_uniform_erase_type; 4022 4022 - return -EINVAL; 4023 4023 - } 4024 4024 - 4025 4025 - /* 4026 4026 - * BFPT advertises all the erase types supported by all the possible 4027 4027 - * map configurations. Mask out the erase types that are not supported 4028 4028 - * by the current map configuration. 4029 4029 - */ 4030 4030 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) 4031 4031 - if (!(regions_erase_type & BIT(erase[i].idx))) 4032 4032 - spi_nor_set_erase_type(&erase[i], 0, 0xFF); 4033 4033 - 4034 4034 - spi_nor_region_mark_end(&region[i - 1]); 4035 4035 - 4036 4036 - return 0; 4037 4037 - } 4038 4038 - 4039 4039 - /** 4040 4040 - * spi_nor_parse_smpt() - parse Sector Map Parameter Table 4041 4041 - * @nor: pointer to a 'struct spi_nor' 4042 4042 - * @smpt_header: sector map parameter table header 4043 4043 - * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' 4044 4044 - * that is used for storing SFDP parsed data 4045 4045 - * 4046 4046 - * This table is optional, but when available, we parse it to identify the 4047 4047 - * location and size of sectors within the main data array of the flash memory 4048 4048 - * device and to identify which Erase Types are supported by each sector. 4049 4049 - * 4050 4050 - * Return: 0 on success, -errno otherwise. 4051 4051 - */ 4052 4052 - static int spi_nor_parse_smpt(struct spi_nor *nor, 4053 4053 - const struct sfdp_parameter_header *smpt_header, 4054 4054 - struct spi_nor_flash_parameter *params) 4055 4055 - { 4056 4056 - const u32 *sector_map; 4057 4057 - u32 *smpt; 4058 4058 - size_t len; 4059 4059 - u32 addr; 4060 4060 - int i, ret; 4061 4061 - 4062 4062 - /* Read the Sector Map Parameter Table. */ 4063 4063 - len = smpt_header->length * sizeof(*smpt); 4064 4064 - smpt = kmalloc(len, GFP_KERNEL); 4065 4065 - if (!smpt) 4066 4066 - return -ENOMEM; 4067 4067 - 4068 4068 - addr = SFDP_PARAM_HEADER_PTP(smpt_header); 4069 4069 - ret = spi_nor_read_sfdp(nor, addr, len, smpt); 4070 4070 - if (ret) 4071 4071 - goto out; 4072 4072 - 4073 4073 - /* Fix endianness of the SMPT DWORDs. */ 4074 4074 - for (i = 0; i < smpt_header->length; i++) 4075 4075 - smpt[i] = le32_to_cpu(smpt[i]); 4076 4076 - 4077 4077 - sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length); 4078 4078 - if (IS_ERR(sector_map)) { 4079 4079 - ret = PTR_ERR(sector_map); 4080 4080 - goto out; 4081 4081 - } 4082 4082 - 4083 4083 - ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map); 4084 4084 - if (ret) 4085 4085 - goto out; 4086 4086 - 4087 4087 - spi_nor_regions_sort_erase_types(&params->erase_map); 4088 4088 - /* fall through */ 4089 4089 - out: 4090 4090 - kfree(smpt); 4091 4091 - return ret; 4092 4092 - } 4093 4093 - 4094 4094 - #define SFDP_4BAIT_DWORD_MAX 2 4095 4095 - 4096 4096 - struct sfdp_4bait { 4097 4097 - /* The hardware capability. */ 4098 4098 - u32 hwcaps; 4099 4099 - 4100 4100 - /* 4101 4101 - * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether 4102 4102 - * the associated 4-byte address op code is supported. 4103 4103 - */ 4104 4104 - u32 supported_bit; 4105 4105 - }; 4106 4106 - 4107 4107 - /** 4108 4108 - * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table 4109 4109 - * @nor: pointer to a 'struct spi_nor'. 4110 4110 - * @param_header: pointer to the 'struct sfdp_parameter_header' describing 4111 4111 - * the 4-Byte Address Instruction Table length and version. 4112 4112 - * @params: pointer to the 'struct spi_nor_flash_parameter' to be. 4113 4113 - * 4114 4114 - * Return: 0 on success, -errno otherwise. 4115 4115 - */ 4116 4116 - static int spi_nor_parse_4bait(struct spi_nor *nor, 4117 4117 - const struct sfdp_parameter_header *param_header, 4118 4118 - struct spi_nor_flash_parameter *params) 4119 4119 - { 4120 4120 - static const struct sfdp_4bait reads[] = { 4121 4121 - { SNOR_HWCAPS_READ, BIT(0) }, 4122 4122 - { SNOR_HWCAPS_READ_FAST, BIT(1) }, 4123 4123 - { SNOR_HWCAPS_READ_1_1_2, BIT(2) }, 4124 4124 - { SNOR_HWCAPS_READ_1_2_2, BIT(3) }, 4125 4125 - { SNOR_HWCAPS_READ_1_1_4, BIT(4) }, 4126 4126 - { SNOR_HWCAPS_READ_1_4_4, BIT(5) }, 4127 4127 - { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) }, 4128 4128 - { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) }, 4129 4129 - { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) }, 4130 4130 - }; 4131 4131 - static const struct sfdp_4bait programs[] = { 4132 4132 - { SNOR_HWCAPS_PP, BIT(6) }, 4133 4133 - { SNOR_HWCAPS_PP_1_1_4, BIT(7) }, 4134 4134 - { SNOR_HWCAPS_PP_1_4_4, BIT(8) }, 4135 4135 - }; 4136 4136 - static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = { 4137 4137 - { 0u /* not used */, BIT(9) }, 4138 4138 - { 0u /* not used */, BIT(10) }, 4139 4139 - { 0u /* not used */, BIT(11) }, 4140 4140 - { 0u /* not used */, BIT(12) }, 4141 4141 - }; 4142 4142 - struct spi_nor_pp_command *params_pp = params->page_programs; 4143 4143 - struct spi_nor_erase_map *map = &params->erase_map; 4144 4144 - struct spi_nor_erase_type *erase_type = map->erase_type; 4145 4145 - u32 *dwords; 4146 4146 - size_t len; 4147 4147 - u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask; 4148 4148 - int i, ret; 4149 4149 - 4150 4150 - if (param_header->major != SFDP_JESD216_MAJOR || 4151 4151 - param_header->length < SFDP_4BAIT_DWORD_MAX) 4152 4152 - return -EINVAL; 4153 4153 - 4154 4154 - /* Read the 4-byte Address Instruction Table. */ 4155 4155 - len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX; 4156 4156 - 4157 4157 - /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */ 4158 4158 - dwords = kmalloc(len, GFP_KERNEL); 4159 4159 - if (!dwords) 4160 4160 - return -ENOMEM; 4161 4161 - 4162 4162 - addr = SFDP_PARAM_HEADER_PTP(param_header); 4163 4163 - ret = spi_nor_read_sfdp(nor, addr, len, dwords); 4164 4164 - if (ret) 4165 4165 - goto out; 4166 4166 - 4167 4167 - /* Fix endianness of the 4BAIT DWORDs. */ 4168 4168 - for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++) 4169 4169 - dwords[i] = le32_to_cpu(dwords[i]); 4170 4170 - 4171 4171 - /* 4172 4172 - * Compute the subset of (Fast) Read commands for which the 4-byte 4173 4173 - * version is supported. 4174 4174 - */ 4175 4175 - discard_hwcaps = 0; 4176 4176 - read_hwcaps = 0; 4177 4177 - for (i = 0; i < ARRAY_SIZE(reads); i++) { 4178 4178 - const struct sfdp_4bait *read = &reads[i]; 4179 4179 - 4180 4180 - discard_hwcaps |= read->hwcaps; 4181 4181 - if ((params->hwcaps.mask & read->hwcaps) && 4182 4182 - (dwords[0] & read->supported_bit)) 4183 4183 - read_hwcaps |= read->hwcaps; 4184 4184 - } 4185 4185 - 4186 4186 - /* 4187 4187 - * Compute the subset of Page Program commands for which the 4-byte 4188 4188 - * version is supported. 4189 4189 - */ 4190 4190 - pp_hwcaps = 0; 4191 4191 - for (i = 0; i < ARRAY_SIZE(programs); i++) { 4192 4192 - const struct sfdp_4bait *program = &programs[i]; 4193 4193 - 4194 4194 - /* 4195 4195 - * The 4 Byte Address Instruction (Optional) Table is the only 4196 4196 - * SFDP table that indicates support for Page Program Commands. 4197 4197 - * Bypass the params->hwcaps.mask and consider 4BAIT the biggest 4198 4198 - * authority for specifying Page Program support. 4199 4199 - */ 4200 4200 - discard_hwcaps |= program->hwcaps; 4201 4201 - if (dwords[0] & program->supported_bit) 4202 4202 - pp_hwcaps |= program->hwcaps; 4203 4203 - } 4204 4204 - 4205 4205 - /* 4206 4206 - * Compute the subset of Sector Erase commands for which the 4-byte 4207 4207 - * version is supported. 4208 4208 - */ 4209 4209 - erase_mask = 0; 4210 4210 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 4211 4211 - const struct sfdp_4bait *erase = &erases[i]; 4212 4212 - 4213 4213 - if (dwords[0] & erase->supported_bit) 4214 4214 - erase_mask |= BIT(i); 4215 4215 - } 4216 4216 - 4217 4217 - /* Replicate the sort done for the map's erase types in BFPT. */ 4218 4218 - erase_mask = spi_nor_sort_erase_mask(map, erase_mask); 4219 4219 - 4220 4220 - /* 4221 4221 - * We need at least one 4-byte op code per read, program and erase 4222 4222 - * operation; the .read(), .write() and .erase() hooks share the 4223 4223 - * nor->addr_width value. 4224 4224 - */ 4225 4225 - if (!read_hwcaps || !pp_hwcaps || !erase_mask) 4226 4226 - goto out; 4227 4227 - 4228 4228 - /* 4229 4229 - * Discard all operations from the 4-byte instruction set which are 4230 4230 - * not supported by this memory. 4231 4231 - */ 4232 4232 - params->hwcaps.mask &= ~discard_hwcaps; 4233 4233 - params->hwcaps.mask |= (read_hwcaps | pp_hwcaps); 4234 4234 - 4235 4235 - /* Use the 4-byte address instruction set. */ 4236 4236 - for (i = 0; i < SNOR_CMD_READ_MAX; i++) { 4237 4237 - struct spi_nor_read_command *read_cmd = &params->reads[i]; 4238 4238 - 4239 4239 - read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode); 4240 4240 - } 4241 4241 - 4242 4242 - /* 4BAIT is the only SFDP table that indicates page program support. */ 4243 4243 - if (pp_hwcaps & SNOR_HWCAPS_PP) 4244 4244 - spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP], 4245 4245 - SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 4246 4246 - if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4) 4247 4247 - spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_1_4], 4248 4248 - SPINOR_OP_PP_1_1_4_4B, 4249 4249 - SNOR_PROTO_1_1_4); 4250 4250 - if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4) 4251 4251 - spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_4_4], 4252 4252 - SPINOR_OP_PP_1_4_4_4B, 4253 4253 - SNOR_PROTO_1_4_4); 4254 4254 - 4255 4255 - for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 4256 4256 - if (erase_mask & BIT(i)) 4257 4257 - erase_type[i].opcode = (dwords[1] >> 4258 4258 - erase_type[i].idx * 8) & 0xFF; 4259 4259 - else 4260 4260 - spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF); 4261 4261 - } 4262 4262 - 4263 4263 - /* 4264 4264 - * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes() 4265 4265 - * later because we already did the conversion to 4byte opcodes. Also, 4266 4266 - * this latest function implements a legacy quirk for the erase size of 4267 4267 - * Spansion memory. However this quirk is no longer needed with new 4268 4268 - * SFDP compliant memories. 4269 4269 - */ 4270 4270 - nor->addr_width = 4; 4271 4271 - nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT; 4272 4272 - 4273 4273 - /* fall through */ 4274 4274 - out: 4275 4275 - kfree(dwords); 4276 4276 - return ret; 4277 4277 - } 4278 4278 - 4279 4279 - /** 4280 4280 - * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 4281 4281 - * @nor: pointer to a 'struct spi_nor' 4282 4282 - * @params: pointer to the 'struct spi_nor_flash_parameter' to be 4283 4283 - * filled 4284 4284 - * 4285 4285 - * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 4286 4286 - * specification. This is a standard which tends to supported by almost all 4287 4287 - * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 4288 4288 - * runtime the main parameters needed to perform basic SPI flash operations such 4289 4289 - * as Fast Read, Page Program or Sector Erase commands. 4290 4290 - * 4291 4291 - * Return: 0 on success, -errno otherwise. 4292 4292 - */ 4293 4293 - static int spi_nor_parse_sfdp(struct spi_nor *nor, 4294 4294 - struct spi_nor_flash_parameter *params) 4295 4295 - { 4296 4296 - const struct sfdp_parameter_header *param_header, *bfpt_header; 4297 4297 - struct sfdp_parameter_header *param_headers = NULL; 4298 4298 - struct sfdp_header header; 4299 4299 - struct device *dev = nor->dev; 4300 4300 - size_t psize; 4301 4301 - int i, err; 4302 4302 - 4303 4303 - /* Get the SFDP header. */ 4304 4304 - err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); 4305 4305 - if (err < 0) 4306 4306 - return err; 4307 4307 - 4308 4308 - /* Check the SFDP header version. */ 4309 4309 - if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 4310 4310 - header.major != SFDP_JESD216_MAJOR) 4311 4311 - return -EINVAL; 4312 4312 - 4313 4313 - /* 4314 4314 - * Verify that the first and only mandatory parameter header is a 4315 4315 - * Basic Flash Parameter Table header as specified in JESD216. 4316 4316 - */ 4317 4317 - bfpt_header = &header.bfpt_header; 4318 4318 - if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 4319 4319 - bfpt_header->major != SFDP_JESD216_MAJOR) 4320 4320 - return -EINVAL; 4321 4321 - 4322 4322 - /* 4323 4323 - * Allocate memory then read all parameter headers with a single 4324 4324 - * Read SFDP command. These parameter headers will actually be parsed 4325 4325 - * twice: a first time to get the latest revision of the basic flash 4326 4326 - * parameter table, then a second time to handle the supported optional 4327 4327 - * tables. 4328 4328 - * Hence we read the parameter headers once for all to reduce the 4329 4329 - * processing time. Also we use kmalloc() instead of devm_kmalloc() 4330 4330 - * because we don't need to keep these parameter headers: the allocated 4331 4331 - * memory is always released with kfree() before exiting this function. 4332 4332 - */ 4333 4333 - if (header.nph) { 4334 4334 - psize = header.nph * sizeof(*param_headers); 4335 4335 - 4336 4336 - param_headers = kmalloc(psize, GFP_KERNEL); 4337 4337 - if (!param_headers) 4338 4338 - return -ENOMEM; 4339 4339 - 4340 4340 - err = spi_nor_read_sfdp(nor, sizeof(header), 4341 4341 - psize, param_headers); 4342 4342 - if (err < 0) { 4343 4343 - dev_dbg(dev, "failed to read SFDP parameter headers\n"); 4344 4344 - goto exit; 4345 4345 - } 4346 4346 - } 4347 4347 - 4348 4348 - /* 4349 4349 - * Check other parameter headers to get the latest revision of 4350 4350 - * the basic flash parameter table. 4351 4351 - */ 4352 4352 - for (i = 0; i < header.nph; i++) { 4353 4353 - param_header = &param_headers[i]; 4354 4354 - 4355 4355 - if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 4356 4356 - param_header->major == SFDP_JESD216_MAJOR && 4357 4357 - (param_header->minor > bfpt_header->minor || 4358 4358 - (param_header->minor == bfpt_header->minor && 4359 4359 - param_header->length > bfpt_header->length))) 4360 4360 - bfpt_header = param_header; 4361 4361 - } 4362 4362 - 4363 4363 - err = spi_nor_parse_bfpt(nor, bfpt_header, params); 4364 4364 - if (err) 4365 4365 - goto exit; 4366 4366 - 4367 4367 - /* Parse optional parameter tables. */ 4368 4368 - for (i = 0; i < header.nph; i++) { 4369 4369 - param_header = &param_headers[i]; 4370 4370 - 4371 4371 - switch (SFDP_PARAM_HEADER_ID(param_header)) { 4372 4372 - case SFDP_SECTOR_MAP_ID: 4373 4373 - err = spi_nor_parse_smpt(nor, param_header, params); 4374 4374 - break; 4375 4375 - 4376 4376 - case SFDP_4BAIT_ID: 4377 4377 - err = spi_nor_parse_4bait(nor, param_header, params); 4378 4378 - break; 4379 4379 - 4380 4380 - default: 4381 4381 - break; 4382 4382 - } 4383 4383 - 4384 4384 - if (err) { 4385 4385 - dev_warn(dev, "Failed to parse optional parameter table: %04x\n", 4386 4386 - SFDP_PARAM_HEADER_ID(param_header)); 4387 4387 - /* 4388 4388 - * Let's not drop all information we extracted so far 4389 4389 - * if optional table parsers fail. In case of failing, 4390 4390 - * each optional parser is responsible to roll back to 4391 4391 - * the previously known spi_nor data. 4392 4392 - */ 4393 4393 - err = 0; 4394 4394 - } 4395 4395 - } 4396 4396 - 4397 4397 - exit: 4398 4398 - kfree(param_headers); 4399 4399 - return err; 4400 4400 - } 4401 4401 - 4402 4402 - static int spi_nor_select_read(struct spi_nor *nor, 4403 4403 - u32 shared_hwcaps) 4404 4404 - { 4405 4405 - int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 4406 4406 - const struct spi_nor_read_command *read; 4407 4407 - 4408 4408 - if (best_match < 0) 4409 4409 - return -EINVAL; 4410 4410 - 4411 4411 - cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 4412 4412 - if (cmd < 0) 4413 4413 - return -EINVAL; 4414 4414 - 4415 4415 - read = &nor->params.reads[cmd]; 4416 4416 - nor->read_opcode = read->opcode; 4417 4417 - nor->read_proto = read->proto; 4418 4418 - 4419 4419 - /* 4420 4420 - * In the spi-nor framework, we don't need to make the difference 4421 4421 - * between mode clock cycles and wait state clock cycles. 4422 4422 - * Indeed, the value of the mode clock cycles is used by a QSPI 4423 4423 - * flash memory to know whether it should enter or leave its 0-4-4 4424 4424 - * (Continuous Read / XIP) mode. 4425 4425 - * eXecution In Place is out of the scope of the mtd sub-system. 4426 4426 - * Hence we choose to merge both mode and wait state clock cycles 4427 4427 - * into the so called dummy clock cycles. 4428 4428 - */ 4429 4429 - nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 4430 4430 - return 0; 4431 4431 - } 4432 4432 - 4433 4433 - static int spi_nor_select_pp(struct spi_nor *nor, 4434 4434 - u32 shared_hwcaps) 4435 4435 - { 4436 4436 - int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 4437 4437 - const struct spi_nor_pp_command *pp; 4438 4438 - 4439 4439 - if (best_match < 0) 4440 4440 - return -EINVAL; 4441 4441 - 4442 4442 - cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 4443 4443 - if (cmd < 0) 4444 4444 - return -EINVAL; 4445 4445 - 4446 4446 - pp = &nor->params.page_programs[cmd]; 4447 4447 - nor->program_opcode = pp->opcode; 4448 4448 - nor->write_proto = pp->proto; 4449 4449 - return 0; 4450 4450 - } 4451 4451 - 4452 4452 - /** 4453 4453 - * spi_nor_select_uniform_erase() - select optimum uniform erase type 4454 4454 - * @map: the erase map of the SPI NOR 4455 4455 - * @wanted_size: the erase type size to search for. Contains the value of 4456 4456 - * info->sector_size or of the "small sector" size in case 4457 4457 - * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined. 4458 4458 - * 4459 4459 - * Once the optimum uniform sector erase command is found, disable all the 4460 4460 - * other. 4461 4461 - * 4462 4462 - * Return: pointer to erase type on success, NULL otherwise. 4463 4463 - */ 4464 4464 - static const struct spi_nor_erase_type * 4465 4465 - spi_nor_select_uniform_erase(struct spi_nor_erase_map *map, 4466 4466 - const u32 wanted_size) 4467 4467 - { 4468 4468 - const struct spi_nor_erase_type *tested_erase, *erase = NULL; 4469 4469 - int i; 4470 4470 - u8 uniform_erase_type = map->uniform_erase_type; 4471 4471 - 4472 4472 - for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 4473 4473 - if (!(uniform_erase_type & BIT(i))) 4474 4474 - continue; 4475 4475 - 4476 4476 - tested_erase = &map->erase_type[i]; 4477 4477 - 4478 4478 - /* 4479 4479 - * If the current erase size is the one, stop here: 4480 4480 - * we have found the right uniform Sector Erase command. 4481 4481 - */ 4482 4482 - if (tested_erase->size == wanted_size) { 4483 4483 - erase = tested_erase; 4484 4484 - break; 4485 4485 - } 4486 4486 - 4487 4487 - /* 4488 4488 - * Otherwise, the current erase size is still a valid canditate. 4489 4489 - * Select the biggest valid candidate. 4490 4490 - */ 4491 4491 - if (!erase && tested_erase->size) 4492 4492 - erase = tested_erase; 4493 4493 - /* keep iterating to find the wanted_size */ 4494 4494 - } 4495 4495 - 4496 4496 - if (!erase) 4497 4497 - return NULL; 4498 4498 - 4499 4499 - /* Disable all other Sector Erase commands. */ 4500 4500 - map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 4501 4501 - map->uniform_erase_type |= BIT(erase - map->erase_type); 4502 4502 - return erase; 4503 4503 - } 4504 4504 - 4505 4505 - static int spi_nor_select_erase(struct spi_nor *nor) 4506 4506 - { 4507 4507 - struct spi_nor_erase_map *map = &nor->params.erase_map; 4508 4508 - const struct spi_nor_erase_type *erase = NULL; 4509 4509 - struct mtd_info *mtd = &nor->mtd; 4510 4510 - u32 wanted_size = nor->info->sector_size; 4511 4511 - int i; 4512 4512 - 4513 4513 - /* 4514 4514 - * The previous implementation handling Sector Erase commands assumed 4515 4515 - * that the SPI flash memory has an uniform layout then used only one 4516 4516 - * of the supported erase sizes for all Sector Erase commands. 4517 4517 - * So to be backward compatible, the new implementation also tries to 4518 4518 - * manage the SPI flash memory as uniform with a single erase sector 4519 4519 - * size, when possible. 4520 4520 - */ 4521 4521 - #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 4522 4522 - /* prefer "small sector" erase if possible */ 4523 4523 - wanted_size = 4096u; 4524 4524 - #endif 4525 4525 - 4526 4526 - if (spi_nor_has_uniform_erase(nor)) { 4527 4527 - erase = spi_nor_select_uniform_erase(map, wanted_size); 4528 4528 - if (!erase) 4529 4529 - return -EINVAL; 4530 4530 - nor->erase_opcode = erase->opcode; 4531 4531 - mtd->erasesize = erase->size; 4532 4532 - return 0; 4533 4533 - } 4534 4534 - 4535 4535 - /* 4536 4536 - * For non-uniform SPI flash memory, set mtd->erasesize to the 4537 4537 - * maximum erase sector size. No need to set nor->erase_opcode. 4538 4538 - */ 4539 4539 - for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 4540 4540 - if (map->erase_type[i].size) { 4541 4541 - erase = &map->erase_type[i]; 4542 4542 - break; 4543 4543 - } 4544 4544 - } 4545 4545 - 4546 4546 - if (!erase) 4547 4547 - return -EINVAL; 4548 4548 - 4549 4549 - mtd->erasesize = erase->size; 4550 4550 - return 0; 4551 4551 - } 4552 4552 - 4553 4553 - static int spi_nor_default_setup(struct spi_nor *nor, 4554 4554 - const struct spi_nor_hwcaps *hwcaps) 4555 4555 - { 4556 4556 - struct spi_nor_flash_parameter *params = &nor->params; 4557 4557 - u32 ignored_mask, shared_mask; 4558 4558 - int err; 4559 4559 - 4560 4560 - /* 4561 4561 - * Keep only the hardware capabilities supported by both the SPI 4562 4562 - * controller and the SPI flash memory. 4563 4563 - */ 4564 4564 - shared_mask = hwcaps->mask & params->hwcaps.mask; 4565 4565 - 4566 4566 - if (nor->spimem) { 4567 4567 - /* 4568 4568 - * When called from spi_nor_probe(), all caps are set and we 4569 4569 - * need to discard some of them based on what the SPI 4570 4570 - * controller actually supports (using spi_mem_supports_op()). 4571 4571 - */ 4572 4572 - spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 4573 4573 - } else { 4574 4574 - /* 4575 4575 - * SPI n-n-n protocols are not supported when the SPI 4576 4576 - * controller directly implements the spi_nor interface. 4577 4577 - * Yet another reason to switch to spi-mem. 4578 4578 - */ 4579 4579 - ignored_mask = SNOR_HWCAPS_X_X_X; 4580 4580 - if (shared_mask & ignored_mask) { 4581 4581 - dev_dbg(nor->dev, 4582 4582 - "SPI n-n-n protocols are not supported.\n"); 4583 4583 - shared_mask &= ~ignored_mask; 4584 4584 - } 4585 4585 - } 4586 4586 - 4587 4587 - /* Select the (Fast) Read command. */ 4588 4588 - err = spi_nor_select_read(nor, shared_mask); 4589 4589 - if (err) { 4590 4590 - dev_dbg(nor->dev, 4591 4591 - "can't select read settings supported by both the SPI controller and memory.\n"); 4592 4592 - return err; 4593 4593 - } 4594 4594 - 4595 4595 - /* Select the Page Program command. */ 4596 4596 - err = spi_nor_select_pp(nor, shared_mask); 4597 4597 - if (err) { 4598 4598 - dev_dbg(nor->dev, 4599 4599 - "can't select write settings supported by both the SPI controller and memory.\n"); 4600 4600 - return err; 4601 4601 - } 4602 4602 - 4603 4603 - /* Select the Sector Erase command. */ 4604 4604 - err = spi_nor_select_erase(nor); 4605 4605 - if (err) { 4606 4606 - dev_dbg(nor->dev, 4607 4607 - "can't select erase settings supported by both the SPI controller and memory.\n"); 4608 4608 - return err; 4609 4609 - } 4610 4610 - 4611 4611 - return 0; 4612 4612 - } 4613 4613 - 4614 4614 - static int spi_nor_setup(struct spi_nor *nor, 4615 4615 - const struct spi_nor_hwcaps *hwcaps) 4616 4616 - { 4617 4617 - if (!nor->params.setup) 4618 4618 - return 0; 4619 4619 - 4620 4620 - return nor->params.setup(nor, hwcaps); 4621 4621 - } 4622 4622 - 4623 4623 - static void atmel_set_default_init(struct spi_nor *nor) 4624 4624 - { 4625 4625 - nor->flags |= SNOR_F_HAS_LOCK; 4626 4626 - } 4627 4627 - 4628 4628 - static void intel_set_default_init(struct spi_nor *nor) 4629 4629 - { 4630 4630 - nor->flags |= SNOR_F_HAS_LOCK; 4631 4631 - } 4632 4632 - 4633 4633 - static void issi_set_default_init(struct spi_nor *nor) 4634 4634 - { 4635 4635 - nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; 4636 4636 - } 4637 4637 - 4638 4638 - static void macronix_set_default_init(struct spi_nor *nor) 4639 4639 - { 4640 4640 - nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; 4641 4641 - nor->params.set_4byte = macronix_set_4byte; 4642 4642 - } 4643 4643 - 4644 4644 - static void sst_set_default_init(struct spi_nor *nor) 4645 4645 - { 4646 4646 - nor->flags |= SNOR_F_HAS_LOCK; 4647 4647 - } 4648 4648 - 4649 4649 - static void st_micron_set_default_init(struct spi_nor *nor) 4650 4650 - { 4651 4651 - nor->flags |= SNOR_F_HAS_LOCK; 4652 4652 - nor->flags &= ~SNOR_F_HAS_16BIT_SR; 4653 4653 - nor->params.quad_enable = NULL; 4654 4654 - nor->params.set_4byte = st_micron_set_4byte; 4655 4655 - } 4656 4656 - 4657 4657 - static void winbond_set_default_init(struct spi_nor *nor) 4658 4658 - { 4659 4659 - nor->params.set_4byte = winbond_set_4byte; 4660 4660 - } 4661 4661 - 4662 4662 - /** 4663 4663 - * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 4664 4664 - * settings based on MFR register and ->default_init() hook. 4665 4665 - * @nor: pointer to a 'struct spi-nor'. 4666 4666 - */ 4667 4667 - static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 4668 4668 - { 4669 4669 - /* Init flash parameters based on MFR */ 4670 4670 - switch (JEDEC_MFR(nor->info)) { 4671 4671 - case SNOR_MFR_ATMEL: 4672 4672 - atmel_set_default_init(nor); 4673 4673 - break; 4674 4674 - 4675 4675 - case SNOR_MFR_INTEL: 4676 4676 - intel_set_default_init(nor); 4677 4677 - break; 4678 4678 - 4679 4679 - case SNOR_MFR_ISSI: 4680 4680 - issi_set_default_init(nor); 4681 4681 - break; 4682 4682 - 4683 4683 - case SNOR_MFR_MACRONIX: 4684 4684 - macronix_set_default_init(nor); 4685 4685 - break; 4686 4686 - 4687 4687 - case SNOR_MFR_ST: 4688 4688 - case SNOR_MFR_MICRON: 4689 4689 - st_micron_set_default_init(nor); 4690 4690 - break; 4691 4691 - 4692 4692 - case SNOR_MFR_SST: 4693 4693 - sst_set_default_init(nor); 4694 4694 - break; 4695 4695 - 4696 4696 - case SNOR_MFR_WINBOND: 4697 4697 - winbond_set_default_init(nor); 4698 4698 - break; 4699 4699 - 4700 4700 - default: 4701 4701 - break; 4702 4702 - } 4703 4703 - 4704 4704 - if (nor->info->fixups && nor->info->fixups->default_init) 4705 4705 - nor->info->fixups->default_init(nor); 4706 4706 - } 4707 4707 - 4708 4708 - /** 4709 4709 - * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings 4710 4710 - * based on JESD216 SFDP standard. 4711 4711 - * @nor: pointer to a 'struct spi-nor'. 4712 4712 - * 4713 4713 - * The method has a roll-back mechanism: in case the SFDP parsing fails, the 4714 4714 - * legacy flash parameters and settings will be restored. 4715 4715 - */ 4716 4716 - static void spi_nor_sfdp_init_params(struct spi_nor *nor) 4717 4717 - { 4718 4718 - struct spi_nor_flash_parameter sfdp_params; 4719 4719 - 4720 4720 - memcpy(&sfdp_params, &nor->params, sizeof(sfdp_params)); 4721 4721 - 4722 4722 - if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 4723 4723 - nor->addr_width = 0; 4724 4724 - nor->flags &= ~SNOR_F_4B_OPCODES; 4725 4725 - } else { 4726 4726 - memcpy(&nor->params, &sfdp_params, sizeof(nor->params)); 4727 4727 - } 4728 4728 - } 4729 4729 - 4730 4730 - /** 4731 4731 - * spi_nor_info_init_params() - Initialize the flash's parameters and settings 4732 4732 - * based on nor->info data. 4733 4733 - * @nor: pointer to a 'struct spi-nor'. 4734 4734 - */ 4735 4735 - static void spi_nor_info_init_params(struct spi_nor *nor) 4736 4736 - { 4737 4737 - struct spi_nor_flash_parameter *params = &nor->params; 4738 4738 - struct spi_nor_erase_map *map = &params->erase_map; 4739 4739 - const struct flash_info *info = nor->info; 4740 4740 - struct device_node *np = spi_nor_get_flash_node(nor); 4741 4741 - u8 i, erase_mask; 4742 4742 - 4743 4743 - /* Initialize legacy flash parameters and settings. */ 4744 4744 - params->quad_enable = spi_nor_sr2_bit1_quad_enable; 4745 4745 - params->set_4byte = spansion_set_4byte; 4746 4746 - params->setup = spi_nor_default_setup; 4747 4747 - /* Default to 16-bit Write Status (01h) Command */ 4748 4748 - nor->flags |= SNOR_F_HAS_16BIT_SR; 4749 4749 - 4750 4750 - /* Set SPI NOR sizes. */ 4751 4751 - params->size = (u64)info->sector_size * info->n_sectors; 4752 4752 - params->page_size = info->page_size; 4753 4753 - 4754 4754 - if (!(info->flags & SPI_NOR_NO_FR)) { 4755 4755 - /* Default to Fast Read for DT and non-DT platform devices. */ 4756 4756 - params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 4757 4757 - 4758 4758 - /* Mask out Fast Read if not requested at DT instantiation. */ 4759 4759 - if (np && !of_property_read_bool(np, "m25p,fast-read")) 4760 4760 - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 4761 4761 - } 4762 4762 - 4763 4763 - /* (Fast) Read settings. */ 4764 4764 - params->hwcaps.mask |= SNOR_HWCAPS_READ; 4765 4765 - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ], 4766 4766 - 0, 0, SPINOR_OP_READ, 4767 4767 - SNOR_PROTO_1_1_1); 4768 4768 - 4769 4769 - if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 4770 4770 - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST], 4771 4771 - 0, 8, SPINOR_OP_READ_FAST, 4772 4772 - SNOR_PROTO_1_1_1); 4773 4773 - 4774 4774 - if (info->flags & SPI_NOR_DUAL_READ) { 4775 4775 - params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 4776 4776 - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2], 4777 4777 - 0, 8, SPINOR_OP_READ_1_1_2, 4778 4778 - SNOR_PROTO_1_1_2); 4779 4779 - } 4780 4780 - 4781 4781 - if (info->flags & SPI_NOR_QUAD_READ) { 4782 4782 - params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 4783 4783 - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4], 4784 4784 - 0, 8, SPINOR_OP_READ_1_1_4, 4785 4785 - SNOR_PROTO_1_1_4); 4786 4786 - } 4787 4787 - 4788 4788 - if (info->flags & SPI_NOR_OCTAL_READ) { 4789 4789 - params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 4790 4790 - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8], 4791 4791 - 0, 8, SPINOR_OP_READ_1_1_8, 4792 4792 - SNOR_PROTO_1_1_8); 4793 4793 - } 4794 4794 - 4795 4795 - /* Page Program settings. */ 4796 4796 - params->hwcaps.mask |= SNOR_HWCAPS_PP; 4797 4797 - spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP], 4798 4798 - SPINOR_OP_PP, SNOR_PROTO_1_1_1); 4799 4799 - 4800 4800 - /* 4801 4801 - * Sector Erase settings. Sort Erase Types in ascending order, with the 4802 4802 - * smallest erase size starting at BIT(0). 4803 4803 - */ 4804 4804 - erase_mask = 0; 4805 4805 - i = 0; 4806 4806 - if (info->flags & SECT_4K_PMC) { 4807 4807 - erase_mask |= BIT(i); 4808 4808 - spi_nor_set_erase_type(&map->erase_type[i], 4096u, 4809 4809 - SPINOR_OP_BE_4K_PMC); 4810 4810 - i++; 4811 4811 - } else if (info->flags & SECT_4K) { 4812 4812 - erase_mask |= BIT(i); 4813 4813 - spi_nor_set_erase_type(&map->erase_type[i], 4096u, 4814 4814 - SPINOR_OP_BE_4K); 4815 4815 - i++; 4816 4816 - } 4817 4817 - erase_mask |= BIT(i); 4818 4818 - spi_nor_set_erase_type(&map->erase_type[i], info->sector_size, 4819 4819 - SPINOR_OP_SE); 4820 4820 - spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 4821 4821 - } 4822 4822 - 4823 4823 - static void spansion_post_sfdp_fixups(struct spi_nor *nor) 4824 4824 - { 4825 4825 - if (nor->params.size <= SZ_16M) 4826 4826 - return; 4827 4827 - 4828 4828 - nor->flags |= SNOR_F_4B_OPCODES; 4829 4829 - /* No small sector erase for 4-byte command set */ 4830 4830 - nor->erase_opcode = SPINOR_OP_SE; 4831 4831 - nor->mtd.erasesize = nor->info->sector_size; 4832 4832 - } 4833 4833 - 4834 4834 - static void s3an_post_sfdp_fixups(struct spi_nor *nor) 4835 4835 - { 4836 4836 - nor->params.setup = s3an_nor_setup; 4837 4837 - } 4838 4838 - 4839 4839 - /** 4840 4840 - * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings 4841 4841 - * after SFDP has been parsed (is also called for SPI NORs that do not 4842 4842 - * support RDSFDP). 4843 4843 - * @nor: pointer to a 'struct spi_nor' 4844 4844 - * 4845 4845 - * Typically used to tweak various parameters that could not be extracted by 4846 4846 - * other means (i.e. when information provided by the SFDP/flash_info tables 4847 4847 - * are incomplete or wrong). 4848 4848 - */ 4849 4849 - static void spi_nor_post_sfdp_fixups(struct spi_nor *nor) 4850 4850 - { 4851 4851 - switch (JEDEC_MFR(nor->info)) { 4852 4852 - case SNOR_MFR_SPANSION: 4853 4853 - spansion_post_sfdp_fixups(nor); 4854 4854 - break; 4855 4855 - 4856 4856 - default: 4857 4857 - break; 4858 4858 - } 4859 4859 - 4860 4860 - if (nor->info->flags & SPI_S3AN) 4861 4861 - s3an_post_sfdp_fixups(nor); 4862 4862 - 4863 4863 - if (nor->info->fixups && nor->info->fixups->post_sfdp) 4864 4864 - nor->info->fixups->post_sfdp(nor); 4865 4865 - } 4866 4866 - 4867 4867 - /** 4868 4868 - * spi_nor_late_init_params() - Late initialization of default flash parameters. 4869 4869 - * @nor: pointer to a 'struct spi_nor' 4870 4870 - * 4871 4871 - * Used to set default flash parameters and settings when the ->default_init() 4872 4872 - * hook or the SFDP parser let voids. 4873 4873 - */ 4874 4874 - static void spi_nor_late_init_params(struct spi_nor *nor) 4875 4875 - { 4876 4876 - /* 4877 4877 - * NOR protection support. When locking_ops are not provided, we pick 4878 4878 - * the default ones. 4879 4879 - */ 4880 4880 - if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops) 4881 4881 - nor->params.locking_ops = &stm_locking_ops; 4882 4882 - } 4883 4883 - 4884 4884 - /** 4885 4885 - * spi_nor_init_params() - Initialize the flash's parameters and settings. 4886 4886 - * @nor: pointer to a 'struct spi-nor'. 4887 4887 - * 4888 4888 - * The flash parameters and settings are initialized based on a sequence of 4889 4889 - * calls that are ordered by priority: 4890 4890 - * 4891 4891 - * 1/ Default flash parameters initialization. The initializations are done 4892 4892 - * based on nor->info data: 4893 4893 - * spi_nor_info_init_params() 4894 4894 - * 4895 4895 - * which can be overwritten by: 4896 4896 - * 2/ Manufacturer flash parameters initialization. The initializations are 4897 4897 - * done based on MFR register, or when the decisions can not be done solely 4898 4898 - * based on MFR, by using specific flash_info tweeks, ->default_init(): 4899 4899 - * spi_nor_manufacturer_init_params() 4900 4900 - * 4901 4901 - * which can be overwritten by: 4902 4902 - * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 4903 4903 - * should be more accurate that the above. 4904 4904 - * spi_nor_sfdp_init_params() 4905 4905 - * 4906 4906 - * Please note that there is a ->post_bfpt() fixup hook that can overwrite 4907 4907 - * the flash parameters and settings immediately after parsing the Basic 4908 4908 - * Flash Parameter Table. 4909 4909 - * 4910 4910 - * which can be overwritten by: 4911 4911 - * 4/ Post SFDP flash parameters initialization. Used to tweak various 4912 4912 - * parameters that could not be extracted by other means (i.e. when 4913 4913 - * information provided by the SFDP/flash_info tables are incomplete or 4914 4914 - * wrong). 4915 4915 - * spi_nor_post_sfdp_fixups() 4916 4916 - * 4917 4917 - * 5/ Late default flash parameters initialization, used when the 4918 4918 - * ->default_init() hook or the SFDP parser do not set specific params. 4919 4919 - * spi_nor_late_init_params() 4920 4920 - */ 4921 4921 - static void spi_nor_init_params(struct spi_nor *nor) 4922 4922 - { 4923 4923 - spi_nor_info_init_params(nor); 4924 4924 - 4925 4925 - spi_nor_manufacturer_init_params(nor); 4926 4926 - 4927 4927 - if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 4928 4928 - !(nor->info->flags & SPI_NOR_SKIP_SFDP)) 4929 4929 - spi_nor_sfdp_init_params(nor); 4930 4930 - 4931 4931 - spi_nor_post_sfdp_fixups(nor); 4932 4932 - 4933 4933 - spi_nor_late_init_params(nor); 4934 4934 - } 4935 4935 - 4936 4936 - /** 4937 4937 - * spi_nor_quad_enable() - enable Quad I/O if needed. 4938 4938 - * @nor: pointer to a 'struct spi_nor' 4939 4939 - * 4940 4940 - * Return: 0 on success, -errno otherwise. 4941 4941 - */ 4942 4942 - static int spi_nor_quad_enable(struct spi_nor *nor) 4943 4943 - { 4944 4944 - if (!nor->params.quad_enable) 4945 4945 - return 0; 4946 4946 - 4947 4947 - if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 4948 4948 - spi_nor_get_protocol_width(nor->write_proto) == 4)) 4949 4949 - return 0; 4950 4950 - 4951 4951 - return nor->params.quad_enable(nor); 4952 4952 - } 4953 4953 - 4954 4954 - /** 4955 4955 - * spi_nor_unlock_all() - Unlocks the entire flash memory array. 4956 4956 - * @nor: pointer to a 'struct spi_nor'. 4957 4957 - * 4958 4958 - * Some SPI NOR flashes are write protected by default after a power-on reset 4959 4959 - * cycle, in order to avoid inadvertent writes during power-up. Backward 4960 4960 - * compatibility imposes to unlock the entire flash memory array at power-up 4961 4961 - * by default. 4962 4962 - */ 4963 4963 - static int spi_nor_unlock_all(struct spi_nor *nor) 4964 4964 - { 4965 4965 - if (nor->flags & SNOR_F_HAS_LOCK) 4966 4966 - return spi_nor_unlock(&nor->mtd, 0, nor->params.size); 4967 4967 - 4968 4968 - return 0; 4969 4969 - } 4970 4970 - 4971 4971 - static int spi_nor_init(struct spi_nor *nor) 4972 4972 - { 4973 4973 - int err; 4974 4974 - 4975 4975 - err = spi_nor_quad_enable(nor); 4976 4976 - if (err) { 4977 4977 - dev_dbg(nor->dev, "quad mode not supported\n"); 4978 4978 - return err; 4979 4979 - } 4980 4980 - 4981 4981 - err = spi_nor_unlock_all(nor); 4982 4982 - if (err) { 4983 4983 - dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n"); 4984 4984 - return err; 4985 4985 - } 4986 4986 - 4987 4987 - if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) { 4988 4988 - /* 4989 4989 - * If the RESET# pin isn't hooked up properly, or the system 4990 4990 - * otherwise doesn't perform a reset command in the boot 4991 4991 - * sequence, it's impossible to 100% protect against unexpected 4992 4992 - * reboots (e.g., crashes). Warn the user (or hopefully, system 4993 4993 - * designer) that this is bad. 4994 4994 - */ 4995 4995 - WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 4996 4996 - "enabling reset hack; may not recover from unexpected reboots\n"); 4997 4997 - nor->params.set_4byte(nor, true); 4998 4998 - } 4999 4999 - 5000 5000 - return 0; 5001 5001 - } 5002 5002 - 5003 5003 - /* mtd resume handler */ 5004 5004 - static void spi_nor_resume(struct mtd_info *mtd) 5005 5005 - { 5006 5006 - struct spi_nor *nor = mtd_to_spi_nor(mtd); 5007 5007 - struct device *dev = nor->dev; 5008 5008 - int ret; 5009 5009 - 5010 5010 - /* re-initialize the nor chip */ 5011 5011 - ret = spi_nor_init(nor); 5012 5012 - if (ret) 5013 5013 - dev_err(dev, "resume() failed\n"); 5014 5014 - } 5015 5015 - 5016 5016 - void spi_nor_restore(struct spi_nor *nor) 5017 5017 - { 5018 5018 - /* restore the addressing mode */ 5019 5019 - if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 5020 5020 - nor->flags & SNOR_F_BROKEN_RESET) 5021 5021 - nor->params.set_4byte(nor, false); 5022 5022 - } 5023 5023 - EXPORT_SYMBOL_GPL(spi_nor_restore); 5024 5024 - 5025 5025 - static const struct flash_info *spi_nor_match_id(const char *name) 5026 5026 - { 5027 5027 - const struct flash_info *id = spi_nor_ids; 5028 5028 - 5029 5029 - while (id->name) { 5030 5030 - if (!strcmp(name, id->name)) 5031 5031 - return id; 5032 5032 - id++; 5033 5033 - } 5034 5034 - return NULL; 5035 5035 - } 5036 5036 - 5037 5037 - static int spi_nor_set_addr_width(struct spi_nor *nor) 5038 5038 - { 5039 5039 - if (nor->addr_width) { 5040 5040 - /* already configured from SFDP */ 5041 5041 - } else if (nor->info->addr_width) { 5042 5042 - nor->addr_width = nor->info->addr_width; 5043 5043 - } else if (nor->mtd.size > 0x1000000) { 5044 5044 - /* enable 4-byte addressing if the device exceeds 16MiB */ 5045 5045 - nor->addr_width = 4; 5046 5046 - } else { 5047 5047 - nor->addr_width = 3; 5048 5048 - } 5049 5049 - 5050 5050 - if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 5051 5051 - dev_dbg(nor->dev, "address width is too large: %u\n", 5052 5052 - nor->addr_width); 5053 5053 - return -EINVAL; 5054 5054 - } 5055 5055 - 5056 5056 - /* Set 4byte opcodes when possible. */ 5057 5057 - if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES && 5058 5058 - !(nor->flags & SNOR_F_HAS_4BAIT)) 5059 5059 - spi_nor_set_4byte_opcodes(nor); 5060 5060 - 5061 5061 - return 0; 5062 5062 - } 5063 5063 - 5064 5064 - static void spi_nor_debugfs_init(struct spi_nor *nor, 5065 5065 - const struct flash_info *info) 5066 5066 - { 5067 5067 - struct mtd_info *mtd = &nor->mtd; 5068 5068 - 5069 5069 - mtd->dbg.partname = info->name; 5070 5070 - mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN", 5071 5071 - info->id_len, info->id); 5072 5072 - } 5073 5073 - 5074 5074 - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 5075 5075 - const char *name) 5076 5076 - { 5077 5077 - const struct flash_info *info = NULL; 5078 5078 - 5079 5079 - if (name) 5080 5080 - info = spi_nor_match_id(name); 5081 5081 - /* Try to auto-detect if chip name wasn't specified or not found */ 5082 5082 - if (!info) 5083 5083 - info = spi_nor_read_id(nor); 5084 5084 - if (IS_ERR_OR_NULL(info)) 5085 5085 - return ERR_PTR(-ENOENT); 5086 5086 - 5087 5087 - /* 5088 5088 - * If caller has specified name of flash model that can normally be 5089 5089 - * detected using JEDEC, let's verify it. 5090 5090 - */ 5091 5091 - if (name && info->id_len) { 5092 5092 - const struct flash_info *jinfo; 5093 5093 - 5094 5094 - jinfo = spi_nor_read_id(nor); 5095 5095 - if (IS_ERR(jinfo)) { 5096 5096 - return jinfo; 5097 5097 - } else if (jinfo != info) { 5098 5098 - /* 5099 5099 - * JEDEC knows better, so overwrite platform ID. We 5100 5100 - * can't trust partitions any longer, but we'll let 5101 5101 - * mtd apply them anyway, since some partitions may be 5102 5102 - * marked read-only, and we don't want to lose that 5103 5103 - * information, even if it's not 100% accurate. 5104 5104 - */ 5105 5105 - dev_warn(nor->dev, "found %s, expected %s\n", 5106 5106 - jinfo->name, info->name); 5107 5107 - info = jinfo; 5108 5108 - } 5109 5109 - } 5110 5110 - 5111 5111 - return info; 5112 5112 - } 5113 5113 - 5114 5114 - int spi_nor_scan(struct spi_nor *nor, const char *name, 5115 5115 - const struct spi_nor_hwcaps *hwcaps) 5116 5116 - { 5117 5117 - const struct flash_info *info; 5118 5118 - struct device *dev = nor->dev; 5119 5119 - struct mtd_info *mtd = &nor->mtd; 5120 5120 - struct device_node *np = spi_nor_get_flash_node(nor); 5121 5121 - struct spi_nor_flash_parameter *params = &nor->params; 5122 5122 - int ret; 5123 5123 - int i; 5124 5124 - 5125 5125 - ret = spi_nor_check(nor); 5126 5126 - if (ret) 5127 5127 - return ret; 5128 5128 - 5129 5129 - /* Reset SPI protocol for all commands. */ 5130 5130 - nor->reg_proto = SNOR_PROTO_1_1_1; 5131 5131 - nor->read_proto = SNOR_PROTO_1_1_1; 5132 5132 - nor->write_proto = SNOR_PROTO_1_1_1; 5133 5133 - 5134 5134 - /* 5135 5135 - * We need the bounce buffer early to read/write registers when going 5136 5136 - * through the spi-mem layer (buffers have to be DMA-able). 5137 5137 - * For spi-mem drivers, we'll reallocate a new buffer if 5138 5138 - * nor->page_size turns out to be greater than PAGE_SIZE (which 5139 5139 - * shouldn't happen before long since NOR pages are usually less 5140 5140 - * than 1KB) after spi_nor_scan() returns. 5141 5141 - */ 5142 5142 - nor->bouncebuf_size = PAGE_SIZE; 5143 5143 - nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 5144 5144 - GFP_KERNEL); 5145 5145 - if (!nor->bouncebuf) 5146 5146 - return -ENOMEM; 5147 5147 - 5148 5148 - info = spi_nor_get_flash_info(nor, name); 5149 5149 - if (IS_ERR(info)) 5150 5150 - return PTR_ERR(info); 5151 5151 - 5152 5152 - nor->info = info; 5153 5153 - 5154 5154 - spi_nor_debugfs_init(nor, info); 5155 5155 - 5156 5156 - mutex_init(&nor->lock); 5157 5157 - 5158 5158 - /* 5159 5159 - * Make sure the XSR_RDY flag is set before calling 5160 5160 - * spi_nor_wait_till_ready(). Xilinx S3AN share MFR 5161 5161 - * with Atmel spi-nor 5162 5162 - */ 5163 5163 - if (info->flags & SPI_NOR_XSR_RDY) 5164 5164 - nor->flags |= SNOR_F_READY_XSR_RDY; 5165 5165 - 5166 5166 - if (info->flags & SPI_NOR_HAS_LOCK) 5167 5167 - nor->flags |= SNOR_F_HAS_LOCK; 5168 5168 - 5169 5169 - /* Init flash parameters based on flash_info struct and SFDP */ 5170 5170 - spi_nor_init_params(nor); 5171 5171 - 5172 5172 - if (!mtd->name) 5173 5173 - mtd->name = dev_name(dev); 5174 5174 - mtd->priv = nor; 5175 5175 - mtd->type = MTD_NORFLASH; 5176 5176 - mtd->writesize = 1; 5177 5177 - mtd->flags = MTD_CAP_NORFLASH; 5178 5178 - mtd->size = params->size; 5179 5179 - mtd->_erase = spi_nor_erase; 5180 5180 - mtd->_read = spi_nor_read; 5181 5181 - mtd->_resume = spi_nor_resume; 5182 5182 - 5183 5183 - if (nor->params.locking_ops) { 5184 5184 - mtd->_lock = spi_nor_lock; 5185 5185 - mtd->_unlock = spi_nor_unlock; 5186 5186 - mtd->_is_locked = spi_nor_is_locked; 5187 5187 - } 5188 5188 - 5189 5189 - /* sst nor chips use AAI word program */ 5190 5190 - if (info->flags & SST_WRITE) 5191 5191 - mtd->_write = sst_write; 5192 5192 - else 5193 5193 - mtd->_write = spi_nor_write; 5194 5194 - 5195 5195 - if (info->flags & USE_FSR) 5196 5196 - nor->flags |= SNOR_F_USE_FSR; 5197 5197 - if (info->flags & SPI_NOR_HAS_TB) { 5198 5198 - nor->flags |= SNOR_F_HAS_SR_TB; 5199 5199 - if (info->flags & SPI_NOR_TB_SR_BIT6) 5200 5200 - nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 5201 5201 - } 5202 5202 - 5203 5203 - if (info->flags & NO_CHIP_ERASE) 5204 5204 - nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 5205 5205 - if (info->flags & USE_CLSR) 5206 5206 - nor->flags |= SNOR_F_USE_CLSR; 5207 5207 - 5208 5208 - if (info->flags & SPI_NOR_NO_ERASE) 5209 5209 - mtd->flags |= MTD_NO_ERASE; 5210 5210 - 5211 5211 - mtd->dev.parent = dev; 5212 5212 - nor->page_size = params->page_size; 5213 5213 - mtd->writebufsize = nor->page_size; 5214 5214 - 5215 5215 - if (of_property_read_bool(np, "broken-flash-reset")) 5216 5216 - nor->flags |= SNOR_F_BROKEN_RESET; 5217 5217 - 5218 5218 - /* 5219 5219 - * Configure the SPI memory: 5220 5220 - * - select op codes for (Fast) Read, Page Program and Sector Erase. 5221 5221 - * - set the number of dummy cycles (mode cycles + wait states). 5222 5222 - * - set the SPI protocols for register and memory accesses. 5223 5223 - */ 5224 5224 - ret = spi_nor_setup(nor, hwcaps); 5225 5225 - if (ret) 5226 5226 - return ret; 5227 5227 - 5228 5228 - if (info->flags & SPI_NOR_4B_OPCODES) 5229 5229 - nor->flags |= SNOR_F_4B_OPCODES; 5230 5230 - 5231 5231 - ret = spi_nor_set_addr_width(nor); 5232 5232 - if (ret) 5233 5233 - return ret; 5234 5234 - 5235 5235 - /* Send all the required SPI flash commands to initialize device */ 5236 5236 - ret = spi_nor_init(nor); 5237 5237 - if (ret) 5238 5238 - return ret; 5239 5239 - 5240 5240 - dev_info(dev, "%s (%lld Kbytes)\n", info->name, 5241 5241 - (long long)mtd->size >> 10); 5242 5242 - 5243 5243 - dev_dbg(dev, 5244 5244 - "mtd .name = %s, .size = 0x%llx (%lldMiB), " 5245 5245 - ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 5246 5246 - mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 5247 5247 - mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 5248 5248 - 5249 5249 - if (mtd->numeraseregions) 5250 5250 - for (i = 0; i < mtd->numeraseregions; i++) 5251 5251 - dev_dbg(dev, 5252 5252 - "mtd.eraseregions[%d] = { .offset = 0x%llx, " 5253 5253 - ".erasesize = 0x%.8x (%uKiB), " 5254 5254 - ".numblocks = %d }\n", 5255 5255 - i, (long long)mtd->eraseregions[i].offset, 5256 5256 - mtd->eraseregions[i].erasesize, 5257 5257 - mtd->eraseregions[i].erasesize / 1024, 5258 5258 - mtd->eraseregions[i].numblocks); 5259 5259 - return 0; 5260 5260 - } 5261 5261 - EXPORT_SYMBOL_GPL(spi_nor_scan); 5262 5262 - 5263 5263 - static int spi_nor_probe(struct spi_mem *spimem) 5264 5264 - { 5265 5265 - struct spi_device *spi = spimem->spi; 5266 5266 - struct flash_platform_data *data = dev_get_platdata(&spi->dev); 5267 5267 - struct spi_nor *nor; 5268 5268 - /* 5269 5269 - * Enable all caps by default. The core will mask them after 5270 5270 - * checking what's really supported using spi_mem_supports_op(). 5271 5271 - */ 5272 5272 - const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 5273 5273 - char *flash_name; 5274 5274 - int ret; 5275 5275 - 5276 5276 - nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 5277 5277 - if (!nor) 5278 5278 - return -ENOMEM; 5279 5279 - 5280 5280 - nor->spimem = spimem; 5281 5281 - nor->dev = &spi->dev; 5282 5282 - spi_nor_set_flash_node(nor, spi->dev.of_node); 5283 5283 - 5284 5284 - spi_mem_set_drvdata(spimem, nor); 5285 5285 - 5286 5286 - if (data && data->name) 5287 5287 - nor->mtd.name = data->name; 5288 5288 - 5289 5289 - if (!nor->mtd.name) 5290 5290 - nor->mtd.name = spi_mem_get_name(spimem); 5291 5291 - 5292 5292 - /* 5293 5293 - * For some (historical?) reason many platforms provide two different 5294 5294 - * names in flash_platform_data: "name" and "type". Quite often name is 5295 5295 - * set to "m25p80" and then "type" provides a real chip name. 5296 5296 - * If that's the case, respect "type" and ignore a "name". 5297 5297 - */ 5298 5298 - if (data && data->type) 5299 5299 - flash_name = data->type; 5300 5300 - else if (!strcmp(spi->modalias, "spi-nor")) 5301 5301 - flash_name = NULL; /* auto-detect */ 5302 5302 - else 5303 5303 - flash_name = spi->modalias; 5304 5304 - 5305 5305 - ret = spi_nor_scan(nor, flash_name, &hwcaps); 5306 5306 - if (ret) 5307 5307 - return ret; 5308 5308 - 5309 5309 - /* 5310 5310 - * None of the existing parts have > 512B pages, but let's play safe 5311 5311 - * and add this logic so that if anyone ever adds support for such 5312 5312 - * a NOR we don't end up with buffer overflows. 5313 5313 - */ 5314 5314 - if (nor->page_size > PAGE_SIZE) { 5315 5315 - nor->bouncebuf_size = nor->page_size; 5316 5316 - devm_kfree(nor->dev, nor->bouncebuf); 5317 5317 - nor->bouncebuf = devm_kmalloc(nor->dev, 5318 5318 - nor->bouncebuf_size, 5319 5319 - GFP_KERNEL); 5320 5320 - if (!nor->bouncebuf) 5321 5321 - return -ENOMEM; 5322 5322 - } 5323 5323 - 5324 5324 - return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 5325 5325 - data ? data->nr_parts : 0); 5326 5326 - } 5327 5327 - 5328 5328 - static int spi_nor_remove(struct spi_mem *spimem) 5329 5329 - { 5330 5330 - struct spi_nor *nor = spi_mem_get_drvdata(spimem); 5331 5331 - 5332 5332 - spi_nor_restore(nor); 5333 5333 - 5334 5334 - /* Clean up MTD stuff. */ 5335 5335 - return mtd_device_unregister(&nor->mtd); 5336 5336 - } 5337 5337 - 5338 5338 - static void spi_nor_shutdown(struct spi_mem *spimem) 5339 5339 - { 5340 5340 - struct spi_nor *nor = spi_mem_get_drvdata(spimem); 5341 5341 - 5342 5342 - spi_nor_restore(nor); 5343 5343 - } 5344 5344 - 5345 5345 - /* 5346 5346 - * Do NOT add to this array without reading the following: 5347 5347 - * 5348 5348 - * Historically, many flash devices are bound to this driver by their name. But 5349 5349 - * since most of these flash are compatible to some extent, and their 5350 5350 - * differences can often be differentiated by the JEDEC read-ID command, we 5351 5351 - * encourage new users to add support to the spi-nor library, and simply bind 5352 5352 - * against a generic string here (e.g., "jedec,spi-nor"). 5353 5353 - * 5354 5354 - * Many flash names are kept here in this list (as well as in spi-nor.c) to 5355 5355 - * keep them available as module aliases for existing platforms. 5356 5356 - */ 5357 5357 - static const struct spi_device_id spi_nor_dev_ids[] = { 5358 5358 - /* 5359 5359 - * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 5360 5360 - * hack around the fact that the SPI core does not provide uevent 5361 5361 - * matching for .of_match_table 5362 5362 - */ 5363 5363 - {"spi-nor"}, 5364 5364 - 5365 5365 - /* 5366 5366 - * Entries not used in DTs that should be safe to drop after replacing 5367 5367 - * them with "spi-nor" in platform data. 5368 5368 - */ 5369 5369 - {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 5370 5370 - 5371 5371 - /* 5372 5372 - * Entries that were used in DTs without "jedec,spi-nor" fallback and 5373 5373 - * should be kept for backward compatibility. 5374 5374 - */ 5375 5375 - {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 5376 5376 - {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 5377 5377 - {"mx25l25635e"},{"mx66l51235l"}, 5378 5378 - {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 5379 5379 - {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 5380 5380 - {"s25fl064k"}, 5381 5381 - {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 5382 5382 - {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 5383 5383 - {"m25p64"}, {"m25p128"}, 5384 5384 - {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 5385 5385 - {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 5386 5386 - 5387 5387 - /* Flashes that can't be detected using JEDEC */ 5388 5388 - {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 5389 5389 - {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 5390 5390 - {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 5391 5391 - 5392 5392 - /* Everspin MRAMs (non-JEDEC) */ 5393 5393 - { "mr25h128" }, /* 128 Kib, 40 MHz */ 5394 5394 - { "mr25h256" }, /* 256 Kib, 40 MHz */ 5395 5395 - { "mr25h10" }, /* 1 Mib, 40 MHz */ 5396 5396 - { "mr25h40" }, /* 4 Mib, 40 MHz */ 5397 5397 - 5398 5398 - { }, 5399 5399 - }; 5400 5400 - MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 5401 5401 - 5402 5402 - static const struct of_device_id spi_nor_of_table[] = { 5403 5403 - /* 5404 5404 - * Generic compatibility for SPI NOR that can be identified by the 5405 5405 - * JEDEC READ ID opcode (0x9F). Use this, if possible. 5406 5406 - */ 5407 5407 - { .compatible = "jedec,spi-nor" }, 5408 5408 - { /* sentinel */ }, 5409 5409 - }; 5410 5410 - MODULE_DEVICE_TABLE(of, spi_nor_of_table); 5411 5411 - 5412 5412 - /* 5413 5413 - * REVISIT: many of these chips have deep power-down modes, which 5414 5414 - * should clearly be entered on suspend() to minimize power use. 5415 5415 - * And also when they're otherwise idle... 5416 5416 - */ 5417 5417 - static struct spi_mem_driver spi_nor_driver = { 5418 5418 - .spidrv = { 5419 5419 - .driver = { 5420 5420 - .name = "spi-nor", 5421 5421 - .of_match_table = spi_nor_of_table, 5422 5422 - }, 5423 5423 - .id_table = spi_nor_dev_ids, 5424 5424 - }, 5425 5425 - .probe = spi_nor_probe, 5426 5426 - .remove = spi_nor_remove, 5427 5427 - .shutdown = spi_nor_shutdown, 5428 5428 - }; 5429 5429 - module_spi_mem_driver(spi_nor_driver); 5430 5430 - 5431 5431 - MODULE_LICENSE("GPL v2"); 5432 5432 - MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 5433 5433 - MODULE_AUTHOR("Mike Lavender"); 5434 5434 - MODULE_DESCRIPTION("framework for SPI NOR");

+151

drivers/mtd/spi-nor/sst.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info sst_parts[] = { 12 12 + /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 13 13 + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, 14 14 + SECT_4K | SST_WRITE) }, 15 15 + { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, 16 16 + SECT_4K | SST_WRITE) }, 17 17 + { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, 18 18 + SECT_4K | SST_WRITE) }, 19 19 + { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, 20 20 + SECT_4K | SST_WRITE) }, 21 21 + { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 22 22 + { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, 23 23 + SECT_4K | SST_WRITE) }, 24 24 + { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, 25 25 + SECT_4K | SST_WRITE) }, 26 26 + { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, 27 27 + SECT_4K | SST_WRITE) }, 28 28 + { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, 29 29 + { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, 30 30 + { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, 31 31 + SECT_4K | SST_WRITE) }, 32 32 + { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, 33 33 + SECT_4K | SST_WRITE) }, 34 34 + { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32, 35 35 + SECT_4K | SPI_NOR_DUAL_READ | 36 36 + SPI_NOR_QUAD_READ) }, 37 37 + { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, 38 38 + SECT_4K | SPI_NOR_DUAL_READ) }, 39 39 + { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, 40 40 + SECT_4K | SPI_NOR_DUAL_READ | 41 41 + SPI_NOR_QUAD_READ) }, 42 42 + }; 43 43 + 44 44 + static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 45 45 + size_t *retlen, const u_char *buf) 46 46 + { 47 47 + struct spi_nor *nor = mtd_to_spi_nor(mtd); 48 48 + size_t actual = 0; 49 49 + int ret; 50 50 + 51 51 + dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 52 52 + 53 53 + ret = spi_nor_lock_and_prep(nor); 54 54 + if (ret) 55 55 + return ret; 56 56 + 57 57 + ret = spi_nor_write_enable(nor); 58 58 + if (ret) 59 59 + goto out; 60 60 + 61 61 + nor->sst_write_second = false; 62 62 + 63 63 + /* Start write from odd address. */ 64 64 + if (to % 2) { 65 65 + nor->program_opcode = SPINOR_OP_BP; 66 66 + 67 67 + /* write one byte. */ 68 68 + ret = spi_nor_write_data(nor, to, 1, buf); 69 69 + if (ret < 0) 70 70 + goto out; 71 71 + WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret); 72 72 + ret = spi_nor_wait_till_ready(nor); 73 73 + if (ret) 74 74 + goto out; 75 75 + 76 76 + to++; 77 77 + actual++; 78 78 + } 79 79 + 80 80 + /* Write out most of the data here. */ 81 81 + for (; actual < len - 1; actual += 2) { 82 82 + nor->program_opcode = SPINOR_OP_AAI_WP; 83 83 + 84 84 + /* write two bytes. */ 85 85 + ret = spi_nor_write_data(nor, to, 2, buf + actual); 86 86 + if (ret < 0) 87 87 + goto out; 88 88 + WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret); 89 89 + ret = spi_nor_wait_till_ready(nor); 90 90 + if (ret) 91 91 + goto out; 92 92 + to += 2; 93 93 + nor->sst_write_second = true; 94 94 + } 95 95 + nor->sst_write_second = false; 96 96 + 97 97 + ret = spi_nor_write_disable(nor); 98 98 + if (ret) 99 99 + goto out; 100 100 + 101 101 + ret = spi_nor_wait_till_ready(nor); 102 102 + if (ret) 103 103 + goto out; 104 104 + 105 105 + /* Write out trailing byte if it exists. */ 106 106 + if (actual != len) { 107 107 + ret = spi_nor_write_enable(nor); 108 108 + if (ret) 109 109 + goto out; 110 110 + 111 111 + nor->program_opcode = SPINOR_OP_BP; 112 112 + ret = spi_nor_write_data(nor, to, 1, buf + actual); 113 113 + if (ret < 0) 114 114 + goto out; 115 115 + WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret); 116 116 + ret = spi_nor_wait_till_ready(nor); 117 117 + if (ret) 118 118 + goto out; 119 119 + 120 120 + actual += 1; 121 121 + 122 122 + ret = spi_nor_write_disable(nor); 123 123 + } 124 124 + out: 125 125 + *retlen += actual; 126 126 + spi_nor_unlock_and_unprep(nor); 127 127 + return ret; 128 128 + } 129 129 + 130 130 + static void sst_default_init(struct spi_nor *nor) 131 131 + { 132 132 + nor->flags |= SNOR_F_HAS_LOCK; 133 133 + } 134 134 + 135 135 + static void sst_post_sfdp_fixups(struct spi_nor *nor) 136 136 + { 137 137 + if (nor->info->flags & SST_WRITE) 138 138 + nor->mtd._write = sst_write; 139 139 + } 140 140 + 141 141 + static const struct spi_nor_fixups sst_fixups = { 142 142 + .default_init = sst_default_init, 143 143 + .post_sfdp = sst_post_sfdp_fixups, 144 144 + }; 145 145 + 146 146 + const struct spi_nor_manufacturer spi_nor_sst = { 147 147 + .name = "sst", 148 148 + .parts = sst_parts, 149 149 + .nparts = ARRAY_SIZE(sst_parts), 150 150 + .fixups = &sst_fixups, 151 151 + };

+112

drivers/mtd/spi-nor/winbond.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info winbond_parts[] = { 12 12 + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 13 13 + { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 14 14 + { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 15 15 + { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 16 16 + { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 17 17 + { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 18 18 + { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 19 19 + { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 20 20 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 21 21 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 22 22 + { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 23 23 + { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32, 24 24 + SECT_4K | SPI_NOR_DUAL_READ | 25 25 + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | 26 26 + SPI_NOR_HAS_TB) }, 27 27 + { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 28 28 + { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 29 29 + { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 30 30 + { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 31 31 + { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 32 32 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 33 33 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 34 34 + { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 35 35 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 36 36 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 37 37 + }, 38 38 + { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, 39 39 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 40 40 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 41 41 + { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 42 42 + { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 43 43 + { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 44 44 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 45 45 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 46 46 + { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 47 47 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 48 48 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 49 49 + { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256, 50 50 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 51 51 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 52 52 + { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 53 53 + { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 54 54 + { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 55 55 + { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, 56 56 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 57 57 + SPI_NOR_4B_OPCODES) }, 58 58 + { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512, 59 59 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 60 60 + { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, 61 61 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 62 62 + { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 63 63 + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 64 64 + }; 65 65 + 66 66 + /** 67 67 + * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes. 68 68 + * @nor: pointer to 'struct spi_nor'. 69 69 + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 70 70 + * address mode. 71 71 + * 72 72 + * Return: 0 on success, -errno otherwise. 73 73 + */ 74 74 + static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 75 75 + { 76 76 + int ret; 77 77 + 78 78 + ret = spi_nor_set_4byte_addr_mode(nor, enable); 79 79 + if (ret || enable) 80 80 + return ret; 81 81 + 82 82 + /* 83 83 + * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address 84 84 + * Register to be set to 1, so all 3-byte-address reads come from the 85 85 + * second 16M. We must clear the register to enable normal behavior. 86 86 + */ 87 87 + ret = spi_nor_write_enable(nor); 88 88 + if (ret) 89 89 + return ret; 90 90 + 91 91 + ret = spi_nor_write_ear(nor, 0); 92 92 + if (ret) 93 93 + return ret; 94 94 + 95 95 + return spi_nor_write_disable(nor); 96 96 + } 97 97 + 98 98 + static void winbond_default_init(struct spi_nor *nor) 99 99 + { 100 100 + nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode; 101 101 + } 102 102 + 103 103 + static const struct spi_nor_fixups winbond_fixups = { 104 104 + .default_init = winbond_default_init, 105 105 + }; 106 106 + 107 107 + const struct spi_nor_manufacturer spi_nor_winbond = { 108 108 + .name = "winbond", 109 109 + .parts = winbond_parts, 110 110 + .nparts = ARRAY_SIZE(winbond_parts), 111 111 + .fixups = &winbond_fixups, 112 112 + };

+94

drivers/mtd/spi-nor/xilinx.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info xilinx_parts[] = { 12 12 + /* Xilinx S3AN Internal Flash */ 13 13 + { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, 14 14 + { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, 15 15 + { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, 16 16 + { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, 17 17 + { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, 18 18 + }; 19 19 + 20 20 + /* 21 21 + * This code converts an address to the Default Address Mode, that has non 22 22 + * power of two page sizes. We must support this mode because it is the default 23 23 + * mode supported by Xilinx tools, it can access the whole flash area and 24 24 + * changing over to the Power-of-two mode is irreversible and corrupts the 25 25 + * original data. 26 26 + * Addr can safely be unsigned int, the biggest S3AN device is smaller than 27 27 + * 4 MiB. 28 28 + */ 29 29 + static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr) 30 30 + { 31 31 + u32 offset, page; 32 32 + 33 33 + offset = addr % nor->page_size; 34 34 + page = addr / nor->page_size; 35 35 + page <<= (nor->page_size > 512) ? 10 : 9; 36 36 + 37 37 + return page | offset; 38 38 + } 39 39 + 40 40 + static int xilinx_nor_setup(struct spi_nor *nor, 41 41 + const struct spi_nor_hwcaps *hwcaps) 42 42 + { 43 43 + int ret; 44 44 + 45 45 + ret = spi_nor_xread_sr(nor, nor->bouncebuf); 46 46 + if (ret) 47 47 + return ret; 48 48 + 49 49 + nor->erase_opcode = SPINOR_OP_XSE; 50 50 + nor->program_opcode = SPINOR_OP_XPP; 51 51 + nor->read_opcode = SPINOR_OP_READ; 52 52 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 53 53 + 54 54 + /* 55 55 + * This flashes have a page size of 264 or 528 bytes (known as 56 56 + * Default addressing mode). It can be changed to a more standard 57 57 + * Power of two mode where the page size is 256/512. This comes 58 58 + * with a price: there is 3% less of space, the data is corrupted 59 59 + * and the page size cannot be changed back to default addressing 60 60 + * mode. 61 61 + * 62 62 + * The current addressing mode can be read from the XRDSR register 63 63 + * and should not be changed, because is a destructive operation. 64 64 + */ 65 65 + if (nor->bouncebuf[0] & XSR_PAGESIZE) { 66 66 + /* Flash in Power of 2 mode */ 67 67 + nor->page_size = (nor->page_size == 264) ? 256 : 512; 68 68 + nor->mtd.writebufsize = nor->page_size; 69 69 + nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors; 70 70 + nor->mtd.erasesize = 8 * nor->page_size; 71 71 + } else { 72 72 + /* Flash in Default addressing mode */ 73 73 + nor->params->convert_addr = s3an_convert_addr; 74 74 + nor->mtd.erasesize = nor->info->sector_size; 75 75 + } 76 76 + 77 77 + return 0; 78 78 + } 79 79 + 80 80 + static void xilinx_post_sfdp_fixups(struct spi_nor *nor) 81 81 + { 82 82 + nor->params->setup = xilinx_nor_setup; 83 83 + } 84 84 + 85 85 + static const struct spi_nor_fixups xilinx_fixups = { 86 86 + .post_sfdp = xilinx_post_sfdp_fixups, 87 87 + }; 88 88 + 89 89 + const struct spi_nor_manufacturer spi_nor_xilinx = { 90 90 + .name = "xilinx", 91 91 + .parts = xilinx_parts, 92 92 + .nparts = ARRAY_SIZE(xilinx_parts), 93 93 + .fixups = &xilinx_fixups, 94 94 + };

+23

drivers/mtd/spi-nor/xmc.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2005, Intec Automation Inc. 4 4 + * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 5 + */ 6 6 + 7 7 + #include <linux/mtd/spi-nor.h> 8 8 + 9 9 + #include "core.h" 10 10 + 11 11 + static const struct flash_info xmc_parts[] = { 12 12 + /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 13 13 + { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, 14 14 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 15 15 + { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, 16 16 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 17 17 + }; 18 18 + 19 19 + const struct spi_nor_manufacturer spi_nor_xmc = { 20 20 + .name = "xmc", 21 21 + .parts = xmc_parts, 22 22 + .nparts = ARRAY_SIZE(xmc_parts), 23 23 + };

+1 -1

drivers/mtd/ubi/attach.c

reviewed

··· 1059 1059 * be a result of power cut during erasure. 1060 1060 */ 1061 1061 ai->maybe_bad_peb_count += 1; 1062 1062 - /* fall through */ 1062 1062 + fallthrough; 1063 1063 case UBI_IO_BAD_HDR: 1064 1064 /* 1065 1065 * If we're facing a bad VID header we have to drop *all*

+2 -2

drivers/mtd/ubi/build.c

reviewed

··· 1342 1342 switch (*endp) { 1343 1343 case 'G': 1344 1344 result *= 1024; 1345 1345 - /* fall through */ 1345 1345 + fallthrough; 1346 1346 case 'M': 1347 1347 result *= 1024; 1348 1348 - /* fall through */ 1348 1348 + fallthrough; 1349 1349 case 'K': 1350 1350 result *= 1024; 1351 1351 if (endp[1] == 'i' && endp[2] == 'B')

+115 -10

include/linux/mtd/mtd.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 #include <linux/uio.h> 11 11 + #include <linux/list.h> 11 12 #include <linux/notifier.h> 12 13 #include <linux/device.h> 13 14 #include <linux/of.h> ··· 195 194 const char *partid; 196 195 }; 197 196 197 197 + /** 198 198 + * struct mtd_part - MTD partition specific fields 199 199 + * 200 200 + * @node: list node used to add an MTD partition to the parent partition list 201 201 + * @offset: offset of the partition relatively to the parent offset 202 202 + * @flags: original flags (before the mtdpart logic decided to tweak them based 203 203 + * on flash constraints, like eraseblock/pagesize alignment) 204 204 + * 205 205 + * This struct is embedded in mtd_info and contains partition-specific 206 206 + * properties/fields. 207 207 + */ 208 208 + struct mtd_part { 209 209 + struct list_head node; 210 210 + u64 offset; 211 211 + u32 flags; 212 212 + }; 213 213 + 214 214 + /** 215 215 + * struct mtd_master - MTD master specific fields 216 216 + * 217 217 + * @partitions_lock: lock protecting accesses to the partition list. Protects 218 218 + * not only the master partition list, but also all 219 219 + * sub-partitions. 220 220 + * @suspended: et to 1 when the device is suspended, 0 otherwise 221 221 + * 222 222 + * This struct is embedded in mtd_info and contains master-specific 223 223 + * properties/fields. The master is the root MTD device from the MTD partition 224 224 + * point of view. 225 225 + */ 226 226 + struct mtd_master { 227 227 + struct mutex partitions_lock; 228 228 + unsigned int suspended : 1; 229 229 + }; 230 230 + 198 231 struct mtd_info { 199 232 u_char type; 200 233 uint32_t flags; 201 201 - uint32_t orig_flags; /* Flags as before running mtd checks */ 202 234 uint64_t size; // Total size of the MTD 203 235 204 236 /* "Major" erase size for the device. Naïve users may take this ··· 373 339 int usecount; 374 340 struct mtd_debug_info dbg; 375 341 struct nvmem_device *nvmem; 342 342 + 343 343 + /* 344 344 + * Parent device from the MTD partition point of view. 345 345 + * 346 346 + * MTD masters do not have any parent, MTD partitions do. The parent 347 347 + * MTD device can itself be a partition. 348 348 + */ 349 349 + struct mtd_info *parent; 350 350 + 351 351 + /* List of partitions attached to this MTD device */ 352 352 + struct list_head partitions; 353 353 + 354 354 + union { 355 355 + struct mtd_part part; 356 356 + struct mtd_master master; 357 357 + }; 376 358 }; 359 359 + 360 360 + static inline struct mtd_info *mtd_get_master(struct mtd_info *mtd) 361 361 + { 362 362 + while (mtd->parent) 363 363 + mtd = mtd->parent; 364 364 + 365 365 + return mtd; 366 366 + } 367 367 + 368 368 + static inline u64 mtd_get_master_ofs(struct mtd_info *mtd, u64 ofs) 369 369 + { 370 370 + while (mtd->parent) { 371 371 + ofs += mtd->part.offset; 372 372 + mtd = mtd->parent; 373 373 + } 374 374 + 375 375 + return ofs; 376 376 + } 377 377 + 378 378 + static inline bool mtd_is_partition(const struct mtd_info *mtd) 379 379 + { 380 380 + return mtd->parent; 381 381 + } 382 382 + 383 383 + static inline bool mtd_has_partitions(const struct mtd_info *mtd) 384 384 + { 385 385 + return !list_empty(&mtd->partitions); 386 386 + } 377 387 378 388 int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, 379 389 struct mtd_oob_region *oobecc); ··· 470 392 static inline int mtd_max_bad_blocks(struct mtd_info *mtd, 471 393 loff_t ofs, size_t len) 472 394 { 473 473 - if (!mtd->_max_bad_blocks) 395 395 + struct mtd_info *master = mtd_get_master(mtd); 396 396 + 397 397 + if (!master->_max_bad_blocks) 474 398 return -ENOTSUPP; 475 399 476 400 if (mtd->size < (len + ofs) || ofs < 0) 477 401 return -EINVAL; 478 402 479 479 - return mtd->_max_bad_blocks(mtd, ofs, len); 403 403 + return master->_max_bad_blocks(master, mtd_get_master_ofs(mtd, ofs), 404 404 + len); 480 405 } 481 406 482 407 int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit, ··· 520 439 521 440 static inline void mtd_sync(struct mtd_info *mtd) 522 441 { 523 523 - if (mtd->_sync) 524 524 - mtd->_sync(mtd); 442 442 + struct mtd_info *master = mtd_get_master(mtd); 443 443 + 444 444 + if (master->_sync) 445 445 + master->_sync(master); 525 446 } 526 447 527 448 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); ··· 535 452 536 453 static inline int mtd_suspend(struct mtd_info *mtd) 537 454 { 538 538 - return mtd->_suspend ? mtd->_suspend(mtd) : 0; 455 455 + struct mtd_info *master = mtd_get_master(mtd); 456 456 + int ret; 457 457 + 458 458 + if (master->master.suspended) 459 459 + return 0; 460 460 + 461 461 + ret = master->_suspend ? master->_suspend(master) : 0; 462 462 + if (ret) 463 463 + return ret; 464 464 + 465 465 + master->master.suspended = 1; 466 466 + return 0; 539 467 } 540 468 541 469 static inline void mtd_resume(struct mtd_info *mtd) 542 470 { 543 543 - if (mtd->_resume) 544 544 - mtd->_resume(mtd); 471 471 + struct mtd_info *master = mtd_get_master(mtd); 472 472 + 473 473 + if (!master->master.suspended) 474 474 + return; 475 475 + 476 476 + if (master->_resume) 477 477 + master->_resume(master); 478 478 + 479 479 + master->master.suspended = 0; 545 480 } 546 481 547 482 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) ··· 639 538 640 539 static inline int mtd_has_oob(const struct mtd_info *mtd) 641 540 { 642 642 - return mtd->_read_oob && mtd->_write_oob; 541 541 + struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd); 542 542 + 543 543 + return master->_read_oob && master->_write_oob; 643 544 } 644 545 645 546 static inline int mtd_type_is_nand(const struct mtd_info *mtd) ··· 651 548 652 549 static inline int mtd_can_have_bb(const struct mtd_info *mtd) 653 550 { 654 654 - return !!mtd->_block_isbad; 551 551 + struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd); 552 552 + 553 553 + return !!master->_block_isbad; 655 554 } 656 555 657 556 /* Kernel-side ioctl definitions */

-1

include/linux/mtd/partitions.h

reviewed

··· 105 105 module_driver(__mtd_part_parser, register_mtd_parser, \ 106 106 deregister_mtd_parser) 107 107 108 108 - int mtd_is_partition(const struct mtd_info *mtd); 109 108 int mtd_add_partition(struct mtd_info *master, const char *name, 110 109 long long offset, long long length); 111 110 int mtd_del_partition(struct mtd_info *master, int partno);

+10 -1

include/linux/mtd/rawnand.h

reviewed

··· 1064 1064 * @lock: lock protecting the suspended field. Also used to 1065 1065 * serialize accesses to the NAND device. 1066 1066 * @suspended: set to 1 when the device is suspended, 0 when it's not. 1067 1067 + * @suspend: [REPLACEABLE] specific NAND device suspend operation 1068 1068 + * @resume: [REPLACEABLE] specific NAND device resume operation 1067 1069 * @bbt: [INTERN] bad block table pointer 1068 1070 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1069 1071 * lookup. ··· 1079 1077 * @manufacturer: [INTERN] Contains manufacturer information 1080 1078 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1081 1079 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1080 1080 + * @lock_area: [REPLACEABLE] specific NAND chip lock operation 1081 1081 + * @unlock_area: [REPLACEABLE] specific NAND chip unlock operation 1082 1082 */ 1083 1083 1084 1084 struct nand_chip { ··· 1121 1117 1122 1118 struct mutex lock; 1123 1119 unsigned int suspended : 1; 1120 1120 + int (*suspend)(struct nand_chip *chip); 1121 1121 + void (*resume)(struct nand_chip *chip); 1124 1122 1125 1123 uint8_t *oob_poi; 1126 1124 struct nand_controller *controller; ··· 1142 1136 const struct nand_manufacturer *desc; 1143 1137 void *priv; 1144 1138 } manufacturer; 1139 1139 + 1140 1140 + int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1141 1141 + int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len); 1145 1142 }; 1146 1143 1147 1144 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; ··· 1224 1215 * struct nand_flash_dev - NAND Flash Device ID Structure 1225 1216 * @name: a human-readable name of the NAND chip 1226 1217 * @dev_id: the device ID (the second byte of the full chip ID array) 1227 1227 - * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1218 1218 + * @mfr_id: manufacturer ID part of the full chip ID array (refers the same 1228 1219 * memory address as ``id[0]``) 1229 1220 * @dev_id: device ID part of the full chip ID array (refers the same memory 1230 1221 * address as ``id[1]``)

+19 -266

include/linux/mtd/spi-nor.h

reviewed

··· 12 12 #include <linux/spi/spi-mem.h> 13 13 14 14 /* 15 15 - * Manufacturer IDs 16 16 - * 17 17 - * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 18 18 - * Sometimes these are the same as CFI IDs, but sometimes they aren't. 19 19 - */ 20 20 - #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 21 21 - #define SNOR_MFR_GIGADEVICE 0xc8 22 22 - #define SNOR_MFR_INTEL CFI_MFR_INTEL 23 23 - #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ 24 24 - #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ 25 25 - #define SNOR_MFR_ISSI CFI_MFR_PMC 26 26 - #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 27 27 - #define SNOR_MFR_SPANSION CFI_MFR_AMD 28 28 - #define SNOR_MFR_SST CFI_MFR_SST 29 29 - #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 30 30 - 31 31 - /* 32 15 * Note on opcode nomenclature: some opcodes have a format like 33 16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 34 17 * of I/O lines used for the opcode, address, and data (respectively). The ··· 111 128 #define SR_BP0 BIT(2) /* Block protect 0 */ 112 129 #define SR_BP1 BIT(3) /* Block protect 1 */ 113 130 #define SR_BP2 BIT(4) /* Block protect 2 */ 131 131 + #define SR_BP3 BIT(5) /* Block protect 3 */ 114 132 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ 133 133 + #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */ 115 134 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ 116 135 #define SR_SRWD BIT(7) /* SR write protect */ 117 136 /* Spansion/Cypress specific status bits */ ··· 121 136 #define SR_P_ERR BIT(6) 122 137 123 138 #define SR1_QUAD_EN_BIT6 BIT(6) 139 139 + 140 140 + #define SR_BP_SHIFT 2 124 141 125 142 /* Enhanced Volatile Configuration Register bits */ 126 143 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ ··· 212 225 return spi_nor_get_protocol_data_nbits(proto); 213 226 } 214 227 215 215 - enum spi_nor_option_flags { 216 216 - SNOR_F_USE_FSR = BIT(0), 217 217 - SNOR_F_HAS_SR_TB = BIT(1), 218 218 - SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 219 219 - SNOR_F_READY_XSR_RDY = BIT(3), 220 220 - SNOR_F_USE_CLSR = BIT(4), 221 221 - SNOR_F_BROKEN_RESET = BIT(5), 222 222 - SNOR_F_4B_OPCODES = BIT(6), 223 223 - SNOR_F_HAS_4BAIT = BIT(7), 224 224 - SNOR_F_HAS_LOCK = BIT(8), 225 225 - SNOR_F_HAS_16BIT_SR = BIT(9), 226 226 - SNOR_F_NO_READ_CR = BIT(10), 227 227 - SNOR_F_HAS_SR_TB_BIT6 = BIT(11), 228 228 - 229 229 - }; 230 230 - 231 231 - /** 232 232 - * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type 233 233 - * @size: the size of the sector/block erased by the erase type. 234 234 - * JEDEC JESD216B imposes erase sizes to be a power of 2. 235 235 - * @size_shift: @size is a power of 2, the shift is stored in 236 236 - * @size_shift. 237 237 - * @size_mask: the size mask based on @size_shift. 238 238 - * @opcode: the SPI command op code to erase the sector/block. 239 239 - * @idx: Erase Type index as sorted in the Basic Flash Parameter 240 240 - * Table. It will be used to synchronize the supported 241 241 - * Erase Types with the ones identified in the SFDP 242 242 - * optional tables. 243 243 - */ 244 244 - struct spi_nor_erase_type { 245 245 - u32 size; 246 246 - u32 size_shift; 247 247 - u32 size_mask; 248 248 - u8 opcode; 249 249 - u8 idx; 250 250 - }; 251 251 - 252 252 - /** 253 253 - * struct spi_nor_erase_command - Used for non-uniform erases 254 254 - * The structure is used to describe a list of erase commands to be executed 255 255 - * once we validate that the erase can be performed. The elements in the list 256 256 - * are run-length encoded. 257 257 - * @list: for inclusion into the list of erase commands. 258 258 - * @count: how many times the same erase command should be 259 259 - * consecutively used. 260 260 - * @size: the size of the sector/block erased by the command. 261 261 - * @opcode: the SPI command op code to erase the sector/block. 262 262 - */ 263 263 - struct spi_nor_erase_command { 264 264 - struct list_head list; 265 265 - u32 count; 266 266 - u32 size; 267 267 - u8 opcode; 268 268 - }; 269 269 - 270 270 - /** 271 271 - * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region 272 272 - * @offset: the offset in the data array of erase region start. 273 273 - * LSB bits are used as a bitmask encoding flags to 274 274 - * determine if this region is overlaid, if this region is 275 275 - * the last in the SPI NOR flash memory and to indicate 276 276 - * all the supported erase commands inside this region. 277 277 - * The erase types are sorted in ascending order with the 278 278 - * smallest Erase Type size being at BIT(0). 279 279 - * @size: the size of the region in bytes. 280 280 - */ 281 281 - struct spi_nor_erase_region { 282 282 - u64 offset; 283 283 - u64 size; 284 284 - }; 285 285 - 286 286 - #define SNOR_ERASE_TYPE_MAX 4 287 287 - #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) 288 288 - 289 289 - #define SNOR_LAST_REGION BIT(4) 290 290 - #define SNOR_OVERLAID_REGION BIT(5) 291 291 - 292 292 - #define SNOR_ERASE_FLAGS_MAX 6 293 293 - #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) 294 294 - 295 295 - /** 296 296 - * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map 297 297 - * @regions: array of erase regions. The regions are consecutive in 298 298 - * address space. Walking through the regions is done 299 299 - * incrementally. 300 300 - * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform 301 301 - * sector size (legacy implementation). 302 302 - * @erase_type: an array of erase types shared by all the regions. 303 303 - * The erase types are sorted in ascending order, with the 304 304 - * smallest Erase Type size being the first member in the 305 305 - * erase_type array. 306 306 - * @uniform_erase_type: bitmask encoding erase types that can erase the 307 307 - * entire memory. This member is completed at init by 308 308 - * uniform and non-uniform SPI NOR flash memories if they 309 309 - * support at least one erase type that can erase the 310 310 - * entire memory. 311 311 - */ 312 312 - struct spi_nor_erase_map { 313 313 - struct spi_nor_erase_region *regions; 314 314 - struct spi_nor_erase_region uniform_region; 315 315 - struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; 316 316 - u8 uniform_erase_type; 317 317 - }; 318 318 - 319 228 /** 320 229 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies 321 230 * supported by the SPI controller (bus master). ··· 287 404 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ 288 405 SNOR_HWCAPS_PP_MASK) 289 406 290 290 - struct spi_nor_read_command { 291 291 - u8 num_mode_clocks; 292 292 - u8 num_wait_states; 293 293 - u8 opcode; 294 294 - enum spi_nor_protocol proto; 295 295 - }; 296 296 - 297 297 - struct spi_nor_pp_command { 298 298 - u8 opcode; 299 299 - enum spi_nor_protocol proto; 300 300 - }; 301 301 - 302 302 - enum spi_nor_read_command_index { 303 303 - SNOR_CMD_READ, 304 304 - SNOR_CMD_READ_FAST, 305 305 - SNOR_CMD_READ_1_1_1_DTR, 306 306 - 307 307 - /* Dual SPI */ 308 308 - SNOR_CMD_READ_1_1_2, 309 309 - SNOR_CMD_READ_1_2_2, 310 310 - SNOR_CMD_READ_2_2_2, 311 311 - SNOR_CMD_READ_1_2_2_DTR, 312 312 - 313 313 - /* Quad SPI */ 314 314 - SNOR_CMD_READ_1_1_4, 315 315 - SNOR_CMD_READ_1_4_4, 316 316 - SNOR_CMD_READ_4_4_4, 317 317 - SNOR_CMD_READ_1_4_4_DTR, 318 318 - 319 319 - /* Octal SPI */ 320 320 - SNOR_CMD_READ_1_1_8, 321 321 - SNOR_CMD_READ_1_8_8, 322 322 - SNOR_CMD_READ_8_8_8, 323 323 - SNOR_CMD_READ_1_8_8_DTR, 324 324 - 325 325 - SNOR_CMD_READ_MAX 326 326 - }; 327 327 - 328 328 - enum spi_nor_pp_command_index { 329 329 - SNOR_CMD_PP, 330 330 - 331 331 - /* Quad SPI */ 332 332 - SNOR_CMD_PP_1_1_4, 333 333 - SNOR_CMD_PP_1_4_4, 334 334 - SNOR_CMD_PP_4_4_4, 335 335 - 336 336 - /* Octal SPI */ 337 337 - SNOR_CMD_PP_1_1_8, 338 338 - SNOR_CMD_PP_1_8_8, 339 339 - SNOR_CMD_PP_8_8_8, 340 340 - 341 341 - SNOR_CMD_PP_MAX 342 342 - }; 343 343 - 344 344 - /* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */ 407 407 + /* Forward declaration that is used in 'struct spi_nor_controller_ops' */ 345 408 struct spi_nor; 346 409 347 410 /** ··· 318 489 int (*erase)(struct spi_nor *nor, loff_t offs); 319 490 }; 320 491 321 321 - /** 322 322 - * struct spi_nor_locking_ops - SPI NOR locking methods 323 323 - * @lock: lock a region of the SPI NOR. 324 324 - * @unlock: unlock a region of the SPI NOR. 325 325 - * @is_locked: check if a region of the SPI NOR is completely locked 326 326 - */ 327 327 - struct spi_nor_locking_ops { 328 328 - int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 329 329 - int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 330 330 - int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 331 331 - }; 332 332 - 333 333 - /** 334 334 - * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. 335 335 - * Includes legacy flash parameters and settings that can be overwritten 336 336 - * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 337 337 - * Serial Flash Discoverable Parameters (SFDP) tables. 338 338 - * 339 339 - * @size: the flash memory density in bytes. 340 340 - * @page_size: the page size of the SPI NOR flash memory. 341 341 - * @hwcaps: describes the read and page program hardware 342 342 - * capabilities. 343 343 - * @reads: read capabilities ordered by priority: the higher index 344 344 - * in the array, the higher priority. 345 345 - * @page_programs: page program capabilities ordered by priority: the 346 346 - * higher index in the array, the higher priority. 347 347 - * @erase_map: the erase map parsed from the SFDP Sector Map Parameter 348 348 - * Table. 349 349 - * @quad_enable: enables SPI NOR quad mode. 350 350 - * @set_4byte: puts the SPI NOR in 4 byte addressing mode. 351 351 - * @convert_addr: converts an absolute address into something the flash 352 352 - * will understand. Particularly useful when pagesize is 353 353 - * not a power-of-2. 354 354 - * @setup: configures the SPI NOR memory. Useful for SPI NOR 355 355 - * flashes that have peculiarities to the SPI NOR standard 356 356 - * e.g. different opcodes, specific address calculation, 357 357 - * page size, etc. 358 358 - * @locking_ops: SPI NOR locking methods. 359 359 - */ 360 360 - struct spi_nor_flash_parameter { 361 361 - u64 size; 362 362 - u32 page_size; 363 363 - 364 364 - struct spi_nor_hwcaps hwcaps; 365 365 - struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 366 366 - struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 367 367 - 368 368 - struct spi_nor_erase_map erase_map; 369 369 - 370 370 - int (*quad_enable)(struct spi_nor *nor); 371 371 - int (*set_4byte)(struct spi_nor *nor, bool enable); 372 372 - u32 (*convert_addr)(struct spi_nor *nor, u32 addr); 373 373 - int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); 374 374 - 375 375 - const struct spi_nor_locking_ops *locking_ops; 376 376 - }; 377 377 - 378 378 - /** 379 379 - * struct flash_info - Forward declaration of a structure used internally by 380 380 - * spi_nor_scan() 492 492 + /* 493 493 + * Forward declarations that are used internally by the core and manufacturer 494 494 + * drivers. 381 495 */ 382 496 struct flash_info; 497 497 + struct spi_nor_manufacturer; 498 498 + struct spi_nor_flash_parameter; 383 499 384 500 /** 385 501 * struct spi_nor - Structure for defining a the SPI NOR layer ··· 336 562 * layer is not DMA-able 337 563 * @bouncebuf_size: size of the bounce buffer 338 564 * @info: spi-nor part JDEC MFR id and other info 565 565 + * @manufacturer: spi-nor manufacturer 339 566 * @page_size: the page size of the SPI NOR 340 567 * @addr_width: number of address bytes 341 568 * @erase_opcode: the opcode for erasing a sector ··· 353 578 * The structure includes legacy flash parameters and 354 579 * settings that can be overwritten by the spi_nor_fixups 355 580 * hooks, or dynamically when parsing the SFDP tables. 581 581 + * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes. 356 582 * @priv: the private data 357 583 */ 358 584 struct spi_nor { ··· 364 588 u8 *bouncebuf; 365 589 size_t bouncebuf_size; 366 590 const struct flash_info *info; 591 591 + const struct spi_nor_manufacturer *manufacturer; 367 592 u32 page_size; 368 593 u8 addr_width; 369 594 u8 erase_opcode; ··· 379 602 380 603 const struct spi_nor_controller_ops *controller_ops; 381 604 382 382 - struct spi_nor_flash_parameter params; 605 605 + struct spi_nor_flash_parameter *params; 606 606 + 607 607 + struct { 608 608 + struct spi_mem_dirmap_desc *rdesc; 609 609 + struct spi_mem_dirmap_desc *wdesc; 610 610 + } dirmap; 383 611 384 612 void *priv; 385 613 }; 386 386 - 387 387 - static u64 __maybe_unused 388 388 - spi_nor_region_is_last(const struct spi_nor_erase_region *region) 389 389 - { 390 390 - return region->offset & SNOR_LAST_REGION; 391 391 - } 392 392 - 393 393 - static u64 __maybe_unused 394 394 - spi_nor_region_end(const struct spi_nor_erase_region *region) 395 395 - { 396 396 - return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 397 397 - } 398 398 - 399 399 - static void __maybe_unused 400 400 - spi_nor_region_mark_end(struct spi_nor_erase_region *region) 401 401 - { 402 402 - region->offset |= SNOR_LAST_REGION; 403 403 - } 404 404 - 405 405 - static void __maybe_unused 406 406 - spi_nor_region_mark_overlay(struct spi_nor_erase_region *region) 407 407 - { 408 408 - region->offset |= SNOR_OVERLAID_REGION; 409 409 - } 410 410 - 411 411 - static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor) 412 412 - { 413 413 - return !!nor->params.erase_map.uniform_erase_type; 414 414 - } 415 614 416 615 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 417 616 struct device_node *np)

+45 -22

include/linux/mtd/spinand.h

reviewed

··· 32 32 SPI_MEM_OP_NO_DUMMY, \ 33 33 SPI_MEM_OP_NO_DATA) 34 34 35 35 - #define SPINAND_READID_OP(ndummy, buf, len) \ 35 35 + #define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 36 36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 37 37 - SPI_MEM_OP_NO_ADDR, \ 37 37 + SPI_MEM_OP_ADDR(naddr, 0, 1), \ 38 38 SPI_MEM_OP_DUMMY(ndummy, 1), \ 39 39 SPI_MEM_OP_DATA_IN(len, buf, 1)) 40 40 ··· 176 176 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 177 177 * be extended if required 178 178 * @len: ID length 179 179 - * 180 180 - * struct_spinand_id->data contains all bytes returned after a READ_ID command, 181 181 - * including dummy bytes if the chip does not emit ID bytes right after the 182 182 - * READ_ID command. The responsibility to extract real ID bytes is left to 183 183 - * struct_manufacurer_ops->detect(). 184 179 */ 185 180 struct spinand_id { 186 181 u8 data[SPINAND_MAX_ID_LEN]; 187 182 int len; 188 183 }; 189 184 185 185 + enum spinand_readid_method { 186 186 + SPINAND_READID_METHOD_OPCODE, 187 187 + SPINAND_READID_METHOD_OPCODE_ADDR, 188 188 + SPINAND_READID_METHOD_OPCODE_DUMMY, 189 189 + }; 190 190 + 191 191 + /** 192 192 + * struct spinand_devid - SPI NAND device id structure 193 193 + * @id: device id of current chip 194 194 + * @len: number of bytes in device id 195 195 + * @method: method to read chip id 196 196 + * There are 3 possible variants: 197 197 + * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 198 198 + * after read_id opcode. 199 199 + * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 200 200 + * read_id opcode + 1-byte address. 201 201 + * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 202 202 + * read_id opcode + 1 dummy byte. 203 203 + */ 204 204 + struct spinand_devid { 205 205 + const u8 *id; 206 206 + const u8 len; 207 207 + const enum spinand_readid_method method; 208 208 + }; 209 209 + 190 210 /** 191 211 * struct manufacurer_ops - SPI NAND manufacturer specific operations 192 192 - * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed 193 193 - * the core calls the struct_manufacurer_ops->detect() hook of each 194 194 - * registered manufacturer until one of them return 1. Note that 195 195 - * the first thing to check in this hook is that the manufacturer ID 196 196 - * in struct_spinand_device->id matches the manufacturer whose 197 197 - * ->detect() hook has been called. Should return 1 if there's a 198 198 - * match, 0 if the manufacturer ID does not match and a negative 199 199 - * error code otherwise. When true is returned, the core assumes 200 200 - * that properties of the NAND chip (spinand->base.memorg and 201 201 - * spinand->base.eccreq) have been filled 202 212 * @init: initialize a SPI NAND device 203 213 * @cleanup: cleanup a SPI NAND device 204 214 * 205 215 * Each SPI NAND manufacturer driver should implement this interface so that 206 206 - * NAND chips coming from this vendor can be detected and initialized properly. 216 216 + * NAND chips coming from this vendor can be initialized properly. 207 217 */ 208 218 struct spinand_manufacturer_ops { 209 209 - int (*detect)(struct spinand_device *spinand); 210 219 int (*init)(struct spinand_device *spinand); 211 220 void (*cleanup)(struct spinand_device *spinand); 212 221 }; ··· 224 215 * struct spinand_manufacturer - SPI NAND manufacturer instance 225 216 * @id: manufacturer ID 226 217 * @name: manufacturer name 218 218 + * @devid_len: number of bytes in device ID 219 219 + * @chips: supported SPI NANDs under current manufacturer 220 220 + * @nchips: number of SPI NANDs available in chips array 227 221 * @ops: manufacturer operations 228 222 */ 229 223 struct spinand_manufacturer { 230 224 u8 id; 231 225 char *name; 226 226 + const struct spinand_info *chips; 227 227 + const size_t nchips; 232 228 const struct spinand_manufacturer_ops *ops; 233 229 }; 234 230 ··· 284 270 }; 285 271 286 272 #define SPINAND_HAS_QE_BIT BIT(0) 273 273 + #define SPINAND_HAS_CR_FEAT_BIT BIT(1) 287 274 288 275 /** 289 276 * struct spinand_info - Structure used to describe SPI NAND chips ··· 306 291 */ 307 292 struct spinand_info { 308 293 const char *model; 309 309 - u16 devid; 294 294 + struct spinand_devid devid; 310 295 u32 flags; 311 296 struct nand_memory_organization memorg; 312 297 struct nand_ecc_req eccreq; ··· 319 304 int (*select_target)(struct spinand_device *spinand, 320 305 unsigned int target); 321 306 }; 307 307 + 308 308 + #define SPINAND_ID(__method, ...) \ 309 309 + { \ 310 310 + .id = (const u8[]){ __VA_ARGS__ }, \ 311 311 + .len = sizeof((u8[]){ __VA_ARGS__ }), \ 312 312 + .method = __method, \ 313 313 + } 322 314 323 315 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 324 316 { \ ··· 473 451 nanddev_set_of_node(&spinand->base, np); 474 452 } 475 453 476 476 - int spinand_match_and_init(struct spinand_device *dev, 454 454 + int spinand_match_and_init(struct spinand_device *spinand, 477 455 const struct spinand_info *table, 478 478 - unsigned int table_size, u16 devid); 456 456 + unsigned int table_size, 457 457 + enum spinand_readid_method rdid_method); 479 458 480 459 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 481 460 int spinand_select_target(struct spinand_device *spinand, unsigned int target);