Merge branch 'refactoring-rvu-nic-driver'

+2 -2

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

··· 227 227 u16 maxlen; 228 228 int err; 229 229 230 - maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 230 + maxlen = pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 231 231 232 232 mutex_lock(&pfvf->mbox.lock); 233 233 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); ··· 236 236 return -ENOMEM; 237 237 } 238 238 239 - req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 239 + req->maxlen = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 240 240 241 241 /* Use max receive length supported by hardware for loopback devices */ 242 242 if (is_otx2_lbkvf(pfvf->pdev))

+15

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

··· 228 228 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 229 229 u16 matchall_ipolicer; 230 230 u32 dwrr_mtu; 231 + u32 max_mtu; 231 232 u8 smq_link_type; 232 233 233 234 /* HW settings, coalescing etc */ ··· 997 996 int stack_pages, int numptrs, int buf_size, int type); 998 997 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 999 998 int pool_id, int numptrs); 999 + int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1000 + void otx2_free_queue_mem(struct otx2_qset *qset); 1001 + int otx2_alloc_queue_mem(struct otx2_nic *pf); 1002 + int otx2_init_hw_resources(struct otx2_nic *pfvf); 1003 + void otx2_free_hw_resources(struct otx2_nic *pf); 1004 + int otx2_wq_init(struct otx2_nic *pf); 1005 + int otx2_check_pf_usable(struct otx2_nic *pf); 1006 + int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1007 + int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1008 + int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1009 + void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1010 + void otx2_disable_mbox_intr(struct otx2_nic *pf); 1011 + void otx2_disable_napi(struct otx2_nic *pf); 1012 + irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1000 1013 1001 1014 /* RSS configuration APIs*/ 1002 1015 int otx2_rss_init(struct otx2_nic *pfvf);

+136 -92

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

··· 1008 1008 return IRQ_HANDLED; 1009 1009 } 1010 1010 1011 - static void otx2_disable_mbox_intr(struct otx2_nic *pf) 1011 + void otx2_disable_mbox_intr(struct otx2_nic *pf) 1012 1012 { 1013 1013 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1014 1014 ··· 1017 1017 free_irq(vector, pf); 1018 1018 } 1019 1019 1020 - static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1020 + int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1021 1021 { 1022 1022 struct otx2_hw *hw = &pf->hw; 1023 1023 struct msg_req *req; ··· 1061 1061 return 0; 1062 1062 } 1063 1063 1064 - static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1064 + void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1065 1065 { 1066 1066 struct mbox *mbox = &pf->mbox; 1067 1067 ··· 1077 1077 otx2_mbox_destroy(&mbox->mbox_up); 1078 1078 } 1079 1079 1080 - static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1080 + int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1081 1081 { 1082 1082 struct mbox *mbox = &pf->mbox; 1083 1083 void __iomem *hwbase; ··· 1379 1379 return IRQ_HANDLED; 1380 1380 } 1381 1381 1382 - static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1382 + irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1383 1383 { 1384 1384 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1385 1385 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; ··· 1399 1399 return IRQ_HANDLED; 1400 1400 } 1401 1401 1402 - static void otx2_disable_napi(struct otx2_nic *pf) 1402 + void otx2_disable_napi(struct otx2_nic *pf) 1403 1403 { 1404 1404 struct otx2_qset *qset = &pf->qset; 1405 1405 struct otx2_cq_poll *cq_poll; 1406 + struct work_struct *work; 1406 1407 int qidx; 1407 1408 1408 1409 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1409 1410 cq_poll = &qset->napi[qidx]; 1410 - cancel_work_sync(&cq_poll->dim.work); 1411 + work = &cq_poll->dim.work; 1412 + if (work->func) 1413 + cancel_work_sync(work); 1411 1414 napi_disable(&cq_poll->napi); 1412 1415 netif_napi_del(&cq_poll->napi); 1413 1416 } ··· 1480 1477 return ALIGN(rbuf_size, 2048); 1481 1478 } 1482 1479 1483 - static int otx2_init_hw_resources(struct otx2_nic *pf) 1480 + int otx2_init_hw_resources(struct otx2_nic *pf) 1484 1481 { 1485 1482 struct nix_lf_free_req *free_req; 1486 1483 struct mbox *mbox = &pf->mbox; ··· 1605 1602 return err; 1606 1603 } 1607 1604 1608 - static void otx2_free_hw_resources(struct otx2_nic *pf) 1605 + void otx2_free_hw_resources(struct otx2_nic *pf) 1609 1606 { 1610 1607 struct otx2_qset *qset = &pf->qset; 1611 1608 struct nix_lf_free_req *free_req; ··· 1773 1770 dim->state = DIM_START_MEASURE; 1774 1771 } 1775 1772 1776 - int otx2_open(struct net_device *netdev) 1773 + void otx2_free_queue_mem(struct otx2_qset *qset) 1777 1774 { 1778 - struct otx2_nic *pf = netdev_priv(netdev); 1779 - struct otx2_cq_poll *cq_poll = NULL; 1780 - struct otx2_qset *qset = &pf->qset; 1781 - int err = 0, qidx, vec; 1782 - char *irq_name; 1775 + kfree(qset->sq); 1776 + qset->sq = NULL; 1777 + kfree(qset->cq); 1778 + qset->cq = NULL; 1779 + kfree(qset->rq); 1780 + qset->rq = NULL; 1781 + kfree(qset->napi); 1782 + qset->napi = NULL; 1783 + } 1783 1784 1784 - netif_carrier_off(netdev); 1785 + int otx2_alloc_queue_mem(struct otx2_nic *pf) 1786 + { 1787 + struct otx2_qset *qset = &pf->qset; 1788 + struct otx2_cq_poll *cq_poll; 1789 + 1785 1790 1786 1791 /* RQ and SQs are mapped to different CQs, 1787 1792 * so find out max CQ IRQs (i.e CINTs) needed. ··· 1809 1798 /* CQ size of SQ */ 1810 1799 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1811 1800 1812 - err = -ENOMEM; 1813 1801 qset->cq = kcalloc(pf->qset.cq_cnt, 1814 1802 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1815 1803 if (!qset->cq) ··· 1823 1813 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1824 1814 if (!qset->rq) 1825 1815 goto err_free_mem; 1816 + 1817 + return 0; 1818 + 1819 + err_free_mem: 1820 + otx2_free_queue_mem(qset); 1821 + return -ENOMEM; 1822 + } 1823 + 1824 + int otx2_open(struct net_device *netdev) 1825 + { 1826 + struct otx2_nic *pf = netdev_priv(netdev); 1827 + struct otx2_cq_poll *cq_poll = NULL; 1828 + struct otx2_qset *qset = &pf->qset; 1829 + int err = 0, qidx, vec; 1830 + char *irq_name; 1831 + 1832 + netif_carrier_off(netdev); 1833 + 1834 + err = otx2_alloc_queue_mem(pf); 1835 + if (err) 1836 + return err; 1826 1837 1827 1838 err = otx2_init_hw_resources(pf); 1828 1839 if (err) ··· 2010 1979 otx2_disable_napi(pf); 2011 1980 otx2_free_hw_resources(pf); 2012 1981 err_free_mem: 2013 - kfree(qset->sq); 2014 - kfree(qset->cq); 2015 - kfree(qset->rq); 2016 - kfree(qset->napi); 1982 + otx2_free_queue_mem(qset); 2017 1983 return err; 2018 1984 } 2019 1985 EXPORT_SYMBOL(otx2_open); ··· 2075 2047 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2076 2048 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2077 2049 2078 - 2079 - kfree(qset->sq); 2080 - kfree(qset->cq); 2081 - kfree(qset->rq); 2082 - kfree(qset->napi); 2050 + otx2_free_queue_mem(qset); 2083 2051 /* Do not clear RQ/SQ ringsize settings */ 2084 2052 memset_startat(qset, 0, sqe_cnt); 2085 2053 return 0; ··· 2810 2786 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2811 2787 }; 2812 2788 2813 - static int otx2_wq_init(struct otx2_nic *pf) 2789 + int otx2_wq_init(struct otx2_nic *pf) 2814 2790 { 2815 2791 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2816 2792 if (!pf->otx2_wq) ··· 2821 2797 return 0; 2822 2798 } 2823 2799 2824 - static int otx2_check_pf_usable(struct otx2_nic *nic) 2800 + int otx2_check_pf_usable(struct otx2_nic *nic) 2825 2801 { 2826 2802 u64 rev; 2827 2803 ··· 2839 2815 return 0; 2840 2816 } 2841 2817 2842 - static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2818 + int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2843 2819 { 2844 2820 struct otx2_hw *hw = &pf->hw; 2845 2821 int num_vec, err; ··· 2896 2872 } 2897 2873 } 2898 2874 2875 + int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) 2876 + { 2877 + struct device *dev = &pdev->dev; 2878 + struct otx2_hw *hw = &pf->hw; 2879 + int num_vec, err; 2880 + 2881 + num_vec = pci_msix_vec_count(pdev); 2882 + hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2883 + GFP_KERNEL); 2884 + if (!hw->irq_name) 2885 + return -ENOMEM; 2886 + 2887 + hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2888 + sizeof(cpumask_var_t), GFP_KERNEL); 2889 + if (!hw->affinity_mask) 2890 + return -ENOMEM; 2891 + 2892 + /* Map CSRs */ 2893 + pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2894 + if (!pf->reg_base) { 2895 + dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2896 + return -ENOMEM; 2897 + } 2898 + 2899 + err = otx2_check_pf_usable(pf); 2900 + if (err) 2901 + return err; 2902 + 2903 + err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2904 + RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2905 + if (err < 0) { 2906 + dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2907 + __func__, num_vec); 2908 + return err; 2909 + } 2910 + 2911 + otx2_setup_dev_hw_settings(pf); 2912 + 2913 + /* Init PF <=> AF mailbox stuff */ 2914 + err = otx2_pfaf_mbox_init(pf); 2915 + if (err) 2916 + goto err_free_irq_vectors; 2917 + 2918 + /* Register mailbox interrupt */ 2919 + err = otx2_register_mbox_intr(pf, true); 2920 + if (err) 2921 + goto err_mbox_destroy; 2922 + 2923 + /* Request AF to attach NPA and NIX LFs to this PF. 2924 + * NIX and NPA LFs are needed for this PF to function as a NIC. 2925 + */ 2926 + err = otx2_attach_npa_nix(pf); 2927 + if (err) 2928 + goto err_disable_mbox_intr; 2929 + 2930 + err = otx2_realloc_msix_vectors(pf); 2931 + if (err) 2932 + goto err_detach_rsrc; 2933 + 2934 + err = cn10k_lmtst_init(pf); 2935 + if (err) 2936 + goto err_detach_rsrc; 2937 + 2938 + return 0; 2939 + 2940 + err_detach_rsrc: 2941 + if (pf->hw.lmt_info) 2942 + free_percpu(pf->hw.lmt_info); 2943 + if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2944 + qmem_free(pf->dev, pf->dync_lmt); 2945 + otx2_detach_resources(&pf->mbox); 2946 + err_disable_mbox_intr: 2947 + otx2_disable_mbox_intr(pf); 2948 + err_mbox_destroy: 2949 + otx2_pfaf_mbox_destroy(pf); 2950 + err_free_irq_vectors: 2951 + pci_free_irq_vectors(hw->pdev); 2952 + 2953 + return err; 2954 + } 2955 + 2899 2956 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2900 2957 { 2901 2958 struct device *dev = &pdev->dev; ··· 2984 2879 struct net_device *netdev; 2985 2880 struct otx2_nic *pf; 2986 2881 struct otx2_hw *hw; 2987 - int num_vec; 2988 2882 2989 2883 err = pcim_enable_device(pdev); 2990 2884 if (err) { ··· 3034 2930 /* Use CQE of 128 byte descriptor size by default */ 3035 2931 hw->xqe_size = 128; 3036 2932 3037 - num_vec = pci_msix_vec_count(pdev); 3038 - hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 3039 - GFP_KERNEL); 3040 - if (!hw->irq_name) { 3041 - err = -ENOMEM; 3042 - goto err_free_netdev; 3043 - } 3044 - 3045 - hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 3046 - sizeof(cpumask_var_t), GFP_KERNEL); 3047 - if (!hw->affinity_mask) { 3048 - err = -ENOMEM; 3049 - goto err_free_netdev; 3050 - } 3051 - 3052 - /* Map CSRs */ 3053 - pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 3054 - if (!pf->reg_base) { 3055 - dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 3056 - err = -ENOMEM; 3057 - goto err_free_netdev; 3058 - } 3059 - 3060 - err = otx2_check_pf_usable(pf); 2933 + err = otx2_init_rsrc(pdev, pf); 3061 2934 if (err) 3062 2935 goto err_free_netdev; 3063 - 3064 - err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 3065 - RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 3066 - if (err < 0) { 3067 - dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 3068 - __func__, num_vec); 3069 - goto err_free_netdev; 3070 - } 3071 - 3072 - otx2_setup_dev_hw_settings(pf); 3073 - 3074 - /* Init PF <=> AF mailbox stuff */ 3075 - err = otx2_pfaf_mbox_init(pf); 3076 - if (err) 3077 - goto err_free_irq_vectors; 3078 - 3079 - /* Register mailbox interrupt */ 3080 - err = otx2_register_mbox_intr(pf, true); 3081 - if (err) 3082 - goto err_mbox_destroy; 3083 - 3084 - /* Request AF to attach NPA and NIX LFs to this PF. 3085 - * NIX and NPA LFs are needed for this PF to function as a NIC. 3086 - */ 3087 - err = otx2_attach_npa_nix(pf); 3088 - if (err) 3089 - goto err_disable_mbox_intr; 3090 - 3091 - err = otx2_realloc_msix_vectors(pf); 3092 - if (err) 3093 - goto err_detach_rsrc; 3094 2936 3095 2937 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 3096 - if (err) 3097 - goto err_detach_rsrc; 3098 - 3099 - err = cn10k_lmtst_init(pf); 3100 2938 if (err) 3101 2939 goto err_detach_rsrc; 3102 2940 ··· 3104 3058 3105 3059 netdev->min_mtu = OTX2_MIN_MTU; 3106 3060 netdev->max_mtu = otx2_get_max_mtu(pf); 3061 + hw->max_mtu = netdev->max_mtu; 3107 3062 3108 3063 /* reset CGX/RPM MAC stats */ 3109 3064 otx2_reset_mac_stats(pf); ··· 3165 3118 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3166 3119 qmem_free(pf->dev, pf->dync_lmt); 3167 3120 otx2_detach_resources(&pf->mbox); 3168 - err_disable_mbox_intr: 3169 3121 otx2_disable_mbox_intr(pf); 3170 - err_mbox_destroy: 3171 3122 otx2_pfaf_mbox_destroy(pf); 3172 - err_free_irq_vectors: 3173 3123 pci_free_irq_vectors(hw->pdev); 3174 3124 err_free_netdev: 3175 3125 pci_set_drvdata(pdev, NULL);

+3 -2

drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c

··· 500 500 .ndo_setup_tc = otx2_setup_tc, 501 501 }; 502 502 503 - static int otx2_wq_init(struct otx2_nic *vf) 503 + static int otx2_vf_wq_init(struct otx2_nic *vf) 504 504 { 505 505 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 506 506 if (!vf->otx2_wq) ··· 671 671 672 672 netdev->min_mtu = OTX2_MIN_MTU; 673 673 netdev->max_mtu = otx2_get_max_mtu(vf); 674 + hw->max_mtu = netdev->max_mtu; 674 675 675 676 /* To distinguish, for LBK VFs set netdev name explicitly */ 676 677 if (is_otx2_lbkvf(vf->pdev)) { ··· 689 688 goto err_ptp_destroy; 690 689 } 691 690 692 - err = otx2_wq_init(vf); 691 + err = otx2_vf_wq_init(vf); 693 692 if (err) 694 693 goto err_unreg_netdev; 695 694

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