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riscv: dts: starfive: visionfive-v1: Setup ethernet phy

The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
RGMII-ID, but requires manual adjustment of the RX internal delay to
work properly.

The default RX delay provided by the driver is 1.95 ns, which proves to
be too high. Applying a 50% reduction seems to mitigate the issue.

Also note this adjustment is not necessary on BeagleV Starlight SBC,
which uses a Microchip PHY. Hence, there is no indication of a
misbehaviour on the GMAC side, but most likely the issue stems from
the Motorcomm PHY.

While at it, drop the redundant gpio include, which is already provided
by jh7100-common.dtsi.

Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

authored by

Cristian Ciocaltea and committed by
Conor Dooley e16d3dc0 6e204aa2

+21 -1
+21 -1
arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
··· 6 6 7 7 /dts-v1/; 8 8 #include "jh7100-common.dtsi" 9 - #include <dt-bindings/gpio/gpio.h> 10 9 11 10 / { 12 11 model = "StarFive VisionFive V1"; ··· 15 16 compatible = "gpio-restart"; 16 17 gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; 17 18 priority = <224>; 19 + }; 20 + }; 21 + 22 + &gmac { 23 + phy-handle = <&phy>; 24 + }; 25 + 26 + /* 27 + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires 28 + * manual adjustment of the RX internal delay to work properly. The default 29 + * RX delay provided by the driver (1.95ns) is too high, but applying a 50% 30 + * reduction seems to mitigate the issue. 31 + * 32 + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC, 33 + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one 34 + * responsible for the misbehaviour, not the GMAC. 35 + */ 36 + &mdio { 37 + phy: ethernet-phy@0 { 38 + reg = <0>; 39 + rx-internal-delay-ps = <900>; 18 40 }; 19 41 };