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phy: fix build breakage: add PHY_MODE_SATA

Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
build failure for me, with today's linux.git.

Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
in the Marvell Berlin SATA PHY driver.

Fix the build by:

1) Renaming Marvell's defined value to a more scoped name,
in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.

2) Adding the missing enum, which was going to be added anyway as part
of [1].

[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com

Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")

Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Acked-by: Jens Axboe <axboe@kernel.dk>
Acked-by: Olof Johansson <olof@lixom.net>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

John Hubbard and committed by
Linus Torvalds e1706720 b8c3b899

+4 -2
+3 -2
drivers/phy/marvell/phy-berlin-sata.c
··· 32 32 33 33 /* register 0x01 */ 34 34 #define REF_FREF_SEL_25 BIT(0) 35 - #define PHY_MODE_SATA (0x0 << 5) 35 + #define PHY_BERLIN_MODE_SATA (0x0 << 5) 36 36 37 37 /* register 0x02 */ 38 38 #define USE_MAX_PLL_RATE BIT(12) ··· 102 102 103 103 /* set PHY mode and ref freq to 25 MHz */ 104 104 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, 105 - 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA); 105 + 0x00ff, 106 + REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA); 106 107 107 108 /* set PHY up to 6 Gbps */ 108 109 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
+1
include/linux/phy/phy.h
··· 42 42 PHY_MODE_PCIE, 43 43 PHY_MODE_ETHERNET, 44 44 PHY_MODE_MIPI_DPHY, 45 + PHY_MODE_SATA 45 46 }; 46 47 47 48 /**