tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull ARM64 fixes from Catalin Marinas:
- Exception level check at boot time (for completeness, not triggering
any bug before)
- I/D-cache synchronisation logic for huge pages
- Config symbol typo

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: fix el2_setup check of CurrentEL
arm64: mm: Make icache synchronisation logic huge page aware
arm64: mm: Fix horrendous config typo

Linus Torvalds e1a08b85 77c4cf17

+9 -6
+1 -1
arch/arm64/include/asm/pgtable.h
··· 292 292 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 293 293 PMD_TYPE_SECT) 294 294 295 - #ifdef ARM64_64K_PAGES 295 + #ifdef CONFIG_ARM64_64K_PAGES 296 296 #define pud_sect(pud) (0) 297 297 #else 298 298 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
+4
arch/arm64/include/asm/ptrace.h
··· 21 21 22 22 #include <uapi/asm/ptrace.h> 23 23 24 + /* Current Exception Level values, as contained in CurrentEL */ 25 + #define CurrentEL_EL1 (1 << 2) 26 + #define CurrentEL_EL2 (2 << 2) 27 + 24 28 /* AArch32-specific ptrace requests */ 25 29 #define COMPAT_PTRACE_GETREGS 12 26 30 #define COMPAT_PTRACE_SETREGS 13
+1 -2
arch/arm64/kernel/efi-entry.S
··· 78 78 79 79 /* Turn off Dcache and MMU */ 80 80 mrs x0, CurrentEL 81 - cmp x0, #PSR_MODE_EL2t 82 - ccmp x0, #PSR_MODE_EL2h, #0x4, ne 81 + cmp x0, #CurrentEL_EL2 83 82 b.ne 1f 84 83 mrs x0, sctlr_el2 85 84 bic x0, x0, #1 << 0 // clear SCTLR.M
+1 -2
arch/arm64/kernel/head.S
··· 270 270 */ 271 271 ENTRY(el2_setup) 272 272 mrs x0, CurrentEL 273 - cmp x0, #PSR_MODE_EL2t 274 - ccmp x0, #PSR_MODE_EL2h, #0x4, ne 273 + cmp x0, #CurrentEL_EL2 275 274 b.ne 1f 276 275 mrs x0, sctlr_el2 277 276 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
+2 -1
arch/arm64/mm/flush.c
··· 79 79 return; 80 80 81 81 if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { 82 - __flush_dcache_area(page_address(page), PAGE_SIZE); 82 + __flush_dcache_area(page_address(page), 83 + PAGE_SIZE << compound_order(page)); 83 84 __flush_icache_all(); 84 85 } else if (icache_is_aivivt()) { 85 86 __flush_icache_all();