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clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc

All SoC supported by this driver supports the RETAIN_FF_ENABLE flag,
so it should be enabled here.

This feature enables registers to maintain their state after
dis/re-enabling the GDSC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org

authored by

Robert Foss and committed by
Bjorn Andersson e1a297a6 b5f84650

+1 -1
+1 -1
drivers/clk/qcom/dispcc-sm8250.c
··· 1137 1137 .name = "mdss_gdsc", 1138 1138 }, 1139 1139 .pwrsts = PWRSTS_OFF_ON, 1140 - .flags = HW_CTRL, 1140 + .flags = HW_CTRL | RETAIN_FF_ENABLE, 1141 1141 }; 1142 1142 1143 1143 static struct clk_regmap *disp_cc_sm8250_clocks[] = {