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net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz

Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
Loongson STMMAC use 125MHz clocks and need 62 freq division to within
2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
to 100-150MHz, otherwise some PHYs may link fail.

Cc: stable@vger.kernel.org
Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson")
Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Huacai Chen and committed by
Jakub Kicinski e1aa5ef8 c89477ad

+2 -2
+2 -2
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
··· 91 91 /* Get bus_id, this can be overwritten later */ 92 92 plat->bus_id = pci_dev_id(pdev); 93 93 94 - /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 95 - plat->clk_csr = STMMAC_CSR_20_35M; 94 + /* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */ 95 + plat->clk_csr = STMMAC_CSR_100_150M; 96 96 plat->core_type = DWMAC_CORE_GMAC; 97 97 plat->force_sf_dma_mode = 1; 98 98