Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Reserve ECAM so we don't assign it to PCI BARs; this works around
bugs where BIOS included ECAM in a PNP0A03 host bridge window,
didn't reserve it via a PNP0C02 motherboard device, and didn't
allocate space for SR-IOV VF BARs (Bjorn Helgaas)
- Add MMCONFIG/ECAM debug logging (Bjorn Helgaas)
- Rename 'MMCONFIG' to 'ECAM' to match spec usage (Bjorn Helgaas)
- Log device type (Root Port, Switch Port, etc) during enumeration
(Bjorn Helgaas)
- Log bridges before downstream devices so the dmesg order is more
logical (Bjorn Helgaas)
- Log resource names (BAR 0, VF BAR 0, bridge window, etc)
consistently instead of a mix of names and "reg 0x10" (Puranjay
Mohan, Bjorn Helgaas)
- Fix 64GT/s effective data rate calculation to use 1b/1b encoding
rather than the 8b/10b or 128b/130b used by lower rates (Ilpo
Järvinen)
- Use PCI_HEADER_TYPE_* instead of literals in x86, powerpc, SCSI
lpfc (Ilpo Järvinen)
- Clean up open-coded PCIBIOS return code mangling (Ilpo Järvinen)
Resource management:
- Restructure pci_dev_for_each_resource() to avoid computing the
address of an out-of-bounds array element (the bounds check was
performed later so the element was never actually *read*, but it's
nicer to avoid even computing an out-of-bounds address) (Andy
Shevchenko)
Driver binding:
- Convert pci-host-common.c platform .remove() callback to
.remove_new() returning 'void' since it's not useful to return
error codes here (Uwe Kleine-König)
- Convert exynos, keystone, kirin from .remove() to .remove_new(),
which returns void instead of int (Uwe Kleine-König)
- Drop unused struct pci_driver.node member (Mathias Krause)
Virtualization:
- Add ACS quirk for more Zhaoxin Root Ports (LeoLiuoc)
Error handling:
- Log AER errors as "Correctable" (not "Corrected") or
"Uncorrectable" to match spec terminology (Bjorn Helgaas)
- Decode Requester ID when no error info found instead of printing
the raw hex value (Bjorn Helgaas)
Endpoint framework:
- Use a unique test pattern for each BAR in the pci_endpoint_test to
make it easier to debug address translation issues (Niklas Cassel)
Broadcom STB PCIe controller driver:
- Add DT property "brcm,clkreq-mode" and driver support for different
CLKREQ# modes to make ASPM L1.x states possible (Jim Quinlan)
Freescale Layerscape PCIe controller driver:
- Add suspend/resume support for Layerscape LS1043a and LS1021a,
including software-managed PME_Turn_Off and transitions between L0,
L2/L3_Ready Link states (Frank Li)
MediaTek PCIe controller driver:
- Clear MSI interrupt status before handler to avoid missing MSIs
that occur after the handler (qizhong cheng)
MediaTek PCIe Gen3 controller driver:
- Update mediatek-gen3 translation window setup to handle MMIO space
that is not a power of two in size (Jianjun Wang)
Qualcomm PCIe controller driver:
- Increase qcom iommu-map maxItems to accommodate SDX55 (five
entries) and SDM845 (sixteen entries) (Krzysztof Kozlowski)
- Describe qcom,pcie-sc8180x clocks and resets accurately (Krzysztof
Kozlowski)
- Describe qcom,pcie-sm8150 clocks and resets accurately (Krzysztof
Kozlowski)
- Correct the qcom "reset-name" property, previously incorrectly
called "reset-names" (Krzysztof Kozlowski)
- Document qcom,pcie-sm8650, based on qcom,pcie-sm8550 (Neil
Armstrong)
Renesas R-Car PCIe controller driver:
- Replace of_device.h with explicit of.h include to untangle header
usage (Rob Herring)
- Add DT and driver support for optional miniPCIe 1.5v and 3.3v
regulators on KingFisher (Wolfram Sang)
SiFive FU740 PCIe controller driver:
- Convert fu740 CONFIG_PCIE_FU740 dependency from SOC_SIFIVE to
ARCH_SIFIVE (Conor Dooley)
Synopsys DesignWare PCIe controller driver:
- Align iATU mapping for endpoint MSI-X (Niklas Cassel)
- Drop "host_" prefix from struct dw_pcie_host_ops members (Yoshihiro
Shimoda)
- Drop "ep_" prefix from struct dw_pcie_ep_ops members (Yoshihiro
Shimoda)
- Rename struct dw_pcie_ep_ops.func_conf_select() to
.get_dbi_offset() to be more descriptive (Yoshihiro Shimoda)
- Add Endpoint DBI accessors to encapsulate offset lookups (Yoshihiro
Shimoda)
TI J721E PCIe driver:
- Add j721e DT and driver support for 'num-lanes' for devices that
support x1, x2, or x4 Links (Matt Ranostay)
- Add j721e DT compatible strings and driver support for j784s4 (Matt
Ranostay)
- Make TI J721E Kconfig depend on ARCH_K3 since the hardware is
specific to those TI SoC parts (Peter Robinson)
TI Keystone PCIe controller driver:
- Hold power management references to all PHYs while enabling them to
avoid a race when one provides clocks to others (Siddharth
Vadapalli)
Xilinx XDMA PCIe controller driver:
- Remove redundant dev_err(), since platform_get_irq() and
platform_get_irq_byname() already log errors (Yang Li)
- Fix uninitialized symbols in xilinx_pl_dma_pcie_setup_irq()
(Krzysztof Wilczyński)
- Fix xilinx_pl_dma_pcie_init_irq_domain() error return when
irq_domain_add_linear() fails (Harshit Mogalapalli)
MicroSemi Switchtec management driver:
- Do dma_mrpc cleanup during switchtec_pci_remove() to match its devm
ioremapping in switchtec_pci_probe(). Previously the cleanup was
done in stdev_release(), which used stale pointers if stdev->cdev
happened to be open when the PCI device was removed (Daniel
Stodden)
Miscellaneous:
- Convert interrupt terminology from "legacy" to "INTx" to be more
specific and match spec terminology (Damien Le Moal)
- In dw-xdata-pcie, pci_endpoint_test, and vmd, replace usage of
deprecated ida_simple_*() API with ida_alloc() and ida_free()
(Christophe JAILLET)"
* tag 'pci-v6.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (97 commits)
PCI: Fix kernel-doc issues
PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device
dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode"
PCI: mediatek-gen3: Fix translation window size calculation
PCI: mediatek: Clear interrupt status before dispatching handler
PCI: keystone: Fix race condition when initializing PHYs
PCI: xilinx-xdma: Fix error code in xilinx_pl_dma_pcie_init_irq_domain()
PCI: xilinx-xdma: Fix uninitialized symbols in xilinx_pl_dma_pcie_setup_irq()
PCI: rcar-gen4: Fix -Wvoid-pointer-to-enum-cast error
PCI: iproc: Fix -Wvoid-pointer-to-enum-cast warning
PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers
PCI: dwc: Rename .func_conf_select to .get_dbi_offset in struct dw_pcie_ep_ops
PCI: dwc: Rename .ep_init to .init in struct dw_pcie_ep_ops
PCI: dwc: Drop host prefix from struct dw_pcie_host_ops members
misc: pci_endpoint_test: Use a unique test pattern for each BAR
PCI: j721e: Make TI J721E depend on ARCH_K3
PCI: j721e: Add TI J784S4 PCIe configuration
PCI/AER: Use explicit register sizes for struct members
PCI/AER: Decode Requester ID when no error info found
PCI/AER: Use 'Correctable' and 'Uncorrectable' spec terms for errors
...
+1519
-877
+1
-1
Documentation/PCI/boot-interrupts.rst
+1
-1
Documentation/PCI/boot-interrupts.rst
···
61
61
==========
62
62
63
63
The use of threaded interrupts is the most likely condition to trigger
64
-
this problem today. Threaded interrupts may not be reenabled after the IRQ
64
+
this problem today. Threaded interrupts may not be re-enabled after the IRQ
65
65
handler wakes. These "one shot" conditions mean that the threaded interrupt
66
66
needs to keep the interrupt line masked until the threaded handler has run.
67
67
Especially when dealing with high data rate interrupts, the thread needs to
+1
-1
Documentation/PCI/msi-howto.rst
+1
-1
Documentation/PCI/msi-howto.rst
···
236
236
Disabling MSIs below a bridge
237
237
-----------------------------
238
238
239
-
Some PCI bridges are not able to route MSIs between busses properly.
239
+
Some PCI bridges are not able to route MSIs between buses properly.
240
240
In this case, MSIs must be disabled on all devices behind the bridge.
241
241
242
242
Some bridges allow you to enable MSIs by changing some bits in their
+18
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+18
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
···
64
64
65
65
aspm-no-l0s: true
66
66
67
+
brcm,clkreq-mode:
68
+
description: A string that determines the operating
69
+
clkreq mode of the PCIe RC HW with respect to controlling the refclk
70
+
signal. There are three different modes -- "safe", which drives the
71
+
refclk signal unconditionally and will work for all devices but does
72
+
not provide any power savings; "no-l1ss" -- which provides Clock
73
+
Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
74
+
power savings. If the downstream device connected to the RC is L1SS
75
+
capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
76
+
potentially hanging the system; "default" -- which provides L0s, L1,
77
+
and L1SS, but not compliant to provide Clock Power Management;
78
+
specifically, may not be able to meet the T_CLRon max timing of 400ns
79
+
as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI
80
+
Express Mini CEM 2.1 specification. This situation is atypical and
81
+
should happen only with older devices.
82
+
$ref: /schemas/types.yaml#/definitions/string
83
+
enum: [ safe, no-l1ss, default ]
84
+
67
85
brcm,scb-sizes:
68
86
description: u64 giving the 64bit PCIe memory
69
87
viewport size of a memory controller. There may be up to
+60
-3
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+60
-3
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
···
42
42
- qcom,pcie-sm8450-pcie1
43
43
- qcom,pcie-sm8550
44
44
- items:
45
+
- enum:
46
+
- qcom,pcie-sm8650
47
+
- const: qcom,pcie-sm8550
48
+
- items:
45
49
- const: qcom,pcie-msm8998
46
50
- const: qcom,pcie-msm8996
47
51
···
66
62
maxItems: 8
67
63
68
64
iommu-map:
69
-
maxItems: 2
65
+
minItems: 1
66
+
maxItems: 16
70
67
71
68
# Common definitions for clocks, clock-names and reset.
72
69
# Platform constraints are described later.
···
93
88
minItems: 1
94
89
maxItems: 12
95
90
96
-
resets-names:
91
+
reset-names:
97
92
minItems: 1
98
93
maxItems: 12
99
94
···
488
483
compatible:
489
484
contains:
490
485
enum:
486
+
- qcom,pcie-sc8180x
487
+
then:
488
+
properties:
489
+
clocks:
490
+
minItems: 8
491
+
maxItems: 8
492
+
clock-names:
493
+
items:
494
+
- const: pipe # PIPE clock
495
+
- const: aux # Auxiliary clock
496
+
- const: cfg # Configuration clock
497
+
- const: bus_master # Master AXI clock
498
+
- const: bus_slave # Slave AXI clock
499
+
- const: slave_q2a # Slave Q2A clock
500
+
- const: ref # REFERENCE clock
501
+
- const: tbu # PCIe TBU clock
502
+
resets:
503
+
maxItems: 1
504
+
reset-names:
505
+
items:
506
+
- const: pci # PCIe core reset
507
+
508
+
- if:
509
+
properties:
510
+
compatible:
511
+
contains:
512
+
enum:
491
513
- qcom,pcie-sdm845
492
514
then:
493
515
oneOf:
···
558
526
compatible:
559
527
contains:
560
528
enum:
561
-
- qcom,pcie-sc8180x
562
529
- qcom,pcie-sm8150
530
+
then:
531
+
properties:
532
+
clocks:
533
+
minItems: 8
534
+
maxItems: 8
535
+
clock-names:
536
+
items:
537
+
- const: pipe # PIPE clock
538
+
- const: aux # Auxiliary clock
539
+
- const: cfg # Configuration clock
540
+
- const: bus_master # Master AXI clock
541
+
- const: bus_slave # Slave AXI clock
542
+
- const: slave_q2a # Slave Q2A clock
543
+
- const: tbu # PCIe TBU clock
544
+
- const: ref # REFERENCE clock
545
+
resets:
546
+
maxItems: 1
547
+
reset-names:
548
+
items:
549
+
- const: pci # PCIe core reset
550
+
551
+
- if:
552
+
properties:
553
+
compatible:
554
+
contains:
555
+
enum:
563
556
- qcom,pcie-sm8250
564
557
then:
565
558
oneOf:
+11
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
+11
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
···
68
68
phy-names:
69
69
const: pcie
70
70
71
+
vpcie1v5-supply:
72
+
description: The 1.5v regulator to use for PCIe.
73
+
74
+
vpcie3v3-supply:
75
+
description: The 3.3v regulator to use for PCIe.
76
+
77
+
vpcie12v-supply:
78
+
description: The 12v regulator to use for PCIe.
79
+
71
80
required:
72
81
- compatible
73
82
- reg
···
130
121
clock-names = "pcie", "pcie_bus";
131
122
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
132
123
resets = <&cpg 319>;
124
+
vpcie3v3-supply = <&pcie_3v3>;
125
+
vpcie12v-supply = <&pcie_12v>;
133
126
};
134
127
};
+2
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+2
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
···
49
49
- description: APB clock for PCIe
50
50
- description: Auxiliary clock for PCIe
51
51
- description: PIPE clock
52
+
- description: Reference clock for PCIe
52
53
53
54
clock-names:
54
55
minItems: 5
···
60
59
- const: pclk
61
60
- const: aux
62
61
- const: pipe
62
+
- const: ref
63
63
64
64
interrupts:
65
65
items:
+36
-3
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+36
-3
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
···
10
10
maintainers:
11
11
- Kishon Vijay Abraham I <kishon@ti.com>
12
12
13
-
allOf:
14
-
- $ref: cdns-pcie-ep.yaml#
15
-
16
13
properties:
17
14
compatible:
18
15
oneOf:
19
16
- const: ti,j721e-pcie-ep
17
+
- const: ti,j784s4-pcie-ep
20
18
- description: PCIe EP controller in AM64
21
19
items:
22
20
- const: ti,am64-pcie-ep
···
62
64
interrupt-names:
63
65
items:
64
66
- const: link_state
67
+
68
+
allOf:
69
+
- $ref: cdns-pcie-ep.yaml#
70
+
- if:
71
+
properties:
72
+
compatible:
73
+
enum:
74
+
- ti,am64-pcie-ep
75
+
then:
76
+
properties:
77
+
num-lanes:
78
+
const: 1
79
+
80
+
- if:
81
+
properties:
82
+
compatible:
83
+
enum:
84
+
- ti,j7200-pcie-ep
85
+
- ti,j721e-pcie-ep
86
+
then:
87
+
properties:
88
+
num-lanes:
89
+
minimum: 1
90
+
maximum: 2
91
+
92
+
- if:
93
+
properties:
94
+
compatible:
95
+
enum:
96
+
- ti,j784s4-pcie-ep
97
+
then:
98
+
properties:
99
+
num-lanes:
100
+
minimum: 1
101
+
maximum: 4
65
102
66
103
required:
67
104
- compatible
+36
-3
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+36
-3
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
···
10
10
maintainers:
11
11
- Kishon Vijay Abraham I <kishon@ti.com>
12
12
13
-
allOf:
14
-
- $ref: cdns-pcie-host.yaml#
15
-
16
13
properties:
17
14
compatible:
18
15
oneOf:
19
16
- const: ti,j721e-pcie-host
17
+
- const: ti,j784s4-pcie-host
20
18
- description: PCIe controller in AM64
21
19
items:
22
20
- const: ti,am64-pcie-host
···
91
93
92
94
interrupts:
93
95
maxItems: 1
96
+
97
+
allOf:
98
+
- $ref: cdns-pcie-host.yaml#
99
+
- if:
100
+
properties:
101
+
compatible:
102
+
enum:
103
+
- ti,am64-pcie-host
104
+
then:
105
+
properties:
106
+
num-lanes:
107
+
const: 1
108
+
109
+
- if:
110
+
properties:
111
+
compatible:
112
+
enum:
113
+
- ti,j7200-pcie-host
114
+
- ti,j721e-pcie-host
115
+
then:
116
+
properties:
117
+
num-lanes:
118
+
minimum: 1
119
+
maximum: 2
120
+
121
+
- if:
122
+
properties:
123
+
compatible:
124
+
enum:
125
+
- ti,j784s4-pcie-host
126
+
then:
127
+
properties:
128
+
num-lanes:
129
+
minimum: 1
130
+
maximum: 4
94
131
95
132
required:
96
133
- compatible
+3
-13
Documentation/driver-api/pci/p2pdma.rst
+3
-13
Documentation/driver-api/pci/p2pdma.rst
···
83
83
Client Drivers
84
84
--------------
85
85
86
-
A client driver typically only has to conditionally change its DMA map
87
-
routine to use the mapping function :c:func:`pci_p2pdma_map_sg()` instead
88
-
of the usual :c:func:`dma_map_sg()` function. Memory mapped in this
89
-
way does not need to be unmapped.
90
-
91
-
The client may also, optionally, make use of
92
-
:c:func:`is_pci_p2pdma_page()` to determine when to use the P2P mapping
93
-
functions and when to use the regular mapping functions. In some
94
-
situations, it may be more appropriate to use a flag to indicate a
95
-
given request is P2P memory and map appropriately. It is important to
96
-
ensure that struct pages that back P2P memory stay out of code that
97
-
does not have support for them as other code may treat the pages as
98
-
regular memory which may not be appropriate.
86
+
A client driver only has to use the mapping API :c:func:`dma_map_sg()`
87
+
and :c:func:`dma_unmap_sg()` functions as usual, and the implementation
88
+
will do the right thing for the P2P capable memory.
99
89
100
90
101
91
Orchestrator Drivers
+2
-2
arch/powerpc/sysdev/fsl_pci.c
+2
-2
arch/powerpc/sysdev/fsl_pci.c
···
54
54
55
55
/* if we aren't in host mode don't bother */
56
56
pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
57
-
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
57
+
if ((hdr_type & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_BRIDGE)
58
58
return;
59
59
60
60
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
···
581
581
hose->ops = &fsl_indirect_pcie_ops;
582
582
/* For PCIE read HEADER_TYPE to identify controller mode */
583
583
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
584
-
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
584
+
if ((hdr_type & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_BRIDGE)
585
585
goto no_bridge;
586
586
587
587
} else {
+1
-2
arch/x86/kernel/aperture_64.c
+1
-2
arch/x86/kernel/aperture_64.c
+2
-2
arch/x86/kernel/early-quirks.c
+2
-2
arch/x86/kernel/early-quirks.c
···
779
779
type = read_pci_config_byte(num, slot, func,
780
780
PCI_HEADER_TYPE);
781
781
782
-
if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
782
+
if ((type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) {
783
783
sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
784
784
if (sec > num)
785
785
early_pci_scan_bus(sec);
786
786
}
787
787
788
-
if (!(type & 0x80))
788
+
if (!(type & PCI_HEADER_TYPE_MFD))
789
789
return -1;
790
790
791
791
return 0;
+3
arch/x86/pci/acpi.c
+3
arch/x86/pci/acpi.c
···
283
283
info->mcfg_added = false;
284
284
seg = info->sd.domain;
285
285
286
+
dev_dbg(dev, "%s(%04x %pR ECAM %pa)\n", __func__, seg,
287
+
&root->secondary, &root->mcfg_addr);
288
+
286
289
/* return success if MMCFG is not in use */
287
290
if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
288
291
return 0;
+1
-1
arch/x86/pci/mmconfig_32.c
+1
-1
arch/x86/pci/mmconfig_32.c
+21
-21
arch/x86/pci/mmconfig_64.c
+21
-21
arch/x86/pci/mmconfig_64.c
···
6
6
* space mapped. This allows lockless config space operation.
7
7
*/
8
8
9
+
#define pr_fmt(fmt) "PCI: " fmt
10
+
9
11
#include <linux/pci.h>
10
12
#include <linux/init.h>
11
13
#include <linux/acpi.h>
···
15
13
#include <linux/rcupdate.h>
16
14
#include <asm/e820/api.h>
17
15
#include <asm/pci_x86.h>
18
-
19
-
#define PREFIX "PCI: "
20
16
21
17
static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
22
18
{
···
111
111
return addr;
112
112
}
113
113
114
+
int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
115
+
{
116
+
cfg->virt = mcfg_ioremap(cfg);
117
+
if (!cfg->virt) {
118
+
pr_err("can't map ECAM at %pR\n", &cfg->res);
119
+
return -ENOMEM;
120
+
}
121
+
122
+
return 0;
123
+
}
124
+
125
+
void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
126
+
{
127
+
if (cfg && cfg->virt) {
128
+
iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
129
+
cfg->virt = NULL;
130
+
}
131
+
}
132
+
114
133
int __init pci_mmcfg_arch_init(void)
115
134
{
116
135
struct pci_mmcfg_region *cfg;
···
151
132
152
133
list_for_each_entry(cfg, &pci_mmcfg_list, list)
153
134
pci_mmcfg_arch_unmap(cfg);
154
-
}
155
-
156
-
int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
157
-
{
158
-
cfg->virt = mcfg_ioremap(cfg);
159
-
if (!cfg->virt) {
160
-
pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
161
-
return -ENOMEM;
162
-
}
163
-
164
-
return 0;
165
-
}
166
-
167
-
void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
168
-
{
169
-
if (cfg && cfg->virt) {
170
-
iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
171
-
cfg->virt = NULL;
172
-
}
173
135
}
+21
-7
arch/x86/pci/pcbios.c
+21
-7
arch/x86/pci/pcbios.c
···
3
3
* BIOS32 and PCI BIOS handling.
4
4
*/
5
5
6
+
#include <linux/bits.h>
7
+
#include <linux/bitfield.h>
6
8
#include <linux/pci.h>
7
9
#include <linux/init.h>
8
10
#include <linux/slab.h>
···
31
29
#define PCIBIOS_HW_TYPE1_SPEC 0x10
32
30
#define PCIBIOS_HW_TYPE2_SPEC 0x20
33
31
32
+
/*
33
+
* Returned in EAX:
34
+
* - AH: return code
35
+
*/
36
+
#define PCIBIOS_RETURN_CODE GENMASK(15, 8)
37
+
34
38
int pcibios_enabled;
39
+
40
+
static u8 pcibios_get_return_code(u32 eax)
41
+
{
42
+
return FIELD_GET(PCIBIOS_RETURN_CODE, eax);
43
+
}
35
44
36
45
/* According to the BIOS specification at:
37
46
* http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
···
167
154
: "memory");
168
155
local_irq_restore(flags);
169
156
170
-
status = (eax >> 8) & 0xff;
157
+
status = pcibios_get_return_code(eax);
171
158
hw_mech = eax & 0xff;
172
159
major_ver = (ebx >> 8) & 0xff;
173
160
minor_ver = ebx & 0xff;
···
240
227
241
228
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
242
229
243
-
return (int)((result & 0xff00) >> 8);
230
+
return pcibios_get_return_code(result);
244
231
}
245
232
246
233
static int pci_bios_write(unsigned int seg, unsigned int bus,
···
282
269
283
270
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
284
271
285
-
return (int)((result & 0xff00) >> 8);
272
+
return pcibios_get_return_code(result);
286
273
}
287
274
288
275
···
398
385
"m" (opt)
399
386
: "memory");
400
387
DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
401
-
if (ret & 0xff00)
402
-
printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
403
-
else if (opt.size) {
388
+
ret = pcibios_get_return_code(ret);
389
+
if (ret) {
390
+
printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", ret);
391
+
} else if (opt.size) {
404
392
rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
405
393
if (rt) {
406
394
memset(rt, 0, sizeof(struct irq_routing_table));
···
429
415
"b" ((dev->bus->number << 8) | dev->devfn),
430
416
"c" ((irq << 8) | (pin + 10)),
431
417
"S" (&pci_indirect));
432
-
return !(ret & 0xff00);
418
+
return pcibios_get_return_code(ret) == PCIBIOS_SUCCESSFUL;
433
419
}
434
420
EXPORT_SYMBOL(pcibios_set_irq_routing);
435
421
+3
-3
drivers/misc/dw-xdata-pcie.c
+3
-3
drivers/misc/dw-xdata-pcie.c
···
333
333
334
334
dw->pdev = pdev;
335
335
336
-
id = ida_simple_get(&xdata_ida, 0, 0, GFP_KERNEL);
336
+
id = ida_alloc(&xdata_ida, GFP_KERNEL);
337
337
if (id < 0) {
338
338
dev_err(dev, "xData: unable to get id\n");
339
339
return id;
···
377
377
kfree(dw->misc_dev.name);
378
378
379
379
err_ida_remove:
380
-
ida_simple_remove(&xdata_ida, id);
380
+
ida_free(&xdata_ida, id);
381
381
382
382
return err;
383
383
}
···
396
396
dw_xdata_stop(dw);
397
397
misc_deregister(&dw->misc_dev);
398
398
kfree(dw->misc_dev.name);
399
-
ida_simple_remove(&xdata_ida, id);
399
+
ida_free(&xdata_ida, id);
400
400
}
401
401
402
402
static const struct pci_device_id dw_xdata_pcie_id_table[] = {
+30
-20
drivers/misc/pci_endpoint_test.c
+30
-20
drivers/misc/pci_endpoint_test.c
···
28
28
#define DRV_MODULE_NAME "pci-endpoint-test"
29
29
30
30
#define IRQ_TYPE_UNDEFINED -1
31
-
#define IRQ_TYPE_LEGACY 0
31
+
#define IRQ_TYPE_INTX 0
32
32
#define IRQ_TYPE_MSI 1
33
33
#define IRQ_TYPE_MSIX 2
34
34
35
35
#define PCI_ENDPOINT_TEST_MAGIC 0x0
36
36
37
37
#define PCI_ENDPOINT_TEST_COMMAND 0x4
38
-
#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
38
+
#define COMMAND_RAISE_INTX_IRQ BIT(0)
39
39
#define COMMAND_RAISE_MSI_IRQ BIT(1)
40
40
#define COMMAND_RAISE_MSIX_IRQ BIT(2)
41
41
#define COMMAND_READ BIT(3)
···
183
183
bool res = true;
184
184
185
185
switch (type) {
186
-
case IRQ_TYPE_LEGACY:
187
-
irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
186
+
case IRQ_TYPE_INTX:
187
+
irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
188
188
if (irq < 0)
189
189
dev_err(dev, "Failed to get Legacy interrupt\n");
190
190
break;
···
244
244
245
245
fail:
246
246
switch (irq_type) {
247
-
case IRQ_TYPE_LEGACY:
247
+
case IRQ_TYPE_INTX:
248
248
dev_err(dev, "Failed to request IRQ %d for Legacy\n",
249
249
pci_irq_vector(pdev, i));
250
250
break;
···
263
263
return false;
264
264
}
265
265
266
+
static const u32 bar_test_pattern[] = {
267
+
0xA0A0A0A0,
268
+
0xA1A1A1A1,
269
+
0xA2A2A2A2,
270
+
0xA3A3A3A3,
271
+
0xA4A4A4A4,
272
+
0xA5A5A5A5,
273
+
};
274
+
266
275
static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
267
276
enum pci_barno barno)
268
277
{
···
289
280
size = 0x4;
290
281
291
282
for (j = 0; j < size; j += 4)
292
-
pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
283
+
pci_endpoint_test_bar_writel(test, barno, j,
284
+
bar_test_pattern[barno]);
293
285
294
286
for (j = 0; j < size; j += 4) {
295
287
val = pci_endpoint_test_bar_readl(test, barno, j);
296
-
if (val != 0xA0A0A0A0)
288
+
if (val != bar_test_pattern[barno])
297
289
return false;
298
290
}
299
291
300
292
return true;
301
293
}
302
294
303
-
static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
295
+
static bool pci_endpoint_test_intx_irq(struct pci_endpoint_test *test)
304
296
{
305
297
u32 val;
306
298
307
299
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
308
-
IRQ_TYPE_LEGACY);
300
+
IRQ_TYPE_INTX);
309
301
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
310
302
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
311
-
COMMAND_RAISE_LEGACY_IRQ);
303
+
COMMAND_RAISE_INTX_IRQ);
312
304
val = wait_for_completion_timeout(&test->irq_raised,
313
305
msecs_to_jiffies(1000));
314
306
if (!val)
···
395
385
if (use_dma)
396
386
flags |= FLAG_USE_DMA;
397
387
398
-
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
388
+
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
399
389
dev_err(dev, "Invalid IRQ type option\n");
400
390
goto err;
401
391
}
···
531
521
if (use_dma)
532
522
flags |= FLAG_USE_DMA;
533
523
534
-
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
524
+
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
535
525
dev_err(dev, "Invalid IRQ type option\n");
536
526
goto err;
537
527
}
···
631
621
if (use_dma)
632
622
flags |= FLAG_USE_DMA;
633
623
634
-
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
624
+
if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
635
625
dev_err(dev, "Invalid IRQ type option\n");
636
626
goto err;
637
627
}
···
701
691
struct pci_dev *pdev = test->pdev;
702
692
struct device *dev = &pdev->dev;
703
693
704
-
if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
694
+
if (req_irq_type < IRQ_TYPE_INTX || req_irq_type > IRQ_TYPE_MSIX) {
705
695
dev_err(dev, "Invalid IRQ type option\n");
706
696
return false;
707
697
}
···
747
737
goto ret;
748
738
ret = pci_endpoint_test_bar(test, bar);
749
739
break;
750
-
case PCITEST_LEGACY_IRQ:
751
-
ret = pci_endpoint_test_legacy_irq(test);
740
+
case PCITEST_INTX_IRQ:
741
+
ret = pci_endpoint_test_intx_irq(test);
752
742
break;
753
743
case PCITEST_MSI:
754
744
case PCITEST_MSIX:
···
811
801
test->irq_type = IRQ_TYPE_UNDEFINED;
812
802
813
803
if (no_msi)
814
-
irq_type = IRQ_TYPE_LEGACY;
804
+
irq_type = IRQ_TYPE_INTX;
815
805
816
806
data = (struct pci_endpoint_test_data *)ent->driver_data;
817
807
if (data) {
···
870
860
871
861
pci_set_drvdata(pdev, test);
872
862
873
-
id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
863
+
id = ida_alloc(&pci_endpoint_test_ida, GFP_KERNEL);
874
864
if (id < 0) {
875
865
err = id;
876
866
dev_err(dev, "Unable to get id\n");
···
917
907
kfree(test->name);
918
908
919
909
err_ida_remove:
920
-
ida_simple_remove(&pci_endpoint_test_ida, id);
910
+
ida_free(&pci_endpoint_test_ida, id);
921
911
922
912
err_iounmap:
923
913
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
···
953
943
misc_deregister(&test->miscdev);
954
944
kfree(misc_device->name);
955
945
kfree(test->name);
956
-
ida_simple_remove(&pci_endpoint_test_ida, id);
946
+
ida_free(&pci_endpoint_test_ida, id);
957
947
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
958
948
if (test->bar[bar])
959
949
pci_iounmap(pdev, test->bar[bar]);
-1
drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-1
drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+2
drivers/pci/controller/cadence/Kconfig
+2
drivers/pci/controller/cadence/Kconfig
···
47
47
48
48
config PCI_J721E_HOST
49
49
bool "TI J721E PCIe controller (host mode)"
50
+
depends on ARCH_K3 || COMPILE_TEST
50
51
depends on OF
51
52
select PCIE_CADENCE_HOST
52
53
select PCI_J721E
···
58
57
59
58
config PCI_J721E_EP
60
59
bool "TI J721E PCIe controller (endpoint mode)"
60
+
depends on ARCH_K3 || COMPILE_TEST
61
61
depends on OF
62
62
depends on PCI_ENDPOINT
63
63
select PCIE_CADENCE_EP
+40
-5
drivers/pci/controller/cadence/pci-j721e.c
+40
-5
drivers/pci/controller/cadence/pci-j721e.c
···
42
42
};
43
43
44
44
#define J721E_MODE_RC BIT(7)
45
-
#define LANE_COUNT_MASK BIT(8)
46
45
#define LANE_COUNT(n) ((n) << 8)
47
46
48
47
#define GENERATION_SEL_MASK GENMASK(1, 0)
49
-
50
-
#define MAX_LANES 2
51
48
52
49
struct j721e_pcie {
53
50
struct cdns_pcie *cdns_pcie;
54
51
struct clk *refclk;
55
52
u32 mode;
56
53
u32 num_lanes;
54
+
u32 max_lanes;
57
55
void __iomem *user_cfg_base;
58
56
void __iomem *intd_cfg_base;
59
57
u32 linkdown_irq_regfield;
···
69
71
unsigned int quirk_disable_flr:1;
70
72
u32 linkdown_irq_regfield;
71
73
unsigned int byte_access_allowed:1;
74
+
unsigned int max_lanes;
72
75
};
73
76
74
77
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
···
205
206
{
206
207
struct device *dev = pcie->cdns_pcie->dev;
207
208
u32 lanes = pcie->num_lanes;
209
+
u32 mask = BIT(8);
208
210
u32 val = 0;
209
211
int ret;
210
212
213
+
if (pcie->max_lanes == 4)
214
+
mask = GENMASK(9, 8);
215
+
211
216
val = LANE_COUNT(lanes - 1);
212
-
ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
217
+
ret = regmap_update_bits(syscon, offset, mask, val);
213
218
if (ret)
214
219
dev_err(dev, "failed to set link count\n");
215
220
···
293
290
.quirk_retrain_flag = true,
294
291
.byte_access_allowed = false,
295
292
.linkdown_irq_regfield = LINK_DOWN,
293
+
.max_lanes = 2,
296
294
};
297
295
298
296
static const struct j721e_pcie_data j721e_pcie_ep_data = {
299
297
.mode = PCI_MODE_EP,
300
298
.linkdown_irq_regfield = LINK_DOWN,
299
+
.max_lanes = 2,
301
300
};
302
301
303
302
static const struct j721e_pcie_data j7200_pcie_rc_data = {
···
307
302
.quirk_detect_quiet_flag = true,
308
303
.linkdown_irq_regfield = J7200_LINK_DOWN,
309
304
.byte_access_allowed = true,
305
+
.max_lanes = 2,
310
306
};
311
307
312
308
static const struct j721e_pcie_data j7200_pcie_ep_data = {
313
309
.mode = PCI_MODE_EP,
314
310
.quirk_detect_quiet_flag = true,
315
311
.quirk_disable_flr = true,
312
+
.max_lanes = 2,
316
313
};
317
314
318
315
static const struct j721e_pcie_data am64_pcie_rc_data = {
319
316
.mode = PCI_MODE_RC,
320
317
.linkdown_irq_regfield = J7200_LINK_DOWN,
321
318
.byte_access_allowed = true,
319
+
.max_lanes = 1,
322
320
};
323
321
324
322
static const struct j721e_pcie_data am64_pcie_ep_data = {
325
323
.mode = PCI_MODE_EP,
326
324
.linkdown_irq_regfield = J7200_LINK_DOWN,
325
+
.max_lanes = 1,
326
+
};
327
+
328
+
static const struct j721e_pcie_data j784s4_pcie_rc_data = {
329
+
.mode = PCI_MODE_RC,
330
+
.quirk_retrain_flag = true,
331
+
.byte_access_allowed = false,
332
+
.linkdown_irq_regfield = LINK_DOWN,
333
+
.max_lanes = 4,
334
+
};
335
+
336
+
static const struct j721e_pcie_data j784s4_pcie_ep_data = {
337
+
.mode = PCI_MODE_EP,
338
+
.linkdown_irq_regfield = LINK_DOWN,
339
+
.max_lanes = 4,
327
340
};
328
341
329
342
static const struct of_device_id of_j721e_pcie_match[] = {
···
368
345
{
369
346
.compatible = "ti,am64-pcie-ep",
370
347
.data = &am64_pcie_ep_data,
348
+
},
349
+
{
350
+
.compatible = "ti,j784s4-pcie-host",
351
+
.data = &j784s4_pcie_rc_data,
352
+
},
353
+
{
354
+
.compatible = "ti,j784s4-pcie-ep",
355
+
.data = &j784s4_pcie_ep_data,
371
356
},
372
357
{},
373
358
};
···
463
432
pcie->user_cfg_base = base;
464
433
465
434
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
466
-
if (ret || num_lanes > MAX_LANES)
435
+
if (ret || num_lanes > data->max_lanes) {
436
+
dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
467
437
num_lanes = 1;
438
+
}
439
+
468
440
pcie->num_lanes = num_lanes;
441
+
pcie->max_lanes = data->max_lanes;
469
442
470
443
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
471
444
return -EINVAL;
+9
-10
drivers/pci/controller/cadence/pcie-cadence-ep.c
+9
-10
drivers/pci/controller/cadence/pcie-cadence-ep.c
···
360
360
writel(0, ep->irq_cpu_addr + offset);
361
361
}
362
362
363
-
static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
364
-
u8 intx)
363
+
static int cdns_pcie_ep_send_intx_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
364
+
u8 intx)
365
365
{
366
366
u16 cmd;
367
367
···
371
371
372
372
cdns_pcie_ep_assert_intx(ep, fn, intx, true);
373
373
/*
374
-
* The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
374
+
* The mdelay() value was taken from dra7xx_pcie_raise_intx_irq()
375
375
*/
376
376
mdelay(1);
377
377
cdns_pcie_ep_assert_intx(ep, fn, intx, false);
···
532
532
}
533
533
534
534
static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
535
-
enum pci_epc_irq_type type,
536
-
u16 interrupt_num)
535
+
unsigned int type, u16 interrupt_num)
537
536
{
538
537
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
539
538
struct cdns_pcie *pcie = &ep->pcie;
540
539
struct device *dev = pcie->dev;
541
540
542
541
switch (type) {
543
-
case PCI_EPC_IRQ_LEGACY:
542
+
case PCI_IRQ_INTX:
544
543
if (vfn > 0) {
545
-
dev_err(dev, "Cannot raise legacy interrupts for VF\n");
544
+
dev_err(dev, "Cannot raise INTX interrupts for VF\n");
546
545
return -EINVAL;
547
546
}
548
-
return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
547
+
return cdns_pcie_ep_send_intx_irq(ep, fn, vfn, 0);
549
548
550
-
case PCI_EPC_IRQ_MSI:
549
+
case PCI_IRQ_MSI:
551
550
return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
552
551
553
-
case PCI_EPC_IRQ_MSIX:
552
+
case PCI_IRQ_MSIX:
554
553
return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
555
554
556
555
default:
+6
-6
drivers/pci/controller/cadence/pcie-cadence.h
+6
-6
drivers/pci/controller/cadence/pcie-cadence.h
···
347
347
* @max_regions: maximum number of regions supported by hardware
348
348
* @ob_region_map: bitmask of mapped outbound regions
349
349
* @ob_addr: base addresses in the AXI bus where the outbound regions start
350
-
* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
350
+
* @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
351
351
* dedicated outbound regions is mapped.
352
352
* @irq_cpu_addr: base address in the CPU space where a write access triggers
353
-
* the sending of a memory write (MSI) / normal message (legacy
353
+
* the sending of a memory write (MSI) / normal message (INTX
354
354
* IRQ) TLP through the PCIe bus.
355
-
* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
355
+
* @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
356
356
* dedicated outbound region.
357
357
* @irq_pci_fn: the latest PCI function that has updated the mapping of
358
-
* the MSI/legacy IRQ dedicated outbound region.
359
-
* @irq_pending: bitmask of asserted legacy IRQs.
358
+
* the MSI/INTX IRQ dedicated outbound region.
359
+
* @irq_pending: bitmask of asserted INTX IRQs.
360
360
* @lock: spin lock to disable interrupts while modifying PCIe controller
361
361
* registers fields (RMW) accessible by both remote RC and EP to
362
362
* minimize time between read and write
···
374
374
u64 irq_pci_addr;
375
375
u8 irq_pci_fn;
376
376
u8 irq_pending;
377
-
/* protect writing to PCI_STATUS while raising legacy interrupts */
377
+
/* protect writing to PCI_STATUS while raising INTX interrupts */
378
378
spinlock_t lock;
379
379
struct cdns_pcie_epf *epf;
380
380
unsigned int quirk_detect_quiet_flag:1;
+1
-1
drivers/pci/controller/dwc/Kconfig
+1
-1
drivers/pci/controller/dwc/Kconfig
···
336
336
config PCIE_FU740
337
337
bool "SiFive FU740 PCIe controller"
338
338
depends on PCI_MSI
339
-
depends on SOC_SIFIVE || COMPILE_TEST
339
+
depends on ARCH_SIFIVE || COMPILE_TEST
340
340
select PCIE_DW_HOST
341
341
help
342
342
Say Y here if you want PCIe controller support for the SiFive
+7
-7
drivers/pci/controller/dwc/pci-dra7xx.c
+7
-7
drivers/pci/controller/dwc/pci-dra7xx.c
···
371
371
}
372
372
373
373
static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
374
-
.host_init = dra7xx_pcie_host_init,
374
+
.init = dra7xx_pcie_host_init,
375
375
};
376
376
377
377
static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
···
386
386
dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
387
387
}
388
388
389
-
static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
389
+
static void dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie *dra7xx)
390
390
{
391
391
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
392
392
mdelay(1);
···
404
404
}
405
405
406
406
static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
407
-
enum pci_epc_irq_type type, u16 interrupt_num)
407
+
unsigned int type, u16 interrupt_num)
408
408
{
409
409
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
410
410
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
411
411
412
412
switch (type) {
413
-
case PCI_EPC_IRQ_LEGACY:
414
-
dra7xx_pcie_raise_legacy_irq(dra7xx);
413
+
case PCI_IRQ_INTX:
414
+
dra7xx_pcie_raise_intx_irq(dra7xx);
415
415
break;
416
-
case PCI_EPC_IRQ_MSI:
416
+
case PCI_IRQ_MSI:
417
417
dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
418
418
break;
419
419
default:
···
436
436
}
437
437
438
438
static const struct dw_pcie_ep_ops pcie_ep_ops = {
439
-
.ep_init = dra7xx_pcie_ep_init,
439
+
.init = dra7xx_pcie_ep_init,
440
440
.raise_irq = dra7xx_pcie_raise_irq,
441
441
.get_features = dra7xx_pcie_get_features,
442
442
};
+3
-5
drivers/pci/controller/dwc/pci-exynos.c
+3
-5
drivers/pci/controller/dwc/pci-exynos.c
···
268
268
}
269
269
270
270
static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
271
-
.host_init = exynos_pcie_host_init,
271
+
.init = exynos_pcie_host_init,
272
272
};
273
273
274
274
static int exynos_add_pcie_port(struct exynos_pcie *ep,
···
375
375
return ret;
376
376
}
377
377
378
-
static int exynos_pcie_remove(struct platform_device *pdev)
378
+
static void exynos_pcie_remove(struct platform_device *pdev)
379
379
{
380
380
struct exynos_pcie *ep = platform_get_drvdata(pdev);
381
381
···
385
385
phy_exit(ep->phy);
386
386
exynos_pcie_deinit_clk_resources(ep);
387
387
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
388
-
389
-
return 0;
390
388
}
391
389
392
390
static int exynos_pcie_suspend_noirq(struct device *dev)
···
429
431
430
432
static struct platform_driver exynos_pcie_driver = {
431
433
.probe = exynos_pcie_probe,
432
-
.remove = exynos_pcie_remove,
434
+
.remove_new = exynos_pcie_remove,
433
435
.driver = {
434
436
.name = "exynos-pcie",
435
437
.of_match_table = exynos_pcie_of_match,
+8
-9
drivers/pci/controller/dwc/pci-imx6.c
+8
-9
drivers/pci/controller/dwc/pci-imx6.c
···
1039
1039
}
1040
1040
1041
1041
static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
1042
-
.host_init = imx6_pcie_host_init,
1043
-
.host_deinit = imx6_pcie_host_exit,
1042
+
.init = imx6_pcie_host_init,
1043
+
.deinit = imx6_pcie_host_exit,
1044
1044
};
1045
1045
1046
1046
static const struct dw_pcie_ops dw_pcie_ops = {
···
1058
1058
}
1059
1059
1060
1060
static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1061
-
enum pci_epc_irq_type type,
1062
-
u16 interrupt_num)
1061
+
unsigned int type, u16 interrupt_num)
1063
1062
{
1064
1063
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1065
1064
1066
1065
switch (type) {
1067
-
case PCI_EPC_IRQ_LEGACY:
1068
-
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
1069
-
case PCI_EPC_IRQ_MSI:
1066
+
case PCI_IRQ_INTX:
1067
+
return dw_pcie_ep_raise_intx_irq(ep, func_no);
1068
+
case PCI_IRQ_MSI:
1070
1069
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
1071
-
case PCI_EPC_IRQ_MSIX:
1070
+
case PCI_IRQ_MSIX:
1072
1071
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
1073
1072
default:
1074
1073
dev_err(pci->dev, "UNKNOWN IRQ type\n");
···
1092
1093
}
1093
1094
1094
1095
static const struct dw_pcie_ep_ops pcie_ep_ops = {
1095
-
.ep_init = imx6_pcie_ep_init,
1096
+
.init = imx6_pcie_ep_init,
1096
1097
.raise_irq = imx6_pcie_ep_raise_irq,
1097
1098
.get_features = imx6_pcie_ep_get_features,
1098
1099
};
+56
-53
drivers/pci/controller/dwc/pci-keystone.c
+56
-53
drivers/pci/controller/dwc/pci-keystone.c
···
115
115
struct dw_pcie *pci;
116
116
/* PCI Device ID */
117
117
u32 device_id;
118
-
int legacy_host_irqs[PCI_NUM_INTX];
119
-
struct device_node *legacy_intc_np;
118
+
int intx_host_irqs[PCI_NUM_INTX];
120
119
121
120
int msi_host_irq;
122
121
int num_lanes;
···
123
124
struct phy **phy;
124
125
struct device_link **link;
125
126
struct device_node *msi_intc_np;
126
-
struct irq_domain *legacy_irq_domain;
127
+
struct irq_domain *intx_irq_domain;
127
128
struct device_node *np;
128
129
129
130
/* Application register space */
···
251
252
return dw_pcie_allocate_domains(pp);
252
253
}
253
254
254
-
static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
255
-
int offset)
255
+
static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie,
256
+
int offset)
256
257
{
257
258
struct dw_pcie *pci = ks_pcie->pci;
258
259
struct device *dev = pci->dev;
···
262
263
263
264
if (BIT(0) & pending) {
264
265
dev_dbg(dev, ": irq: irq_offset %d", offset);
265
-
generic_handle_domain_irq(ks_pcie->legacy_irq_domain, offset);
266
+
generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset);
266
267
}
267
268
268
269
/* EOI the INTx interrupt */
···
306
307
return IRQ_HANDLED;
307
308
}
308
309
309
-
static void ks_pcie_ack_legacy_irq(struct irq_data *d)
310
+
static void ks_pcie_ack_intx_irq(struct irq_data *d)
310
311
{
311
312
}
312
313
313
-
static void ks_pcie_mask_legacy_irq(struct irq_data *d)
314
+
static void ks_pcie_mask_intx_irq(struct irq_data *d)
314
315
{
315
316
}
316
317
317
-
static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
318
+
static void ks_pcie_unmask_intx_irq(struct irq_data *d)
318
319
{
319
320
}
320
321
321
-
static struct irq_chip ks_pcie_legacy_irq_chip = {
322
-
.name = "Keystone-PCI-Legacy-IRQ",
323
-
.irq_ack = ks_pcie_ack_legacy_irq,
324
-
.irq_mask = ks_pcie_mask_legacy_irq,
325
-
.irq_unmask = ks_pcie_unmask_legacy_irq,
322
+
static struct irq_chip ks_pcie_intx_irq_chip = {
323
+
.name = "Keystone-PCI-INTX-IRQ",
324
+
.irq_ack = ks_pcie_ack_intx_irq,
325
+
.irq_mask = ks_pcie_mask_intx_irq,
326
+
.irq_unmask = ks_pcie_unmask_intx_irq,
326
327
};
327
328
328
-
static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
329
-
unsigned int irq,
330
-
irq_hw_number_t hw_irq)
329
+
static int ks_pcie_init_intx_irq_map(struct irq_domain *d,
330
+
unsigned int irq, irq_hw_number_t hw_irq)
331
331
{
332
-
irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
332
+
irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip,
333
333
handle_level_irq);
334
334
irq_set_chip_data(irq, d->host_data);
335
335
336
336
return 0;
337
337
}
338
338
339
-
static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
340
-
.map = ks_pcie_init_legacy_irq_map,
339
+
static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
340
+
.map = ks_pcie_init_intx_irq_map,
341
341
.xlate = irq_domain_xlate_onetwocell,
342
342
};
343
343
···
603
605
}
604
606
605
607
/**
606
-
* ks_pcie_legacy_irq_handler() - Handle legacy interrupt
608
+
* ks_pcie_intx_irq_handler() - Handle INTX interrupt
607
609
* @desc: Pointer to irq descriptor
608
610
*
609
-
* Traverse through pending legacy interrupts and invoke handler for each. Also
611
+
* Traverse through pending INTX interrupts and invoke handler for each. Also
610
612
* takes care of interrupt controller level mask/ack operation.
611
613
*/
612
-
static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
614
+
static void ks_pcie_intx_irq_handler(struct irq_desc *desc)
613
615
{
614
616
unsigned int irq = irq_desc_get_irq(desc);
615
617
struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
616
618
struct dw_pcie *pci = ks_pcie->pci;
617
619
struct device *dev = pci->dev;
618
-
u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
620
+
u32 irq_offset = irq - ks_pcie->intx_host_irqs[0];
619
621
struct irq_chip *chip = irq_desc_get_chip(desc);
620
622
621
-
dev_dbg(dev, ": Handling legacy irq %d\n", irq);
623
+
dev_dbg(dev, ": Handling INTX irq %d\n", irq);
622
624
623
625
/*
624
626
* The chained irq handler installation would have replaced normal
···
626
628
* ack operation.
627
629
*/
628
630
chained_irq_enter(chip, desc);
629
-
ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
631
+
ks_pcie_handle_intx_irq(ks_pcie, irq_offset);
630
632
chained_irq_exit(chip, desc);
631
633
}
632
634
···
684
686
return ret;
685
687
}
686
688
687
-
static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)
689
+
static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie)
688
690
{
689
691
struct device *dev = ks_pcie->pci->dev;
690
-
struct irq_domain *legacy_irq_domain;
692
+
struct irq_domain *intx_irq_domain;
691
693
struct device_node *np = ks_pcie->np;
692
694
struct device_node *intc_np;
693
695
int irq_count, irq, ret = 0, i;
···
695
697
intc_np = of_get_child_by_name(np, "legacy-interrupt-controller");
696
698
if (!intc_np) {
697
699
/*
698
-
* Since legacy interrupts are modeled as edge-interrupts in
700
+
* Since INTX interrupts are modeled as edge-interrupts in
699
701
* AM6, keep it disabled for now.
700
702
*/
701
703
if (ks_pcie->is_am6)
···
717
719
ret = -EINVAL;
718
720
goto err;
719
721
}
720
-
ks_pcie->legacy_host_irqs[i] = irq;
722
+
ks_pcie->intx_host_irqs[i] = irq;
721
723
722
724
irq_set_chained_handler_and_data(irq,
723
-
ks_pcie_legacy_irq_handler,
725
+
ks_pcie_intx_irq_handler,
724
726
ks_pcie);
725
727
}
726
728
727
-
legacy_irq_domain =
728
-
irq_domain_add_linear(intc_np, PCI_NUM_INTX,
729
-
&ks_pcie_legacy_irq_domain_ops, NULL);
730
-
if (!legacy_irq_domain) {
731
-
dev_err(dev, "Failed to add irq domain for legacy irqs\n");
729
+
intx_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX,
730
+
&ks_pcie_intx_irq_domain_ops, NULL);
731
+
if (!intx_irq_domain) {
732
+
dev_err(dev, "Failed to add irq domain for INTX irqs\n");
732
733
ret = -EINVAL;
733
734
goto err;
734
735
}
735
-
ks_pcie->legacy_irq_domain = legacy_irq_domain;
736
+
ks_pcie->intx_irq_domain = intx_irq_domain;
736
737
737
738
for (i = 0; i < PCI_NUM_INTX; i++)
738
739
ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN);
···
805
808
if (!ks_pcie->is_am6)
806
809
pp->bridge->child_ops = &ks_child_pcie_ops;
807
810
808
-
ret = ks_pcie_config_legacy_irq(ks_pcie);
811
+
ret = ks_pcie_config_intx_irq(ks_pcie);
809
812
if (ret)
810
813
return ret;
811
814
···
835
838
}
836
839
837
840
static const struct dw_pcie_host_ops ks_pcie_host_ops = {
838
-
.host_init = ks_pcie_host_init,
839
-
.msi_host_init = ks_pcie_msi_host_init,
841
+
.init = ks_pcie_host_init,
842
+
.msi_init = ks_pcie_msi_host_init,
840
843
};
841
844
842
845
static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
843
-
.host_init = ks_pcie_host_init,
846
+
.init = ks_pcie_host_init,
844
847
};
845
848
846
849
static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
···
878
881
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
879
882
}
880
883
881
-
static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
884
+
static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie)
882
885
{
883
886
struct dw_pcie *pci = ks_pcie->pci;
884
887
u8 int_pin;
···
897
900
}
898
901
899
902
static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
900
-
enum pci_epc_irq_type type,
901
-
u16 interrupt_num)
903
+
unsigned int type, u16 interrupt_num)
902
904
{
903
905
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
904
906
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
905
907
906
908
switch (type) {
907
-
case PCI_EPC_IRQ_LEGACY:
908
-
ks_pcie_am654_raise_legacy_irq(ks_pcie);
909
+
case PCI_IRQ_INTX:
910
+
ks_pcie_am654_raise_intx_irq(ks_pcie);
909
911
break;
910
-
case PCI_EPC_IRQ_MSI:
912
+
case PCI_IRQ_MSI:
911
913
dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
912
914
break;
913
-
case PCI_EPC_IRQ_MSIX:
915
+
case PCI_IRQ_MSIX:
914
916
dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
915
917
break;
916
918
default:
···
940
944
}
941
945
942
946
static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = {
943
-
.ep_init = ks_pcie_am654_ep_init,
947
+
.init = ks_pcie_am654_ep_init,
944
948
.raise_irq = ks_pcie_am654_raise_irq,
945
949
.get_features = &ks_pcie_am654_get_features,
946
950
};
···
1214
1218
goto err_link;
1215
1219
}
1216
1220
1221
+
/* Obtain references to the PHYs */
1222
+
for (i = 0; i < num_lanes; i++)
1223
+
phy_pm_runtime_get_sync(ks_pcie->phy[i]);
1224
+
1217
1225
ret = ks_pcie_enable_phy(ks_pcie);
1226
+
1227
+
/* Release references to the PHYs */
1228
+
for (i = 0; i < num_lanes; i++)
1229
+
phy_pm_runtime_put_sync(ks_pcie->phy[i]);
1230
+
1218
1231
if (ret) {
1219
1232
dev_err(dev, "failed to enable phy\n");
1220
1233
goto err_link;
···
1307
1302
return ret;
1308
1303
}
1309
1304
1310
-
static int ks_pcie_remove(struct platform_device *pdev)
1305
+
static void ks_pcie_remove(struct platform_device *pdev)
1311
1306
{
1312
1307
struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
1313
1308
struct device_link **link = ks_pcie->link;
···
1319
1314
ks_pcie_disable_phy(ks_pcie);
1320
1315
while (num_lanes--)
1321
1316
device_link_del(link[num_lanes]);
1322
-
1323
-
return 0;
1324
1317
}
1325
1318
1326
1319
static struct platform_driver ks_pcie_driver = {
1327
1320
.probe = ks_pcie_probe,
1328
-
.remove = ks_pcie_remove,
1321
+
.remove_new = ks_pcie_remove,
1329
1322
.driver = {
1330
1323
.name = "keystone-pcie",
1331
1324
.of_match_table = ks_pcie_of_match,
+16
-17
drivers/pci/controller/dwc/pci-layerscape-ep.c
+16
-17
drivers/pci/controller/dwc/pci-layerscape-ep.c
···
49
49
bool big_endian;
50
50
};
51
51
52
-
static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
52
+
static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
53
53
{
54
54
struct dw_pcie *pci = pcie->pci;
55
55
···
59
59
return ioread32(pci->dbi_base + offset);
60
60
}
61
61
62
-
static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)
62
+
static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)
63
63
{
64
64
struct dw_pcie *pci = pcie->pci;
65
65
···
76
76
u32 val, cfg;
77
77
u8 offset;
78
78
79
-
val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
80
-
ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
79
+
val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);
80
+
ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
81
81
82
82
if (!val)
83
83
return IRQ_NONE;
···
96
96
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
97
97
dw_pcie_dbi_ro_wr_dis(pci);
98
98
99
-
cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
99
+
cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);
100
100
cfg |= PEX_PF0_CFG_READY;
101
-
ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
101
+
ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
102
102
dw_pcie_ep_linkup(&pci->ep);
103
103
104
104
dev_dbg(pci->dev, "Link up\n");
···
130
130
}
131
131
132
132
/* Enable interrupts */
133
-
val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER);
133
+
val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER);
134
134
val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |
135
135
PEX_PF0_PME_MES_IER_LUDIE;
136
-
ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);
136
+
ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);
137
137
138
138
return 0;
139
139
}
···
166
166
}
167
167
168
168
static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
169
-
enum pci_epc_irq_type type, u16 interrupt_num)
169
+
unsigned int type, u16 interrupt_num)
170
170
{
171
171
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
172
172
173
173
switch (type) {
174
-
case PCI_EPC_IRQ_LEGACY:
175
-
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
176
-
case PCI_EPC_IRQ_MSI:
174
+
case PCI_IRQ_INTX:
175
+
return dw_pcie_ep_raise_intx_irq(ep, func_no);
176
+
case PCI_IRQ_MSI:
177
177
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
178
-
case PCI_EPC_IRQ_MSIX:
178
+
case PCI_IRQ_MSIX:
179
179
return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
180
180
interrupt_num);
181
181
default:
···
184
184
}
185
185
}
186
186
187
-
static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
188
-
u8 func_no)
187
+
static unsigned int ls_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep, u8 func_no)
189
188
{
190
189
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
191
190
struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
···
194
195
}
195
196
196
197
static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
197
-
.ep_init = ls_pcie_ep_init,
198
+
.init = ls_pcie_ep_init,
198
199
.raise_irq = ls_pcie_ep_raise_irq,
199
200
.get_features = ls_pcie_ep_get_features,
200
-
.func_conf_select = ls_pcie_ep_func_conf_select,
201
+
.get_dbi_offset = ls_pcie_ep_get_dbi_offset,
201
202
};
202
203
203
204
static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
+169
-24
drivers/pci/controller/dwc/pci-layerscape.c
+169
-24
drivers/pci/controller/dwc/pci-layerscape.c
···
35
35
#define PF_MCR_PTOMR BIT(0)
36
36
#define PF_MCR_EXL2S BIT(1)
37
37
38
+
/* LS1021A PEXn PM Write Control Register */
39
+
#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64)
40
+
#define PMXMTTURNOFF BIT(31)
41
+
#define SCFG_PEXSFTRSTCR 0x190
42
+
#define PEXSR(idx) BIT(idx)
43
+
44
+
/* LS1043A PEX PME control register */
45
+
#define SCFG_PEXPMECR 0x144
46
+
#define PEXPME(idx) BIT(31 - (idx) * 4)
47
+
48
+
/* LS1043A PEX LUT debug register */
49
+
#define LS_PCIE_LDBG 0x7fc
50
+
#define LDBG_SR BIT(30)
51
+
#define LDBG_WE BIT(31)
52
+
38
53
#define PCIE_IATU_NUM 6
39
54
40
55
struct ls_pcie_drvdata {
41
-
const u32 pf_off;
56
+
const u32 pf_lut_off;
57
+
const struct dw_pcie_host_ops *ops;
58
+
int (*exit_from_l2)(struct dw_pcie_rp *pp);
59
+
bool scfg_support;
42
60
bool pm_support;
43
61
};
44
62
45
63
struct ls_pcie {
46
64
struct dw_pcie *pci;
47
65
const struct ls_pcie_drvdata *drvdata;
48
-
void __iomem *pf_base;
66
+
void __iomem *pf_lut_base;
67
+
struct regmap *scfg;
68
+
int index;
49
69
bool big_endian;
50
70
};
51
71
52
-
#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr)
72
+
#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr)
53
73
#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
54
74
55
75
static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
···
110
90
iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
111
91
}
112
92
113
-
static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)
93
+
static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
114
94
{
115
95
if (pcie->big_endian)
116
-
return ioread32be(pcie->pf_base + off);
96
+
return ioread32be(pcie->pf_lut_base + off);
117
97
118
-
return ioread32(pcie->pf_base + off);
98
+
return ioread32(pcie->pf_lut_base + off);
119
99
}
120
100
121
-
static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)
101
+
static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)
122
102
{
123
103
if (pcie->big_endian)
124
-
iowrite32be(val, pcie->pf_base + off);
104
+
iowrite32be(val, pcie->pf_lut_base + off);
125
105
else
126
-
iowrite32(val, pcie->pf_base + off);
106
+
iowrite32(val, pcie->pf_lut_base + off);
127
107
}
128
108
129
109
static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
···
133
113
u32 val;
134
114
int ret;
135
115
136
-
val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
116
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
137
117
val |= PF_MCR_PTOMR;
138
-
ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
118
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
139
119
140
-
ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
120
+
ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
141
121
val, !(val & PF_MCR_PTOMR),
142
122
PCIE_PME_TO_L2_TIMEOUT_US/10,
143
123
PCIE_PME_TO_L2_TIMEOUT_US);
···
145
125
dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");
146
126
}
147
127
148
-
static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
128
+
static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
149
129
{
150
130
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
151
131
struct ls_pcie *pcie = to_ls_pcie(pci);
···
156
136
* Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link
157
137
* to exit L2 state.
158
138
*/
159
-
val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
139
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
160
140
val |= PF_MCR_EXL2S;
161
-
ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
141
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
162
142
163
143
/*
164
144
* L2 exit timeout of 10ms is not defined in the specifications,
165
145
* it was chosen based on empirical observations.
166
146
*/
167
-
ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
147
+
ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
168
148
val, !(val & PF_MCR_EXL2S),
169
149
1000,
170
150
10000);
171
151
if (ret)
172
152
dev_err(pcie->pci->dev, "L2 exit timeout\n");
153
+
154
+
return ret;
173
155
}
174
156
175
157
static int ls_pcie_host_init(struct dw_pcie_rp *pp)
···
190
168
return 0;
191
169
}
192
170
171
+
static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask)
172
+
{
173
+
/* Send PME_Turn_Off message */
174
+
regmap_write_bits(scfg, reg, mask, mask);
175
+
176
+
/*
177
+
* There is no specific register to check for PME_To_Ack from endpoint.
178
+
* So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US.
179
+
*/
180
+
mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
181
+
182
+
/*
183
+
* Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit
184
+
* to complete the PME_Turn_Off handshake.
185
+
*/
186
+
regmap_write_bits(scfg, reg, mask, 0);
187
+
}
188
+
189
+
static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
190
+
{
191
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
192
+
struct ls_pcie *pcie = to_ls_pcie(pci);
193
+
194
+
scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
195
+
}
196
+
197
+
static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask)
198
+
{
199
+
/* Reset the PEX wrapper to bring the link out of L2 */
200
+
regmap_write_bits(scfg, reg, mask, mask);
201
+
regmap_write_bits(scfg, reg, mask, 0);
202
+
203
+
return 0;
204
+
}
205
+
206
+
static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
207
+
{
208
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
209
+
struct ls_pcie *pcie = to_ls_pcie(pci);
210
+
211
+
return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
212
+
}
213
+
214
+
static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
215
+
{
216
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
217
+
struct ls_pcie *pcie = to_ls_pcie(pci);
218
+
219
+
scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));
220
+
}
221
+
222
+
static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
223
+
{
224
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
225
+
struct ls_pcie *pcie = to_ls_pcie(pci);
226
+
u32 val;
227
+
228
+
/*
229
+
* Reset the PEX wrapper to bring the link out of L2.
230
+
* LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and
231
+
* clearing the soft reset on the PEX module.
232
+
* LDBG_SR: When SR is set to 1, the PEX module enters soft reset.
233
+
*/
234
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
235
+
val |= LDBG_WE;
236
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
237
+
238
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
239
+
val |= LDBG_SR;
240
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
241
+
242
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
243
+
val &= ~LDBG_SR;
244
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
245
+
246
+
val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
247
+
val &= ~LDBG_WE;
248
+
ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
249
+
250
+
return 0;
251
+
}
252
+
193
253
static const struct dw_pcie_host_ops ls_pcie_host_ops = {
194
-
.host_init = ls_pcie_host_init,
254
+
.init = ls_pcie_host_init,
195
255
.pme_turn_off = ls_pcie_send_turnoff_msg,
196
256
};
197
257
258
+
static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {
259
+
.init = ls_pcie_host_init,
260
+
.pme_turn_off = ls1021a_pcie_send_turnoff_msg,
261
+
};
262
+
198
263
static const struct ls_pcie_drvdata ls1021a_drvdata = {
199
-
.pm_support = false,
264
+
.pm_support = true,
265
+
.scfg_support = true,
266
+
.ops = &ls1021a_pcie_host_ops,
267
+
.exit_from_l2 = ls1021a_pcie_exit_from_l2,
268
+
};
269
+
270
+
static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = {
271
+
.init = ls_pcie_host_init,
272
+
.pme_turn_off = ls1043a_pcie_send_turnoff_msg,
273
+
};
274
+
275
+
static const struct ls_pcie_drvdata ls1043a_drvdata = {
276
+
.pf_lut_off = 0x10000,
277
+
.pm_support = true,
278
+
.scfg_support = true,
279
+
.ops = &ls1043a_pcie_host_ops,
280
+
.exit_from_l2 = ls1043a_pcie_exit_from_l2,
200
281
};
201
282
202
283
static const struct ls_pcie_drvdata layerscape_drvdata = {
203
-
.pf_off = 0xc0000,
284
+
.pf_lut_off = 0xc0000,
204
285
.pm_support = true,
286
+
.ops = &ls_pcie_host_ops,
287
+
.exit_from_l2 = ls_pcie_exit_from_l2,
205
288
};
206
289
207
290
static const struct of_device_id ls_pcie_of_match[] = {
208
291
{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
209
292
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
210
293
{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
211
-
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata },
294
+
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
212
295
{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
213
296
{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
214
297
{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
···
328
201
struct dw_pcie *pci;
329
202
struct ls_pcie *pcie;
330
203
struct resource *dbi_base;
204
+
u32 index[2];
205
+
int ret;
331
206
332
207
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
333
208
if (!pcie)
···
342
213
pcie->drvdata = of_device_get_match_data(dev);
343
214
344
215
pci->dev = dev;
345
-
pci->pp.ops = &ls_pcie_host_ops;
346
-
347
216
pcie->pci = pci;
217
+
pci->pp.ops = pcie->drvdata->ops;
348
218
349
219
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
350
220
pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
···
352
224
353
225
pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
354
226
355
-
pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
227
+
pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;
228
+
229
+
if (pcie->drvdata->scfg_support) {
230
+
pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
231
+
if (IS_ERR(pcie->scfg)) {
232
+
dev_err(dev, "No syscfg phandle specified\n");
233
+
return PTR_ERR(pcie->scfg);
234
+
}
235
+
236
+
ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
237
+
if (ret)
238
+
return ret;
239
+
240
+
pcie->index = index[1];
241
+
}
356
242
357
243
if (!ls_pcie_is_bridge(pcie))
358
244
return -ENODEV;
···
389
247
static int ls_pcie_resume_noirq(struct device *dev)
390
248
{
391
249
struct ls_pcie *pcie = dev_get_drvdata(dev);
250
+
int ret;
392
251
393
252
if (!pcie->drvdata->pm_support)
394
253
return 0;
395
254
396
-
ls_pcie_exit_from_l2(&pcie->pci->pp);
255
+
ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp);
256
+
if (ret)
257
+
return ret;
397
258
398
259
return dw_pcie_resume_noirq(pcie->pci);
399
260
}
+1
-1
drivers/pci/controller/dwc/pci-meson.c
+1
-1
drivers/pci/controller/dwc/pci-meson.c
+1
-1
drivers/pci/controller/dwc/pcie-al.c
+1
-1
drivers/pci/controller/dwc/pcie-al.c
+1
-1
drivers/pci/controller/dwc/pcie-armada8k.c
+1
-1
drivers/pci/controller/dwc/pcie-armada8k.c
+6
-6
drivers/pci/controller/dwc/pcie-artpec6.c
+6
-6
drivers/pci/controller/dwc/pcie-artpec6.c
···
333
333
}
334
334
335
335
static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
336
-
.host_init = artpec6_pcie_host_init,
336
+
.init = artpec6_pcie_host_init,
337
337
};
338
338
339
339
static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
···
352
352
}
353
353
354
354
static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
355
-
enum pci_epc_irq_type type, u16 interrupt_num)
355
+
unsigned int type, u16 interrupt_num)
356
356
{
357
357
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
358
358
359
359
switch (type) {
360
-
case PCI_EPC_IRQ_LEGACY:
361
-
dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
360
+
case PCI_IRQ_INTX:
361
+
dev_err(pci->dev, "EP cannot trigger INTx IRQs\n");
362
362
return -EINVAL;
363
-
case PCI_EPC_IRQ_MSI:
363
+
case PCI_IRQ_MSI:
364
364
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
365
365
default:
366
366
dev_err(pci->dev, "UNKNOWN IRQ type\n");
···
370
370
}
371
371
372
372
static const struct dw_pcie_ep_ops pcie_ep_ops = {
373
-
.ep_init = artpec6_pcie_ep_init,
373
+
.init = artpec6_pcie_ep_init,
374
374
.raise_irq = artpec6_pcie_raise_irq,
375
375
};
376
376
+2
-2
drivers/pci/controller/dwc/pcie-bt1.c
+2
-2
drivers/pci/controller/dwc/pcie-bt1.c
···
559
559
}
560
560
561
561
static const struct dw_pcie_host_ops bt1_pcie_host_ops = {
562
-
.host_init = bt1_pcie_host_init,
563
-
.host_deinit = bt1_pcie_host_deinit,
562
+
.init = bt1_pcie_host_init,
563
+
.deinit = bt1_pcie_host_deinit,
564
564
};
565
565
566
566
static struct bt1_pcie *bt1_pcie_create_data(struct platform_device *pdev)
+67
-130
drivers/pci/controller/dwc/pcie-designware-ep.c
+67
-130
drivers/pci/controller/dwc/pcie-designware-ep.c
···
43
43
return NULL;
44
44
}
45
45
46
-
static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
47
-
{
48
-
unsigned int func_offset = 0;
49
-
50
-
if (ep->ops->func_conf_select)
51
-
func_offset = ep->ops->func_conf_select(ep, func_no);
52
-
53
-
return func_offset;
54
-
}
55
-
56
-
static unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, u8 func_no)
57
-
{
58
-
unsigned int dbi2_offset = 0;
59
-
60
-
if (ep->ops->get_dbi2_offset)
61
-
dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
62
-
else if (ep->ops->func_conf_select) /* for backward compatibility */
63
-
dbi2_offset = ep->ops->func_conf_select(ep, func_no);
64
-
65
-
return dbi2_offset;
66
-
}
67
-
68
46
static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
69
47
enum pci_barno bar, int flags)
70
48
{
71
-
unsigned int func_offset, dbi2_offset;
72
49
struct dw_pcie_ep *ep = &pci->ep;
73
-
u32 reg, reg_dbi2;
50
+
u32 reg;
74
51
75
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
76
-
dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
77
-
78
-
reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
79
-
reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
52
+
reg = PCI_BASE_ADDRESS_0 + (4 * bar);
80
53
dw_pcie_dbi_ro_wr_en(pci);
81
-
dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
82
-
dw_pcie_writel_dbi(pci, reg, 0x0);
54
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg, 0x0);
55
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, 0x0);
83
56
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
84
-
dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
85
-
dw_pcie_writel_dbi(pci, reg + 4, 0x0);
57
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0x0);
58
+
dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0x0);
86
59
}
87
60
dw_pcie_dbi_ro_wr_dis(pci);
88
61
}
···
72
99
EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
73
100
74
101
static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
75
-
u8 cap_ptr, u8 cap)
102
+
u8 cap_ptr, u8 cap)
76
103
{
77
-
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
78
-
unsigned int func_offset = 0;
79
104
u8 cap_id, next_cap_ptr;
80
105
u16 reg;
81
106
82
107
if (!cap_ptr)
83
108
return 0;
84
109
85
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
86
-
87
-
reg = dw_pcie_readw_dbi(pci, func_offset + cap_ptr);
110
+
reg = dw_pcie_ep_readw_dbi(ep, func_no, cap_ptr);
88
111
cap_id = (reg & 0x00ff);
89
112
90
113
if (cap_id > PCI_CAP_ID_MAX)
···
95
126
96
127
static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap)
97
128
{
98
-
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
99
-
unsigned int func_offset = 0;
100
129
u8 next_cap_ptr;
101
130
u16 reg;
102
131
103
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
104
-
105
-
reg = dw_pcie_readw_dbi(pci, func_offset + PCI_CAPABILITY_LIST);
132
+
reg = dw_pcie_ep_readw_dbi(ep, func_no, PCI_CAPABILITY_LIST);
106
133
next_cap_ptr = (reg & 0x00ff);
107
134
108
135
return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
···
109
144
{
110
145
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
111
146
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
112
-
unsigned int func_offset = 0;
113
-
114
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
115
147
116
148
dw_pcie_dbi_ro_wr_en(pci);
117
-
dw_pcie_writew_dbi(pci, func_offset + PCI_VENDOR_ID, hdr->vendorid);
118
-
dw_pcie_writew_dbi(pci, func_offset + PCI_DEVICE_ID, hdr->deviceid);
119
-
dw_pcie_writeb_dbi(pci, func_offset + PCI_REVISION_ID, hdr->revid);
120
-
dw_pcie_writeb_dbi(pci, func_offset + PCI_CLASS_PROG, hdr->progif_code);
121
-
dw_pcie_writew_dbi(pci, func_offset + PCI_CLASS_DEVICE,
122
-
hdr->subclass_code | hdr->baseclass_code << 8);
123
-
dw_pcie_writeb_dbi(pci, func_offset + PCI_CACHE_LINE_SIZE,
124
-
hdr->cache_line_size);
125
-
dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_VENDOR_ID,
126
-
hdr->subsys_vendor_id);
127
-
dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id);
128
-
dw_pcie_writeb_dbi(pci, func_offset + PCI_INTERRUPT_PIN,
129
-
hdr->interrupt_pin);
149
+
dw_pcie_ep_writew_dbi(ep, func_no, PCI_VENDOR_ID, hdr->vendorid);
150
+
dw_pcie_ep_writew_dbi(ep, func_no, PCI_DEVICE_ID, hdr->deviceid);
151
+
dw_pcie_ep_writeb_dbi(ep, func_no, PCI_REVISION_ID, hdr->revid);
152
+
dw_pcie_ep_writeb_dbi(ep, func_no, PCI_CLASS_PROG, hdr->progif_code);
153
+
dw_pcie_ep_writew_dbi(ep, func_no, PCI_CLASS_DEVICE,
154
+
hdr->subclass_code | hdr->baseclass_code << 8);
155
+
dw_pcie_ep_writeb_dbi(ep, func_no, PCI_CACHE_LINE_SIZE,
156
+
hdr->cache_line_size);
157
+
dw_pcie_ep_writew_dbi(ep, func_no, PCI_SUBSYSTEM_VENDOR_ID,
158
+
hdr->subsys_vendor_id);
159
+
dw_pcie_ep_writew_dbi(ep, func_no, PCI_SUBSYSTEM_ID, hdr->subsys_id);
160
+
dw_pcie_ep_writeb_dbi(ep, func_no, PCI_INTERRUPT_PIN,
161
+
hdr->interrupt_pin);
130
162
dw_pcie_dbi_ro_wr_dis(pci);
131
163
132
164
return 0;
···
205
243
{
206
244
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
207
245
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
208
-
unsigned int func_offset, dbi2_offset;
209
246
enum pci_barno bar = epf_bar->barno;
210
247
size_t size = epf_bar->size;
211
248
int flags = epf_bar->flags;
212
-
u32 reg, reg_dbi2;
213
249
int ret, type;
250
+
u32 reg;
214
251
215
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
216
-
dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
217
-
218
-
reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
219
-
reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + dbi2_offset;
252
+
reg = PCI_BASE_ADDRESS_0 + (4 * bar);
220
253
221
254
if (!(flags & PCI_BASE_ADDRESS_SPACE))
222
255
type = PCIE_ATU_TYPE_MEM;
···
227
270
228
271
dw_pcie_dbi_ro_wr_en(pci);
229
272
230
-
dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
231
-
dw_pcie_writel_dbi(pci, reg, flags);
273
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
274
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
232
275
233
276
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
234
-
dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
235
-
dw_pcie_writel_dbi(pci, reg + 4, 0);
277
+
dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
278
+
dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
236
279
}
237
280
238
281
ep->epf_bar[bar] = epf_bar;
···
292
335
static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
293
336
{
294
337
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
295
-
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
296
-
u32 val, reg;
297
-
unsigned int func_offset = 0;
298
338
struct dw_pcie_ep_func *ep_func;
339
+
u32 val, reg;
299
340
300
341
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
301
342
if (!ep_func || !ep_func->msi_cap)
302
343
return -EINVAL;
303
344
304
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
305
-
306
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
307
-
val = dw_pcie_readw_dbi(pci, reg);
345
+
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
346
+
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
308
347
if (!(val & PCI_MSI_FLAGS_ENABLE))
309
348
return -EINVAL;
310
349
···
314
361
{
315
362
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
316
363
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
317
-
u32 val, reg;
318
-
unsigned int func_offset = 0;
319
364
struct dw_pcie_ep_func *ep_func;
365
+
u32 val, reg;
320
366
321
367
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
322
368
if (!ep_func || !ep_func->msi_cap)
323
369
return -EINVAL;
324
370
325
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
326
-
327
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
328
-
val = dw_pcie_readw_dbi(pci, reg);
371
+
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
372
+
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
329
373
val &= ~PCI_MSI_FLAGS_QMASK;
330
374
val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, interrupts);
331
375
dw_pcie_dbi_ro_wr_en(pci);
332
-
dw_pcie_writew_dbi(pci, reg, val);
376
+
dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
333
377
dw_pcie_dbi_ro_wr_dis(pci);
334
378
335
379
return 0;
···
335
385
static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
336
386
{
337
387
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
338
-
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
339
-
u32 val, reg;
340
-
unsigned int func_offset = 0;
341
388
struct dw_pcie_ep_func *ep_func;
389
+
u32 val, reg;
342
390
343
391
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
344
392
if (!ep_func || !ep_func->msix_cap)
345
393
return -EINVAL;
346
394
347
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
348
-
349
-
reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS;
350
-
val = dw_pcie_readw_dbi(pci, reg);
395
+
reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
396
+
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
351
397
if (!(val & PCI_MSIX_FLAGS_ENABLE))
352
398
return -EINVAL;
353
399
···
357
411
{
358
412
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
359
413
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
360
-
u32 val, reg;
361
-
unsigned int func_offset = 0;
362
414
struct dw_pcie_ep_func *ep_func;
415
+
u32 val, reg;
363
416
364
417
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
365
418
if (!ep_func || !ep_func->msix_cap)
···
366
421
367
422
dw_pcie_dbi_ro_wr_en(pci);
368
423
369
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
370
-
371
-
reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS;
372
-
val = dw_pcie_readw_dbi(pci, reg);
424
+
reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
425
+
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
373
426
val &= ~PCI_MSIX_FLAGS_QSIZE;
374
427
val |= interrupts;
375
428
dw_pcie_writew_dbi(pci, reg, val);
376
429
377
-
reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE;
430
+
reg = ep_func->msix_cap + PCI_MSIX_TABLE;
378
431
val = offset | bir;
379
-
dw_pcie_writel_dbi(pci, reg, val);
432
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
380
433
381
-
reg = ep_func->msix_cap + func_offset + PCI_MSIX_PBA;
434
+
reg = ep_func->msix_cap + PCI_MSIX_PBA;
382
435
val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
383
-
dw_pcie_writel_dbi(pci, reg, val);
436
+
dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
384
437
385
438
dw_pcie_dbi_ro_wr_dis(pci);
386
439
···
386
443
}
387
444
388
445
static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
389
-
enum pci_epc_irq_type type, u16 interrupt_num)
446
+
unsigned int type, u16 interrupt_num)
390
447
{
391
448
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
392
449
···
439
496
.get_features = dw_pcie_ep_get_features,
440
497
};
441
498
442
-
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
499
+
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
443
500
{
444
501
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
445
502
struct device *dev = pci->dev;
446
503
447
-
dev_err(dev, "EP cannot trigger legacy IRQs\n");
504
+
dev_err(dev, "EP cannot raise INTX IRQs\n");
448
505
449
506
return -EINVAL;
450
507
}
451
-
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
508
+
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
452
509
453
510
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
454
511
u8 interrupt_num)
455
512
{
456
-
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
513
+
u32 msg_addr_lower, msg_addr_upper, reg;
457
514
struct dw_pcie_ep_func *ep_func;
458
515
struct pci_epc *epc = ep->epc;
459
516
unsigned int aligned_offset;
460
-
unsigned int func_offset = 0;
461
517
u16 msg_ctrl, msg_data;
462
-
u32 msg_addr_lower, msg_addr_upper, reg;
463
-
u64 msg_addr;
464
518
bool has_upper;
519
+
u64 msg_addr;
465
520
int ret;
466
521
467
522
ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
468
523
if (!ep_func || !ep_func->msi_cap)
469
524
return -EINVAL;
470
525
471
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
472
-
473
526
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
474
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
475
-
msg_ctrl = dw_pcie_readw_dbi(pci, reg);
527
+
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
528
+
msg_ctrl = dw_pcie_ep_readw_dbi(ep, func_no, reg);
476
529
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
477
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_LO;
478
-
msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
530
+
reg = ep_func->msi_cap + PCI_MSI_ADDRESS_LO;
531
+
msg_addr_lower = dw_pcie_ep_readl_dbi(ep, func_no, reg);
479
532
if (has_upper) {
480
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_HI;
481
-
msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
482
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_64;
483
-
msg_data = dw_pcie_readw_dbi(pci, reg);
533
+
reg = ep_func->msi_cap + PCI_MSI_ADDRESS_HI;
534
+
msg_addr_upper = dw_pcie_ep_readl_dbi(ep, func_no, reg);
535
+
reg = ep_func->msi_cap + PCI_MSI_DATA_64;
536
+
msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
484
537
} else {
485
538
msg_addr_upper = 0;
486
-
reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_32;
487
-
msg_data = dw_pcie_readw_dbi(pci, reg);
539
+
reg = ep_func->msi_cap + PCI_MSI_DATA_32;
540
+
msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
488
541
}
489
542
aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
490
543
msg_addr = ((u64)msg_addr_upper) << 32 |
···
521
582
u16 interrupt_num)
522
583
{
523
584
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
524
-
struct dw_pcie_ep_func *ep_func;
525
585
struct pci_epf_msix_tbl *msix_tbl;
586
+
struct dw_pcie_ep_func *ep_func;
526
587
struct pci_epc *epc = ep->epc;
527
-
unsigned int func_offset = 0;
528
588
u32 reg, msg_data, vec_ctrl;
529
589
unsigned int aligned_offset;
530
590
u32 tbl_offset;
···
535
597
if (!ep_func || !ep_func->msix_cap)
536
598
return -EINVAL;
537
599
538
-
func_offset = dw_pcie_ep_func_select(ep, func_no);
539
-
540
-
reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE;
541
-
tbl_offset = dw_pcie_readl_dbi(pci, reg);
600
+
reg = ep_func->msix_cap + PCI_MSIX_TABLE;
601
+
tbl_offset = dw_pcie_ep_readl_dbi(ep, func_no, reg);
542
602
bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset);
543
603
tbl_offset &= PCI_MSIX_TABLE_OFFSET;
544
604
···
551
615
}
552
616
553
617
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
618
+
msg_addr &= ~aligned_offset;
554
619
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
555
620
epc->mem->window.page_size);
556
621
if (ret)
···
731
794
list_add_tail(&ep_func->list, &ep->func_list);
732
795
}
733
796
734
-
if (ep->ops->ep_init)
735
-
ep->ops->ep_init(ep);
797
+
if (ep->ops->init)
798
+
ep->ops->init(ep);
736
799
737
800
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
738
801
ep->page_size);
+15
-15
drivers/pci/controller/dwc/pcie-designware-host.c
+15
-15
drivers/pci/controller/dwc/pcie-designware-host.c
···
441
441
bridge->ops = &dw_pcie_ops;
442
442
bridge->child_ops = &dw_child_pcie_ops;
443
443
444
-
if (pp->ops->host_init) {
445
-
ret = pp->ops->host_init(pp);
444
+
if (pp->ops->init) {
445
+
ret = pp->ops->init(pp);
446
446
if (ret)
447
447
return ret;
448
448
}
449
449
450
450
if (pci_msi_enabled()) {
451
-
pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
451
+
pp->has_msi_ctrl = !(pp->ops->msi_init ||
452
452
of_property_read_bool(np, "msi-parent") ||
453
453
of_property_read_bool(np, "msi-map"));
454
454
···
464
464
goto err_deinit_host;
465
465
}
466
466
467
-
if (pp->ops->msi_host_init) {
468
-
ret = pp->ops->msi_host_init(pp);
467
+
if (pp->ops->msi_init) {
468
+
ret = pp->ops->msi_init(pp);
469
469
if (ret < 0)
470
470
goto err_deinit_host;
471
471
} else if (pp->has_msi_ctrl) {
···
502
502
if (ret)
503
503
goto err_stop_link;
504
504
505
-
if (pp->ops->host_post_init)
506
-
pp->ops->host_post_init(pp);
505
+
if (pp->ops->post_init)
506
+
pp->ops->post_init(pp);
507
507
508
508
return 0;
509
509
···
518
518
dw_pcie_free_msi(pp);
519
519
520
520
err_deinit_host:
521
-
if (pp->ops->host_deinit)
522
-
pp->ops->host_deinit(pp);
521
+
if (pp->ops->deinit)
522
+
pp->ops->deinit(pp);
523
523
524
524
return ret;
525
525
}
···
539
539
if (pp->has_msi_ctrl)
540
540
dw_pcie_free_msi(pp);
541
541
542
-
if (pp->ops->host_deinit)
543
-
pp->ops->host_deinit(pp);
542
+
if (pp->ops->deinit)
543
+
pp->ops->deinit(pp);
544
544
}
545
545
EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
546
546
···
842
842
return ret;
843
843
}
844
844
845
-
if (pci->pp.ops->host_deinit)
846
-
pci->pp.ops->host_deinit(&pci->pp);
845
+
if (pci->pp.ops->deinit)
846
+
pci->pp.ops->deinit(&pci->pp);
847
847
848
848
pci->suspended = true;
849
849
···
860
860
861
861
pci->suspended = false;
862
862
863
-
if (pci->pp.ops->host_init) {
864
-
ret = pci->pp.ops->host_init(&pci->pp);
863
+
if (pci->pp.ops->init) {
864
+
ret = pci->pp.ops->init(&pci->pp);
865
865
if (ret) {
866
866
dev_err(pci->dev, "Host init failed: %d\n", ret);
867
867
return ret;
+6
-7
drivers/pci/controller/dwc/pcie-designware-plat.c
+6
-7
drivers/pci/controller/dwc/pcie-designware-plat.c
···
42
42
}
43
43
44
44
static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
45
-
enum pci_epc_irq_type type,
46
-
u16 interrupt_num)
45
+
unsigned int type, u16 interrupt_num)
47
46
{
48
47
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
49
48
50
49
switch (type) {
51
-
case PCI_EPC_IRQ_LEGACY:
52
-
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
53
-
case PCI_EPC_IRQ_MSI:
50
+
case PCI_IRQ_INTX:
51
+
return dw_pcie_ep_raise_intx_irq(ep, func_no);
52
+
case PCI_IRQ_MSI:
54
53
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
55
-
case PCI_EPC_IRQ_MSIX:
54
+
case PCI_IRQ_MSIX:
56
55
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
57
56
default:
58
57
dev_err(pci->dev, "UNKNOWN IRQ type\n");
···
73
74
}
74
75
75
76
static const struct dw_pcie_ep_ops pcie_ep_ops = {
76
-
.ep_init = dw_plat_pcie_ep_init,
77
+
.init = dw_plat_pcie_ep_init,
77
78
.raise_irq = dw_plat_pcie_ep_raise_irq,
78
79
.get_features = dw_plat_pcie_get_features,
79
80
};
+102
-9
drivers/pci/controller/dwc/pcie-designware.h
+102
-9
drivers/pci/controller/dwc/pcie-designware.h
···
300
300
};
301
301
302
302
struct dw_pcie_host_ops {
303
-
int (*host_init)(struct dw_pcie_rp *pp);
304
-
void (*host_deinit)(struct dw_pcie_rp *pp);
305
-
void (*host_post_init)(struct dw_pcie_rp *pp);
306
-
int (*msi_host_init)(struct dw_pcie_rp *pp);
303
+
int (*init)(struct dw_pcie_rp *pp);
304
+
void (*deinit)(struct dw_pcie_rp *pp);
305
+
void (*post_init)(struct dw_pcie_rp *pp);
306
+
int (*msi_init)(struct dw_pcie_rp *pp);
307
307
void (*pme_turn_off)(struct dw_pcie_rp *pp);
308
308
};
309
309
···
332
332
333
333
struct dw_pcie_ep_ops {
334
334
void (*pre_init)(struct dw_pcie_ep *ep);
335
-
void (*ep_init)(struct dw_pcie_ep *ep);
335
+
void (*init)(struct dw_pcie_ep *ep);
336
336
void (*deinit)(struct dw_pcie_ep *ep);
337
337
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
338
-
enum pci_epc_irq_type type, u16 interrupt_num);
338
+
unsigned int type, u16 interrupt_num);
339
339
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
340
340
/*
341
341
* Provide a method to implement the different func config space
···
344
344
* return a 0, and implement code in callback function of platform
345
345
* driver.
346
346
*/
347
-
unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
347
+
unsigned int (*get_dbi_offset)(struct dw_pcie_ep *ep, u8 func_no);
348
348
unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
349
349
};
350
350
···
486
486
dw_pcie_write_dbi2(pci, reg, 0x4, val);
487
487
}
488
488
489
+
static inline unsigned int dw_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,
490
+
u8 func_no)
491
+
{
492
+
unsigned int dbi_offset = 0;
493
+
494
+
if (ep->ops->get_dbi_offset)
495
+
dbi_offset = ep->ops->get_dbi_offset(ep, func_no);
496
+
497
+
return dbi_offset;
498
+
}
499
+
500
+
static inline u32 dw_pcie_ep_read_dbi(struct dw_pcie_ep *ep, u8 func_no,
501
+
u32 reg, size_t size)
502
+
{
503
+
unsigned int offset = dw_pcie_ep_get_dbi_offset(ep, func_no);
504
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
505
+
506
+
return dw_pcie_read_dbi(pci, offset + reg, size);
507
+
}
508
+
509
+
static inline void dw_pcie_ep_write_dbi(struct dw_pcie_ep *ep, u8 func_no,
510
+
u32 reg, size_t size, u32 val)
511
+
{
512
+
unsigned int offset = dw_pcie_ep_get_dbi_offset(ep, func_no);
513
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
514
+
515
+
dw_pcie_write_dbi(pci, offset + reg, size, val);
516
+
}
517
+
518
+
static inline void dw_pcie_ep_writel_dbi(struct dw_pcie_ep *ep, u8 func_no,
519
+
u32 reg, u32 val)
520
+
{
521
+
dw_pcie_ep_write_dbi(ep, func_no, reg, 0x4, val);
522
+
}
523
+
524
+
static inline u32 dw_pcie_ep_readl_dbi(struct dw_pcie_ep *ep, u8 func_no,
525
+
u32 reg)
526
+
{
527
+
return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x4);
528
+
}
529
+
530
+
static inline void dw_pcie_ep_writew_dbi(struct dw_pcie_ep *ep, u8 func_no,
531
+
u32 reg, u16 val)
532
+
{
533
+
dw_pcie_ep_write_dbi(ep, func_no, reg, 0x2, val);
534
+
}
535
+
536
+
static inline u16 dw_pcie_ep_readw_dbi(struct dw_pcie_ep *ep, u8 func_no,
537
+
u32 reg)
538
+
{
539
+
return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x2);
540
+
}
541
+
542
+
static inline void dw_pcie_ep_writeb_dbi(struct dw_pcie_ep *ep, u8 func_no,
543
+
u32 reg, u8 val)
544
+
{
545
+
dw_pcie_ep_write_dbi(ep, func_no, reg, 0x1, val);
546
+
}
547
+
548
+
static inline u8 dw_pcie_ep_readb_dbi(struct dw_pcie_ep *ep, u8 func_no,
549
+
u32 reg)
550
+
{
551
+
return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x1);
552
+
}
553
+
554
+
static inline unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
555
+
u8 func_no)
556
+
{
557
+
unsigned int dbi2_offset = 0;
558
+
559
+
if (ep->ops->get_dbi2_offset)
560
+
dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
561
+
else if (ep->ops->get_dbi_offset) /* for backward compatibility */
562
+
dbi2_offset = ep->ops->get_dbi_offset(ep, func_no);
563
+
564
+
return dbi2_offset;
565
+
}
566
+
567
+
static inline void dw_pcie_ep_write_dbi2(struct dw_pcie_ep *ep, u8 func_no,
568
+
u32 reg, size_t size, u32 val)
569
+
{
570
+
unsigned int offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
571
+
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
572
+
573
+
dw_pcie_write_dbi2(pci, offset + reg, size, val);
574
+
}
575
+
576
+
static inline void dw_pcie_ep_writel_dbi2(struct dw_pcie_ep *ep, u8 func_no,
577
+
u32 reg, u32 val)
578
+
{
579
+
dw_pcie_ep_write_dbi2(ep, func_no, reg, 0x4, val);
580
+
}
581
+
489
582
static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
490
583
{
491
584
u32 reg;
···
673
580
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
674
581
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
675
582
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
676
-
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
583
+
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no);
677
584
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
678
585
u8 interrupt_num);
679
586
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
···
706
613
{
707
614
}
708
615
709
-
static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
616
+
static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
710
617
{
711
618
return 0;
712
619
}
+3
-3
drivers/pci/controller/dwc/pcie-dw-rockchip.c
+3
-3
drivers/pci/controller/dwc/pcie-dw-rockchip.c
···
72
72
writel_relaxed(val, rockchip->apb_base + reg);
73
73
}
74
74
75
-
static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
75
+
static void rockchip_pcie_intx_handler(struct irq_desc *desc)
76
76
{
77
77
struct irq_chip *chip = irq_desc_get_chip(desc);
78
78
struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
···
202
202
if (ret < 0)
203
203
dev_err(dev, "failed to init irq domain\n");
204
204
205
-
irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
205
+
irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
206
206
rockchip);
207
207
208
208
/* LTSSM enable control mode */
···
215
215
}
216
216
217
217
static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
218
-
.host_init = rockchip_pcie_host_init,
218
+
.init = rockchip_pcie_host_init,
219
219
};
220
220
221
221
static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
+1
-1
drivers/pci/controller/dwc/pcie-fu740.c
+1
-1
drivers/pci/controller/dwc/pcie-fu740.c
+1
-1
drivers/pci/controller/dwc/pcie-histb.c
+1
-1
drivers/pci/controller/dwc/pcie-histb.c
+1
-1
drivers/pci/controller/dwc/pcie-intel-gw.c
+1
-1
drivers/pci/controller/dwc/pcie-intel-gw.c
+7
-8
drivers/pci/controller/dwc/pcie-keembay.c
+7
-8
drivers/pci/controller/dwc/pcie-keembay.c
···
289
289
}
290
290
291
291
static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
292
-
enum pci_epc_irq_type type,
293
-
u16 interrupt_num)
292
+
unsigned int type, u16 interrupt_num)
294
293
{
295
294
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
296
295
297
296
switch (type) {
298
-
case PCI_EPC_IRQ_LEGACY:
299
-
/* Legacy interrupts are not supported in Keem Bay */
300
-
dev_err(pci->dev, "Legacy IRQ is not supported\n");
297
+
case PCI_IRQ_INTX:
298
+
/* INTx interrupts are not supported in Keem Bay */
299
+
dev_err(pci->dev, "INTx IRQ is not supported\n");
301
300
return -EINVAL;
302
-
case PCI_EPC_IRQ_MSI:
301
+
case PCI_IRQ_MSI:
303
302
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
304
-
case PCI_EPC_IRQ_MSIX:
303
+
case PCI_IRQ_MSIX:
305
304
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
306
305
default:
307
306
dev_err(pci->dev, "Unknown IRQ type %d\n", type);
···
324
325
}
325
326
326
327
static const struct dw_pcie_ep_ops keembay_pcie_ep_ops = {
327
-
.ep_init = keembay_pcie_ep_init,
328
+
.init = keembay_pcie_ep_init,
328
329
.raise_irq = keembay_pcie_ep_raise_irq,
329
330
.get_features = keembay_pcie_get_features,
330
331
};
+8
-13
drivers/pci/controller/dwc/pcie-kirin.c
+8
-13
drivers/pci/controller/dwc/pcie-kirin.c
···
366
366
struct platform_device *pdev)
367
367
{
368
368
struct device *dev = &pdev->dev;
369
-
char name[32];
370
369
int ret, i;
371
370
372
371
/* This is an optional property */
···
386
387
if (pcie->gpio_id_clkreq[i] < 0)
387
388
return pcie->gpio_id_clkreq[i];
388
389
389
-
sprintf(name, "pcie_clkreq_%d", i);
390
-
pcie->clkreq_names[i] = devm_kstrdup_const(dev, name,
391
-
GFP_KERNEL);
390
+
pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
391
+
"pcie_clkreq_%d", i);
392
392
if (!pcie->clkreq_names[i])
393
393
return -ENOMEM;
394
394
}
···
402
404
struct device *dev = &pdev->dev;
403
405
struct device_node *parent, *child;
404
406
int ret, slot, i;
405
-
char name[32];
406
407
407
408
for_each_available_child_of_node(node, parent) {
408
409
for_each_available_child_of_node(parent, child) {
···
427
430
428
431
slot = PCI_SLOT(ret);
429
432
430
-
sprintf(name, "pcie_perst_%d", slot);
431
-
pcie->reset_names[i] = devm_kstrdup_const(dev, name,
432
-
GFP_KERNEL);
433
+
pcie->reset_names[i] = devm_kasprintf(dev, GFP_KERNEL,
434
+
"pcie_perst_%d",
435
+
slot);
433
436
if (!pcie->reset_names[i]) {
434
437
ret = -ENOMEM;
435
438
goto put_node;
···
669
672
};
670
673
671
674
static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
672
-
.host_init = kirin_pcie_host_init,
675
+
.init = kirin_pcie_host_init,
673
676
};
674
677
675
678
static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
···
738
741
return ret;
739
742
}
740
743
741
-
static int kirin_pcie_remove(struct platform_device *pdev)
744
+
static void kirin_pcie_remove(struct platform_device *pdev)
742
745
{
743
746
struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev);
744
747
745
748
dw_pcie_host_deinit(&kirin_pcie->pci->pp);
746
749
747
750
kirin_pcie_power_off(kirin_pcie);
748
-
749
-
return 0;
750
751
}
751
752
752
753
struct kirin_pcie_data {
···
813
818
814
819
static struct platform_driver kirin_pcie_driver = {
815
820
.probe = kirin_pcie_probe,
816
-
.remove = kirin_pcie_remove,
821
+
.remove_new = kirin_pcie_remove,
817
822
.driver = {
818
823
.name = "kirin-pcie",
819
824
.of_match_table = kirin_pcie_match,
+5
-5
drivers/pci/controller/dwc/pcie-qcom-ep.c
+5
-5
drivers/pci/controller/dwc/pcie-qcom-ep.c
···
726
726
}
727
727
728
728
static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
729
-
enum pci_epc_irq_type type, u16 interrupt_num)
729
+
unsigned int type, u16 interrupt_num)
730
730
{
731
731
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
732
732
733
733
switch (type) {
734
-
case PCI_EPC_IRQ_LEGACY:
735
-
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
736
-
case PCI_EPC_IRQ_MSI:
734
+
case PCI_IRQ_INTX:
735
+
return dw_pcie_ep_raise_intx_irq(ep, func_no);
736
+
case PCI_IRQ_MSI:
737
737
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
738
738
default:
739
739
dev_err(pci->dev, "Unknown IRQ type\n");
···
796
796
}
797
797
798
798
static const struct dw_pcie_ep_ops pci_ep_ops = {
799
-
.ep_init = qcom_pcie_ep_init,
799
+
.init = qcom_pcie_ep_init,
800
800
.raise_irq = qcom_pcie_ep_raise_irq,
801
801
.get_features = qcom_pcie_epc_get_features,
802
802
};
+3
-3
drivers/pci/controller/dwc/pcie-qcom.c
+3
-3
drivers/pci/controller/dwc/pcie-qcom.c
···
1247
1247
}
1248
1248
1249
1249
static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1250
-
.host_init = qcom_pcie_host_init,
1251
-
.host_deinit = qcom_pcie_host_deinit,
1252
-
.host_post_init = qcom_pcie_host_post_init,
1250
+
.init = qcom_pcie_host_init,
1251
+
.deinit = qcom_pcie_host_deinit,
1252
+
.post_init = qcom_pcie_host_post_init,
1253
1253
};
1254
1254
1255
1255
/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
+11
-12
drivers/pci/controller/dwc/pcie-rcar-gen4.c
+11
-12
drivers/pci/controller/dwc/pcie-rcar-gen4.c
···
8
8
#include <linux/interrupt.h>
9
9
#include <linux/io.h>
10
10
#include <linux/module.h>
11
-
#include <linux/of_device.h>
11
+
#include <linux/of.h>
12
12
#include <linux/pci.h>
13
13
#include <linux/platform_device.h>
14
14
#include <linux/pm_runtime.h>
···
307
307
}
308
308
309
309
static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
310
-
.host_init = rcar_gen4_pcie_host_init,
311
-
.host_deinit = rcar_gen4_pcie_host_deinit,
310
+
.init = rcar_gen4_pcie_host_init,
311
+
.deinit = rcar_gen4_pcie_host_deinit,
312
312
};
313
313
314
314
static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
···
362
362
}
363
363
364
364
static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
365
-
enum pci_epc_irq_type type,
366
-
u16 interrupt_num)
365
+
unsigned int type, u16 interrupt_num)
367
366
{
368
367
struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
369
368
370
369
switch (type) {
371
-
case PCI_EPC_IRQ_LEGACY:
372
-
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
373
-
case PCI_EPC_IRQ_MSI:
370
+
case PCI_IRQ_INTX:
371
+
return dw_pcie_ep_raise_intx_irq(ep, func_no);
372
+
case PCI_IRQ_MSI:
374
373
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
375
374
default:
376
375
dev_err(dw->dev, "Unknown IRQ type\n");
···
393
394
return &rcar_gen4_pcie_epc_features;
394
395
}
395
396
396
-
static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
397
+
static unsigned int rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,
397
398
u8 func_no)
398
399
{
399
400
return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
···
407
408
408
409
static const struct dw_pcie_ep_ops pcie_ep_ops = {
409
410
.pre_init = rcar_gen4_pcie_ep_pre_init,
410
-
.ep_init = rcar_gen4_pcie_ep_init,
411
+
.init = rcar_gen4_pcie_ep_init,
411
412
.deinit = rcar_gen4_pcie_ep_deinit,
412
413
.raise_irq = rcar_gen4_pcie_ep_raise_irq,
413
414
.get_features = rcar_gen4_pcie_ep_get_features,
414
-
.func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
415
+
.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
415
416
.get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,
416
417
};
417
418
···
435
436
/* Common */
436
437
static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)
437
438
{
438
-
rcar->mode = (enum dw_pcie_device_mode)of_device_get_match_data(&rcar->pdev->dev);
439
+
rcar->mode = (uintptr_t)of_device_get_match_data(&rcar->pdev->dev);
439
440
440
441
switch (rcar->mode) {
441
442
case DW_PCIE_RC_TYPE:
+1
-1
drivers/pci/controller/dwc/pcie-spear13xx.c
+1
-1
drivers/pci/controller/dwc/pcie-spear13xx.c
+10
-11
drivers/pci/controller/dwc/pcie-tegra194.c
+10
-11
drivers/pci/controller/dwc/pcie-tegra194.c
···
773
773
val_w);
774
774
}
775
775
776
-
static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
776
+
static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)
777
777
{
778
778
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
779
779
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
780
780
u32 val;
781
781
782
-
/* Enable legacy interrupt generation */
782
+
/* Enable INTX interrupt generation */
783
783
val = appl_readl(pcie, APPL_INTR_EN_L0_0);
784
784
val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
785
785
val |= APPL_INTR_EN_L0_0_INT_INT_EN;
···
830
830
appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
831
831
832
832
tegra_pcie_enable_system_interrupts(pp);
833
-
tegra_pcie_enable_legacy_interrupts(pp);
833
+
tegra_pcie_enable_intx_interrupts(pp);
834
834
if (IS_ENABLED(CONFIG_PCI_MSI))
835
835
tegra_pcie_enable_msi_interrupts(pp);
836
836
}
···
1060
1060
};
1061
1061
1062
1062
static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
1063
-
.host_init = tegra_pcie_dw_host_init,
1063
+
.init = tegra_pcie_dw_host_init,
1064
1064
};
1065
1065
1066
1066
static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
···
1947
1947
return IRQ_HANDLED;
1948
1948
}
1949
1949
1950
-
static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
1950
+
static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
1951
1951
{
1952
1952
/* Tegra194 supports only INTA */
1953
1953
if (irq > 1)
···
1979
1979
}
1980
1980
1981
1981
static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1982
-
enum pci_epc_irq_type type,
1983
-
u16 interrupt_num)
1982
+
unsigned int type, u16 interrupt_num)
1984
1983
{
1985
1984
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1986
1985
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1987
1986
1988
1987
switch (type) {
1989
-
case PCI_EPC_IRQ_LEGACY:
1990
-
return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1988
+
case PCI_IRQ_INTX:
1989
+
return tegra_pcie_ep_raise_intx_irq(pcie, interrupt_num);
1991
1990
1992
-
case PCI_EPC_IRQ_MSI:
1991
+
case PCI_IRQ_MSI:
1993
1992
return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1994
1993
1995
-
case PCI_EPC_IRQ_MSIX:
1994
+
case PCI_IRQ_MSIX:
1996
1995
return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
1997
1996
1998
1997
default:
+6
-7
drivers/pci/controller/dwc/pcie-uniphier-ep.c
+6
-7
drivers/pci/controller/dwc/pcie-uniphier-ep.c
···
212
212
dw_pcie_ep_reset_bar(pci, bar);
213
213
}
214
214
215
-
static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep)
215
+
static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)
216
216
{
217
217
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
218
218
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
···
256
256
}
257
257
258
258
static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
259
-
enum pci_epc_irq_type type,
260
-
u16 interrupt_num)
259
+
unsigned int type, u16 interrupt_num)
261
260
{
262
261
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
263
262
264
263
switch (type) {
265
-
case PCI_EPC_IRQ_LEGACY:
266
-
return uniphier_pcie_ep_raise_legacy_irq(ep);
267
-
case PCI_EPC_IRQ_MSI:
264
+
case PCI_IRQ_INTX:
265
+
return uniphier_pcie_ep_raise_intx_irq(ep);
266
+
case PCI_IRQ_MSI:
268
267
return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
269
268
interrupt_num);
270
269
default:
···
283
284
}
284
285
285
286
static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
286
-
.ep_init = uniphier_pcie_ep_init,
287
+
.init = uniphier_pcie_ep_init,
287
288
.raise_irq = uniphier_pcie_ep_raise_irq,
288
289
.get_features = uniphier_pcie_get_features,
289
290
};
+7
-7
drivers/pci/controller/dwc/pcie-uniphier.c
+7
-7
drivers/pci/controller/dwc/pcie-uniphier.c
···
67
67
struct clk *clk;
68
68
struct reset_control *rst;
69
69
struct phy *phy;
70
-
struct irq_domain *legacy_irq_domain;
70
+
struct irq_domain *intx_irq_domain;
71
71
};
72
72
73
73
#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
···
253
253
reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
254
254
255
255
for_each_set_bit(bit, ®, PCI_NUM_INTX)
256
-
generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
256
+
generic_handle_domain_irq(pcie->intx_irq_domain, bit);
257
257
258
258
chained_irq_exit(chip, desc);
259
259
}
260
260
261
-
static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
261
+
static int uniphier_pcie_config_intx_irq(struct dw_pcie_rp *pp)
262
262
{
263
263
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
264
264
struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
···
279
279
goto out_put_node;
280
280
}
281
281
282
-
pcie->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
282
+
pcie->intx_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
283
283
&uniphier_intx_domain_ops, pp);
284
-
if (!pcie->legacy_irq_domain) {
284
+
if (!pcie->intx_irq_domain) {
285
285
dev_err(pci->dev, "Failed to get INTx domain\n");
286
286
ret = -ENODEV;
287
287
goto out_put_node;
···
301
301
struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
302
302
int ret;
303
303
304
-
ret = uniphier_pcie_config_legacy_irq(pp);
304
+
ret = uniphier_pcie_config_intx_irq(pp);
305
305
if (ret)
306
306
return ret;
307
307
···
311
311
}
312
312
313
313
static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
314
-
.host_init = uniphier_pcie_host_init,
314
+
.init = uniphier_pcie_host_init,
315
315
};
316
316
317
317
static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie)
+1
-1
drivers/pci/controller/dwc/pcie-visconti.c
+1
-1
drivers/pci/controller/dwc/pcie-visconti.c
+1
-3
drivers/pci/controller/pci-host-common.c
+1
-3
drivers/pci/controller/pci-host-common.c
···
85
85
}
86
86
EXPORT_SYMBOL_GPL(pci_host_common_probe);
87
87
88
-
int pci_host_common_remove(struct platform_device *pdev)
88
+
void pci_host_common_remove(struct platform_device *pdev)
89
89
{
90
90
struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
91
91
···
93
93
pci_stop_root_bus(bridge->bus);
94
94
pci_remove_root_bus(bridge->bus);
95
95
pci_unlock_rescan_remove();
96
-
97
-
return 0;
98
96
}
99
97
EXPORT_SYMBOL_GPL(pci_host_common_remove);
100
98
+1
-1
drivers/pci/controller/pci-host-generic.c
+1
-1
drivers/pci/controller/pci-host-generic.c
+86
-10
drivers/pci/controller/pcie-brcmstb.c
+86
-10
drivers/pci/controller/pcie-brcmstb.c
···
48
48
#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
49
49
#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
50
50
51
+
#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
52
+
#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
53
+
51
54
#define PCIE_RC_DL_MDIO_ADDR 0x1100
52
55
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
53
56
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
···
124
121
125
122
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
126
123
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
124
+
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
127
125
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
128
126
#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
129
-
127
+
#define PCIE_CLKREQ_MASK \
128
+
(PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
129
+
PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
130
130
131
131
#define PCIE_INTR2_CPU_BASE 0x4300
132
132
#define PCIE_MSI_INTR2_BASE 0x4500
···
1034
1028
return 0;
1035
1029
}
1036
1030
1031
+
/*
1032
+
* This extends the timeout period for an access to an internal bus. This
1033
+
* access timeout may occur during L1SS sleep periods, even without the
1034
+
* presence of a PCIe access.
1035
+
*/
1036
+
static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
1037
+
{
1038
+
/* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
1039
+
const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
1040
+
u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
1041
+
1042
+
/* Each unit in timeout register is 1/216,000,000 seconds */
1043
+
writel(216 * timeout_us, pcie->base + REG_OFFSET);
1044
+
}
1045
+
1046
+
static void brcm_config_clkreq(struct brcm_pcie *pcie)
1047
+
{
1048
+
static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n";
1049
+
const char *mode = "default";
1050
+
u32 clkreq_cntl;
1051
+
int ret, tmp;
1052
+
1053
+
ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode);
1054
+
if (ret && ret != -EINVAL) {
1055
+
dev_err(pcie->dev, err_msg);
1056
+
mode = "safe";
1057
+
}
1058
+
1059
+
/* Start out assuming safe mode (both mode bits cleared) */
1060
+
clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1061
+
clkreq_cntl &= ~PCIE_CLKREQ_MASK;
1062
+
1063
+
if (strcmp(mode, "no-l1ss") == 0) {
1064
+
/*
1065
+
* "no-l1ss" -- Provides Clock Power Management, L0s, and
1066
+
* L1, but cannot provide L1 substate (L1SS) power
1067
+
* savings. If the downstream device connected to the RC is
1068
+
* L1SS capable AND the OS enables L1SS, all PCIe traffic
1069
+
* may abruptly halt, potentially hanging the system.
1070
+
*/
1071
+
clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1072
+
/*
1073
+
* We want to un-advertise L1 substates because if the OS
1074
+
* tries to configure the controller into using L1 substate
1075
+
* power savings it may fail or hang when the RC HW is in
1076
+
* "no-l1ss" mode.
1077
+
*/
1078
+
tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1079
+
u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK);
1080
+
writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1081
+
1082
+
} else if (strcmp(mode, "default") == 0) {
1083
+
/*
1084
+
* "default" -- Provides L0s, L1, and L1SS, but not
1085
+
* compliant to provide Clock Power Management;
1086
+
* specifically, may not be able to meet the Tclron max
1087
+
* timing of 400ns as specified in "Dynamic Clock Control",
1088
+
* section 3.2.5.2.2 of the PCIe spec. This situation is
1089
+
* atypical and should happen only with older devices.
1090
+
*/
1091
+
clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
1092
+
brcm_extend_rbus_timeout(pcie);
1093
+
1094
+
} else {
1095
+
/*
1096
+
* "safe" -- No power savings; refclk is driven by RC
1097
+
* unconditionally.
1098
+
*/
1099
+
if (strcmp(mode, "safe") != 0)
1100
+
dev_err(pcie->dev, err_msg);
1101
+
mode = "safe";
1102
+
}
1103
+
writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1104
+
1105
+
dev_info(pcie->dev, "clkreq-mode set to %s\n", mode);
1106
+
}
1107
+
1037
1108
static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1038
1109
{
1039
1110
struct device *dev = pcie->dev;
1040
1111
void __iomem *base = pcie->base;
1041
1112
u16 nlw, cls, lnksta;
1042
1113
bool ssc_good = false;
1043
-
u32 tmp;
1044
1114
int ret, i;
1045
1115
1046
1116
/* Unassert the fundamental reset */
···
1141
1059
return -ENODEV;
1142
1060
}
1143
1061
1062
+
brcm_config_clkreq(pcie);
1063
+
1144
1064
if (pcie->gen)
1145
1065
brcm_pcie_set_gen(pcie, pcie->gen);
1146
1066
···
1160
1076
dev_info(dev, "link up, %s x%u %s\n",
1161
1077
pci_speed_string(pcie_link_speed[cls]), nlw,
1162
1078
ssc_good ? "(SSC)" : "(!SSC)");
1163
-
1164
-
/*
1165
-
* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
1166
-
* is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
1167
-
*/
1168
-
tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1169
-
tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1170
-
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1171
1079
1172
1080
return 0;
1173
1081
}
+1
-1
drivers/pci/controller/pcie-iproc-platform.c
+1
-1
drivers/pci/controller/pcie-iproc-platform.c
+52
-37
drivers/pci/controller/pcie-mediatek-gen3.c
+52
-37
drivers/pci/controller/pcie-mediatek-gen3.c
···
245
245
resource_size_t cpu_addr,
246
246
resource_size_t pci_addr,
247
247
resource_size_t size,
248
-
unsigned long type, int num)
248
+
unsigned long type, int *num)
249
249
{
250
+
resource_size_t remaining = size;
251
+
resource_size_t table_size;
252
+
resource_size_t addr_align;
253
+
const char *range_type;
250
254
void __iomem *table;
251
255
u32 val;
252
256
253
-
if (num >= PCIE_MAX_TRANS_TABLES) {
254
-
dev_err(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
255
-
(unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
256
-
return -ENODEV;
257
+
while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) {
258
+
/* Table size needs to be a power of 2 */
259
+
table_size = BIT(fls(remaining) - 1);
260
+
261
+
if (cpu_addr > 0) {
262
+
addr_align = BIT(ffs(cpu_addr) - 1);
263
+
table_size = min(table_size, addr_align);
264
+
}
265
+
266
+
/* Minimum size of translate table is 4KiB */
267
+
if (table_size < 0x1000) {
268
+
dev_err(pcie->dev, "illegal table size %#llx\n",
269
+
(unsigned long long)table_size);
270
+
return -EINVAL;
271
+
}
272
+
273
+
table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
274
+
writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table);
275
+
writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
276
+
writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
277
+
writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
278
+
279
+
if (type == IORESOURCE_IO) {
280
+
val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
281
+
range_type = "IO";
282
+
} else {
283
+
val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
284
+
range_type = "MEM";
285
+
}
286
+
287
+
writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
288
+
289
+
dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
290
+
range_type, *num, (unsigned long long)cpu_addr,
291
+
(unsigned long long)pci_addr, (unsigned long long)table_size);
292
+
293
+
cpu_addr += table_size;
294
+
pci_addr += table_size;
295
+
remaining -= table_size;
296
+
(*num)++;
257
297
}
258
298
259
-
table = pcie->base + PCIE_TRANS_TABLE_BASE_REG +
260
-
num * PCIE_ATR_TLB_SET_OFFSET;
261
-
262
-
writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1),
263
-
table);
264
-
writel_relaxed(upper_32_bits(cpu_addr),
265
-
table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
266
-
writel_relaxed(lower_32_bits(pci_addr),
267
-
table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
268
-
writel_relaxed(upper_32_bits(pci_addr),
269
-
table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
270
-
271
-
if (type == IORESOURCE_IO)
272
-
val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
273
-
else
274
-
val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
275
-
276
-
writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
299
+
if (remaining)
300
+
dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
301
+
(unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
277
302
278
303
return 0;
279
304
}
···
405
380
resource_size_t cpu_addr;
406
381
resource_size_t pci_addr;
407
382
resource_size_t size;
408
-
const char *range_type;
409
383
410
-
if (type == IORESOURCE_IO) {
384
+
if (type == IORESOURCE_IO)
411
385
cpu_addr = pci_pio_to_address(res->start);
412
-
range_type = "IO";
413
-
} else if (type == IORESOURCE_MEM) {
386
+
else if (type == IORESOURCE_MEM)
414
387
cpu_addr = res->start;
415
-
range_type = "MEM";
416
-
} else {
388
+
else
417
389
continue;
418
-
}
419
390
420
391
pci_addr = res->start - entry->offset;
421
392
size = resource_size(res);
422
393
err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
423
-
type, table_index);
394
+
type, &table_index);
424
395
if (err)
425
396
return err;
426
-
427
-
dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
428
-
range_type, table_index, (unsigned long long)cpu_addr,
429
-
(unsigned long long)pci_addr, (unsigned long long)size);
430
-
431
-
table_index++;
432
397
}
433
398
434
399
return 0;
+8
-2
drivers/pci/controller/pcie-mediatek.c
+8
-2
drivers/pci/controller/pcie-mediatek.c
···
617
617
if (status & MSI_STATUS){
618
618
unsigned long imsi_status;
619
619
620
+
/*
621
+
* The interrupt status can be cleared even if the
622
+
* MSI status remains pending. As such, given the
623
+
* edge-triggered interrupt type, its status should
624
+
* be cleared before being dispatched to the
625
+
* handler of the underlying device.
626
+
*/
627
+
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
620
628
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
621
629
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
622
630
generic_handle_domain_irq(port->inner_domain, bit);
623
631
}
624
-
/* Clear MSI interrupt status */
625
-
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
626
632
}
627
633
}
628
634
+3
-4
drivers/pci/controller/pcie-rcar-ep.c
+3
-4
drivers/pci/controller/pcie-rcar-ep.c
···
402
402
}
403
403
404
404
static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
405
-
enum pci_epc_irq_type type,
406
-
u16 interrupt_num)
405
+
unsigned int type, u16 interrupt_num)
407
406
{
408
407
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
409
408
410
409
switch (type) {
411
-
case PCI_EPC_IRQ_LEGACY:
410
+
case PCI_IRQ_INTX:
412
411
return rcar_pcie_ep_assert_intx(ep, fn, 0);
413
412
414
-
case PCI_EPC_IRQ_MSI:
413
+
case PCI_IRQ_MSI:
415
414
return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
416
415
417
416
default:
+17
-1
drivers/pci/controller/pcie-rcar-host.c
+17
-1
drivers/pci/controller/pcie-rcar-host.c
···
29
29
#include <linux/phy/phy.h>
30
30
#include <linux/platform_device.h>
31
31
#include <linux/pm_runtime.h>
32
+
#include <linux/regulator/consumer.h>
32
33
33
34
#include "pcie-rcar.h"
34
35
···
954
953
{},
955
954
};
956
955
956
+
/* Design note 346 from Linear Technology says order is not important. */
957
+
static const char * const rcar_pcie_supplies[] = {
958
+
"vpcie1v5",
959
+
"vpcie3v3",
960
+
"vpcie12v",
961
+
};
962
+
957
963
static int rcar_pcie_probe(struct platform_device *pdev)
958
964
{
959
965
struct device *dev = &pdev->dev;
966
+
struct pci_host_bridge *bridge;
960
967
struct rcar_pcie_host *host;
961
968
struct rcar_pcie *pcie;
969
+
unsigned int i;
962
970
u32 data;
963
971
int err;
964
-
struct pci_host_bridge *bridge;
965
972
966
973
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
967
974
if (!bridge)
···
979
970
pcie = &host->pcie;
980
971
pcie->dev = dev;
981
972
platform_set_drvdata(pdev, host);
973
+
974
+
for (i = 0; i < ARRAY_SIZE(rcar_pcie_supplies); i++) {
975
+
err = devm_regulator_get_enable_optional(dev, rcar_pcie_supplies[i]);
976
+
if (err < 0 && err != -ENODEV)
977
+
return dev_err_probe(dev, err, "failed to enable regulator: %s\n",
978
+
rcar_pcie_supplies[i]);
979
+
}
982
980
983
981
pm_runtime_enable(pcie->dev);
984
982
err = pm_runtime_get_sync(pcie->dev);
+11
-12
drivers/pci/controller/pcie-rockchip-ep.c
+11
-12
drivers/pci/controller/pcie-rockchip-ep.c
···
26
26
* @max_regions: maximum number of regions supported by hardware
27
27
* @ob_region_map: bitmask of mapped outbound regions
28
28
* @ob_addr: base addresses in the AXI bus where the outbound regions start
29
-
* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
29
+
* @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
30
30
* dedicated outbound regions is mapped.
31
31
* @irq_cpu_addr: base address in the CPU space where a write access triggers
32
-
* the sending of a memory write (MSI) / normal message (legacy
32
+
* the sending of a memory write (MSI) / normal message (INTX
33
33
* IRQ) TLP through the PCIe bus.
34
-
* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
34
+
* @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
35
35
* dedicated outbound region.
36
36
* @irq_pci_fn: the latest PCI function that has updated the mapping of
37
-
* the MSI/legacy IRQ dedicated outbound region.
38
-
* @irq_pending: bitmask of asserted legacy IRQs.
37
+
* the MSI/INTX IRQ dedicated outbound region.
38
+
* @irq_pending: bitmask of asserted INTX IRQs.
39
39
*/
40
40
struct rockchip_pcie_ep {
41
41
struct rockchip_pcie rockchip;
···
325
325
}
326
326
}
327
327
328
-
static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
329
-
u8 intx)
328
+
static int rockchip_pcie_ep_send_intx_irq(struct rockchip_pcie_ep *ep, u8 fn,
329
+
u8 intx)
330
330
{
331
331
u16 cmd;
332
332
···
407
407
}
408
408
409
409
static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
410
-
enum pci_epc_irq_type type,
411
-
u16 interrupt_num)
410
+
unsigned int type, u16 interrupt_num)
412
411
{
413
412
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
414
413
415
414
switch (type) {
416
-
case PCI_EPC_IRQ_LEGACY:
417
-
return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
418
-
case PCI_EPC_IRQ_MSI:
415
+
case PCI_IRQ_INTX:
416
+
return rockchip_pcie_ep_send_intx_irq(ep, fn, 0);
417
+
case PCI_IRQ_MSI:
419
418
return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
420
419
default:
421
420
return -EINVAL;
+2
-2
drivers/pci/controller/pcie-rockchip-host.c
+2
-2
drivers/pci/controller/pcie-rockchip-host.c
···
505
505
return IRQ_HANDLED;
506
506
}
507
507
508
-
static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
508
+
static void rockchip_pcie_intx_handler(struct irq_desc *desc)
509
509
{
510
510
struct irq_chip *chip = irq_desc_get_chip(desc);
511
511
struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
···
553
553
return irq;
554
554
555
555
irq_set_chained_handler_and_data(irq,
556
-
rockchip_pcie_legacy_int_handler,
556
+
rockchip_pcie_intx_handler,
557
557
rockchip);
558
558
559
559
irq = platform_get_irq_byname(pdev, "client");
+5
-9
drivers/pci/controller/pcie-xilinx-dma-pl.c
+5
-9
drivers/pci/controller/pcie-xilinx-dma-pl.c
···
576
576
&intx_domain_ops, port);
577
577
if (!port->intx_domain) {
578
578
dev_err(dev, "Failed to get a INTx IRQ domain\n");
579
-
return PTR_ERR(port->intx_domain);
579
+
return -ENOMEM;
580
580
}
581
581
582
582
irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
···
635
635
err = devm_request_irq(dev, port->intx_irq, xilinx_pl_dma_pcie_intx_flow,
636
636
IRQF_SHARED | IRQF_NO_THREAD, NULL, port);
637
637
if (err) {
638
-
dev_err(dev, "Failed to request INTx IRQ %d\n", irq);
638
+
dev_err(dev, "Failed to request INTx IRQ %d\n", port->intx_irq);
639
639
return err;
640
640
}
641
641
642
642
err = devm_request_irq(dev, port->irq, xilinx_pl_dma_pcie_event_flow,
643
643
IRQF_SHARED | IRQF_NO_THREAD, NULL, port);
644
644
if (err) {
645
-
dev_err(dev, "Failed to request event IRQ %d\n", irq);
645
+
dev_err(dev, "Failed to request event IRQ %d\n", port->irq);
646
646
return err;
647
647
}
648
648
···
684
684
int ret;
685
685
686
686
port->msi.irq_msi0 = platform_get_irq_byname(pdev, "msi0");
687
-
if (port->msi.irq_msi0 <= 0) {
688
-
dev_err(dev, "Unable to find msi0 IRQ line\n");
687
+
if (port->msi.irq_msi0 <= 0)
689
688
return port->msi.irq_msi0;
690
-
}
691
689
692
690
ret = devm_request_irq(dev, port->msi.irq_msi0, xilinx_pl_dma_pcie_msi_handler_low,
693
691
IRQF_SHARED | IRQF_NO_THREAD, "xlnx-pcie-dma-pl",
···
696
698
}
697
699
698
700
port->msi.irq_msi1 = platform_get_irq_byname(pdev, "msi1");
699
-
if (port->msi.irq_msi1 <= 0) {
700
-
dev_err(dev, "Unable to find msi1 IRQ line\n");
701
+
if (port->msi.irq_msi1 <= 0)
701
702
return port->msi.irq_msi1;
702
-
}
703
703
704
704
ret = devm_request_irq(dev, port->msi.irq_msi1, xilinx_pl_dma_pcie_msi_handler_high,
705
705
IRQF_SHARED | IRQF_NO_THREAD, "xlnx-pcie-dma-pl",
+26
-26
drivers/pci/controller/pcie-xilinx-nwl.c
+26
-26
drivers/pci/controller/pcie-xilinx-nwl.c
···
166
166
int irq_intx;
167
167
int irq_misc;
168
168
struct nwl_msi msi;
169
-
struct irq_domain *legacy_irq_domain;
169
+
struct irq_domain *intx_irq_domain;
170
170
struct clk *clk;
171
171
raw_spinlock_t leg_mask_lock;
172
172
};
···
324
324
while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
325
325
MSGF_LEG_SR_MASKALL) != 0) {
326
326
for_each_set_bit(bit, &status, PCI_NUM_INTX)
327
-
generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
327
+
generic_handle_domain_irq(pcie->intx_irq_domain, bit);
328
328
}
329
329
330
330
chained_irq_exit(chip, desc);
···
364
364
chained_irq_exit(chip, desc);
365
365
}
366
366
367
-
static void nwl_mask_leg_irq(struct irq_data *data)
367
+
static void nwl_mask_intx_irq(struct irq_data *data)
368
368
{
369
369
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
370
370
unsigned long flags;
···
378
378
raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
379
379
}
380
380
381
-
static void nwl_unmask_leg_irq(struct irq_data *data)
381
+
static void nwl_unmask_intx_irq(struct irq_data *data)
382
382
{
383
383
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
384
384
unsigned long flags;
···
392
392
raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
393
393
}
394
394
395
-
static struct irq_chip nwl_leg_irq_chip = {
395
+
static struct irq_chip nwl_intx_irq_chip = {
396
396
.name = "nwl_pcie:legacy",
397
-
.irq_enable = nwl_unmask_leg_irq,
398
-
.irq_disable = nwl_mask_leg_irq,
399
-
.irq_mask = nwl_mask_leg_irq,
400
-
.irq_unmask = nwl_unmask_leg_irq,
397
+
.irq_enable = nwl_unmask_intx_irq,
398
+
.irq_disable = nwl_mask_intx_irq,
399
+
.irq_mask = nwl_mask_intx_irq,
400
+
.irq_unmask = nwl_unmask_intx_irq,
401
401
};
402
402
403
-
static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
404
-
irq_hw_number_t hwirq)
403
+
static int nwl_intx_map(struct irq_domain *domain, unsigned int irq,
404
+
irq_hw_number_t hwirq)
405
405
{
406
-
irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
406
+
irq_set_chip_and_handler(irq, &nwl_intx_irq_chip, handle_level_irq);
407
407
irq_set_chip_data(irq, domain->host_data);
408
408
irq_set_status_flags(irq, IRQ_LEVEL);
409
409
410
410
return 0;
411
411
}
412
412
413
-
static const struct irq_domain_ops legacy_domain_ops = {
414
-
.map = nwl_legacy_map,
413
+
static const struct irq_domain_ops intx_domain_ops = {
414
+
.map = nwl_intx_map,
415
415
.xlate = pci_irqd_intx_xlate,
416
416
};
417
417
···
525
525
{
526
526
struct device *dev = pcie->dev;
527
527
struct device_node *node = dev->of_node;
528
-
struct device_node *legacy_intc_node;
528
+
struct device_node *intc_node;
529
529
530
-
legacy_intc_node = of_get_next_child(node, NULL);
531
-
if (!legacy_intc_node) {
530
+
intc_node = of_get_next_child(node, NULL);
531
+
if (!intc_node) {
532
532
dev_err(dev, "No legacy intc node found\n");
533
533
return -EINVAL;
534
534
}
535
535
536
-
pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
537
-
PCI_NUM_INTX,
538
-
&legacy_domain_ops,
539
-
pcie);
540
-
of_node_put(legacy_intc_node);
541
-
if (!pcie->legacy_irq_domain) {
536
+
pcie->intx_irq_domain = irq_domain_add_linear(intc_node,
537
+
PCI_NUM_INTX,
538
+
&intx_domain_ops,
539
+
pcie);
540
+
of_node_put(intc_node);
541
+
if (!pcie->intx_irq_domain) {
542
542
dev_err(dev, "failed to create IRQ domain\n");
543
543
return -ENOMEM;
544
544
}
···
710
710
/* Enable all misc interrupts */
711
711
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
712
712
713
-
/* Disable all legacy interrupts */
713
+
/* Disable all INTX interrupts */
714
714
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
715
715
716
-
/* Clear pending legacy interrupts */
716
+
/* Clear pending INTX interrupts */
717
717
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
718
718
MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
719
719
720
-
/* Enable all legacy interrupts */
720
+
/* Enable all INTX interrupts */
721
721
nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
722
722
723
723
/* Enable the bridge config interrupt */
+3
-3
drivers/pci/controller/vmd.c
+3
-3
drivers/pci/controller/vmd.c
···
984
984
return -ENOMEM;
985
985
986
986
vmd->dev = dev;
987
-
vmd->instance = ida_simple_get(&vmd_instance_ida, 0, 0, GFP_KERNEL);
987
+
vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL);
988
988
if (vmd->instance < 0)
989
989
return vmd->instance;
990
990
···
1026
1026
return 0;
1027
1027
1028
1028
out_release_instance:
1029
-
ida_simple_remove(&vmd_instance_ida, vmd->instance);
1029
+
ida_free(&vmd_instance_ida, vmd->instance);
1030
1030
return err;
1031
1031
}
1032
1032
···
1048
1048
vmd_cleanup_srcu(vmd);
1049
1049
vmd_detach_resources(vmd);
1050
1050
vmd_remove_irq_domain(vmd);
1051
-
ida_simple_remove(&vmd_instance_ida, vmd->instance);
1051
+
ida_free(&vmd_instance_ida, vmd->instance);
1052
1052
}
1053
1053
1054
1054
static void vmd_shutdown(struct pci_dev *dev)
+3
-3
drivers/pci/endpoint/functions/pci-epf-mhi.c
+3
-3
drivers/pci/endpoint/functions/pci-epf-mhi.c
···
205
205
* MHI supplies 0 based MSI vectors but the API expects the vector
206
206
* number to start from 1, so we need to increment the vector by 1.
207
207
*/
208
-
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
208
+
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_IRQ_MSI,
209
209
vector + 1);
210
210
}
211
211
···
644
644
pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
645
645
}
646
646
647
-
static struct pci_epc_event_ops pci_epf_mhi_event_ops = {
647
+
static const struct pci_epc_event_ops pci_epf_mhi_event_ops = {
648
648
.core_init = pci_epf_mhi_core_init,
649
649
.link_up = pci_epf_mhi_link_up,
650
650
.link_down = pci_epf_mhi_link_down,
···
682
682
{},
683
683
};
684
684
685
-
static struct pci_epf_ops pci_epf_mhi_ops = {
685
+
static const struct pci_epf_ops pci_epf_mhi_ops = {
686
686
.unbind = pci_epf_mhi_unbind,
687
687
.bind = pci_epf_mhi_bind,
688
688
};
+3
-3
drivers/pci/endpoint/functions/pci-epf-ntb.c
+3
-3
drivers/pci/endpoint/functions/pci-epf-ntb.c
···
140
140
static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
141
141
{
142
142
enum pci_epc_interface_type type;
143
-
enum pci_epc_irq_type irq_type;
144
143
struct epf_ntb_epc *ntb_epc;
145
144
struct epf_ntb_ctrl *ctrl;
145
+
unsigned int irq_type;
146
146
struct pci_epc *epc;
147
147
u8 func_no, vfunc_no;
148
148
bool is_msix;
···
159
159
ctrl->link_status |= LINK_STATUS_UP;
160
160
else
161
161
ctrl->link_status &= ~LINK_STATUS_UP;
162
-
irq_type = is_msix ? PCI_EPC_IRQ_MSIX : PCI_EPC_IRQ_MSI;
162
+
irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
163
163
ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
164
164
if (ret) {
165
165
dev_err(&epc->dev,
···
2099
2099
return 0;
2100
2100
}
2101
2101
2102
-
static struct pci_epf_ops epf_ntb_ops = {
2102
+
static const struct pci_epf_ops epf_ntb_ops = {
2103
2103
.bind = epf_ntb_bind,
2104
2104
.unbind = epf_ntb_unbind,
2105
2105
.add_cfs = epf_ntb_add_cfs,
+8
-8
drivers/pci/endpoint/functions/pci-epf-test.c
+8
-8
drivers/pci/endpoint/functions/pci-epf-test.c
···
19
19
#include <linux/pci-epf.h>
20
20
#include <linux/pci_regs.h>
21
21
22
-
#define IRQ_TYPE_LEGACY 0
22
+
#define IRQ_TYPE_INTX 0
23
23
#define IRQ_TYPE_MSI 1
24
24
#define IRQ_TYPE_MSIX 2
25
25
26
-
#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
26
+
#define COMMAND_RAISE_INTX_IRQ BIT(0)
27
27
#define COMMAND_RAISE_MSI_IRQ BIT(1)
28
28
#define COMMAND_RAISE_MSIX_IRQ BIT(2)
29
29
#define COMMAND_READ BIT(3)
···
600
600
WRITE_ONCE(reg->status, status);
601
601
602
602
switch (reg->irq_type) {
603
-
case IRQ_TYPE_LEGACY:
603
+
case IRQ_TYPE_INTX:
604
604
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
605
-
PCI_EPC_IRQ_LEGACY, 0);
605
+
PCI_IRQ_INTX, 0);
606
606
break;
607
607
case IRQ_TYPE_MSI:
608
608
count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
···
612
612
return;
613
613
}
614
614
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
615
-
PCI_EPC_IRQ_MSI, reg->irq_number);
615
+
PCI_IRQ_MSI, reg->irq_number);
616
616
break;
617
617
case IRQ_TYPE_MSIX:
618
618
count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
···
622
622
return;
623
623
}
624
624
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
625
-
PCI_EPC_IRQ_MSIX, reg->irq_number);
625
+
PCI_IRQ_MSIX, reg->irq_number);
626
626
break;
627
627
default:
628
628
dev_err(dev, "Failed to raise IRQ, unknown type\n");
···
659
659
}
660
660
661
661
switch (command) {
662
-
case COMMAND_RAISE_LEGACY_IRQ:
662
+
case COMMAND_RAISE_INTX_IRQ:
663
663
case COMMAND_RAISE_MSI_IRQ:
664
664
case COMMAND_RAISE_MSIX_IRQ:
665
665
pci_epf_test_raise_irq(epf_test, reg);
···
973
973
return 0;
974
974
}
975
975
976
-
static struct pci_epf_ops ops = {
976
+
static const struct pci_epf_ops ops = {
977
977
.unbind = pci_epf_test_unbind,
978
978
.bind = pci_epf_test_bind,
979
979
};
+3
-6
drivers/pci/endpoint/functions/pci-epf-vntb.c
+3
-6
drivers/pci/endpoint/functions/pci-epf-vntb.c
···
1172
1172
func_no = ntb->epf->func_no;
1173
1173
vfunc_no = ntb->epf->vfunc_no;
1174
1174
1175
-
ret = pci_epc_raise_irq(ntb->epf->epc,
1176
-
func_no,
1177
-
vfunc_no,
1178
-
PCI_EPC_IRQ_MSI,
1179
-
interrupt_num + 1);
1175
+
ret = pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no,
1176
+
PCI_IRQ_MSI, interrupt_num + 1);
1180
1177
if (ret)
1181
1178
dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
1182
1179
···
1384
1387
}
1385
1388
1386
1389
// EPF driver probe
1387
-
static struct pci_epf_ops epf_ntb_ops = {
1390
+
static const struct pci_epf_ops epf_ntb_ops = {
1388
1391
.bind = epf_ntb_bind,
1389
1392
.unbind = epf_ntb_unbind,
1390
1393
.add_cfs = epf_ntb_add_cfs,
+3
-3
drivers/pci/endpoint/pci-epc-core.c
+3
-3
drivers/pci/endpoint/pci-epc-core.c
···
211
211
* @epc: the EPC device which has to interrupt the host
212
212
* @func_no: the physical endpoint function number in the EPC device
213
213
* @vfunc_no: the virtual endpoint function number in the physical function
214
-
* @type: specify the type of interrupt; legacy, MSI or MSI-X
214
+
* @type: specify the type of interrupt; INTX, MSI or MSI-X
215
215
* @interrupt_num: the MSI or MSI-X interrupt number with range (1-N)
216
216
*
217
-
* Invoke to raise an legacy, MSI or MSI-X interrupt
217
+
* Invoke to raise an INTX, MSI or MSI-X interrupt
218
218
*/
219
219
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
220
-
enum pci_epc_irq_type type, u16 interrupt_num)
220
+
unsigned int type, u16 interrupt_num)
221
221
{
222
222
int ret;
223
223
+5
-2
drivers/pci/iov.c
+5
-2
drivers/pci/iov.c
···
745
745
u16 ctrl, total;
746
746
struct pci_sriov *iov;
747
747
struct resource *res;
748
+
const char *res_name;
748
749
struct pci_dev *pdev;
749
750
750
751
pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
···
786
785
nres = 0;
787
786
for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
788
787
res = &dev->resource[i + PCI_IOV_RESOURCES];
788
+
res_name = pci_resource_name(dev, i + PCI_IOV_RESOURCES);
789
+
789
790
/*
790
791
* If it is already FIXED, don't change it, something
791
792
* (perhaps EA or header fixups) wants it this way.
···
805
802
}
806
803
iov->barsz[i] = resource_size(res);
807
804
res->end = res->start + resource_size(res) * total - 1;
808
-
pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
809
-
i, res, i, total);
805
+
pci_info(dev, "%s %pR: contains BAR %d for %d VFs\n",
806
+
res_name, res, i, total);
810
807
i += bar64;
811
808
nres++;
812
809
}
+74
-11
drivers/pci/pci.c
+74
-11
drivers/pci/pci.c
···
851
851
EXPORT_SYMBOL(pci_find_resource);
852
852
853
853
/**
854
+
* pci_resource_name - Return the name of the PCI resource
855
+
* @dev: PCI device to query
856
+
* @i: index of the resource
857
+
*
858
+
* Return the standard PCI resource (BAR) name according to their index.
859
+
*/
860
+
const char *pci_resource_name(struct pci_dev *dev, unsigned int i)
861
+
{
862
+
static const char * const bar_name[] = {
863
+
"BAR 0",
864
+
"BAR 1",
865
+
"BAR 2",
866
+
"BAR 3",
867
+
"BAR 4",
868
+
"BAR 5",
869
+
"ROM",
870
+
#ifdef CONFIG_PCI_IOV
871
+
"VF BAR 0",
872
+
"VF BAR 1",
873
+
"VF BAR 2",
874
+
"VF BAR 3",
875
+
"VF BAR 4",
876
+
"VF BAR 5",
877
+
#endif
878
+
"bridge window", /* "io" included in %pR */
879
+
"bridge window", /* "mem" included in %pR */
880
+
"bridge window", /* "mem pref" included in %pR */
881
+
};
882
+
static const char * const cardbus_name[] = {
883
+
"BAR 1",
884
+
"unknown",
885
+
"unknown",
886
+
"unknown",
887
+
"unknown",
888
+
"unknown",
889
+
#ifdef CONFIG_PCI_IOV
890
+
"unknown",
891
+
"unknown",
892
+
"unknown",
893
+
"unknown",
894
+
"unknown",
895
+
"unknown",
896
+
#endif
897
+
"CardBus bridge window 0", /* I/O */
898
+
"CardBus bridge window 1", /* I/O */
899
+
"CardBus bridge window 0", /* mem */
900
+
"CardBus bridge window 1", /* mem */
901
+
};
902
+
903
+
if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS &&
904
+
i < ARRAY_SIZE(cardbus_name))
905
+
return cardbus_name[i];
906
+
907
+
if (i < ARRAY_SIZE(bar_name))
908
+
return bar_name[i];
909
+
910
+
return "unknown";
911
+
}
912
+
913
+
/**
854
914
* pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
855
915
* @dev: the PCI device to operate on
856
916
* @pos: config space offset of status word
···
3359
3299
static int pci_ea_read(struct pci_dev *dev, int offset)
3360
3300
{
3361
3301
struct resource *res;
3302
+
const char *res_name;
3362
3303
int ent_size, ent_offset = offset;
3363
3304
resource_size_t start, end;
3364
3305
unsigned long flags;
···
3389
3328
goto out;
3390
3329
3391
3330
res = pci_ea_get_resource(dev, bei, prop);
3331
+
res_name = pci_resource_name(dev, bei);
3392
3332
if (!res) {
3393
3333
pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3394
3334
goto out;
···
3463
3401
res->flags = flags;
3464
3402
3465
3403
if (bei <= PCI_EA_BEI_BAR5)
3466
-
pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3467
-
bei, res, prop);
3404
+
pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3405
+
res_name, res, prop);
3468
3406
else if (bei == PCI_EA_BEI_ROM)
3469
-
pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3470
-
res, prop);
3407
+
pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3408
+
res_name, res, prop);
3471
3409
else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3472
-
pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3473
-
bei - PCI_EA_BEI_VF_BAR0, res, prop);
3410
+
pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3411
+
res_name, res, prop);
3474
3412
else
3475
-
pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3413
+
pci_info(dev, "BEI %d %pR: from Enhanced Allocation, properties %#02x\n",
3476
3414
bei, res, prop);
3477
3415
3478
3416
out:
···
6760
6698
resource_size_t align, bool resize)
6761
6699
{
6762
6700
struct resource *r = &dev->resource[bar];
6701
+
const char *r_name = pci_resource_name(dev, bar);
6763
6702
resource_size_t size;
6764
6703
6765
6704
if (!(r->flags & IORESOURCE_MEM))
6766
6705
return;
6767
6706
6768
6707
if (r->flags & IORESOURCE_PCI_FIXED) {
6769
-
pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6770
-
bar, r, (unsigned long long)align);
6708
+
pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n",
6709
+
r_name, r, (unsigned long long)align);
6771
6710
return;
6772
6711
}
6773
6712
···
6804
6741
* devices and we use the second.
6805
6742
*/
6806
6743
6807
-
pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6808
-
bar, r, (unsigned long long)align);
6744
+
pci_info(dev, "%s %pR: requesting alignment to %#llx\n",
6745
+
r_name, r, (unsigned long long)align);
6809
6746
6810
6747
if (resize) {
6811
6748
r->start = 0;
+3
-1
drivers/pci/pci.h
+3
-1
drivers/pci/pci.h
···
255
255
struct list_head *fail_head);
256
256
bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
257
257
258
+
const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
259
+
258
260
void pci_reassigndev_resource_alignment(struct pci_dev *dev);
259
261
void pci_disable_bridge_window(struct pci_dev *dev);
260
262
struct pci_bus *pci_bus_get(struct pci_bus *bus);
···
274
272
275
273
/* PCIe speed to Mb/s reduced by encoding overhead */
276
274
#define PCIE_SPEED2MBS_ENC(speed) \
277
-
((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
275
+
((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
278
276
(speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
279
277
(speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
280
278
(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
+13
-8
drivers/pci/pcie/aer.c
+13
-8
drivers/pci/pcie/aer.c
···
41
41
#define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
42
42
43
43
struct aer_err_source {
44
-
unsigned int status;
45
-
unsigned int id;
44
+
u32 status; /* PCI_ERR_ROOT_STATUS */
45
+
u32 id; /* PCI_ERR_ROOT_ERR_SRC */
46
46
};
47
47
48
48
struct aer_rpc {
···
435
435
/*
436
436
* AER error strings
437
437
*/
438
-
static const char *aer_error_severity_string[] = {
439
-
"Uncorrected (Non-Fatal)",
440
-
"Uncorrected (Fatal)",
441
-
"Corrected"
438
+
static const char * const aer_error_severity_string[] = {
439
+
"Uncorrectable (Non-Fatal)",
440
+
"Uncorrectable (Fatal)",
441
+
"Correctable"
442
442
};
443
443
444
444
static const char *aer_error_layer[] = {
···
740
740
u8 bus = info->id >> 8;
741
741
u8 devfn = info->id & 0xff;
742
742
743
-
pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
743
+
pci_info(dev, "%s%s error message received from %04x:%02x:%02x.%d\n",
744
744
info->multi_error_valid ? "Multiple " : "",
745
745
aer_error_severity_string[info->severity],
746
746
pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
···
929
929
pci_walk_bus(parent->subordinate, find_device_iter, e_info);
930
930
931
931
if (!e_info->error_dev_num) {
932
-
pci_info(parent, "can't find device of ID%04x\n", e_info->id);
932
+
u8 bus = e_info->id >> 8;
933
+
u8 devfn = e_info->id & 0xff;
934
+
935
+
pci_info(parent, "found no error details for %04x:%02x:%02x.%d\n",
936
+
pci_domain_nr(parent->bus), bus, PCI_SLOT(devfn),
937
+
PCI_FUNC(devfn));
933
938
return false;
934
939
}
935
940
return true;
+134
-84
drivers/pci/probe.c
+134
-84
drivers/pci/probe.c
···
180
180
u64 l64, sz64, mask64;
181
181
u16 orig_cmd;
182
182
struct pci_bus_region region, inverted_region;
183
+
const char *res_name = pci_resource_name(dev, res - dev->resource);
183
184
184
185
mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185
186
···
255
254
256
255
sz64 = pci_size(l64, sz64, mask64);
257
256
if (!sz64) {
258
-
pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259
-
pos);
257
+
pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name);
260
258
goto fail;
261
259
}
262
260
···
265
265
res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266
266
res->start = 0;
267
267
res->end = 0;
268
-
pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269
-
pos, (unsigned long long)sz64);
268
+
pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n",
269
+
res_name, (unsigned long long)sz64);
270
270
goto out;
271
271
}
272
272
···
275
275
res->flags |= IORESOURCE_UNSET;
276
276
res->start = 0;
277
277
res->end = sz64 - 1;
278
-
pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279
-
pos, (unsigned long long)l64);
278
+
pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n",
279
+
res_name, (unsigned long long)l64);
280
280
goto out;
281
281
}
282
282
}
···
302
302
res->flags |= IORESOURCE_UNSET;
303
303
res->start = 0;
304
304
res->end = region.end - region.start;
305
-
pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306
-
pos, (unsigned long long)region.start);
305
+
pci_info(dev, "%s: initial BAR value %#010llx invalid\n",
306
+
res_name, (unsigned long long)region.start);
307
307
}
308
308
309
309
goto out;
···
313
313
res->flags = 0;
314
314
out:
315
315
if (res->flags)
316
-
pci_info(dev, "reg 0x%x: %pR\n", pos, res);
316
+
pci_info(dev, "%s %pR\n", res_name, res);
317
317
318
318
return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319
319
}
···
344
344
}
345
345
}
346
346
347
-
static void pci_read_bridge_windows(struct pci_dev *bridge)
347
+
static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res,
348
+
bool log)
348
349
{
349
-
u16 io;
350
-
u32 pmem, tmp;
351
-
352
-
pci_read_config_word(bridge, PCI_IO_BASE, &io);
353
-
if (!io) {
354
-
pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355
-
pci_read_config_word(bridge, PCI_IO_BASE, &io);
356
-
pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357
-
}
358
-
if (io)
359
-
bridge->io_window = 1;
360
-
361
-
/*
362
-
* DECchip 21050 pass 2 errata: the bridge may miss an address
363
-
* disconnect boundary by one PCI data phase. Workaround: do not
364
-
* use prefetching on this device.
365
-
*/
366
-
if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367
-
return;
368
-
369
-
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370
-
if (!pmem) {
371
-
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372
-
0xffe0fff0);
373
-
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374
-
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375
-
}
376
-
if (!pmem)
377
-
return;
378
-
379
-
bridge->pref_window = 1;
380
-
381
-
if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
-
383
-
/*
384
-
* Bridge claims to have a 64-bit prefetchable memory
385
-
* window; verify that the upper bits are actually
386
-
* writable.
387
-
*/
388
-
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389
-
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390
-
0xffffffff);
391
-
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392
-
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393
-
if (tmp)
394
-
bridge->pref_64_window = 1;
395
-
}
396
-
}
397
-
398
-
static void pci_read_bridge_io(struct pci_bus *child)
399
-
{
400
-
struct pci_dev *dev = child->self;
401
350
u8 io_base_lo, io_limit_lo;
402
351
unsigned long io_mask, io_granularity, base, limit;
403
352
struct pci_bus_region region;
404
-
struct resource *res;
405
353
406
354
io_mask = PCI_IO_RANGE_MASK;
407
355
io_granularity = 0x1000;
···
359
411
io_granularity = 0x400;
360
412
}
361
413
362
-
res = child->resource[0];
363
414
pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
364
415
pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
365
416
base = (io_base_lo & io_mask) << 8;
···
378
431
region.start = base;
379
432
region.end = limit + io_granularity - 1;
380
433
pcibios_bus_to_resource(dev->bus, res, ®ion);
381
-
pci_info(dev, " bridge window %pR\n", res);
434
+
if (log)
435
+
pci_info(dev, " bridge window %pR\n", res);
382
436
}
383
437
}
384
438
385
-
static void pci_read_bridge_mmio(struct pci_bus *child)
439
+
static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res,
440
+
bool log)
386
441
{
387
-
struct pci_dev *dev = child->self;
388
442
u16 mem_base_lo, mem_limit_lo;
389
443
unsigned long base, limit;
390
444
struct pci_bus_region region;
391
-
struct resource *res;
392
445
393
-
res = child->resource[1];
394
446
pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
395
447
pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
396
448
base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
···
399
453
region.start = base;
400
454
region.end = limit + 0xfffff;
401
455
pcibios_bus_to_resource(dev->bus, res, ®ion);
402
-
pci_info(dev, " bridge window %pR\n", res);
456
+
if (log)
457
+
pci_info(dev, " bridge window %pR\n", res);
403
458
}
404
459
}
405
460
406
-
static void pci_read_bridge_mmio_pref(struct pci_bus *child)
461
+
static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,
462
+
bool log)
407
463
{
408
-
struct pci_dev *dev = child->self;
409
464
u16 mem_base_lo, mem_limit_lo;
410
465
u64 base64, limit64;
411
466
pci_bus_addr_t base, limit;
412
467
struct pci_bus_region region;
413
-
struct resource *res;
414
468
415
-
res = child->resource[2];
416
469
pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
417
470
pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
418
471
base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
···
451
506
region.start = base;
452
507
region.end = limit + 0xfffff;
453
508
pcibios_bus_to_resource(dev->bus, res, ®ion);
454
-
pci_info(dev, " bridge window %pR\n", res);
509
+
if (log)
510
+
pci_info(dev, " bridge window %pR\n", res);
455
511
}
512
+
}
513
+
514
+
static void pci_read_bridge_windows(struct pci_dev *bridge)
515
+
{
516
+
u32 buses;
517
+
u16 io;
518
+
u32 pmem, tmp;
519
+
struct resource res;
520
+
521
+
pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);
522
+
res.flags = IORESOURCE_BUS;
523
+
res.start = (buses >> 8) & 0xff;
524
+
res.end = (buses >> 16) & 0xff;
525
+
pci_info(bridge, "PCI bridge to %pR%s\n", &res,
526
+
bridge->transparent ? " (subtractive decode)" : "");
527
+
528
+
pci_read_config_word(bridge, PCI_IO_BASE, &io);
529
+
if (!io) {
530
+
pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
531
+
pci_read_config_word(bridge, PCI_IO_BASE, &io);
532
+
pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
533
+
}
534
+
if (io) {
535
+
bridge->io_window = 1;
536
+
pci_read_bridge_io(bridge, &res, true);
537
+
}
538
+
539
+
pci_read_bridge_mmio(bridge, &res, true);
540
+
541
+
/*
542
+
* DECchip 21050 pass 2 errata: the bridge may miss an address
543
+
* disconnect boundary by one PCI data phase. Workaround: do not
544
+
* use prefetching on this device.
545
+
*/
546
+
if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
547
+
return;
548
+
549
+
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
550
+
if (!pmem) {
551
+
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
552
+
0xffe0fff0);
553
+
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
554
+
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
555
+
}
556
+
if (!pmem)
557
+
return;
558
+
559
+
bridge->pref_window = 1;
560
+
561
+
if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
562
+
563
+
/*
564
+
* Bridge claims to have a 64-bit prefetchable memory
565
+
* window; verify that the upper bits are actually
566
+
* writable.
567
+
*/
568
+
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
569
+
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
570
+
0xffffffff);
571
+
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
572
+
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
573
+
if (tmp)
574
+
bridge->pref_64_window = 1;
575
+
}
576
+
577
+
pci_read_bridge_mmio_pref(bridge, &res, true);
456
578
}
457
579
458
580
void pci_read_bridge_bases(struct pci_bus *child)
···
539
527
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
540
528
child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
541
529
542
-
pci_read_bridge_io(child);
543
-
pci_read_bridge_mmio(child);
544
-
pci_read_bridge_mmio_pref(child);
530
+
pci_read_bridge_io(child->self, child->resource[0], false);
531
+
pci_read_bridge_mmio(child->self, child->resource[1], false);
532
+
pci_read_bridge_mmio_pref(child->self, child->resource[2], false);
545
533
546
534
if (dev->transparent) {
547
535
pci_bus_for_each_resource(child->parent, res) {
···
1829
1817
value, 256, false);
1830
1818
}
1831
1819
1820
+
static const char *pci_type_str(struct pci_dev *dev)
1821
+
{
1822
+
static const char * const str[] = {
1823
+
"PCIe Endpoint",
1824
+
"PCIe Legacy Endpoint",
1825
+
"PCIe unknown",
1826
+
"PCIe unknown",
1827
+
"PCIe Root Port",
1828
+
"PCIe Switch Upstream Port",
1829
+
"PCIe Switch Downstream Port",
1830
+
"PCIe to PCI/PCI-X bridge",
1831
+
"PCI/PCI-X to PCIe bridge",
1832
+
"PCIe Root Complex Integrated Endpoint",
1833
+
"PCIe Root Complex Event Collector",
1834
+
};
1835
+
int type;
1836
+
1837
+
if (pci_is_pcie(dev)) {
1838
+
type = pci_pcie_type(dev);
1839
+
if (type < ARRAY_SIZE(str))
1840
+
return str[type];
1841
+
1842
+
return "PCIe unknown";
1843
+
}
1844
+
1845
+
switch (dev->hdr_type) {
1846
+
case PCI_HEADER_TYPE_NORMAL:
1847
+
return "conventional PCI endpoint";
1848
+
case PCI_HEADER_TYPE_BRIDGE:
1849
+
return "conventional PCI bridge";
1850
+
case PCI_HEADER_TYPE_CARDBUS:
1851
+
return "CardBus bridge";
1852
+
default:
1853
+
return "conventional PCI";
1854
+
}
1855
+
}
1856
+
1832
1857
/**
1833
1858
* pci_setup_device - Fill in class and map information of a device
1834
1859
* @dev: the device structure to fill
···
1936
1887
1937
1888
pci_set_removable(dev);
1938
1889
1939
-
pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1940
-
dev->vendor, dev->device, dev->hdr_type, dev->class);
1890
+
pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n",
1891
+
dev->vendor, dev->device, dev->hdr_type, dev->class,
1892
+
pci_type_str(dev));
1941
1893
1942
1894
/* Device class may be changed after fixup */
1943
1895
class = dev->class >> 8;
···
1979
1929
res = &dev->resource[0];
1980
1930
res->flags = LEGACY_IO_RESOURCE;
1981
1931
pcibios_bus_to_resource(dev->bus, res, ®ion);
1982
-
pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1932
+
pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n",
1983
1933
res);
1984
1934
region.start = 0x3F6;
1985
1935
region.end = 0x3F6;
1986
1936
res = &dev->resource[1];
1987
1937
res->flags = LEGACY_IO_RESOURCE;
1988
1938
pcibios_bus_to_resource(dev->bus, res, ®ion);
1989
-
pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1939
+
pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n",
1990
1940
res);
1991
1941
}
1992
1942
if ((progif & 4) == 0) {
···
1995
1945
res = &dev->resource[2];
1996
1946
res->flags = LEGACY_IO_RESOURCE;
1997
1947
pcibios_bus_to_resource(dev->bus, res, ®ion);
1998
-
pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1948
+
pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n",
1999
1949
res);
2000
1950
region.start = 0x376;
2001
1951
region.end = 0x376;
2002
1952
res = &dev->resource[3];
2003
1953
res->flags = LEGACY_IO_RESOURCE;
2004
1954
pcibios_bus_to_resource(dev->bus, res, ®ion);
2005
-
pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1955
+
pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n",
2006
1956
res);
2007
1957
}
2008
1958
}
+24
-10
drivers/pci/quirks.c
+24
-10
drivers/pci/quirks.c
···
570
570
571
571
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
572
572
struct resource *r = &dev->resource[i];
573
+
const char *r_name = pci_resource_name(dev, i);
573
574
574
575
if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
575
576
r->end = PAGE_SIZE - 1;
576
577
r->start = 0;
577
578
r->flags |= IORESOURCE_UNSET;
578
-
pci_info(dev, "expanded BAR %d to page size: %pR\n",
579
-
i, r);
579
+
pci_info(dev, "%s %pR: expanded to page size\n",
580
+
r_name, r);
580
581
}
581
582
}
582
583
}
···
606
605
u32 region;
607
606
struct pci_bus_region bus_region;
608
607
struct resource *res = dev->resource + pos;
608
+
const char *res_name = pci_resource_name(dev, pos);
609
609
610
610
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
611
611
···
624
622
bus_region.end = region + size - 1;
625
623
pcibios_bus_to_resource(dev->bus, res, &bus_region);
626
624
627
-
pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
628
-
name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
625
+
pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name);
629
626
}
630
627
631
628
/*
···
671
670
bus_region.end = region + size - 1;
672
671
pcibios_bus_to_resource(dev->bus, res, &bus_region);
673
672
673
+
/*
674
+
* "res" is typically a bridge window resource that's not being
675
+
* used for a bridge window, so it's just a place to stash this
676
+
* non-standard resource. Printing "nr" or pci_resource_name() of
677
+
* it doesn't really make sense.
678
+
*/
674
679
if (!pci_claim_resource(dev, nr))
675
680
pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
676
681
}
···
709
702
{
710
703
u32 class = pdev->class;
711
704
712
-
/* Use "USB Device (not host controller)" class */
713
-
pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
714
-
pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
715
-
class, pdev->class);
705
+
if (class != PCI_CLASS_SERIAL_USB_DEVICE) {
706
+
/* Use "USB Device (not host controller)" class */
707
+
pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
708
+
pci_info(pdev,
709
+
"PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
710
+
class, pdev->class);
711
+
}
716
712
}
717
713
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
718
714
quirk_amd_dwc_class);
···
4722
4712
* But the implementation could block peer-to-peer transactions between them
4723
4713
* and provide ACS-like functionality.
4724
4714
*/
4725
-
static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4715
+
static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4726
4716
{
4727
4717
if (!pci_is_pcie(dev) ||
4728
4718
((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4729
4719
(pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4730
4720
return -ENOTTY;
4731
4721
4722
+
/*
4723
+
* Future Zhaoxin Root Ports and Switch Downstream Ports will
4724
+
* implement ACS capability in accordance with the PCIe Spec.
4725
+
*/
4732
4726
switch (dev->device) {
4733
4727
case 0x0710 ... 0x071e:
4734
4728
case 0x0721:
4735
-
case 0x0723 ... 0x0732:
4729
+
case 0x0723 ... 0x0752:
4736
4730
return pci_acs_ctrl_enabled(acs_flags,
4737
4731
PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4738
4732
}
+20
-10
drivers/pci/setup-bus.c
+20
-10
drivers/pci/setup-bus.c
···
213
213
struct list_head *head)
214
214
{
215
215
struct resource *res;
216
+
const char *res_name;
216
217
struct pci_dev_resource *add_res, *tmp;
217
218
struct pci_dev_resource *dev_res;
218
219
resource_size_t add_size, align;
···
223
222
bool found_match = false;
224
223
225
224
res = add_res->res;
225
+
226
226
/* Skip resource that has been reset */
227
227
if (!res->flags)
228
228
goto out;
···
239
237
continue;
240
238
241
239
idx = res - &add_res->dev->resource[0];
240
+
res_name = pci_resource_name(add_res->dev, idx);
242
241
add_size = add_res->add_size;
243
242
align = add_res->min_align;
244
243
if (!resource_size(res)) {
···
252
249
(IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
253
250
if (pci_reassign_resource(add_res->dev, idx,
254
251
add_size, align))
255
-
pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
256
-
(unsigned long long) add_size, idx,
257
-
res);
252
+
pci_info(add_res->dev, "%s %pR: failed to add %llx\n",
253
+
res_name, res,
254
+
(unsigned long long) add_size);
258
255
}
259
256
out:
260
257
list_del(&add_res->list);
···
574
571
static void pci_setup_bridge_io(struct pci_dev *bridge)
575
572
{
576
573
struct resource *res;
574
+
const char *res_name;
577
575
struct pci_bus_region region;
578
576
unsigned long io_mask;
579
577
u8 io_base_lo, io_limit_lo;
···
587
583
588
584
/* Set up the top and bottom of the PCI I/O segment for this bus */
589
585
res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
586
+
res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW);
590
587
pcibios_resource_to_bus(bridge->bus, ®ion, res);
591
588
if (res->flags & IORESOURCE_IO) {
592
589
pci_read_config_word(bridge, PCI_IO_BASE, &l);
···
596
591
l = ((u16) io_limit_lo << 8) | io_base_lo;
597
592
/* Set up upper 16 bits of I/O base/limit */
598
593
io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
599
-
pci_info(bridge, " bridge window %pR\n", res);
594
+
pci_info(bridge, " %s %pR\n", res_name, res);
600
595
} else {
601
596
/* Clear upper 16 bits of I/O base/limit */
602
597
io_upper16 = 0;
···
613
608
static void pci_setup_bridge_mmio(struct pci_dev *bridge)
614
609
{
615
610
struct resource *res;
611
+
const char *res_name;
616
612
struct pci_bus_region region;
617
613
u32 l;
618
614
619
615
/* Set up the top and bottom of the PCI Memory segment for this bus */
620
616
res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
617
+
res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW);
621
618
pcibios_resource_to_bus(bridge->bus, ®ion, res);
622
619
if (res->flags & IORESOURCE_MEM) {
623
620
l = (region.start >> 16) & 0xfff0;
624
621
l |= region.end & 0xfff00000;
625
-
pci_info(bridge, " bridge window %pR\n", res);
622
+
pci_info(bridge, " %s %pR\n", res_name, res);
626
623
} else {
627
624
l = 0x0000fff0;
628
625
}
···
634
627
static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
635
628
{
636
629
struct resource *res;
630
+
const char *res_name;
637
631
struct pci_bus_region region;
638
632
u32 l, bu, lu;
639
633
···
648
640
/* Set up PREF base/limit */
649
641
bu = lu = 0;
650
642
res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
643
+
res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW);
651
644
pcibios_resource_to_bus(bridge->bus, ®ion, res);
652
645
if (res->flags & IORESOURCE_PREFETCH) {
653
646
l = (region.start >> 16) & 0xfff0;
···
657
648
bu = upper_32_bits(region.start);
658
649
lu = upper_32_bits(region.end);
659
650
}
660
-
pci_info(bridge, " bridge window %pR\n", res);
651
+
pci_info(bridge, " %s %pR\n", res_name, res);
661
652
} else {
662
653
l = 0x0000fff0;
663
654
}
···
1022
1013
int i;
1023
1014
1024
1015
pci_dev_for_each_resource(dev, r, i) {
1016
+
const char *r_name = pci_resource_name(dev, i);
1025
1017
resource_size_t r_size;
1026
1018
1027
1019
if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
···
1053
1043
if (order < 0)
1054
1044
order = 0;
1055
1045
if (order >= ARRAY_SIZE(aligns)) {
1056
-
pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1057
-
i, r, (unsigned long long) align);
1046
+
pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n",
1047
+
r_name, r, (unsigned long long) align);
1058
1048
r->flags = 0;
1059
1049
continue;
1060
1050
}
···
2245
2235
for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2246
2236
i++) {
2247
2237
struct resource *res = &bridge->resource[i];
2238
+
const char *res_name = pci_resource_name(bridge, i);
2248
2239
2249
2240
if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2250
2241
continue;
···
2258
2247
if (ret)
2259
2248
goto cleanup;
2260
2249
2261
-
pci_info(bridge, "BAR %d: releasing %pR\n",
2262
-
i, res);
2250
+
pci_info(bridge, "%s %pR: releasing\n", res_name, res);
2263
2251
2264
2252
if (res->parent)
2265
2253
release_resource(res);
+40
-32
drivers/pci/setup-res.c
+40
-32
drivers/pci/setup-res.c
···
30
30
u32 new, check, mask;
31
31
int reg;
32
32
struct resource *res = dev->resource + resno;
33
+
const char *res_name = pci_resource_name(dev, resno);
33
34
34
35
/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
35
36
if (dev->is_virtfn)
···
105
104
pci_read_config_dword(dev, reg, &check);
106
105
107
106
if ((new ^ check) & mask) {
108
-
pci_err(dev, "BAR %d: error updating (%#010x != %#010x)\n",
109
-
resno, new, check);
107
+
pci_err(dev, "%s: error updating (%#010x != %#010x)\n",
108
+
res_name, new, check);
110
109
}
111
110
112
111
if (res->flags & IORESOURCE_MEM_64) {
···
114
113
pci_write_config_dword(dev, reg + 4, new);
115
114
pci_read_config_dword(dev, reg + 4, &check);
116
115
if (check != new) {
117
-
pci_err(dev, "BAR %d: error updating (high %#010x != %#010x)\n",
118
-
resno, new, check);
116
+
pci_err(dev, "%s: error updating (high %#010x != %#010x)\n",
117
+
res_name, new, check);
119
118
}
120
119
}
121
120
···
136
135
int pci_claim_resource(struct pci_dev *dev, int resource)
137
136
{
138
137
struct resource *res = &dev->resource[resource];
138
+
const char *res_name = pci_resource_name(dev, resource);
139
139
struct resource *root, *conflict;
140
140
141
141
if (res->flags & IORESOURCE_UNSET) {
142
-
pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
143
-
resource, res);
142
+
pci_info(dev, "%s %pR: can't claim; no address assigned\n",
143
+
res_name, res);
144
144
return -EINVAL;
145
145
}
146
146
···
155
153
156
154
root = pci_find_parent_resource(dev, res);
157
155
if (!root) {
158
-
pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
159
-
resource, res);
156
+
pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n",
157
+
res_name, res);
160
158
res->flags |= IORESOURCE_UNSET;
161
159
return -EINVAL;
162
160
}
163
161
164
162
conflict = request_resource_conflict(root, res);
165
163
if (conflict) {
166
-
pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
167
-
resource, res, conflict->name, conflict);
164
+
pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n",
165
+
res_name, res, conflict->name, conflict);
168
166
res->flags |= IORESOURCE_UNSET;
169
167
return -EBUSY;
170
168
}
···
203
201
{
204
202
struct resource *root, *conflict;
205
203
resource_size_t fw_addr, start, end;
204
+
const char *res_name = pci_resource_name(dev, resno);
206
205
207
206
fw_addr = pcibios_retrieve_fw_addr(dev, resno);
208
207
if (!fw_addr)
···
234
231
root = &iomem_resource;
235
232
}
236
233
237
-
pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
238
-
resno, res);
234
+
pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res);
239
235
conflict = request_resource_conflict(root, res);
240
236
if (conflict) {
241
-
pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
242
-
resno, res, conflict->name, conflict);
237
+
pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res,
238
+
conflict->name, conflict);
243
239
res->start = start;
244
240
res->end = end;
245
241
res->flags |= IORESOURCE_UNSET;
···
327
325
int pci_assign_resource(struct pci_dev *dev, int resno)
328
326
{
329
327
struct resource *res = dev->resource + resno;
328
+
const char *res_name = pci_resource_name(dev, resno);
330
329
resource_size_t align, size;
331
330
int ret;
332
331
···
337
334
res->flags |= IORESOURCE_UNSET;
338
335
align = pci_resource_alignment(dev, res);
339
336
if (!align) {
340
-
pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
341
-
resno, res);
337
+
pci_info(dev, "%s %pR: can't assign; bogus alignment\n",
338
+
res_name, res);
342
339
return -EINVAL;
343
340
}
344
341
···
351
348
* working, which is better than just leaving it disabled.
352
349
*/
353
350
if (ret < 0) {
354
-
pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
351
+
pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res);
355
352
ret = pci_revert_fw_address(res, dev, resno, size);
356
353
}
357
354
358
355
if (ret < 0) {
359
-
pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
356
+
pci_info(dev, "%s %pR: failed to assign\n", res_name, res);
360
357
return ret;
361
358
}
362
359
363
360
res->flags &= ~IORESOURCE_UNSET;
364
361
res->flags &= ~IORESOURCE_STARTALIGN;
365
-
pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
362
+
pci_info(dev, "%s %pR: assigned\n", res_name, res);
366
363
if (resno < PCI_BRIDGE_RESOURCES)
367
364
pci_update_resource(dev, resno);
368
365
···
370
367
}
371
368
EXPORT_SYMBOL(pci_assign_resource);
372
369
373
-
int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
374
-
resource_size_t min_align)
370
+
int pci_reassign_resource(struct pci_dev *dev, int resno,
371
+
resource_size_t addsize, resource_size_t min_align)
375
372
{
376
373
struct resource *res = dev->resource + resno;
374
+
const char *res_name = pci_resource_name(dev, resno);
377
375
unsigned long flags;
378
376
resource_size_t new_size;
379
377
int ret;
···
385
381
flags = res->flags;
386
382
res->flags |= IORESOURCE_UNSET;
387
383
if (!res->parent) {
388
-
pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
389
-
resno, res);
384
+
pci_info(dev, "%s %pR: can't reassign; unassigned resource\n",
385
+
res_name, res);
390
386
return -EINVAL;
391
387
}
392
388
···
395
391
ret = _pci_assign_resource(dev, resno, new_size, min_align);
396
392
if (ret) {
397
393
res->flags = flags;
398
-
pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
399
-
resno, res, (unsigned long long) addsize);
394
+
pci_info(dev, "%s %pR: failed to expand by %#llx\n",
395
+
res_name, res, (unsigned long long) addsize);
400
396
return ret;
401
397
}
402
398
403
399
res->flags &= ~IORESOURCE_UNSET;
404
400
res->flags &= ~IORESOURCE_STARTALIGN;
405
-
pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
406
-
resno, res, (unsigned long long) addsize);
401
+
pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n",
402
+
res_name, res, (unsigned long long) addsize);
407
403
if (resno < PCI_BRIDGE_RESOURCES)
408
404
pci_update_resource(dev, resno);
409
405
···
413
409
void pci_release_resource(struct pci_dev *dev, int resno)
414
410
{
415
411
struct resource *res = dev->resource + resno;
412
+
const char *res_name = pci_resource_name(dev, resno);
416
413
417
-
pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
414
+
pci_info(dev, "%s %pR: releasing\n", res_name, res);
418
415
419
416
if (!res->parent)
420
417
return;
···
485
480
u16 cmd, old_cmd;
486
481
int i;
487
482
struct resource *r;
483
+
const char *r_name;
488
484
489
485
pci_read_config_word(dev, PCI_COMMAND, &cmd);
490
486
old_cmd = cmd;
···
494
488
if (!(mask & (1 << i)))
495
489
continue;
496
490
491
+
r_name = pci_resource_name(dev, i);
492
+
497
493
if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
498
494
continue;
499
495
if ((i == PCI_ROM_RESOURCE) &&
···
503
495
continue;
504
496
505
497
if (r->flags & IORESOURCE_UNSET) {
506
-
pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
507
-
i, r);
498
+
pci_err(dev, "%s %pR: not assigned; can't enable device\n",
499
+
r_name, r);
508
500
return -EINVAL;
509
501
}
510
502
511
503
if (!r->parent) {
512
-
pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
513
-
i, r);
504
+
pci_err(dev, "%s %pR: not claimed; can't enable device\n",
505
+
r_name, r);
514
506
return -EINVAL;
515
507
}
516
508
+17
-8
drivers/pci/switch/switchtec.c
+17
-8
drivers/pci/switch/switchtec.c
···
1308
1308
{
1309
1309
struct switchtec_dev *stdev = to_stdev(dev);
1310
1310
1311
-
if (stdev->dma_mrpc) {
1312
-
iowrite32(0, &stdev->mmio_mrpc->dma_en);
1313
-
flush_wc_buf(stdev);
1314
-
writeq(0, &stdev->mmio_mrpc->dma_addr);
1315
-
dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
1316
-
stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
1317
-
}
1318
1311
kfree(stdev);
1319
1312
}
1320
1313
···
1351
1358
return ERR_PTR(-ENOMEM);
1352
1359
1353
1360
stdev->alive = true;
1354
-
stdev->pdev = pdev;
1361
+
stdev->pdev = pci_dev_get(pdev);
1355
1362
INIT_LIST_HEAD(&stdev->mrpc_queue);
1356
1363
mutex_init(&stdev->mrpc_mutex);
1357
1364
stdev->mrpc_busy = 0;
···
1384
1391
return stdev;
1385
1392
1386
1393
err_put:
1394
+
pci_dev_put(stdev->pdev);
1387
1395
put_device(&stdev->dev);
1388
1396
return ERR_PTR(rc);
1389
1397
}
···
1638
1644
return 0;
1639
1645
}
1640
1646
1647
+
static void switchtec_exit_pci(struct switchtec_dev *stdev)
1648
+
{
1649
+
if (stdev->dma_mrpc) {
1650
+
iowrite32(0, &stdev->mmio_mrpc->dma_en);
1651
+
flush_wc_buf(stdev);
1652
+
writeq(0, &stdev->mmio_mrpc->dma_addr);
1653
+
dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
1654
+
stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
1655
+
stdev->dma_mrpc = NULL;
1656
+
}
1657
+
}
1658
+
1641
1659
static int switchtec_pci_probe(struct pci_dev *pdev,
1642
1660
const struct pci_device_id *id)
1643
1661
{
···
1709
1703
ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1710
1704
dev_info(&stdev->dev, "unregistered.\n");
1711
1705
stdev_kill(stdev);
1706
+
switchtec_exit_pci(stdev);
1707
+
pci_dev_put(stdev->pdev);
1708
+
stdev->pdev = NULL;
1712
1709
put_device(&stdev->dev);
1713
1710
}
1714
1711
+1
-1
drivers/scsi/lpfc/lpfc_sli.c
+1
-1
drivers/scsi/lpfc/lpfc_sli.c
···
4880
4880
lockdep_assert_held(&phba->hbalock);
4881
4881
4882
4882
pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
4883
-
if (hdrtype != 0x80 ||
4883
+
if (hdrtype != PCI_HEADER_TYPE_MFD ||
4884
4884
(FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
4885
4885
FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
4886
4886
return;
+4
-4
include/linux/aer.h
+4
-4
include/linux/aer.h
+1
-1
include/linux/pci-ecam.h
+1
-1
include/linux/pci-ecam.h
···
93
93
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
94
94
/* for DT-based PCI controllers that support ECAM */
95
95
int pci_host_common_probe(struct platform_device *pdev);
96
-
int pci_host_common_remove(struct platform_device *pdev);
96
+
void pci_host_common_remove(struct platform_device *pdev);
97
97
#endif
98
98
#endif
+3
-10
include/linux/pci-epc.h
+3
-10
include/linux/pci-epc.h
···
19
19
SECONDARY_INTERFACE,
20
20
};
21
21
22
-
enum pci_epc_irq_type {
23
-
PCI_EPC_IRQ_UNKNOWN,
24
-
PCI_EPC_IRQ_LEGACY,
25
-
PCI_EPC_IRQ_MSI,
26
-
PCI_EPC_IRQ_MSIX,
27
-
};
28
-
29
22
static inline const char *
30
23
pci_epc_interface_string(enum pci_epc_interface_type type)
31
24
{
···
72
79
u16 interrupts, enum pci_barno, u32 offset);
73
80
int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
74
81
int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
75
-
enum pci_epc_irq_type type, u16 interrupt_num);
82
+
unsigned int type, u16 interrupt_num);
76
83
int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
77
84
phys_addr_t phys_addr, u8 interrupt_num,
78
85
u32 entry_size, u32 *msi_data,
···
115
122
* struct pci_epc - represents the PCI EPC device
116
123
* @dev: PCI EPC device
117
124
* @pci_epf: list of endpoint functions present in this EPC device
118
-
* list_lock: Mutex for protecting pci_epf list
125
+
* @list_lock: Mutex for protecting pci_epf list
119
126
* @ops: function pointers for performing endpoint operations
120
127
* @windows: array of address space of the endpoint controller
121
128
* @mem: first window of the endpoint controller, which corresponds to
···
222
229
phys_addr_t phys_addr, u8 interrupt_num,
223
230
u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
224
231
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
225
-
enum pci_epc_irq_type type, u16 interrupt_num);
232
+
unsigned int type, u16 interrupt_num);
226
233
int pci_epc_start(struct pci_epc *epc);
227
234
void pci_epc_stop(struct pci_epc *epc);
228
235
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
+2
-2
include/linux/pci-epf.h
+2
-2
include/linux/pci-epf.h
···
68
68
};
69
69
70
70
/**
71
-
* struct pci_epf_event_ops - Callbacks for capturing the EPC events
71
+
* struct pci_epc_event_ops - Callbacks for capturing the EPC events
72
72
* @core_init: Callback for the EPC initialization complete event
73
73
* @link_up: Callback for the EPC link up event
74
74
* @link_down: Callback for the EPC link down event
···
98
98
void (*remove)(struct pci_epf *epf);
99
99
100
100
struct device_driver driver;
101
-
struct pci_epf_ops *ops;
101
+
const struct pci_epf_ops *ops;
102
102
struct module *owner;
103
103
struct list_head epf_group;
104
104
const struct pci_epf_device_id *id_table;
+10
-9
include/linux/pci.h
+10
-9
include/linux/pci.h
···
715
715
716
716
/**
717
717
* pci_is_vga - check if the PCI device is a VGA device
718
+
* @pdev: PCI device
718
719
*
719
720
* The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
720
721
* VGA Base Class and Sub-Classes:
···
886
885
887
886
/**
888
887
* struct pci_driver - PCI driver structure
889
-
* @node: List of driver structures.
890
888
* @name: Driver name.
891
889
* @id_table: Pointer to table of device IDs the driver is
892
890
* interested in. Most drivers should export this
···
940
940
* own I/O address space.
941
941
*/
942
942
struct pci_driver {
943
-
struct list_head node;
944
943
const char *name;
945
944
const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
946
945
int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
···
1072
1073
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1073
1074
};
1074
1075
1075
-
#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1076
+
#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
1076
1077
#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1077
1078
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1078
1079
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1080
+
1081
+
#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* Deprecated! Use PCI_IRQ_INTX */
1079
1082
1080
1083
/* These external functions are only available when PCI support is enabled */
1081
1084
#ifdef CONFIG_PCI
···
2133
2132
(pci_resource_end((dev), (bar)) ? \
2134
2133
resource_size(pci_resource_n((dev), (bar))) : 0)
2135
2134
2136
-
#define __pci_dev_for_each_res0(dev, res, ...) \
2137
-
for (unsigned int __b = 0; \
2138
-
res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2135
+
#define __pci_dev_for_each_res0(dev, res, ...) \
2136
+
for (unsigned int __b = 0; \
2137
+
__b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2139
2138
__b++)
2140
2139
2141
-
#define __pci_dev_for_each_res1(dev, res, __b) \
2142
-
for (__b = 0; \
2143
-
res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2140
+
#define __pci_dev_for_each_res1(dev, res, __b) \
2141
+
for (__b = 0; \
2142
+
__b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2144
2143
__b++)
2145
2144
2146
2145
#define pci_dev_for_each_resource(dev, res, ...) \
+2
-1
include/uapi/linux/pcitest.h
+2
-1
include/uapi/linux/pcitest.h
···
11
11
#define __UAPI_LINUX_PCITEST_H
12
12
13
13
#define PCITEST_BAR _IO('P', 0x1)
14
-
#define PCITEST_LEGACY_IRQ _IO('P', 0x2)
14
+
#define PCITEST_INTX_IRQ _IO('P', 0x2)
15
+
#define PCITEST_LEGACY_IRQ PCITEST_INTX_IRQ
15
16
#define PCITEST_MSI _IOW('P', 0x3, int)
16
17
#define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
17
18
#define PCITEST_READ _IOW('P', 0x5, unsigned long)