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Merge branch 'net-ipa-generalized-register-definitions'

Alex Elder says:

====================
net: ipa: generalized register definitions

This series is quite a bit bigger than what I normally like to send,
and I apologize for that. I would like it to get incorporated in
its entirety this week if possible, and splitting up the series
carries a small risk that wouldn't happen.

Each IPA register has a defined offset, and in most cases, a set
of masks that define the width and position of fields within the
register. Most registers currently use the same offset for all
versions of IPA. Usually fields within registers are also the same
across many versions. Offsets and fields like this are defined
using preprocessor constants.

When a register has a different offset for different versions of
IPA, an inline function is used to determine its offset. And in
places where a field differs between versions, an inline function is
used to determine how a value is encoded within the field, depending
on IPA version.

Starting with IPA version 5.0, the number of IPA endpoints supported
is greater than 32. As a consequence, *many* IPA register offsets
differ considerably from prior versions. This increase in endpoints
also requires a lot of field sizes and/or positions to change (such
as those that contain an endpoint ID).

Defining these things with constants is no longer simple, and rather
than fill the code with one-off functions to define offsets and
encode field values, this series puts in place a new way of defining
IPA registers and their fields. Note that this series creates this
new scheme, but does not add IPA v5.0+ support.

An enumerated type will now define a unique ID for each IPA register.
Each defined register will have a structure that contains its offset
and its name (a printable string). Each version of IPA will have an
array of these register structures, indexed by register ID.

Some "parameterized" registers are duplicated (this is not new).
For example, each endpoint has an INIT_HDR register, and the offset
of a given endpoint's INIT_HDR register is dependent on the endpoint
number (the parameter). In such cases, the register's "stride" is
defined as the distance between two of these registers.

If a register contains fields, each field will have a unique ID
that's used as an index into an array of field masks defined for the
register. The register structure also defines the number of entries
in this field array.

When a register is to be used in code, its register structure will
be fetched using function ipa_reg(). Other functions are then used
to determine the register's offset, or to encode a value into one of
the register's fields, and so on.

Each version of IPA defines the set of registers that are available,
including all fields for these registers. The array of defined
registers is set up at probe time based on the IPA version, and it
is associated with the main IPA structure.
====================

Link: https://lore.kernel.org/r/20220926220931.3261749-1-elder@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski e1d07700 8f1e1658

+3897 -818
+2
drivers/net/ipa/Makefile
··· 13 13 ipa_resource.o ipa_qmi.o ipa_qmi_msg.o \ 14 14 ipa_sysfs.o 15 15 16 + ipa-y += $(IPA_VERSIONS:%=reg/ipa_reg-v%.o) 17 + 16 18 ipa-y += $(IPA_VERSIONS:%=data/ipa_data-v%.o)
+2
drivers/net/ipa/ipa.h
··· 44 44 * @uc_loaded: true after microcontroller has reported it's ready 45 45 * @reg_addr: DMA address used for IPA register access 46 46 * @reg_virt: Virtual address used for IPA register access 47 + * @regs: IPA register definitions 47 48 * @mem_addr: DMA address of IPA-local memory space 48 49 * @mem_virt: Virtual address of IPA-local memory space 49 50 * @mem_offset: Offset from @mem_virt used for access to IPA memory ··· 91 90 92 91 dma_addr_t reg_addr; 93 92 void __iomem *reg_virt; 93 + const struct ipa_regs *regs; 94 94 95 95 dma_addr_t mem_addr; 96 96 void *mem_virt;
+5 -2
drivers/net/ipa/ipa_cmd.c
··· 305 305 /* Check whether offsets passed to register_write are valid */ 306 306 static bool ipa_cmd_register_write_valid(struct ipa *ipa) 307 307 { 308 + const struct ipa_reg *reg; 308 309 const char *name; 309 310 u32 offset; 310 311 ··· 313 312 * offset will fit in a register write IPA immediate command. 314 313 */ 315 314 if (ipa_table_hash_support(ipa)) { 316 - offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version); 315 + reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); 316 + offset = ipa_reg_offset(reg); 317 317 name = "filter/route hash flush"; 318 318 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 319 319 return false; ··· 327 325 * worst case (highest endpoint number) offset of that endpoint 328 326 * fits in the register write command field(s) that must hold it. 329 327 */ 330 - offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1); 328 + reg = ipa_reg(ipa, ENDP_STATUS); 329 + offset = ipa_reg_n_offset(reg, IPA_ENDPOINT_COUNT - 1); 331 330 name = "maximal endpoint status"; 332 331 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 333 332 return false;
+222 -156
drivers/net/ipa/ipa_endpoint.c
··· 72 72 #define IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK GENMASK(31, 22) 73 73 #define IPA_STATUS_FLAGS2_TAG_FMASK GENMASK_ULL(63, 16) 74 74 75 - static u32 aggr_byte_limit_max(enum ipa_version version) 76 - { 77 - if (version < IPA_VERSION_4_5) 78 - return field_max(aggr_byte_limit_fmask(true)); 79 - 80 - return field_max(aggr_byte_limit_fmask(false)); 81 - } 82 - 83 75 /* Compute the aggregation size value to use for a given buffer size */ 84 76 static u32 ipa_aggr_size_kb(u32 rx_buffer_size, bool aggr_hard_limit) 85 77 { ··· 103 111 104 112 if (!data->toward_ipa) { 105 113 const struct ipa_endpoint_rx *rx_config; 114 + const struct ipa_reg *reg; 106 115 u32 buffer_size; 107 116 u32 aggr_size; 108 117 u32 limit; ··· 164 171 */ 165 172 aggr_size = ipa_aggr_size_kb(buffer_size - NET_SKB_PAD, 166 173 rx_config->aggr_hard_limit); 167 - limit = aggr_byte_limit_max(ipa->version); 174 + reg = ipa_reg(ipa, ENDP_INIT_AGGR); 175 + 176 + limit = ipa_reg_field_max(reg, BYTE_LIMIT); 168 177 if (aggr_size > limit) { 169 178 dev_err(dev, "aggregated size too large for RX endpoint %u (%u KB > %u KB)\n", 170 179 data->endpoint_id, aggr_size, limit); ··· 303 308 static bool 304 309 ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) 305 310 { 306 - u32 offset = IPA_REG_ENDP_INIT_CTRL_N_OFFSET(endpoint->endpoint_id); 307 311 struct ipa *ipa = endpoint->ipa; 312 + const struct ipa_reg *reg; 313 + u32 field_id; 314 + u32 offset; 308 315 bool state; 309 316 u32 mask; 310 317 u32 val; ··· 316 319 else 317 320 WARN_ON(ipa->version >= IPA_VERSION_4_0); 318 321 319 - mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK; 320 - 322 + reg = ipa_reg(ipa, ENDP_INIT_CTRL); 323 + offset = ipa_reg_n_offset(reg, endpoint->endpoint_id); 321 324 val = ioread32(ipa->reg_virt + offset); 325 + 326 + field_id = endpoint->toward_ipa ? ENDP_DELAY : ENDP_SUSPEND; 327 + mask = ipa_reg_bit(reg, field_id); 328 + 322 329 state = !!(val & mask); 323 330 324 331 /* Don't bother if it's already in the requested state */ ··· 349 348 { 350 349 u32 mask = BIT(endpoint->endpoint_id); 351 350 struct ipa *ipa = endpoint->ipa; 352 - u32 offset; 351 + const struct ipa_reg *reg; 353 352 u32 val; 354 353 355 354 WARN_ON(!(mask & ipa->available)); 356 355 357 - offset = ipa_reg_state_aggr_active_offset(ipa->version); 358 - val = ioread32(ipa->reg_virt + offset); 356 + reg = ipa_reg(ipa, STATE_AGGR_ACTIVE); 357 + val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); 359 358 360 359 return !!(val & mask); 361 360 } ··· 364 363 { 365 364 u32 mask = BIT(endpoint->endpoint_id); 366 365 struct ipa *ipa = endpoint->ipa; 366 + const struct ipa_reg *reg; 367 367 368 368 WARN_ON(!(mask & ipa->available)); 369 369 370 - iowrite32(mask, ipa->reg_virt + IPA_REG_AGGR_FORCE_CLOSE_OFFSET); 370 + reg = ipa_reg(ipa, AGGR_FORCE_CLOSE); 371 + iowrite32(mask, ipa->reg_virt + ipa_reg_offset(reg)); 371 372 } 372 373 373 374 /** ··· 468 465 while (initialized) { 469 466 u32 endpoint_id = __ffs(initialized); 470 467 struct ipa_endpoint *endpoint; 468 + const struct ipa_reg *reg; 471 469 u32 offset; 472 470 473 471 initialized ^= BIT(endpoint_id); ··· 478 474 if (!(endpoint->ee_id == GSI_EE_MODEM && endpoint->toward_ipa)) 479 475 continue; 480 476 481 - offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id); 477 + reg = ipa_reg(ipa, ENDP_STATUS); 478 + offset = ipa_reg_n_offset(reg, endpoint_id); 482 479 483 480 /* Value written is 0, and all bits are updated. That 484 481 * means status is disabled on the endpoint, and as a ··· 499 494 500 495 static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) 501 496 { 502 - u32 offset = IPA_REG_ENDP_INIT_CFG_N_OFFSET(endpoint->endpoint_id); 497 + u32 endpoint_id = endpoint->endpoint_id; 498 + struct ipa *ipa = endpoint->ipa; 503 499 enum ipa_cs_offload_en enabled; 500 + const struct ipa_reg *reg; 504 501 u32 val = 0; 505 502 503 + reg = ipa_reg(ipa, ENDP_INIT_CFG); 506 504 /* FRAG_OFFLOAD_EN is 0 */ 507 505 if (endpoint->config.checksum) { 508 - enum ipa_version version = endpoint->ipa->version; 506 + enum ipa_version version = ipa->version; 509 507 510 508 if (endpoint->toward_ipa) { 511 509 u32 off; 512 510 513 511 /* Checksum header offset is in 4-byte units */ 514 - off = sizeof(struct rmnet_map_header); 515 - off /= sizeof(u32); 516 - val |= u32_encode_bits(off, 517 - CS_METADATA_HDR_OFFSET_FMASK); 512 + off = sizeof(struct rmnet_map_header) / sizeof(u32); 513 + val |= ipa_reg_encode(reg, CS_METADATA_HDR_OFFSET, off); 518 514 519 515 enabled = version < IPA_VERSION_4_5 520 516 ? IPA_CS_OFFLOAD_UL ··· 528 522 } else { 529 523 enabled = IPA_CS_OFFLOAD_NONE; 530 524 } 531 - val |= u32_encode_bits(enabled, CS_OFFLOAD_EN_FMASK); 525 + val |= ipa_reg_encode(reg, CS_OFFLOAD_EN, enabled); 532 526 /* CS_GEN_QMB_MASTER_SEL is 0 */ 533 527 534 - iowrite32(val, endpoint->ipa->reg_virt + offset); 528 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 535 529 } 536 530 537 531 static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint) 538 532 { 539 - u32 offset; 533 + u32 endpoint_id = endpoint->endpoint_id; 534 + struct ipa *ipa = endpoint->ipa; 535 + const struct ipa_reg *reg; 540 536 u32 val; 541 537 542 538 if (!endpoint->toward_ipa) 543 539 return; 544 540 545 - offset = IPA_REG_ENDP_INIT_NAT_N_OFFSET(endpoint->endpoint_id); 546 - val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK); 541 + reg = ipa_reg(ipa, ENDP_INIT_NAT); 542 + val = ipa_reg_encode(reg, NAT_EN, IPA_NAT_BYPASS); 547 543 548 - iowrite32(val, endpoint->ipa->reg_virt + offset); 544 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 549 545 } 550 546 551 547 static u32 ··· 569 561 } 570 562 571 563 return header_size; 564 + } 565 + 566 + /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 567 + static u32 ipa_header_size_encode(enum ipa_version version, 568 + const struct ipa_reg *reg, u32 header_size) 569 + { 570 + u32 field_max = ipa_reg_field_max(reg, HDR_LEN); 571 + u32 val; 572 + 573 + /* We know field_max can be used as a mask (2^n - 1) */ 574 + val = ipa_reg_encode(reg, HDR_LEN, header_size & field_max); 575 + if (version < IPA_VERSION_4_5) { 576 + WARN_ON(header_size > field_max); 577 + return val; 578 + } 579 + 580 + /* IPA v4.5 adds a few more most-significant bits */ 581 + header_size >>= hweight32(field_max); 582 + WARN_ON(header_size > ipa_reg_field_max(reg, HDR_LEN_MSB)); 583 + val |= ipa_reg_encode(reg, HDR_LEN_MSB, header_size); 584 + 585 + return val; 586 + } 587 + 588 + /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 589 + static u32 ipa_metadata_offset_encode(enum ipa_version version, 590 + const struct ipa_reg *reg, u32 offset) 591 + { 592 + u32 field_max = ipa_reg_field_max(reg, HDR_OFST_METADATA); 593 + u32 val; 594 + 595 + /* We know field_max can be used as a mask (2^n - 1) */ 596 + val = ipa_reg_encode(reg, HDR_OFST_METADATA, offset); 597 + if (version < IPA_VERSION_4_5) { 598 + WARN_ON(offset > field_max); 599 + return val; 600 + } 601 + 602 + /* IPA v4.5 adds a few more most-significant bits */ 603 + offset >>= hweight32(field_max); 604 + WARN_ON(offset > ipa_reg_field_max(reg, HDR_OFST_METADATA_MSB)); 605 + val |= ipa_reg_encode(reg, HDR_OFST_METADATA_MSB, offset); 606 + 607 + return val; 572 608 } 573 609 574 610 /** ··· 638 586 */ 639 587 static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) 640 588 { 641 - u32 offset = IPA_REG_ENDP_INIT_HDR_N_OFFSET(endpoint->endpoint_id); 589 + u32 endpoint_id = endpoint->endpoint_id; 642 590 struct ipa *ipa = endpoint->ipa; 591 + const struct ipa_reg *reg; 643 592 u32 val = 0; 644 593 594 + reg = ipa_reg(ipa, ENDP_INIT_HDR); 645 595 if (endpoint->config.qmap) { 646 596 enum ipa_version version = ipa->version; 647 597 size_t header_size; 648 598 649 599 header_size = ipa_qmap_header_size(version, endpoint); 650 - val = ipa_header_size_encoded(version, header_size); 600 + val = ipa_header_size_encode(version, reg, header_size); 651 601 652 602 /* Define how to fill fields in a received QMAP header */ 653 603 if (!endpoint->toward_ipa) { 654 - u32 off; /* Field offset within header */ 604 + u32 off; /* Field offset within header */ 655 605 656 606 /* Where IPA will write the metadata value */ 657 607 off = offsetof(struct rmnet_map_header, mux_id); 658 - val |= ipa_metadata_offset_encoded(version, off); 608 + val |= ipa_metadata_offset_encode(version, reg, off); 659 609 660 610 /* Where IPA will write the length */ 661 611 off = offsetof(struct rmnet_map_header, pkt_len); 662 612 /* Upper bits are stored in HDR_EXT with IPA v4.5 */ 663 613 if (version >= IPA_VERSION_4_5) 664 - off &= field_mask(HDR_OFST_PKT_SIZE_FMASK); 614 + off &= ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE); 665 615 666 - val |= HDR_OFST_PKT_SIZE_VALID_FMASK; 667 - val |= u32_encode_bits(off, HDR_OFST_PKT_SIZE_FMASK); 616 + val |= ipa_reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); 617 + val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE, off); 668 618 } 669 619 /* For QMAP TX, metadata offset is 0 (modem assumes this) */ 670 - val |= HDR_OFST_METADATA_VALID_FMASK; 620 + val |= ipa_reg_bit(reg, HDR_OFST_METADATA_VALID); 671 621 672 622 /* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */ 673 623 /* HDR_A5_MUX is 0 */ ··· 677 623 /* HDR_METADATA_REG_VALID is 0 (TX only, version < v4.5) */ 678 624 } 679 625 680 - iowrite32(val, ipa->reg_virt + offset); 626 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 681 627 } 682 628 683 629 static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) 684 630 { 685 - u32 offset = IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(endpoint->endpoint_id); 686 631 u32 pad_align = endpoint->config.rx.pad_align; 632 + u32 endpoint_id = endpoint->endpoint_id; 687 633 struct ipa *ipa = endpoint->ipa; 634 + const struct ipa_reg *reg; 688 635 u32 val = 0; 689 636 637 + reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT); 690 638 if (endpoint->config.qmap) { 691 639 /* We have a header, so we must specify its endianness */ 692 - val |= HDR_ENDIANNESS_FMASK; /* big endian */ 640 + val |= ipa_reg_bit(reg, HDR_ENDIANNESS); /* big endian */ 693 641 694 642 /* A QMAP header contains a 6 bit pad field at offset 0. 695 643 * The RMNet driver assumes this field is meaningful in ··· 701 645 * (although 0) should be ignored. 702 646 */ 703 647 if (!endpoint->toward_ipa) { 704 - val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK; 648 + val |= ipa_reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); 705 649 /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */ 706 - val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK; 650 + val |= ipa_reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); 707 651 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */ 708 652 } 709 653 } 710 654 711 655 /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */ 712 656 if (!endpoint->toward_ipa) 713 - val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK); 657 + val |= ipa_reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align); 714 658 715 659 /* IPA v4.5 adds some most-significant bits to a few fields, 716 660 * two of which are defined in the HDR (not HDR_EXT) register. ··· 718 662 if (ipa->version >= IPA_VERSION_4_5) { 719 663 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */ 720 664 if (endpoint->config.qmap && !endpoint->toward_ipa) { 721 - u32 off; 665 + u32 mask = ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE); 666 + u32 off; /* Field offset within header */ 722 667 723 668 off = offsetof(struct rmnet_map_header, pkt_len); 724 - off >>= hweight32(HDR_OFST_PKT_SIZE_FMASK); 725 - val |= u32_encode_bits(off, 726 - HDR_OFST_PKT_SIZE_MSB_FMASK); 669 + /* Low bits are in the ENDP_INIT_HDR register */ 670 + off >>= hweight32(mask); 671 + val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off); 727 672 /* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */ 728 673 } 729 674 } 730 - iowrite32(val, ipa->reg_virt + offset); 675 + 676 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 731 677 } 732 678 733 679 static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) 734 680 { 735 681 u32 endpoint_id = endpoint->endpoint_id; 682 + struct ipa *ipa = endpoint->ipa; 683 + const struct ipa_reg *reg; 736 684 u32 val = 0; 737 685 u32 offset; 738 686 739 687 if (endpoint->toward_ipa) 740 688 return; /* Register not valid for TX endpoints */ 741 689 742 - offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id); 690 + reg = ipa_reg(ipa, ENDP_INIT_HDR_METADATA_MASK); 691 + offset = ipa_reg_n_offset(reg, endpoint_id); 743 692 744 693 /* Note that HDR_ENDIANNESS indicates big endian header fields */ 745 694 if (endpoint->config.qmap) 746 695 val = (__force u32)cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK); 747 696 748 - iowrite32(val, endpoint->ipa->reg_virt + offset); 697 + iowrite32(val, ipa->reg_virt + offset); 749 698 } 750 699 751 700 static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) 752 701 { 753 - u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id); 702 + struct ipa *ipa = endpoint->ipa; 703 + const struct ipa_reg *reg; 704 + u32 offset; 754 705 u32 val; 755 706 756 707 if (!endpoint->toward_ipa) 757 708 return; /* Register not valid for RX endpoints */ 758 709 710 + reg = ipa_reg(ipa, ENDP_INIT_MODE); 759 711 if (endpoint->config.dma_mode) { 760 712 enum ipa_endpoint_name name = endpoint->config.dma_endpoint; 761 - u32 dma_endpoint_id; 713 + u32 dma_endpoint_id = ipa->name_map[name]->endpoint_id; 762 714 763 - dma_endpoint_id = endpoint->ipa->name_map[name]->endpoint_id; 764 - 765 - val = u32_encode_bits(IPA_DMA, MODE_FMASK); 766 - val |= u32_encode_bits(dma_endpoint_id, DEST_PIPE_INDEX_FMASK); 715 + val = ipa_reg_encode(reg, ENDP_MODE, IPA_DMA); 716 + val |= ipa_reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id); 767 717 } else { 768 - val = u32_encode_bits(IPA_BASIC, MODE_FMASK); 718 + val = ipa_reg_encode(reg, ENDP_MODE, IPA_BASIC); 769 719 } 770 720 /* All other bits unspecified (and 0) */ 771 721 772 - iowrite32(val, endpoint->ipa->reg_virt + offset); 773 - } 774 - 775 - /* Encoded values for AGGR endpoint register fields */ 776 - static u32 aggr_byte_limit_encoded(enum ipa_version version, u32 limit) 777 - { 778 - if (version < IPA_VERSION_4_5) 779 - return u32_encode_bits(limit, aggr_byte_limit_fmask(true)); 780 - 781 - return u32_encode_bits(limit, aggr_byte_limit_fmask(false)); 722 + offset = ipa_reg_n_offset(reg, endpoint->endpoint_id); 723 + iowrite32(val, ipa->reg_virt + offset); 782 724 } 783 725 784 726 /* For IPA v4.5+, times are expressed using Qtime. The AP uses one of two ··· 804 750 } 805 751 806 752 /* Encode the aggregation timer limit (microseconds) based on IPA version */ 807 - static u32 aggr_time_limit_encode(enum ipa_version version, u32 microseconds) 753 + static u32 aggr_time_limit_encode(struct ipa *ipa, const struct ipa_reg *reg, 754 + u32 microseconds) 808 755 { 809 - u32 fmask; 756 + u32 max; 810 757 u32 val; 811 758 812 759 if (!microseconds) 813 760 return 0; /* Nothing to compute if time limit is 0 */ 814 761 815 - if (version >= IPA_VERSION_4_5) { 762 + max = ipa_reg_field_max(reg, TIME_LIMIT); 763 + if (ipa->version >= IPA_VERSION_4_5) { 816 764 u32 gran_sel; 817 765 int ret; 818 766 819 767 /* Compute the Qtime limit value to use */ 820 - fmask = aggr_time_limit_fmask(false); 821 - ret = ipa_qtime_val(microseconds, field_max(fmask)); 768 + ret = ipa_qtime_val(microseconds, max); 822 769 if (ret < 0) { 823 770 val = -ret; 824 - gran_sel = AGGR_GRAN_SEL_FMASK; 771 + gran_sel = ipa_reg_bit(reg, AGGR_GRAN_SEL); 825 772 } else { 826 773 val = ret; 827 774 gran_sel = 0; 828 775 } 829 776 830 - return gran_sel | u32_encode_bits(val, fmask); 777 + return gran_sel | ipa_reg_encode(reg, TIME_LIMIT, val); 831 778 } 832 779 833 - /* We set aggregation granularity in ipa_hardware_config() */ 834 - fmask = aggr_time_limit_fmask(true); 780 + /* We program aggregation granularity in ipa_hardware_config() */ 835 781 val = DIV_ROUND_CLOSEST(microseconds, IPA_AGGR_GRANULARITY); 836 - WARN(val > field_max(fmask), 837 - "aggr_time_limit too large (%u > %u usec)\n", 838 - val, field_max(fmask) * IPA_AGGR_GRANULARITY); 782 + WARN(val > max, "aggr_time_limit too large (%u > %u usec)\n", 783 + microseconds, max * IPA_AGGR_GRANULARITY); 839 784 840 - return u32_encode_bits(val, fmask); 841 - } 842 - 843 - static u32 aggr_sw_eof_active_encoded(enum ipa_version version, bool enabled) 844 - { 845 - u32 val = enabled ? 1 : 0; 846 - 847 - if (version < IPA_VERSION_4_5) 848 - return u32_encode_bits(val, aggr_sw_eof_active_fmask(true)); 849 - 850 - return u32_encode_bits(val, aggr_sw_eof_active_fmask(false)); 785 + return ipa_reg_encode(reg, TIME_LIMIT, val); 851 786 } 852 787 853 788 static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) 854 789 { 855 - u32 offset = IPA_REG_ENDP_INIT_AGGR_N_OFFSET(endpoint->endpoint_id); 856 - enum ipa_version version = endpoint->ipa->version; 790 + u32 endpoint_id = endpoint->endpoint_id; 791 + struct ipa *ipa = endpoint->ipa; 792 + const struct ipa_reg *reg; 857 793 u32 val = 0; 858 794 795 + reg = ipa_reg(ipa, ENDP_INIT_AGGR); 859 796 if (endpoint->config.aggregation) { 860 797 if (!endpoint->toward_ipa) { 861 798 const struct ipa_endpoint_rx *rx_config; 862 799 u32 buffer_size; 863 - bool close_eof; 864 800 u32 limit; 865 801 866 802 rx_config = &endpoint->config.rx; 867 - val |= u32_encode_bits(IPA_ENABLE_AGGR, AGGR_EN_FMASK); 868 - val |= u32_encode_bits(IPA_GENERIC, AGGR_TYPE_FMASK); 803 + val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR); 804 + val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_GENERIC); 869 805 870 806 buffer_size = rx_config->buffer_size; 871 807 limit = ipa_aggr_size_kb(buffer_size - NET_SKB_PAD, 872 808 rx_config->aggr_hard_limit); 873 - val |= aggr_byte_limit_encoded(version, limit); 809 + val |= ipa_reg_encode(reg, BYTE_LIMIT, limit); 874 810 875 811 limit = rx_config->aggr_time_limit; 876 - val |= aggr_time_limit_encode(version, limit); 812 + val |= aggr_time_limit_encode(ipa, reg, limit); 877 813 878 814 /* AGGR_PKT_LIMIT is 0 (unlimited) */ 879 815 880 - close_eof = rx_config->aggr_close_eof; 881 - val |= aggr_sw_eof_active_encoded(version, close_eof); 816 + if (rx_config->aggr_close_eof) 817 + val |= ipa_reg_bit(reg, SW_EOF_ACTIVE); 882 818 } else { 883 - val |= u32_encode_bits(IPA_ENABLE_DEAGGR, 884 - AGGR_EN_FMASK); 885 - val |= u32_encode_bits(IPA_QCMAP, AGGR_TYPE_FMASK); 819 + val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR); 820 + val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_QCMAP); 886 821 /* other fields ignored */ 887 822 } 888 823 /* AGGR_FORCE_CLOSE is 0 */ 889 824 /* AGGR_GRAN_SEL is 0 for IPA v4.5 */ 890 825 } else { 891 - val |= u32_encode_bits(IPA_BYPASS_AGGR, AGGR_EN_FMASK); 826 + val |= ipa_reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR); 892 827 /* other fields ignored */ 893 828 } 894 829 895 - iowrite32(val, endpoint->ipa->reg_virt + offset); 830 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 896 831 } 897 832 898 833 /* The head-of-line blocking timer is defined as a tick count. For ··· 892 849 * Return the encoded value representing the timeout period provided 893 850 * that should be written to the ENDP_INIT_HOL_BLOCK_TIMER register. 894 851 */ 895 - static u32 hol_block_timer_encode(struct ipa *ipa, u32 microseconds) 852 + static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, 853 + u32 microseconds) 896 854 { 897 855 u32 width; 898 856 u32 scale; ··· 906 862 return 0; /* Nothing to compute if timer period is 0 */ 907 863 908 864 if (ipa->version >= IPA_VERSION_4_5) { 865 + u32 max = ipa_reg_field_max(reg, TIMER_LIMIT); 909 866 u32 gran_sel; 910 867 int ret; 911 868 912 869 /* Compute the Qtime limit value to use */ 913 - ret = ipa_qtime_val(microseconds, field_max(TIME_LIMIT_FMASK)); 870 + ret = ipa_qtime_val(microseconds, max); 914 871 if (ret < 0) { 915 872 val = -ret; 916 - gran_sel = GRAN_SEL_FMASK; 873 + gran_sel = ipa_reg_bit(reg, TIMER_GRAN_SEL); 917 874 } else { 918 875 val = ret; 919 876 gran_sel = 0; 920 877 } 921 878 922 - return gran_sel | u32_encode_bits(val, TIME_LIMIT_FMASK); 879 + return gran_sel | ipa_reg_encode(reg, TIMER_LIMIT, val); 923 880 } 924 881 925 - /* Use 64 bit arithmetic to avoid overflow... */ 882 + /* Use 64 bit arithmetic to avoid overflow */ 926 883 rate = ipa_core_clock_rate(ipa); 927 884 ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC); 928 - /* ...but we still need to fit into a 32-bit register */ 929 - WARN_ON(ticks > U32_MAX); 885 + 886 + /* We still need the result to fit into the field */ 887 + WARN_ON(ticks > ipa_reg_field_max(reg, TIMER_BASE_VALUE)); 930 888 931 889 /* IPA v3.5.1 through v4.1 just record the tick count */ 932 890 if (ipa->version < IPA_VERSION_4_2) 933 - return (u32)ticks; 891 + return ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks); 934 892 935 893 /* For IPA v4.2, the tick count is represented by base and 936 894 * scale fields within the 32-bit timer register, where: ··· 942 896 * count, and extract the number of bits in the base field 943 897 * such that high bit is included. 944 898 */ 945 - high = fls(ticks); /* 1..32 */ 946 - width = HWEIGHT32(BASE_VALUE_FMASK); 899 + high = fls(ticks); /* 1..32 (or warning above) */ 900 + width = hweight32(ipa_reg_fmask(reg, TIMER_BASE_VALUE)); 947 901 scale = high > width ? high - width : 0; 948 902 if (scale) { 949 903 /* If we're scaling, round up to get a closer result */ ··· 953 907 scale++; 954 908 } 955 909 956 - val = u32_encode_bits(scale, SCALE_FMASK); 957 - val |= u32_encode_bits(ticks >> scale, BASE_VALUE_FMASK); 910 + val = ipa_reg_encode(reg, TIMER_SCALE, scale); 911 + val |= ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale); 958 912 959 913 return val; 960 914 } ··· 965 919 { 966 920 u32 endpoint_id = endpoint->endpoint_id; 967 921 struct ipa *ipa = endpoint->ipa; 968 - u32 offset; 922 + const struct ipa_reg *reg; 969 923 u32 val; 970 924 971 925 /* This should only be changed when HOL_BLOCK_EN is disabled */ 972 - offset = IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(endpoint_id); 973 - val = hol_block_timer_encode(ipa, microseconds); 974 - iowrite32(val, ipa->reg_virt + offset); 926 + reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_TIMER); 927 + val = hol_block_timer_encode(ipa, reg, microseconds); 928 + 929 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 975 930 } 976 931 977 932 static void 978 933 ipa_endpoint_init_hol_block_en(struct ipa_endpoint *endpoint, bool enable) 979 934 { 980 935 u32 endpoint_id = endpoint->endpoint_id; 936 + struct ipa *ipa = endpoint->ipa; 937 + const struct ipa_reg *reg; 981 938 u32 offset; 982 939 u32 val; 983 940 984 - val = enable ? HOL_BLOCK_EN_FMASK : 0; 985 - offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id); 986 - iowrite32(val, endpoint->ipa->reg_virt + offset); 941 + reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_EN); 942 + offset = ipa_reg_n_offset(reg, endpoint_id); 943 + val = enable ? ipa_reg_bit(reg, HOL_BLOCK_EN) : 0; 944 + 945 + iowrite32(val, ipa->reg_virt + offset); 946 + 987 947 /* When enabling, the register must be written twice for IPA v4.5+ */ 988 - if (enable && endpoint->ipa->version >= IPA_VERSION_4_5) 989 - iowrite32(val, endpoint->ipa->reg_virt + offset); 948 + if (enable && ipa->version >= IPA_VERSION_4_5) 949 + iowrite32(val, ipa->reg_virt + offset); 990 950 } 991 951 992 952 /* Assumes HOL_BLOCK is in disabled state */ ··· 1025 973 1026 974 static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint) 1027 975 { 1028 - u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id); 976 + u32 endpoint_id = endpoint->endpoint_id; 977 + struct ipa *ipa = endpoint->ipa; 978 + const struct ipa_reg *reg; 1029 979 u32 val = 0; 1030 980 1031 981 if (!endpoint->toward_ipa) 1032 982 return; /* Register not valid for RX endpoints */ 1033 983 984 + reg = ipa_reg(ipa, ENDP_INIT_DEAGGR); 1034 985 /* DEAGGR_HDR_LEN is 0 */ 1035 986 /* PACKET_OFFSET_VALID is 0 */ 1036 987 /* PACKET_OFFSET_LOCATION is ignored (not valid) */ 1037 988 /* MAX_PACKET_LEN is 0 (not enforced) */ 1038 989 1039 - iowrite32(val, endpoint->ipa->reg_virt + offset); 990 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 1040 991 } 1041 992 1042 993 static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint) 1043 994 { 1044 - u32 offset = IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(endpoint->endpoint_id); 995 + u32 resource_group = endpoint->config.resource_group; 996 + u32 endpoint_id = endpoint->endpoint_id; 1045 997 struct ipa *ipa = endpoint->ipa; 998 + const struct ipa_reg *reg; 1046 999 u32 val; 1047 1000 1048 - val = rsrc_grp_encoded(ipa->version, endpoint->config.resource_group); 1049 - iowrite32(val, ipa->reg_virt + offset); 1001 + reg = ipa_reg(ipa, ENDP_INIT_RSRC_GRP); 1002 + val = ipa_reg_encode(reg, ENDP_RSRC_GRP, resource_group); 1003 + 1004 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 1050 1005 } 1051 1006 1052 1007 static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) 1053 1008 { 1054 - u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id); 1055 - u32 val = 0; 1009 + u32 endpoint_id = endpoint->endpoint_id; 1010 + struct ipa *ipa = endpoint->ipa; 1011 + const struct ipa_reg *reg; 1012 + u32 val; 1056 1013 1057 1014 if (!endpoint->toward_ipa) 1058 1015 return; /* Register not valid for RX endpoints */ 1059 1016 1017 + reg = ipa_reg(ipa, ENDP_INIT_SEQ); 1018 + 1060 1019 /* Low-order byte configures primary packet processing */ 1061 - val |= u32_encode_bits(endpoint->config.tx.seq_type, SEQ_TYPE_FMASK); 1020 + val = ipa_reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type); 1062 1021 1063 1022 /* Second byte (if supported) configures replicated packet processing */ 1064 - if (endpoint->ipa->version < IPA_VERSION_4_5) 1065 - val |= u32_encode_bits(endpoint->config.tx.seq_rep_type, 1066 - SEQ_REP_TYPE_FMASK); 1023 + if (ipa->version < IPA_VERSION_4_5) 1024 + val |= ipa_reg_encode(reg, SEQ_REP_TYPE, 1025 + endpoint->config.tx.seq_rep_type); 1067 1026 1068 - iowrite32(val, endpoint->ipa->reg_virt + offset); 1027 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 1069 1028 } 1070 1029 1071 1030 /** ··· 1126 1063 { 1127 1064 u32 endpoint_id = endpoint->endpoint_id; 1128 1065 struct ipa *ipa = endpoint->ipa; 1066 + const struct ipa_reg *reg; 1129 1067 u32 val = 0; 1130 - u32 offset; 1131 1068 1132 - offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id); 1133 - 1069 + reg = ipa_reg(ipa, ENDP_STATUS); 1134 1070 if (endpoint->config.status_enable) { 1135 - val |= STATUS_EN_FMASK; 1071 + val |= ipa_reg_bit(reg, STATUS_EN); 1136 1072 if (endpoint->toward_ipa) { 1137 1073 enum ipa_endpoint_name name; 1138 1074 u32 status_endpoint_id; ··· 1139 1077 name = endpoint->config.tx.status_endpoint; 1140 1078 status_endpoint_id = ipa->name_map[name]->endpoint_id; 1141 1079 1142 - val |= u32_encode_bits(status_endpoint_id, 1143 - STATUS_ENDP_FMASK); 1080 + val |= ipa_reg_encode(reg, STATUS_ENDP, 1081 + status_endpoint_id); 1144 1082 } 1145 1083 /* STATUS_LOCATION is 0, meaning status element precedes 1146 - * packet (not present for IPA v4.5) 1084 + * packet (not present for IPA v4.5+) 1147 1085 */ 1148 - /* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v3.5.1) */ 1086 + /* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v4.0+) */ 1149 1087 } 1150 1088 1151 - iowrite32(val, ipa->reg_virt + offset); 1089 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); 1152 1090 } 1153 1091 1154 1092 static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint, ··· 1488 1426 1489 1427 void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id) 1490 1428 { 1429 + const struct ipa_reg *reg; 1491 1430 u32 val; 1492 1431 1432 + reg = ipa_reg(ipa, ROUTE); 1493 1433 /* ROUTE_DIS is 0 */ 1494 - val = u32_encode_bits(endpoint_id, ROUTE_DEF_PIPE_FMASK); 1495 - val |= ROUTE_DEF_HDR_TABLE_FMASK; 1496 - val |= u32_encode_bits(0, ROUTE_DEF_HDR_OFST_FMASK); 1497 - val |= u32_encode_bits(endpoint_id, ROUTE_FRAG_DEF_PIPE_FMASK); 1498 - val |= ROUTE_DEF_RETAIN_HDR_FMASK; 1434 + val = ipa_reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id); 1435 + val |= ipa_reg_bit(reg, ROUTE_DEF_HDR_TABLE); 1436 + /* ROUTE_DEF_HDR_OFST is 0 */ 1437 + val |= ipa_reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id); 1438 + val |= ipa_reg_bit(reg, ROUTE_DEF_RETAIN_HDR); 1499 1439 1500 - iowrite32(val, ipa->reg_virt + IPA_REG_ROUTE_OFFSET); 1440 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 1501 1441 } 1502 1442 1503 1443 void ipa_endpoint_default_route_clear(struct ipa *ipa) ··· 1843 1779 int ipa_endpoint_config(struct ipa *ipa) 1844 1780 { 1845 1781 struct device *dev = &ipa->pdev->dev; 1782 + const struct ipa_reg *reg; 1846 1783 u32 initialized; 1847 1784 u32 rx_base; 1848 1785 u32 rx_mask; ··· 1870 1805 /* Find out about the endpoints supplied by the hardware, and ensure 1871 1806 * the highest one doesn't exceed the number we support. 1872 1807 */ 1873 - val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET); 1808 + reg = ipa_reg(ipa, FLAVOR_0); 1809 + val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); 1874 1810 1875 1811 /* Our RX is an IPA producer */ 1876 - rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK); 1877 - max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK); 1812 + rx_base = ipa_reg_decode(reg, PROD_LOWEST, val); 1813 + max = rx_base + ipa_reg_decode(reg, MAX_PROD_PIPES, val); 1878 1814 if (max > IPA_ENDPOINT_MAX) { 1879 1815 dev_err(dev, "too many endpoints (%u > %u)\n", 1880 1816 max, IPA_ENDPOINT_MAX); ··· 1884 1818 rx_mask = GENMASK(max - 1, rx_base); 1885 1819 1886 1820 /* Our TX is an IPA consumer */ 1887 - max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK); 1821 + max = ipa_reg_decode(reg, MAX_CONS_PIPES, val); 1888 1822 tx_mask = GENMASK(max - 1, 0); 1889 1823 1890 1824 ipa->available = rx_mask | tx_mask;
+27 -18
drivers/net/ipa/ipa_interrupt.c
··· 53 53 { 54 54 bool uc_irq = ipa_interrupt_uc(interrupt, irq_id); 55 55 struct ipa *ipa = interrupt->ipa; 56 + const struct ipa_reg *reg; 56 57 u32 mask = BIT(irq_id); 57 58 u32 offset; 58 59 59 60 /* For microcontroller interrupts, clear the interrupt right away, 60 61 * "to avoid clearing unhandled interrupts." 61 62 */ 62 - offset = ipa_reg_irq_clr_offset(ipa->version); 63 + reg = ipa_reg(ipa, IPA_IRQ_CLR); 64 + offset = ipa_reg_offset(reg); 63 65 if (uc_irq) 64 66 iowrite32(mask, ipa->reg_virt + offset); 65 67 ··· 82 80 struct ipa_interrupt *interrupt = dev_id; 83 81 struct ipa *ipa = interrupt->ipa; 84 82 u32 enabled = interrupt->enabled; 83 + const struct ipa_reg *reg; 85 84 struct device *dev; 86 85 u32 pending; 87 86 u32 offset; ··· 98 95 * including conditions whose interrupt is not enabled. Handle 99 96 * only the enabled ones. 100 97 */ 101 - offset = ipa_reg_irq_stts_offset(ipa->version); 98 + reg = ipa_reg(ipa, IPA_IRQ_STTS); 99 + offset = ipa_reg_offset(reg); 102 100 pending = ioread32(ipa->reg_virt + offset); 103 101 while ((mask = pending & enabled)) { 104 102 do { ··· 116 112 if (pending) { 117 113 dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n", 118 114 pending); 119 - offset = ipa_reg_irq_clr_offset(ipa->version); 115 + reg = ipa_reg(ipa, IPA_IRQ_CLR); 116 + offset = ipa_reg_offset(reg); 120 117 iowrite32(pending, ipa->reg_virt + offset); 121 118 } 122 119 out_power_put: ··· 133 128 { 134 129 struct ipa *ipa = interrupt->ipa; 135 130 u32 mask = BIT(endpoint_id); 131 + const struct ipa_reg *reg; 136 132 u32 offset; 137 133 u32 val; 138 134 ··· 143 137 if (ipa->version == IPA_VERSION_3_0) 144 138 return; 145 139 146 - offset = ipa_reg_irq_suspend_en_offset(ipa->version); 140 + reg = ipa_reg(ipa, IRQ_SUSPEND_EN); 141 + offset = ipa_reg_offset(reg); 147 142 val = ioread32(ipa->reg_virt + offset); 148 143 if (enable) 149 144 val |= mask; ··· 171 164 void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) 172 165 { 173 166 struct ipa *ipa = interrupt->ipa; 174 - u32 offset; 167 + const struct ipa_reg *reg; 175 168 u32 val; 176 169 177 - offset = ipa_reg_irq_suspend_info_offset(ipa->version); 178 - val = ioread32(ipa->reg_virt + offset); 170 + reg = ipa_reg(ipa, IRQ_SUSPEND_INFO); 171 + val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); 179 172 180 173 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ 181 174 if (ipa->version == IPA_VERSION_3_0) 182 175 return; 183 176 184 - offset = ipa_reg_irq_suspend_clr_offset(ipa->version); 185 - iowrite32(val, ipa->reg_virt + offset); 177 + reg = ipa_reg(ipa, IRQ_SUSPEND_CLR); 178 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 186 179 } 187 180 188 181 /* Simulate arrival of an IPA TX_SUSPEND interrupt */ ··· 196 189 enum ipa_irq_id ipa_irq, ipa_irq_handler_t handler) 197 190 { 198 191 struct ipa *ipa = interrupt->ipa; 199 - u32 offset; 192 + const struct ipa_reg *reg; 200 193 201 194 if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT)) 202 195 return; ··· 205 198 206 199 /* Update the IPA interrupt mask to enable it */ 207 200 interrupt->enabled |= BIT(ipa_irq); 208 - offset = ipa_reg_irq_en_offset(ipa->version); 209 - iowrite32(interrupt->enabled, ipa->reg_virt + offset); 201 + 202 + reg = ipa_reg(ipa, IPA_IRQ_EN); 203 + iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg)); 210 204 } 211 205 212 206 /* Remove the handler for an IPA interrupt type */ ··· 215 207 ipa_interrupt_remove(struct ipa_interrupt *interrupt, enum ipa_irq_id ipa_irq) 216 208 { 217 209 struct ipa *ipa = interrupt->ipa; 218 - u32 offset; 210 + const struct ipa_reg *reg; 219 211 220 212 if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT)) 221 213 return; 222 214 223 215 /* Update the IPA interrupt mask to disable it */ 224 216 interrupt->enabled &= ~BIT(ipa_irq); 225 - offset = ipa_reg_irq_en_offset(ipa->version); 226 - iowrite32(interrupt->enabled, ipa->reg_virt + offset); 217 + 218 + reg = ipa_reg(ipa, IPA_IRQ_EN); 219 + iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg)); 227 220 228 221 interrupt->handler[ipa_irq] = NULL; 229 222 } ··· 234 225 { 235 226 struct device *dev = &ipa->pdev->dev; 236 227 struct ipa_interrupt *interrupt; 228 + const struct ipa_reg *reg; 237 229 unsigned int irq; 238 - u32 offset; 239 230 int ret; 240 231 241 232 ret = platform_get_irq_byname(ipa->pdev, "ipa"); ··· 253 244 interrupt->irq = irq; 254 245 255 246 /* Start with all IPA interrupts disabled */ 256 - offset = ipa_reg_irq_en_offset(ipa->version); 257 - iowrite32(0, ipa->reg_virt + offset); 247 + reg = ipa_reg(ipa, IPA_IRQ_EN); 248 + iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); 258 249 259 250 ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT, 260 251 "ipa", interrupt);
+100 -64
drivers/net/ipa/ipa_main.c
··· 186 186 static void 187 187 ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data) 188 188 { 189 + const struct ipa_reg *reg; 189 190 u32 val; 190 191 191 192 /* IPA v4.5+ has no backward compatibility register */ 192 193 if (ipa->version >= IPA_VERSION_4_5) 193 194 return; 194 195 196 + reg = ipa_reg(ipa, IPA_BCR); 195 197 val = data->backward_compat; 196 - iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); 198 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 197 199 } 198 200 199 201 static void ipa_hardware_config_tx(struct ipa *ipa) 200 202 { 201 203 enum ipa_version version = ipa->version; 204 + const struct ipa_reg *reg; 205 + u32 offset; 202 206 u32 val; 203 207 204 208 if (version <= IPA_VERSION_4_0 || version >= IPA_VERSION_4_5) 205 209 return; 206 210 207 211 /* Disable PA mask to allow HOLB drop */ 208 - val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 212 + reg = ipa_reg(ipa, IPA_TX_CFG); 213 + offset = ipa_reg_offset(reg); 209 214 210 - val &= ~PA_MASK_EN_FMASK; 215 + val = ioread32(ipa->reg_virt + offset); 211 216 212 - iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 217 + val &= ~ipa_reg_bit(reg, PA_MASK_EN); 218 + 219 + iowrite32(val, ipa->reg_virt + offset); 213 220 } 214 221 215 222 static void ipa_hardware_config_clkon(struct ipa *ipa) 216 223 { 217 224 enum ipa_version version = ipa->version; 225 + const struct ipa_reg *reg; 218 226 u32 val; 219 227 220 - if (version < IPA_VERSION_3_1 || version >= IPA_VERSION_4_5) 228 + if (version >= IPA_VERSION_4_5) 229 + return; 230 + 231 + if (version < IPA_VERSION_4_0 && version != IPA_VERSION_3_1) 221 232 return; 222 233 223 234 /* Implement some hardware workarounds */ 224 - if (version >= IPA_VERSION_4_0) { 235 + reg = ipa_reg(ipa, CLKON_CFG); 236 + if (version == IPA_VERSION_3_1) { 237 + /* Disable MISC clock gating */ 238 + val = ipa_reg_bit(reg, CLKON_MISC); 239 + } else { /* IPA v4.0+ */ 225 240 /* Enable open global clocks in the CLKON configuration */ 226 - val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; 227 - } else if (version == IPA_VERSION_3_1) { 228 - val = MISC_FMASK; /* Disable MISC clock gating */ 229 - } else { 230 - return; 241 + val = ipa_reg_bit(reg, CLKON_GLOBAL); 242 + val |= ipa_reg_bit(reg, GLOBAL_2X_CLK); 231 243 } 232 244 233 - iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); 245 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 234 246 } 235 247 236 248 /* Configure bus access behavior for IPA components */ 237 249 static void ipa_hardware_config_comp(struct ipa *ipa) 238 250 { 251 + const struct ipa_reg *reg; 252 + u32 offset; 239 253 u32 val; 240 254 241 255 /* Nothing to configure prior to IPA v4.0 */ 242 256 if (ipa->version < IPA_VERSION_4_0) 243 257 return; 244 258 245 - val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 259 + reg = ipa_reg(ipa, COMP_CFG); 260 + offset = ipa_reg_offset(reg); 261 + val = ioread32(ipa->reg_virt + offset); 246 262 247 263 if (ipa->version == IPA_VERSION_4_0) { 248 - val &= ~IPA_QMB_SELECT_CONS_EN_FMASK; 249 - val &= ~IPA_QMB_SELECT_PROD_EN_FMASK; 250 - val &= ~IPA_QMB_SELECT_GLOBAL_EN_FMASK; 264 + val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_CONS_EN); 265 + val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_PROD_EN); 266 + val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN); 251 267 } else if (ipa->version < IPA_VERSION_4_5) { 252 - val |= GSI_MULTI_AXI_MASTERS_DIS_FMASK; 268 + val |= ipa_reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS); 253 269 } else { 254 - /* For IPA v4.5 IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN is 0 */ 270 + /* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */ 255 271 } 256 272 257 - val |= GSI_MULTI_INORDER_RD_DIS_FMASK; 258 - val |= GSI_MULTI_INORDER_WR_DIS_FMASK; 273 + val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); 274 + val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_WR_DIS); 259 275 260 - iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 276 + iowrite32(val, ipa->reg_virt + offset); 261 277 } 262 278 263 279 /* Configure DDR and (possibly) PCIe max read/write QSB values */ ··· 282 266 { 283 267 const struct ipa_qsb_data *data0; 284 268 const struct ipa_qsb_data *data1; 269 + const struct ipa_reg *reg; 285 270 u32 val; 286 271 287 272 /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */ ··· 291 274 data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE]; 292 275 293 276 /* Max outstanding write accesses for QSB masters */ 294 - val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK); 277 + reg = ipa_reg(ipa, QSB_MAX_WRITES); 278 + 279 + val = ipa_reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes); 295 280 if (data->qsb_count > 1) 296 - val |= u32_encode_bits(data1->max_writes, 297 - GEN_QMB_1_MAX_WRITES_FMASK); 298 - iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET); 281 + val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_WRITES, 282 + data1->max_writes); 283 + 284 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 299 285 300 286 /* Max outstanding read accesses for QSB masters */ 301 - val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK); 287 + reg = ipa_reg(ipa, QSB_MAX_READS); 288 + 289 + val = ipa_reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads); 302 290 if (ipa->version >= IPA_VERSION_4_0) 303 - val |= u32_encode_bits(data0->max_reads_beats, 304 - GEN_QMB_0_MAX_READS_BEATS_FMASK); 291 + val |= ipa_reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS, 292 + data0->max_reads_beats); 305 293 if (data->qsb_count > 1) { 306 - val |= u32_encode_bits(data1->max_reads, 307 - GEN_QMB_1_MAX_READS_FMASK); 294 + val = ipa_reg_encode(reg, GEN_QMB_1_MAX_READS, 295 + data1->max_reads); 308 296 if (ipa->version >= IPA_VERSION_4_0) 309 - val |= u32_encode_bits(data1->max_reads_beats, 310 - GEN_QMB_1_MAX_READS_BEATS_FMASK); 297 + val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS, 298 + data1->max_reads_beats); 311 299 } 312 - iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); 300 + 301 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 313 302 } 314 303 315 304 /* The internal inactivity timer clock is used for the aggregation timer */ ··· 351 328 */ 352 329 static void ipa_qtime_config(struct ipa *ipa) 353 330 { 331 + const struct ipa_reg *reg; 332 + u32 offset; 354 333 u32 val; 355 334 356 335 /* Timer clock divider must be disabled when we change the rate */ 357 - iowrite32(0, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 336 + reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG); 337 + iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); 358 338 339 + reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG); 359 340 /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */ 360 - val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK); 361 - val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK); 341 + val = ipa_reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT); 342 + val |= ipa_reg_bit(reg, DPL_TIMESTAMP_SEL); 362 343 /* Configure tag and NAT Qtime timestamp resolution as well */ 363 - val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK); 364 - val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK); 365 - iowrite32(val, ipa->reg_virt + IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET); 344 + val = ipa_reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT); 345 + val = ipa_reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT); 346 + 347 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 366 348 367 349 /* Set granularity of pulse generators used for other timers */ 368 - val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK); 369 - val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK); 370 - val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK); 371 - iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET); 350 + reg = ipa_reg(ipa, TIMERS_PULSE_GRAN_CFG); 351 + val = ipa_reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US); 352 + val |= ipa_reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS); 353 + val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS); 354 + 355 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 372 356 373 357 /* Actual divider is 1 more than value supplied here */ 374 - val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK); 375 - iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 358 + reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG); 359 + offset = ipa_reg_offset(reg); 360 + val = ipa_reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1); 361 + 362 + iowrite32(val, ipa->reg_virt + offset); 376 363 377 364 /* Divider value is set; re-enable the common timer clock divider */ 378 - val |= u32_encode_bits(1, DIV_ENABLE_FMASK); 379 - iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 365 + val |= ipa_reg_bit(reg, DIV_ENABLE); 366 + 367 + iowrite32(val, ipa->reg_virt + offset); 380 368 } 381 369 382 370 /* Before IPA v4.5 timing is controlled by a counter register */ 383 371 static void ipa_hardware_config_counter(struct ipa *ipa) 384 372 { 385 - u32 granularity; 373 + u32 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); 374 + const struct ipa_reg *reg; 386 375 u32 val; 387 376 388 - granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); 389 - 390 - val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); 391 - 392 - iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); 377 + reg = ipa_reg(ipa, COUNTER_CFG); 378 + /* If defined, EOT_COAL_GRANULARITY is 0 */ 379 + val = ipa_reg_encode(reg, AGGR_GRANULARITY, granularity); 380 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 393 381 } 394 382 395 383 static void ipa_hardware_config_timing(struct ipa *ipa) ··· 413 379 414 380 static void ipa_hardware_config_hashing(struct ipa *ipa) 415 381 { 416 - u32 offset; 382 + const struct ipa_reg *reg; 417 383 418 384 if (ipa->version != IPA_VERSION_4_2) 419 385 return; 420 386 421 387 /* IPA v4.2 does not support hashed tables, so disable them */ 422 - offset = ipa_reg_filt_rout_hash_en_offset(IPA_VERSION_4_2); 423 - iowrite32(0, ipa->reg_virt + offset); 388 + reg = ipa_reg(ipa, FILT_ROUT_HASH_EN); 389 + 390 + /* IPV6_ROUTER_HASH, IPV6_FILTER_HASH, IPV4_ROUTER_HASH, 391 + * IPV4_FILTER_HASH are all zero. 392 + */ 393 + iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); 424 394 } 425 395 426 396 static void ipa_idle_indication_cfg(struct ipa *ipa, 427 397 u32 enter_idle_debounce_thresh, 428 398 bool const_non_idle_enable) 429 399 { 430 - u32 offset; 400 + const struct ipa_reg *reg; 431 401 u32 val; 432 402 433 - val = u32_encode_bits(enter_idle_debounce_thresh, 434 - ENTER_IDLE_DEBOUNCE_THRESH_FMASK); 403 + reg = ipa_reg(ipa, IDLE_INDICATION_CFG); 404 + val = ipa_reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH, 405 + enter_idle_debounce_thresh); 435 406 if (const_non_idle_enable) 436 - val |= CONST_NON_IDLE_ENABLE_FMASK; 407 + val |= ipa_reg_bit(reg, CONST_NON_IDLE_ENABLE); 437 408 438 - offset = ipa_reg_idle_indication_cfg_offset(ipa->version); 439 - iowrite32(val, ipa->reg_virt + offset); 409 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 440 410 } 441 411 442 412 /** ··· 691 653 692 654 /* Aggregation granularity value can't be 0, and must fit */ 693 655 BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY)); 694 - BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) > 695 - field_max(AGGR_GRANULARITY_FMASK)); 696 656 } 697 657 698 658 /**
+11 -5
drivers/net/ipa/ipa_mem.c
··· 75 75 int ipa_mem_setup(struct ipa *ipa) 76 76 { 77 77 dma_addr_t addr = ipa->zero_addr; 78 + const struct ipa_reg *reg; 78 79 const struct ipa_mem *mem; 79 80 struct gsi_trans *trans; 80 81 u32 offset; ··· 113 112 /* Tell the hardware where the processing context area is located */ 114 113 mem = ipa_mem_find(ipa, IPA_MEM_MODEM_PROC_CTX); 115 114 offset = ipa->mem_offset + mem->offset; 116 - val = proc_cntxt_base_addr_encoded(ipa->version, offset); 117 - iowrite32(val, ipa->reg_virt + IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET); 115 + 116 + reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT); 117 + val = ipa_reg_encode(reg, IPA_BASE_ADDR, offset); 118 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 118 119 119 120 return 0; 120 121 } ··· 309 306 int ipa_mem_config(struct ipa *ipa) 310 307 { 311 308 struct device *dev = &ipa->pdev->dev; 309 + const struct ipa_reg *reg; 312 310 const struct ipa_mem *mem; 313 311 dma_addr_t addr; 314 312 u32 mem_size; ··· 318 314 u32 i; 319 315 320 316 /* Check the advertised location and size of the shared memory area */ 321 - val = ioread32(ipa->reg_virt + IPA_REG_SHARED_MEM_SIZE_OFFSET); 317 + reg = ipa_reg(ipa, SHARED_MEM_SIZE); 318 + val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); 322 319 323 320 /* The fields in the register are in 8 byte units */ 324 - ipa->mem_offset = 8 * u32_get_bits(val, SHARED_MEM_BADDR_FMASK); 321 + ipa->mem_offset = 8 * ipa_reg_decode(reg, MEM_BADDR, val); 322 + 325 323 /* Make sure the end is within the region's mapped space */ 326 - mem_size = 8 * u32_get_bits(val, SHARED_MEM_SIZE_FMASK); 324 + mem_size = 8 * ipa_reg_decode(reg, MEM_SIZE, val); 327 325 328 326 /* If the sizes don't match, issue a warning */ 329 327 if (ipa->mem_offset + mem_size < ipa->mem_size) {
+95
drivers/net/ipa/ipa_reg.c
··· 9 9 #include "ipa.h" 10 10 #include "ipa_reg.h" 11 11 12 + /* Is this register valid and defined for the current IPA version? */ 13 + static bool ipa_reg_valid(struct ipa *ipa, enum ipa_reg_id reg_id) 14 + { 15 + enum ipa_version version = ipa->version; 16 + bool valid; 17 + 18 + /* Check for bogus (out of range) register IDs */ 19 + if ((u32)reg_id >= ipa->regs->reg_count) 20 + return false; 21 + 22 + switch (reg_id) { 23 + case IPA_BCR: 24 + case COUNTER_CFG: 25 + valid = version < IPA_VERSION_4_5; 26 + break; 27 + 28 + case IPA_TX_CFG: 29 + case FLAVOR_0: 30 + case IDLE_INDICATION_CFG: 31 + valid = version >= IPA_VERSION_3_5; 32 + break; 33 + 34 + case QTIME_TIMESTAMP_CFG: 35 + case TIMERS_XO_CLK_DIV_CFG: 36 + case TIMERS_PULSE_GRAN_CFG: 37 + valid = version >= IPA_VERSION_4_5; 38 + break; 39 + 40 + case SRC_RSRC_GRP_45_RSRC_TYPE: 41 + case DST_RSRC_GRP_45_RSRC_TYPE: 42 + valid = version <= IPA_VERSION_3_1 || 43 + version == IPA_VERSION_4_5; 44 + break; 45 + 46 + case SRC_RSRC_GRP_67_RSRC_TYPE: 47 + case DST_RSRC_GRP_67_RSRC_TYPE: 48 + valid = version <= IPA_VERSION_3_1; 49 + break; 50 + 51 + case ENDP_FILTER_ROUTER_HSH_CFG: 52 + valid = version != IPA_VERSION_4_2; 53 + break; 54 + 55 + case IRQ_SUSPEND_EN: 56 + case IRQ_SUSPEND_CLR: 57 + valid = version >= IPA_VERSION_3_1; 58 + break; 59 + 60 + default: 61 + valid = true; /* Others should be defined for all versions */ 62 + break; 63 + } 64 + 65 + /* To be valid, it must be defined */ 66 + 67 + return valid && ipa->regs->reg[reg_id]; 68 + } 69 + 70 + const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id) 71 + { 72 + if (WARN_ON(!ipa_reg_valid(ipa, reg_id))) 73 + return NULL; 74 + 75 + return ipa->regs->reg[reg_id]; 76 + } 77 + 78 + static const struct ipa_regs *ipa_regs(enum ipa_version version) 79 + { 80 + switch (version) { 81 + case IPA_VERSION_3_1: 82 + return &ipa_regs_v3_1; 83 + case IPA_VERSION_3_5_1: 84 + return &ipa_regs_v3_5_1; 85 + case IPA_VERSION_4_2: 86 + return &ipa_regs_v4_2; 87 + case IPA_VERSION_4_5: 88 + return &ipa_regs_v4_5; 89 + case IPA_VERSION_4_9: 90 + return &ipa_regs_v4_9; 91 + case IPA_VERSION_4_11: 92 + return &ipa_regs_v4_11; 93 + default: 94 + return NULL; 95 + } 96 + } 97 + 12 98 int ipa_reg_init(struct ipa *ipa) 13 99 { 14 100 struct device *dev = &ipa->pdev->dev; 101 + const struct ipa_regs *regs; 15 102 struct resource *res; 103 + 104 + regs = ipa_regs(ipa->version); 105 + if (!regs) 106 + return -EINVAL; 107 + 108 + if (WARN_ON(regs->reg_count > IPA_REG_ID_COUNT)) 109 + return -EINVAL; 16 110 17 111 /* Setup IPA register memory */ 18 112 res = platform_get_resource_byname(ipa->pdev, IORESOURCE_MEM, ··· 122 28 return -ENOMEM; 123 29 } 124 30 ipa->reg_addr = res->start; 31 + ipa->regs = regs; 125 32 126 33 return 0; 127 34 }
+431 -532
drivers/net/ipa/ipa_reg.h
··· 7 7 #define _IPA_REG_H_ 8 8 9 9 #include <linux/bitfield.h> 10 + #include <linux/bug.h> 10 11 11 12 #include "ipa_version.h" 12 13 ··· 66 65 * of valid bits for the register. 67 66 */ 68 67 69 - #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 70 - /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 71 - #define ENABLE_FMASK GENMASK(0, 0) 72 - /* The next field is present for IPA v4.7+ */ 73 - #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 74 - #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 75 - #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 76 - #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 77 - /* The next field is not present for IPA v4.5+ */ 78 - #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 79 - /* The next twelve fields are present for IPA v4.0+ */ 80 - #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 81 - #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 82 - #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 83 - #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 84 - #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 85 - #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 86 - #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 87 - #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 88 - #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 89 - #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 90 - #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 91 - #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 92 - /* The next five fields are present for IPA v4.9+ */ 93 - #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 94 - #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 95 - #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 96 - #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 97 - #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 68 + /* enum ipa_reg_id - IPA register IDs */ 69 + enum ipa_reg_id { 70 + COMP_CFG, 71 + CLKON_CFG, 72 + ROUTE, 73 + SHARED_MEM_SIZE, 74 + QSB_MAX_WRITES, 75 + QSB_MAX_READS, 76 + FILT_ROUT_HASH_EN, 77 + FILT_ROUT_HASH_FLUSH, 78 + STATE_AGGR_ACTIVE, 79 + IPA_BCR, /* Not IPA v4.5+ */ 80 + LOCAL_PKT_PROC_CNTXT, 81 + AGGR_FORCE_CLOSE, 82 + COUNTER_CFG, /* Not IPA v4.5+ */ 83 + IPA_TX_CFG, /* IPA v3.5+ */ 84 + FLAVOR_0, /* IPA v3.5+ */ 85 + IDLE_INDICATION_CFG, /* IPA v3.5+ */ 86 + QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 87 + TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 88 + TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 89 + SRC_RSRC_GRP_01_RSRC_TYPE, 90 + SRC_RSRC_GRP_23_RSRC_TYPE, 91 + SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 92 + SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 93 + DST_RSRC_GRP_01_RSRC_TYPE, 94 + DST_RSRC_GRP_23_RSRC_TYPE, 95 + DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 96 + DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 97 + ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 98 + ENDP_INIT_CFG, 99 + ENDP_INIT_NAT, /* TX only */ 100 + ENDP_INIT_HDR, 101 + ENDP_INIT_HDR_EXT, 102 + ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 103 + ENDP_INIT_MODE, /* TX only */ 104 + ENDP_INIT_AGGR, 105 + ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 106 + ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 107 + ENDP_INIT_DEAGGR, /* TX only */ 108 + ENDP_INIT_RSRC_GRP, 109 + ENDP_INIT_SEQ, /* TX only */ 110 + ENDP_STATUS, 111 + ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 112 + /* The IRQ registers are only used for GSI_EE_AP */ 113 + IPA_IRQ_STTS, 114 + IPA_IRQ_EN, 115 + IPA_IRQ_CLR, 116 + IPA_IRQ_UC, 117 + IRQ_SUSPEND_INFO, 118 + IRQ_SUSPEND_EN, /* IPA v3.1+ */ 119 + IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 120 + IPA_REG_ID_COUNT, /* Last; not an ID */ 121 + }; 98 122 99 - /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ 100 - static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, 101 - u32 mask) 102 - { 103 - WARN_ON(version < IPA_VERSION_4_0); 123 + /** 124 + * struct ipa_reg - An IPA register descriptor 125 + * @offset: Register offset relative to base of the "ipa-reg" memory 126 + * @stride: Distance between two instances, if parameterized 127 + * @fcount: Number of entries in the @fmask array 128 + * @fmask: Array of mask values defining position and width of fields 129 + * @name: Upper-case name of the IPA register 130 + */ 131 + struct ipa_reg { 132 + u32 offset; 133 + u32 stride; 134 + u32 fcount; 135 + const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ 136 + const char *name; 137 + }; 104 138 105 - if (version < IPA_VERSION_4_9) 106 - return u32_encode_bits(mask, GENMASK(20, 17)); 139 + /* Helper macro for defining "simple" (non-parameterized) registers */ 140 + #define IPA_REG(__NAME, __reg_id, __offset) \ 141 + IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 107 142 108 - if (version == IPA_VERSION_4_9) 109 - return u32_encode_bits(mask, GENMASK(24, 22)); 143 + /* Helper macro for defining parameterized registers, specifying stride */ 144 + #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 145 + static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 146 + .name = #__NAME, \ 147 + .offset = __offset, \ 148 + .stride = __stride, \ 149 + } 110 150 111 - return u32_encode_bits(mask, GENMASK(23, 22)); 112 - } 151 + #define IPA_REG_FIELDS(__NAME, __name, __offset) \ 152 + IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) 113 153 114 - /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ 115 - static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, 116 - bool enable) 117 - { 118 - u32 val = enable ? 1 : 0; 154 + #define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ 155 + static const struct ipa_reg ipa_reg_ ## __name = { \ 156 + .name = #__NAME, \ 157 + .offset = __offset, \ 158 + .stride = __stride, \ 159 + .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ 160 + .fmask = ipa_reg_ ## __name ## _fmask, \ 161 + } 119 162 120 - WARN_ON(version < IPA_VERSION_4_5); 163 + /** 164 + * struct ipa_regs - Description of registers supported by hardware 165 + * @reg_count: Number of registers in the @reg[] array 166 + * @reg: Array of register descriptors 167 + */ 168 + struct ipa_regs { 169 + u32 reg_count; 170 + const struct ipa_reg **reg; 171 + }; 121 172 122 - if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) 123 - return u32_encode_bits(val, GENMASK(21, 21)); 173 + /* COMP_CFG register */ 174 + enum ipa_reg_comp_cfg_field_id { 175 + COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 176 + RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 177 + GSI_SNOC_BYPASS_DIS, 178 + GEN_QMB_0_SNOC_BYPASS_DIS, 179 + GEN_QMB_1_SNOC_BYPASS_DIS, 180 + IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 181 + IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 182 + IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 183 + GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 184 + GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 185 + GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 186 + GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 187 + GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 188 + GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 189 + GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 190 + GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 191 + GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 192 + IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 193 + QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 194 + GENQMB_AOOOWR, /* IPA v4.9+ */ 195 + IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 196 + GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 197 + GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 198 + ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 199 + FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 200 + }; 124 201 125 - return u32_encode_bits(val, GENMASK(17, 17)); 126 - } 202 + /* CLKON_CFG register */ 203 + enum ipa_reg_clkon_cfg_field_id { 204 + CLKON_RX, 205 + CLKON_PROC, 206 + TX_WRAPPER, 207 + CLKON_MISC, 208 + RAM_ARB, 209 + FTCH_HPS, 210 + FTCH_DPS, 211 + CLKON_HPS, 212 + CLKON_DPS, 213 + RX_HPS_CMDQS, 214 + HPS_DPS_CMDQS, 215 + DPS_TX_CMDQS, 216 + RSRC_MNGR, 217 + CTX_HANDLER, 218 + ACK_MNGR, 219 + D_DCPH, 220 + H_DCPH, 221 + CLKON_DCMP, /* IPA v4.5+ */ 222 + NTF_TX_CMDQS, /* IPA v3.5+ */ 223 + CLKON_TX_0, /* IPA v3.5+ */ 224 + CLKON_TX_1, /* IPA v3.5+ */ 225 + CLKON_FNR, /* IPA v3.5.1+ */ 226 + QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 227 + AGGR_WRAPPER, /* IPA v4.0+ */ 228 + RAM_SLAVEWAY, /* IPA v4.0+ */ 229 + CLKON_QMB, /* IPA v4.0+ */ 230 + WEIGHT_ARB, /* IPA v4.0+ */ 231 + GSI_IF, /* IPA v4.0+ */ 232 + CLKON_GLOBAL, /* IPA v4.0+ */ 233 + GLOBAL_2X_CLK, /* IPA v4.0+ */ 234 + DPL_FIFO, /* IPA v4.5+ */ 235 + DRBIP, /* IPA v4.7+ */ 236 + }; 127 237 128 - #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 129 - #define RX_FMASK GENMASK(0, 0) 130 - #define PROC_FMASK GENMASK(1, 1) 131 - #define TX_WRAPPER_FMASK GENMASK(2, 2) 132 - #define MISC_FMASK GENMASK(3, 3) 133 - #define RAM_ARB_FMASK GENMASK(4, 4) 134 - #define FTCH_HPS_FMASK GENMASK(5, 5) 135 - #define FTCH_DPS_FMASK GENMASK(6, 6) 136 - #define HPS_FMASK GENMASK(7, 7) 137 - #define DPS_FMASK GENMASK(8, 8) 138 - #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 139 - #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 140 - #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 141 - #define RSRC_MNGR_FMASK GENMASK(12, 12) 142 - #define CTX_HANDLER_FMASK GENMASK(13, 13) 143 - #define ACK_MNGR_FMASK GENMASK(14, 14) 144 - #define D_DCPH_FMASK GENMASK(15, 15) 145 - #define H_DCPH_FMASK GENMASK(16, 16) 146 - /* The next field is not present for IPA v4.5+ */ 147 - #define DCMP_FMASK GENMASK(17, 17) 148 - /* The next three fields are present for IPA v3.5+ */ 149 - #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 150 - #define TX_0_FMASK GENMASK(19, 19) 151 - #define TX_1_FMASK GENMASK(20, 20) 152 - /* The next field is present for IPA v3.5.1+ */ 153 - #define FNR_FMASK GENMASK(21, 21) 154 - /* The next eight fields are present for IPA v4.0+ */ 155 - #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 156 - #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 157 - #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 158 - #define QMB_FMASK GENMASK(25, 25) 159 - #define WEIGHT_ARB_FMASK GENMASK(26, 26) 160 - #define GSI_IF_FMASK GENMASK(27, 27) 161 - #define GLOBAL_FMASK GENMASK(28, 28) 162 - #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 163 - /* The next field is present for IPA v4.5+ */ 164 - #define DPL_FIFO_FMASK GENMASK(30, 30) 165 - /* The next field is present for IPA v4.7+ */ 166 - #define DRBIP_FMASK GENMASK(31, 31) 238 + /* ROUTE register */ 239 + enum ipa_reg_route_field_id { 240 + ROUTE_DIS, 241 + ROUTE_DEF_PIPE, 242 + ROUTE_DEF_HDR_TABLE, 243 + ROUTE_DEF_HDR_OFST, 244 + ROUTE_FRAG_DEF_PIPE, 245 + ROUTE_DEF_RETAIN_HDR, 246 + }; 167 247 168 - #define IPA_REG_ROUTE_OFFSET 0x00000048 169 - #define ROUTE_DIS_FMASK GENMASK(0, 0) 170 - #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 171 - #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 172 - #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 173 - #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 174 - #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 248 + /* SHARED_MEM_SIZE register */ 249 + enum ipa_reg_shared_mem_size_field_id { 250 + MEM_SIZE, 251 + MEM_BADDR, 252 + }; 175 253 176 - #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 177 - #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 178 - #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 254 + /* QSB_MAX_WRITES register */ 255 + enum ipa_reg_qsb_max_writes_field_id { 256 + GEN_QMB_0_MAX_WRITES, 257 + GEN_QMB_1_MAX_WRITES, 258 + }; 179 259 180 - #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 181 - #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 182 - #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 260 + /* QSB_MAX_READS register */ 261 + enum ipa_reg_qsb_max_reads_field_id { 262 + GEN_QMB_0_MAX_READS, 263 + GEN_QMB_1_MAX_READS, 264 + GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 265 + GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 266 + }; 183 267 184 - #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 185 - #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 186 - #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 187 - /* The next two fields are present for IPA v4.0+ */ 188 - #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 189 - #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 268 + /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 269 + enum ipa_reg_rout_hash_field_id { 270 + IPV6_ROUTER_HASH, 271 + IPV6_FILTER_HASH, 272 + IPV4_ROUTER_HASH, 273 + IPV4_FILTER_HASH, 274 + }; 190 275 191 - static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 192 - { 193 - if (version < IPA_VERSION_4_0) 194 - return 0x000008c; 195 - 196 - return 0x0000148; 197 - } 198 - 199 - static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 200 - { 201 - if (version < IPA_VERSION_4_0) 202 - return 0x0000090; 203 - 204 - return 0x000014c; 205 - } 206 - 207 - /* The next four fields are used for the hash enable and flush registers */ 208 - #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 209 - #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 210 - #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 211 - #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 212 - 213 - /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 214 - static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 215 - { 216 - if (version < IPA_VERSION_4_0) 217 - return 0x0000010c; 218 - 219 - return 0x000000b4; 220 - } 221 - 222 - /* The next register is not present for IPA v4.5+ */ 223 - #define IPA_REG_BCR_OFFSET 0x000001d0 276 + /* BCR register */ 224 277 enum ipa_bcr_compat { 225 278 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 226 279 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ ··· 288 233 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 289 234 }; 290 235 291 - /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 292 - #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 236 + /* LOCAL_PKT_PROC_CNTXT register */ 237 + enum ipa_reg_local_pkt_proc_cntxt_field_id { 238 + IPA_BASE_ADDR, 239 + }; 293 240 294 - /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 295 - static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 296 - u32 addr) 297 - { 298 - if (version < IPA_VERSION_4_5) 299 - return u32_encode_bits(addr, GENMASK(16, 0)); 241 + /* COUNTER_CFG register */ 242 + enum ipa_reg_counter_cfg_field_id { 243 + EOT_COAL_GRANULARITY, /* Not v3.5+ */ 244 + AGGR_GRANULARITY, 245 + }; 300 246 301 - return u32_encode_bits(addr, GENMASK(17, 0)); 302 - } 247 + /* IPA_TX_CFG register */ 248 + enum ipa_reg_ipa_tx_cfg_field_id { 249 + TX0_PREFETCH_DISABLE, /* Not v4.0+ */ 250 + TX1_PREFETCH_DISABLE, /* Not v4.0+ */ 251 + PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ 252 + PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ 253 + DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ 254 + DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ 255 + DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ 256 + PA_MASK_EN, /* v4.0+ */ 257 + PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ 258 + DUAL_TX_ENABLE, /* v4.5+ */ 259 + SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ 260 + SSPND_PA_NO_BQ_STATE, /* v4.2 only */ 261 + }; 303 262 304 - /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 305 - #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 263 + /* FLAVOR_0 register */ 264 + enum ipa_reg_flavor_0_field_id { 265 + MAX_PIPES, 266 + MAX_CONS_PIPES, 267 + MAX_PROD_PIPES, 268 + PROD_LOWEST, 269 + }; 306 270 307 - /* The next register is not present for IPA v4.5+ */ 308 - #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 309 - /* The next field is not present for IPA v3.5+ */ 310 - #define EOT_COAL_GRANULARITY_FMASK GENMASK(3, 0) 311 - #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 271 + /* IDLE_INDICATION_CFG register */ 272 + enum ipa_reg_idle_indication_cfg_field_id { 273 + ENTER_IDLE_DEBOUNCE_THRESH, 274 + CONST_NON_IDLE_ENABLE, 275 + }; 312 276 313 - /* The next register is present for IPA v3.5+ */ 314 - #define IPA_REG_TX_CFG_OFFSET 0x000001fc 315 - /* The next three fields are not present for IPA v4.0+ */ 316 - #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 317 - #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 318 - #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 319 - /* The next six fields are present for IPA v4.0+ */ 320 - #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 321 - #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 322 - #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 323 - #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 324 - #define PA_MASK_EN_FMASK GENMASK(12, 12) 325 - #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 326 - /* The next field is present for IPA v4.5+ */ 327 - #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 328 - /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 329 - #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 330 - /* The next field is present for IPA v4.2 only */ 331 - #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 277 + /* QTIME_TIMESTAMP_CFG register */ 278 + enum ipa_reg_qtime_timestamp_cfg_field_id { 279 + DPL_TIMESTAMP_LSB, 280 + DPL_TIMESTAMP_SEL, 281 + TAG_TIMESTAMP_LSB, 282 + NAT_TIMESTAMP_LSB, 283 + }; 332 284 333 - /* The next register is present for IPA v3.5+ */ 334 - #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 335 - #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 336 - #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 337 - #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 338 - #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 285 + /* TIMERS_XO_CLK_DIV_CFG register */ 286 + enum ipa_reg_timers_xo_clk_div_cfg_field_id { 287 + DIV_VALUE, 288 + DIV_ENABLE, 289 + }; 339 290 340 - /* The next register is present for IPA v3.5+ */ 341 - static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 342 - { 343 - if (version >= IPA_VERSION_4_2) 344 - return 0x00000240; 291 + /* TIMERS_PULSE_GRAN_CFG register */ 292 + enum ipa_reg_timers_pulse_gran_cfg_field_id { 293 + PULSE_GRAN_0, 294 + PULSE_GRAN_1, 295 + PULSE_GRAN_2, 296 + }; 345 297 346 - return 0x00000220; 347 - } 348 - 349 - #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 350 - #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 351 - 352 - /* The next register is present for IPA v4.5+ */ 353 - #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 354 - #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 355 - #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 356 - #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 357 - #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 358 - 359 - /* The next register is present for IPA v4.5+ */ 360 - #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 361 - #define DIV_VALUE_FMASK GENMASK(8, 0) 362 - #define DIV_ENABLE_FMASK GENMASK(31, 31) 363 - 364 - /* The next register is present for IPA v4.5+ */ 365 - #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 366 - #define GRAN_0_FMASK GENMASK(2, 0) 367 - #define GRAN_1_FMASK GENMASK(5, 3) 368 - #define GRAN_2_FMASK GENMASK(8, 6) 369 - /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 298 + /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 370 299 enum ipa_pulse_gran { 371 300 IPA_GRAN_10_US = 0x0, 372 301 IPA_GRAN_20_US = 0x1, ··· 362 323 IPA_GRAN_655350_US = 0x7, 363 324 }; 364 325 365 - /* Not all of the following are present (depends on IPA version) */ 366 - #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 367 - (0x00000400 + 0x0020 * (rt)) 368 - #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 369 - (0x00000404 + 0x0020 * (rt)) 370 - #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 371 - (0x00000408 + 0x0020 * (rt)) 372 - #define IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 373 - (0x0000040c + 0x0020 * (rt)) 374 - #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 375 - (0x00000500 + 0x0020 * (rt)) 376 - #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 377 - (0x00000504 + 0x0020 * (rt)) 378 - #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 379 - (0x00000508 + 0x0020 * (rt)) 380 - #define IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 381 - (0x0000050c + 0x0020 * (rt)) 382 - /* The next four fields are used for all resource group registers */ 383 - #define X_MIN_LIM_FMASK GENMASK(5, 0) 384 - #define X_MAX_LIM_FMASK GENMASK(13, 8) 385 - /* The next two fields are not always present (if resource count is odd) */ 386 - #define Y_MIN_LIM_FMASK GENMASK(21, 16) 387 - #define Y_MAX_LIM_FMASK GENMASK(29, 24) 326 + /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 327 + enum ipa_reg_rsrc_grp_rsrc_type_field_id { 328 + X_MIN_LIM, 329 + X_MAX_LIM, 330 + Y_MIN_LIM, 331 + Y_MAX_LIM, 332 + }; 388 333 389 - #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 390 - (0x00000800 + 0x0070 * (ep)) 391 - /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 392 - #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 393 - /* Valid only for TX (IPA consumer) endpoints */ 394 - #define ENDP_DELAY_FMASK GENMASK(1, 1) 334 + /* ENDP_INIT_CTRL register */ 335 + enum ipa_reg_endp_init_ctrl_field_id { 336 + ENDP_SUSPEND, /* Not v4.0+ */ 337 + ENDP_DELAY, /* Not v4.2+ */ 338 + }; 395 339 396 - #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 397 - (0x00000808 + 0x0070 * (ep)) 398 - #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 399 - #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 400 - #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 401 - #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 340 + /* ENDP_INIT_CFG register */ 341 + enum ipa_reg_endp_init_cfg_field_id { 342 + FRAG_OFFLOAD_EN, 343 + CS_OFFLOAD_EN, 344 + CS_METADATA_HDR_OFFSET, 345 + CS_GEN_QMB_MASTER_SEL, 346 + }; 402 347 403 348 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 404 349 enum ipa_cs_offload_en { ··· 392 369 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 393 370 }; 394 371 395 - /* Valid only for TX (IPA consumer) endpoints */ 396 - #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 397 - (0x0000080c + 0x0070 * (ep)) 398 - #define NAT_EN_FMASK GENMASK(1, 0) 372 + /* ENDP_INIT_NAT register */ 373 + enum ipa_reg_endp_init_nat_field_id { 374 + NAT_EN, 375 + }; 399 376 400 377 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 401 378 enum ipa_nat_en { ··· 404 381 IPA_NAT_DST = 0x2, 405 382 }; 406 383 407 - #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 408 - (0x00000810 + 0x0070 * (ep)) 409 - #define HDR_LEN_FMASK GENMASK(5, 0) 410 - #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 411 - #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 412 - #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 413 - #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 414 - #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 415 - /* The next field is not present for IPA v4.9+ */ 416 - #define HDR_A5_MUX_FMASK GENMASK(26, 26) 417 - #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 418 - /* The next field is not present for IPA v4.5+ */ 419 - #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 420 - /* The next two fields are present for IPA v4.5+ */ 421 - #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 422 - #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 384 + /* ENDP_INIT_HDR register */ 385 + enum ipa_reg_endp_init_hdr_field_id { 386 + HDR_LEN, 387 + HDR_OFST_METADATA_VALID, 388 + HDR_OFST_METADATA, 389 + HDR_ADDITIONAL_CONST_LEN, 390 + HDR_OFST_PKT_SIZE_VALID, 391 + HDR_OFST_PKT_SIZE, 392 + HDR_A5_MUX, /* Not v4.9+ */ 393 + HDR_LEN_INC_DEAGG_HDR, 394 + HDR_METADATA_REG_VALID, /* Not v4.5+ */ 395 + HDR_LEN_MSB, /* v4.5+ */ 396 + HDR_OFST_METADATA_MSB, /* v4.5+ */ 397 + }; 423 398 424 - /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 425 - static inline u32 ipa_header_size_encoded(enum ipa_version version, 426 - u32 header_size) 427 - { 428 - u32 size = header_size & field_mask(HDR_LEN_FMASK); 429 - u32 val; 399 + /* ENDP_INIT_HDR_EXT register */ 400 + enum ipa_reg_endp_init_hdr_ext_field_id { 401 + HDR_ENDIANNESS, 402 + HDR_TOTAL_LEN_OR_PAD_VALID, 403 + HDR_TOTAL_LEN_OR_PAD, 404 + HDR_PAYLOAD_LEN_INC_PADDING, 405 + HDR_TOTAL_LEN_OR_PAD_OFFSET, 406 + HDR_PAD_TO_ALIGNMENT, 407 + HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ 408 + HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ 409 + HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ 410 + }; 430 411 431 - val = u32_encode_bits(size, HDR_LEN_FMASK); 432 - if (version < IPA_VERSION_4_5) { 433 - WARN_ON(header_size != size); 434 - return val; 435 - } 436 - 437 - /* IPA v4.5 adds a few more most-significant bits */ 438 - size = header_size >> hweight32(HDR_LEN_FMASK); 439 - val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 440 - 441 - return val; 442 - } 443 - 444 - /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 445 - static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 446 - u32 offset) 447 - { 448 - u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 449 - u32 val; 450 - 451 - val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 452 - if (version < IPA_VERSION_4_5) { 453 - WARN_ON(offset != off); 454 - return val; 455 - } 456 - 457 - /* IPA v4.5 adds a few more most-significant bits */ 458 - off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 459 - val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 460 - 461 - return val; 462 - } 463 - 464 - #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 465 - (0x00000814 + 0x0070 * (ep)) 466 - #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 467 - #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 468 - #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 469 - #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 470 - #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 471 - #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 472 - /* The next three fields are present for IPA v4.5+ */ 473 - #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 474 - #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 475 - #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 476 - 477 - /* Valid only for RX (IPA producer) endpoints */ 478 - #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 479 - (0x00000818 + 0x0070 * (rxep)) 480 - 481 - /* Valid only for TX (IPA consumer) endpoints */ 482 - #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 483 - (0x00000820 + 0x0070 * (txep)) 484 - #define MODE_FMASK GENMASK(2, 0) 485 - /* The next field is present for IPA v4.5+ */ 486 - #define DCPH_ENABLE_FMASK GENMASK(3, 3) 487 - #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 488 - #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 489 - #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 490 - #define PAD_EN_FMASK GENMASK(29, 29) 491 - /* The next field is not present for IPA v4.5+ */ 492 - #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 493 - /* The next field is present for IPA v4.9+ */ 494 - #define DRBIP_ACL_ENABLE_FMASK GENMASK(30, 30) 412 + /* ENDP_INIT_MODE register */ 413 + enum ipa_reg_endp_init_mode_field_id { 414 + ENDP_MODE, 415 + DCPH_ENABLE, /* v4.5+ */ 416 + DEST_PIPE_INDEX, 417 + BYTE_THRESHOLD, 418 + PIPE_REPLICATION_EN, 419 + PAD_EN, 420 + HDR_FTCH_DISABLE, /* v4.5+ */ 421 + DRBIP_ACL_ENABLE, /* v4.9+ */ 422 + }; 495 423 496 424 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 497 425 enum ipa_mode { ··· 452 478 IPA_DMA = 0x3, 453 479 }; 454 480 455 - #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 456 - (0x00000824 + 0x0070 * (ep)) 457 - #define AGGR_EN_FMASK GENMASK(1, 0) 458 - #define AGGR_TYPE_FMASK GENMASK(4, 2) 459 - 460 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 461 - static inline u32 aggr_byte_limit_fmask(bool legacy) 462 - { 463 - return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 464 - } 465 - 466 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 467 - static inline u32 aggr_time_limit_fmask(bool legacy) 468 - { 469 - return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 470 - } 471 - 472 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 473 - static inline u32 aggr_pkt_limit_fmask(bool legacy) 474 - { 475 - return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 476 - } 477 - 478 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 479 - static inline u32 aggr_sw_eof_active_fmask(bool legacy) 480 - { 481 - return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 482 - } 483 - 484 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 485 - static inline u32 aggr_force_close_fmask(bool legacy) 486 - { 487 - return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 488 - } 489 - 490 - /* The legacy value is used for IPA hardware before IPA v4.5 */ 491 - static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 492 - { 493 - return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 494 - } 495 - 496 - /* The next field is present for IPA v4.5+ */ 497 - #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 481 + /* ENDP_INIT_AGGR register */ 482 + enum ipa_reg_endp_init_aggr_field_id { 483 + AGGR_EN, 484 + AGGR_TYPE, 485 + BYTE_LIMIT, 486 + TIME_LIMIT, 487 + PKT_LIMIT, 488 + SW_EOF_ACTIVE, 489 + FORCE_CLOSE, 490 + HARD_BYTE_LIMIT_EN, 491 + AGGR_GRAN_SEL, 492 + }; 498 493 499 494 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 500 495 enum ipa_aggr_en { ··· 483 540 IPA_QCMAP = 0x6, 484 541 }; 485 542 486 - /* Valid only for RX (IPA producer) endpoints */ 487 - #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 488 - (0x0000082c + 0x0070 * (rxep)) 489 - #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 543 + /* ENDP_INIT_HOL_BLOCK_EN register */ 544 + enum ipa_reg_endp_init_hol_block_en_field_id { 545 + HOL_BLOCK_EN, 546 + }; 490 547 491 - /* Valid only for RX (IPA producer) endpoints */ 492 - #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 493 - (0x00000830 + 0x0070 * (rxep)) 494 - /* The next two fields are present for IPA v4.2 only */ 495 - #define BASE_VALUE_FMASK GENMASK(4, 0) 496 - #define SCALE_FMASK GENMASK(12, 8) 497 - /* The next two fields are present for IPA v4.5 */ 498 - #define TIME_LIMIT_FMASK GENMASK(4, 0) 499 - #define GRAN_SEL_FMASK GENMASK(8, 8) 548 + /* ENDP_INIT_HOL_BLOCK_TIMER register */ 549 + enum ipa_reg_endp_init_hol_block_timer_field_id { 550 + TIMER_BASE_VALUE, /* Not v4.5+ */ 551 + TIMER_SCALE, /* v4.2 only */ 552 + TIMER_LIMIT, /* v4.5+ */ 553 + TIMER_GRAN_SEL, /* v4.5+ */ 554 + }; 500 555 501 - /* Valid only for TX (IPA consumer) endpoints */ 502 - #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 503 - (0x00000834 + 0x0070 * (txep)) 504 - #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 505 - #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 506 - #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 507 - #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 508 - #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 509 - #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 556 + /* ENDP_INIT_DEAGGR register */ 557 + enum ipa_reg_endp_deaggr_field_id { 558 + DEAGGR_HDR_LEN, 559 + SYSPIPE_ERR_DETECTION, 560 + PACKET_OFFSET_VALID, 561 + PACKET_OFFSET_LOCATION, 562 + IGNORE_MIN_PKT_ERR, 563 + MAX_PACKET_LEN, 564 + }; 510 565 511 - #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 512 - (0x00000838 + 0x0070 * (ep)) 513 - /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 514 - static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 515 - { 516 - if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 517 - return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 566 + /* ENDP_INIT_RSRC_GRP register */ 567 + enum ipa_reg_endp_init_rsrc_grp_field_id { 568 + ENDP_RSRC_GRP, 569 + }; 518 570 519 - if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 520 - return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 521 - 522 - return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 523 - } 524 - 525 - /* Valid only for TX (IPA consumer) endpoints */ 526 - #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 527 - (0x0000083c + 0x0070 * (txep)) 528 - #define SEQ_TYPE_FMASK GENMASK(7, 0) 529 - /* The next field must be zero for IPA v4.5+ */ 530 - #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 571 + /* ENDP_INIT_SEQ register */ 572 + enum ipa_reg_endp_init_seq_field_id { 573 + SEQ_TYPE, 574 + SEQ_REP_TYPE, /* Not v4.5+ */ 575 + }; 531 576 532 577 /** 533 578 * enum ipa_seq_type - HPS and DPS sequencer type ··· 559 628 IPA_SEQ_REP_DMA_PARSER = 0x08, 560 629 }; 561 630 562 - #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 563 - (0x00000840 + 0x0070 * (ep)) 564 - #define STATUS_EN_FMASK GENMASK(0, 0) 565 - #define STATUS_ENDP_FMASK GENMASK(5, 1) 566 - /* The next field is not present for IPA v4.5+ */ 567 - #define STATUS_LOCATION_FMASK GENMASK(8, 8) 568 - /* The next field is present for IPA v4.0+ */ 569 - #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 631 + /* ENDP_STATUS register */ 632 + enum ipa_reg_endp_status_field_id { 633 + STATUS_EN, 634 + STATUS_ENDP, 635 + STATUS_LOCATION, /* Not v4.5+ */ 636 + STATUS_PKT_SUPPRESS, /* v4.0+ */ 637 + }; 570 638 571 - /* The next register is not present for IPA v4.2 (which no hashing support) */ 572 - #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 573 - (0x0000085c + 0x0070 * (er)) 574 - #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 575 - #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 576 - #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 577 - #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 578 - #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 579 - #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 580 - #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 581 - #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 639 + /* ENDP_FILTER_ROUTER_HSH_CFG register */ 640 + enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 641 + FILTER_HASH_MSK_SRC_ID, 642 + FILTER_HASH_MSK_SRC_IP, 643 + FILTER_HASH_MSK_DST_IP, 644 + FILTER_HASH_MSK_SRC_PORT, 645 + FILTER_HASH_MSK_DST_PORT, 646 + FILTER_HASH_MSK_PROTOCOL, 647 + FILTER_HASH_MSK_METADATA, 648 + FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 582 649 583 - #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 584 - #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 585 - #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 586 - #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 587 - #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 588 - #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 589 - #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 590 - #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 650 + ROUTER_HASH_MSK_SRC_ID, 651 + ROUTER_HASH_MSK_SRC_IP, 652 + ROUTER_HASH_MSK_DST_IP, 653 + ROUTER_HASH_MSK_SRC_PORT, 654 + ROUTER_HASH_MSK_DST_PORT, 655 + ROUTER_HASH_MSK_PROTOCOL, 656 + ROUTER_HASH_MSK_METADATA, 657 + ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 658 + }; 591 659 592 - static inline u32 ipa_reg_irq_stts_ee_n_offset(enum ipa_version version, 593 - u32 ee) 594 - { 595 - if (version < IPA_VERSION_4_9) 596 - return 0x00003008 + 0x1000 * ee; 597 - 598 - return 0x00004008 + 0x1000 * ee; 599 - } 600 - 601 - static inline u32 ipa_reg_irq_stts_offset(enum ipa_version version) 602 - { 603 - return ipa_reg_irq_stts_ee_n_offset(version, GSI_EE_AP); 604 - } 605 - 606 - static inline u32 ipa_reg_irq_en_ee_n_offset(enum ipa_version version, u32 ee) 607 - { 608 - if (version < IPA_VERSION_4_9) 609 - return 0x0000300c + 0x1000 * ee; 610 - 611 - return 0x0000400c + 0x1000 * ee; 612 - } 613 - 614 - static inline u32 ipa_reg_irq_en_offset(enum ipa_version version) 615 - { 616 - return ipa_reg_irq_en_ee_n_offset(version, GSI_EE_AP); 617 - } 618 - 619 - static inline u32 ipa_reg_irq_clr_ee_n_offset(enum ipa_version version, u32 ee) 620 - { 621 - if (version < IPA_VERSION_4_9) 622 - return 0x00003010 + 0x1000 * ee; 623 - 624 - return 0x00004010 + 0x1000 * ee; 625 - } 626 - 627 - static inline u32 ipa_reg_irq_clr_offset(enum ipa_version version) 628 - { 629 - return ipa_reg_irq_clr_ee_n_offset(version, GSI_EE_AP); 630 - } 631 - 660 + /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 632 661 /** 633 662 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 634 663 * @IPA_IRQ_UC_0: Microcontroller event interrupt ··· 664 773 IPA_IRQ_COUNT, /* Last; not an id */ 665 774 }; 666 775 667 - static inline u32 ipa_reg_irq_uc_ee_n_offset(enum ipa_version version, u32 ee) 668 - { 669 - if (version < IPA_VERSION_4_9) 670 - return 0x0000301c + 0x1000 * ee; 776 + /* IPA_IRQ_UC register */ 777 + enum ipa_reg_ipa_irq_uc_field_id { 778 + UC_INTR, 779 + }; 671 780 672 - return 0x0000401c + 0x1000 * ee; 781 + extern const struct ipa_regs ipa_regs_v3_1; 782 + extern const struct ipa_regs ipa_regs_v3_5_1; 783 + extern const struct ipa_regs ipa_regs_v4_2; 784 + extern const struct ipa_regs ipa_regs_v4_5; 785 + extern const struct ipa_regs ipa_regs_v4_9; 786 + extern const struct ipa_regs ipa_regs_v4_11; 787 + 788 + /* Return the field mask for a field in a register */ 789 + static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) 790 + { 791 + if (!reg || WARN_ON(field_id >= reg->fcount)) 792 + return 0; 793 + 794 + return reg->fmask[field_id]; 673 795 } 674 796 675 - static inline u32 ipa_reg_irq_uc_offset(enum ipa_version version) 797 + /* Return the mask for a single-bit field in a register */ 798 + static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) 676 799 { 677 - return ipa_reg_irq_uc_ee_n_offset(version, GSI_EE_AP); 800 + u32 fmask = ipa_reg_fmask(reg, field_id); 801 + 802 + WARN_ON(!is_power_of_2(fmask)); 803 + 804 + return fmask; 678 805 } 679 806 680 - #define UC_INTR_FMASK GENMASK(0, 0) 681 - 682 - /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 807 + /* Encode a value into the given field of a register */ 683 808 static inline u32 684 - ipa_reg_irq_suspend_info_ee_n_offset(enum ipa_version version, u32 ee) 809 + ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) 685 810 { 686 - if (version == IPA_VERSION_3_0) 687 - return 0x00003098 + 0x1000 * ee; 811 + u32 fmask = ipa_reg_fmask(reg, field_id); 688 812 689 - if (version < IPA_VERSION_4_9) 690 - return 0x00003030 + 0x1000 * ee; 813 + if (!fmask) 814 + return 0; 691 815 692 - return 0x00004030 + 0x1000 * ee; 816 + val <<= __ffs(fmask); 817 + if (WARN_ON(val & ~fmask)) 818 + return 0; 819 + 820 + return val; 693 821 } 694 822 823 + /* Given a register value, decode (extract) the value in the given field */ 695 824 static inline u32 696 - ipa_reg_irq_suspend_info_offset(enum ipa_version version) 825 + ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) 697 826 { 698 - return ipa_reg_irq_suspend_info_ee_n_offset(version, GSI_EE_AP); 827 + u32 fmask = ipa_reg_fmask(reg, field_id); 828 + 829 + return fmask ? (val & fmask) >> __ffs(fmask) : 0; 699 830 } 700 831 701 - /* ipa->available defines the valid bits in the SUSPEND_EN register */ 702 - static inline u32 703 - ipa_reg_irq_suspend_en_ee_n_offset(enum ipa_version version, u32 ee) 832 + /* Return the maximum value representable by the given field; always 2^n - 1 */ 833 + static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) 704 834 { 705 - WARN_ON(version == IPA_VERSION_3_0); 835 + u32 fmask = ipa_reg_fmask(reg, field_id); 706 836 707 - if (version < IPA_VERSION_4_9) 708 - return 0x00003034 + 0x1000 * ee; 709 - 710 - return 0x00004034 + 0x1000 * ee; 837 + return fmask ? fmask >> __ffs(fmask) : 0; 711 838 } 712 839 713 - static inline u32 714 - ipa_reg_irq_suspend_en_offset(enum ipa_version version) 840 + const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 841 + 842 + /* Returns 0 for NULL reg; warning will have already been issued */ 843 + static inline u32 ipa_reg_offset(const struct ipa_reg *reg) 715 844 { 716 - return ipa_reg_irq_suspend_en_ee_n_offset(version, GSI_EE_AP); 845 + return reg ? reg->offset : 0; 717 846 } 718 847 719 - /* ipa->available defines the valid bits in the SUSPEND_CLR register */ 720 - static inline u32 721 - ipa_reg_irq_suspend_clr_ee_n_offset(enum ipa_version version, u32 ee) 848 + /* Returns 0 for NULL reg; warning will have already been issued */ 849 + static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) 722 850 { 723 - WARN_ON(version == IPA_VERSION_3_0); 724 - 725 - if (version < IPA_VERSION_4_9) 726 - return 0x00003038 + 0x1000 * ee; 727 - 728 - return 0x00004038 + 0x1000 * ee; 729 - } 730 - 731 - static inline u32 732 - ipa_reg_irq_suspend_clr_offset(enum ipa_version version) 733 - { 734 - return ipa_reg_irq_suspend_clr_ee_n_offset(version, GSI_EE_AP); 851 + return reg ? reg->offset + n * reg->stride : 0; 735 852 } 736 853 737 854 int ipa_reg_init(struct ipa *ipa);
+33 -30
drivers/net/ipa/ipa_resource.c
··· 69 69 } 70 70 71 71 static void 72 - ipa_resource_config_common(struct ipa *ipa, u32 offset, 72 + ipa_resource_config_common(struct ipa *ipa, u32 resource_type, 73 + const struct ipa_reg *reg, 73 74 const struct ipa_resource_limits *xlimits, 74 75 const struct ipa_resource_limits *ylimits) 75 76 { 76 77 u32 val; 77 78 78 - val = u32_encode_bits(xlimits->min, X_MIN_LIM_FMASK); 79 - val |= u32_encode_bits(xlimits->max, X_MAX_LIM_FMASK); 79 + val = ipa_reg_encode(reg, X_MIN_LIM, xlimits->min); 80 + val |= ipa_reg_encode(reg, X_MAX_LIM, xlimits->max); 80 81 if (ylimits) { 81 - val |= u32_encode_bits(ylimits->min, Y_MIN_LIM_FMASK); 82 - val |= u32_encode_bits(ylimits->max, Y_MAX_LIM_FMASK); 82 + val |= ipa_reg_encode(reg, Y_MIN_LIM, ylimits->min); 83 + val |= ipa_reg_encode(reg, Y_MAX_LIM, ylimits->max); 83 84 } 84 85 85 - iowrite32(val, ipa->reg_virt + offset); 86 + iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, resource_type)); 86 87 } 87 88 88 89 static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type, ··· 92 91 u32 group_count = data->rsrc_group_src_count; 93 92 const struct ipa_resource_limits *ylimits; 94 93 const struct ipa_resource *resource; 95 - u32 offset; 94 + const struct ipa_reg *reg; 96 95 97 96 resource = &data->resource_src[resource_type]; 98 97 99 - offset = IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(resource_type); 98 + reg = ipa_reg(ipa, SRC_RSRC_GRP_01_RSRC_TYPE); 100 99 ylimits = group_count == 1 ? NULL : &resource->limits[1]; 101 - ipa_resource_config_common(ipa, offset, &resource->limits[0], ylimits); 102 - 100 + ipa_resource_config_common(ipa, resource_type, reg, 101 + &resource->limits[0], ylimits); 103 102 if (group_count < 3) 104 103 return; 105 104 106 - offset = IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(resource_type); 105 + reg = ipa_reg(ipa, SRC_RSRC_GRP_23_RSRC_TYPE); 107 106 ylimits = group_count == 3 ? NULL : &resource->limits[3]; 108 - ipa_resource_config_common(ipa, offset, &resource->limits[2], ylimits); 109 - 107 + ipa_resource_config_common(ipa, resource_type, reg, 108 + &resource->limits[2], ylimits); 110 109 if (group_count < 5) 111 110 return; 112 111 113 - offset = IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(resource_type); 112 + reg = ipa_reg(ipa, SRC_RSRC_GRP_45_RSRC_TYPE); 114 113 ylimits = group_count == 5 ? NULL : &resource->limits[5]; 115 - ipa_resource_config_common(ipa, offset, &resource->limits[4], ylimits); 116 - 114 + ipa_resource_config_common(ipa, resource_type, reg, 115 + &resource->limits[4], ylimits); 117 116 if (group_count < 7) 118 117 return; 119 118 120 - offset = IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(resource_type); 119 + reg = ipa_reg(ipa, SRC_RSRC_GRP_67_RSRC_TYPE); 121 120 ylimits = group_count == 7 ? NULL : &resource->limits[7]; 122 - ipa_resource_config_common(ipa, offset, &resource->limits[6], ylimits); 121 + ipa_resource_config_common(ipa, resource_type, reg, 122 + &resource->limits[6], ylimits); 123 123 } 124 124 125 125 static void ipa_resource_config_dst(struct ipa *ipa, u32 resource_type, ··· 129 127 u32 group_count = data->rsrc_group_dst_count; 130 128 const struct ipa_resource_limits *ylimits; 131 129 const struct ipa_resource *resource; 132 - u32 offset; 130 + const struct ipa_reg *reg; 133 131 134 132 resource = &data->resource_dst[resource_type]; 135 133 136 - offset = IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(resource_type); 134 + reg = ipa_reg(ipa, DST_RSRC_GRP_01_RSRC_TYPE); 137 135 ylimits = group_count == 1 ? NULL : &resource->limits[1]; 138 - ipa_resource_config_common(ipa, offset, &resource->limits[0], ylimits); 139 - 136 + ipa_resource_config_common(ipa, resource_type, reg, 137 + &resource->limits[0], ylimits); 140 138 if (group_count < 3) 141 139 return; 142 140 143 - offset = IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(resource_type); 141 + reg = ipa_reg(ipa, DST_RSRC_GRP_23_RSRC_TYPE); 144 142 ylimits = group_count == 3 ? NULL : &resource->limits[3]; 145 - ipa_resource_config_common(ipa, offset, &resource->limits[2], ylimits); 146 - 143 + ipa_resource_config_common(ipa, resource_type, reg, 144 + &resource->limits[2], ylimits); 147 145 if (group_count < 5) 148 146 return; 149 147 150 - offset = IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(resource_type); 148 + reg = ipa_reg(ipa, DST_RSRC_GRP_45_RSRC_TYPE); 151 149 ylimits = group_count == 5 ? NULL : &resource->limits[5]; 152 - ipa_resource_config_common(ipa, offset, &resource->limits[4], ylimits); 153 - 150 + ipa_resource_config_common(ipa, resource_type, reg, 151 + &resource->limits[4], ylimits); 154 152 if (group_count < 7) 155 153 return; 156 154 157 - offset = IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(resource_type); 155 + reg = ipa_reg(ipa, DST_RSRC_GRP_67_RSRC_TYPE); 158 156 ylimits = group_count == 7 ? NULL : &resource->limits[7]; 159 - ipa_resource_config_common(ipa, offset, &resource->limits[6], ylimits); 157 + ipa_resource_config_common(ipa, resource_type, reg, 158 + &resource->limits[6], ylimits); 160 159 } 161 160 162 161 /* Configure resources; there is no ipa_resource_deconfig() */
+20 -7
drivers/net/ipa/ipa_table.c
··· 384 384 385 385 int ipa_table_hash_flush(struct ipa *ipa) 386 386 { 387 - u32 offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version); 387 + const struct ipa_reg *reg; 388 388 struct gsi_trans *trans; 389 + u32 offset; 389 390 u32 val; 390 391 391 392 if (!ipa_table_hash_support(ipa)) ··· 398 397 return -EBUSY; 399 398 } 400 399 401 - val = IPV4_FILTER_HASH_FMASK | IPV6_FILTER_HASH_FMASK; 402 - val |= IPV6_ROUTER_HASH_FMASK | IPV4_ROUTER_HASH_FMASK; 400 + reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); 401 + offset = ipa_reg_offset(reg); 402 + 403 + val = ipa_reg_bit(reg, IPV6_ROUTER_HASH); 404 + val |= ipa_reg_bit(reg, IPV6_FILTER_HASH); 405 + val |= ipa_reg_bit(reg, IPV4_ROUTER_HASH); 406 + val |= ipa_reg_bit(reg, IPV4_FILTER_HASH); 403 407 404 408 ipa_cmd_register_write_add(trans, offset, val, val, false); 405 409 ··· 522 516 static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint) 523 517 { 524 518 u32 endpoint_id = endpoint->endpoint_id; 519 + struct ipa *ipa = endpoint->ipa; 520 + const struct ipa_reg *reg; 525 521 u32 offset; 526 522 u32 val; 527 523 528 - offset = IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(endpoint_id); 524 + reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); 529 525 526 + offset = ipa_reg_n_offset(reg, endpoint_id); 530 527 val = ioread32(endpoint->ipa->reg_virt + offset); 531 528 532 529 /* Zero all filter-related fields, preserving the rest */ 533 - val &= ~IPA_REG_ENDP_FILTER_HASH_MSK_ALL; 530 + val &= ~ipa_reg_fmask(reg, FILTER_HASH_MSK_ALL); 534 531 535 532 iowrite32(val, endpoint->ipa->reg_virt + offset); 536 533 } ··· 574 565 */ 575 566 static void ipa_route_tuple_zero(struct ipa *ipa, u32 route_id) 576 567 { 577 - u32 offset = IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(route_id); 568 + const struct ipa_reg *reg; 569 + u32 offset; 578 570 u32 val; 571 + 572 + reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); 573 + offset = ipa_reg_n_offset(reg, route_id); 579 574 580 575 val = ioread32(ipa->reg_virt + offset); 581 576 582 577 /* Zero all route-related fields, preserving the rest */ 583 - val &= ~IPA_REG_ENDP_ROUTER_HASH_MSK_ALL; 578 + val &= ~ipa_reg_fmask(reg, ROUTER_HASH_MSK_ALL); 584 579 585 580 iowrite32(val, ipa->reg_virt + offset); 586 581 }
+5 -4
drivers/net/ipa/ipa_uc.c
··· 222 222 static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param) 223 223 { 224 224 struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); 225 - u32 offset; 225 + const struct ipa_reg *reg; 226 226 u32 val; 227 227 228 228 /* Fill in the command data */ ··· 233 233 shared->response_param = 0; 234 234 235 235 /* Use an interrupt to tell the microcontroller the command is ready */ 236 - val = u32_encode_bits(1, UC_INTR_FMASK); 237 - offset = ipa_reg_irq_uc_offset(ipa->version); 238 - iowrite32(val, ipa->reg_virt + offset); 236 + reg = ipa_reg(ipa, IPA_IRQ_UC); 237 + val = ipa_reg_bit(reg, UC_INTR); 238 + 239 + iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); 239 240 } 240 241 241 242 /* Tell the microcontroller the AP is shutting down */
+478
drivers/net/ipa/reg/ipa_reg-v3.1.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + [COMP_CFG_ENABLE] = BIT(0), 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 + /* Bits 5-31 reserved */ 17 + }; 18 + 19 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 20 + 21 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 22 + [CLKON_RX] = BIT(0), 23 + [CLKON_PROC] = BIT(1), 24 + [TX_WRAPPER] = BIT(2), 25 + [CLKON_MISC] = BIT(3), 26 + [RAM_ARB] = BIT(4), 27 + [FTCH_HPS] = BIT(5), 28 + [FTCH_DPS] = BIT(6), 29 + [CLKON_HPS] = BIT(7), 30 + [CLKON_DPS] = BIT(8), 31 + [RX_HPS_CMDQS] = BIT(9), 32 + [HPS_DPS_CMDQS] = BIT(10), 33 + [DPS_TX_CMDQS] = BIT(11), 34 + [RSRC_MNGR] = BIT(12), 35 + [CTX_HANDLER] = BIT(13), 36 + [ACK_MNGR] = BIT(14), 37 + [D_DCPH] = BIT(15), 38 + [H_DCPH] = BIT(16), 39 + /* Bits 17-31 reserved */ 40 + }; 41 + 42 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 43 + 44 + static const u32 ipa_reg_route_fmask[] = { 45 + [ROUTE_DIS] = BIT(0), 46 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 47 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 48 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 49 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 50 + /* Bits 22-23 reserved */ 51 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 52 + /* Bits 25-31 reserved */ 53 + }; 54 + 55 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 56 + 57 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 58 + [MEM_SIZE] = GENMASK(15, 0), 59 + [MEM_BADDR] = GENMASK(31, 16), 60 + }; 61 + 62 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 63 + 64 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 65 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 66 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 67 + /* Bits 8-31 reserved */ 68 + }; 69 + 70 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 71 + 72 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 73 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 74 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 75 + }; 76 + 77 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 78 + 79 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 80 + [IPV6_ROUTER_HASH] = BIT(0), 81 + /* Bits 1-3 reserved */ 82 + [IPV6_FILTER_HASH] = BIT(4), 83 + /* Bits 5-7 reserved */ 84 + [IPV4_ROUTER_HASH] = BIT(8), 85 + /* Bits 9-11 reserved */ 86 + [IPV4_FILTER_HASH] = BIT(12), 87 + /* Bits 13-31 reserved */ 88 + }; 89 + 90 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 91 + 92 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 93 + [IPV6_ROUTER_HASH] = BIT(0), 94 + /* Bits 1-3 reserved */ 95 + [IPV6_FILTER_HASH] = BIT(4), 96 + /* Bits 5-7 reserved */ 97 + [IPV4_ROUTER_HASH] = BIT(8), 98 + /* Bits 9-11 reserved */ 99 + [IPV4_FILTER_HASH] = BIT(12), 100 + /* Bits 13-31 reserved */ 101 + }; 102 + 103 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 104 + 105 + /* Valid bits defined by ipa->available */ 106 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); 107 + 108 + IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); 109 + 110 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 111 + [IPA_BASE_ADDR] = GENMASK(16, 0), 112 + /* Bits 17-31 reserved */ 113 + }; 114 + 115 + /* Offset must be a multiple of 8 */ 116 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 117 + 118 + /* Valid bits defined by ipa->available */ 119 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 120 + 121 + static const u32 ipa_reg_counter_cfg_fmask[] = { 122 + [EOT_COAL_GRANULARITY] = GENMASK(3, 0), 123 + [AGGR_GRANULARITY] = GENMASK(8, 4), 124 + /* Bits 5-31 reserved */ 125 + }; 126 + 127 + IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 128 + 129 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 130 + [X_MIN_LIM] = GENMASK(5, 0), 131 + /* Bits 6-7 reserved */ 132 + [X_MAX_LIM] = GENMASK(13, 8), 133 + /* Bits 14-15 reserved */ 134 + [Y_MIN_LIM] = GENMASK(21, 16), 135 + /* Bits 22-23 reserved */ 136 + [Y_MAX_LIM] = GENMASK(29, 24), 137 + /* Bits 30-31 reserved */ 138 + }; 139 + 140 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 141 + 0x00000400, 0x0020); 142 + 143 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 144 + [X_MIN_LIM] = GENMASK(5, 0), 145 + /* Bits 6-7 reserved */ 146 + [X_MAX_LIM] = GENMASK(13, 8), 147 + /* Bits 14-15 reserved */ 148 + [Y_MIN_LIM] = GENMASK(21, 16), 149 + /* Bits 22-23 reserved */ 150 + [Y_MAX_LIM] = GENMASK(29, 24), 151 + /* Bits 30-31 reserved */ 152 + }; 153 + 154 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 155 + 0x00000404, 0x0020); 156 + 157 + static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 158 + [X_MIN_LIM] = GENMASK(5, 0), 159 + /* Bits 6-7 reserved */ 160 + [X_MAX_LIM] = GENMASK(13, 8), 161 + /* Bits 14-15 reserved */ 162 + [Y_MIN_LIM] = GENMASK(21, 16), 163 + /* Bits 22-23 reserved */ 164 + [Y_MAX_LIM] = GENMASK(29, 24), 165 + /* Bits 30-31 reserved */ 166 + }; 167 + 168 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 169 + 0x00000408, 0x0020); 170 + 171 + static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 172 + [X_MIN_LIM] = GENMASK(5, 0), 173 + /* Bits 6-7 reserved */ 174 + [X_MAX_LIM] = GENMASK(13, 8), 175 + /* Bits 14-15 reserved */ 176 + [Y_MIN_LIM] = GENMASK(21, 16), 177 + /* Bits 22-23 reserved */ 178 + [Y_MAX_LIM] = GENMASK(29, 24), 179 + /* Bits 30-31 reserved */ 180 + }; 181 + 182 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 183 + 0x0000040c, 0x0020); 184 + 185 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 186 + [X_MIN_LIM] = GENMASK(5, 0), 187 + /* Bits 6-7 reserved */ 188 + [X_MAX_LIM] = GENMASK(13, 8), 189 + /* Bits 14-15 reserved */ 190 + [Y_MIN_LIM] = GENMASK(21, 16), 191 + /* Bits 22-23 reserved */ 192 + [Y_MAX_LIM] = GENMASK(29, 24), 193 + /* Bits 30-31 reserved */ 194 + }; 195 + 196 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 197 + 0x00000500, 0x0020); 198 + 199 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 200 + [X_MIN_LIM] = GENMASK(5, 0), 201 + /* Bits 6-7 reserved */ 202 + [X_MAX_LIM] = GENMASK(13, 8), 203 + /* Bits 14-15 reserved */ 204 + [Y_MIN_LIM] = GENMASK(21, 16), 205 + /* Bits 22-23 reserved */ 206 + [Y_MAX_LIM] = GENMASK(29, 24), 207 + /* Bits 30-31 reserved */ 208 + }; 209 + 210 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 211 + 0x00000504, 0x0020); 212 + 213 + static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 214 + [X_MIN_LIM] = GENMASK(5, 0), 215 + /* Bits 6-7 reserved */ 216 + [X_MAX_LIM] = GENMASK(13, 8), 217 + /* Bits 14-15 reserved */ 218 + [Y_MIN_LIM] = GENMASK(21, 16), 219 + /* Bits 22-23 reserved */ 220 + [Y_MAX_LIM] = GENMASK(29, 24), 221 + /* Bits 30-31 reserved */ 222 + }; 223 + 224 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 225 + 0x00000508, 0x0020); 226 + 227 + static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 228 + [X_MIN_LIM] = GENMASK(5, 0), 229 + /* Bits 6-7 reserved */ 230 + [X_MAX_LIM] = GENMASK(13, 8), 231 + /* Bits 14-15 reserved */ 232 + [Y_MIN_LIM] = GENMASK(21, 16), 233 + /* Bits 22-23 reserved */ 234 + [Y_MAX_LIM] = GENMASK(29, 24), 235 + /* Bits 30-31 reserved */ 236 + }; 237 + 238 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 239 + 0x0000050c, 0x0020); 240 + 241 + static const u32 ipa_reg_endp_init_ctrl_fmask[] = { 242 + [ENDP_SUSPEND] = BIT(0), 243 + [ENDP_DELAY] = BIT(1), 244 + /* Bits 2-31 reserved */ 245 + }; 246 + 247 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 248 + 249 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 250 + [FRAG_OFFLOAD_EN] = BIT(0), 251 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 252 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 253 + /* Bit 7 reserved */ 254 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 255 + /* Bits 9-31 reserved */ 256 + }; 257 + 258 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 259 + 260 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 261 + [NAT_EN] = GENMASK(1, 0), 262 + /* Bits 2-31 reserved */ 263 + }; 264 + 265 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 266 + 267 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 268 + [HDR_LEN] = GENMASK(5, 0), 269 + [HDR_OFST_METADATA_VALID] = BIT(6), 270 + [HDR_OFST_METADATA] = GENMASK(12, 7), 271 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 272 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 273 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 274 + [HDR_A5_MUX] = BIT(26), 275 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 276 + [HDR_METADATA_REG_VALID] = BIT(28), 277 + /* Bits 29-31 reserved */ 278 + }; 279 + 280 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 281 + 282 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 283 + [HDR_ENDIANNESS] = BIT(0), 284 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 285 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 286 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 287 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 288 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 289 + /* Bits 14-31 reserved */ 290 + }; 291 + 292 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 293 + 294 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 295 + 0x00000818, 0x0070); 296 + 297 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 298 + [ENDP_MODE] = GENMASK(2, 0), 299 + /* Bit 3 reserved */ 300 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 301 + /* Bits 9-11 reserved */ 302 + [BYTE_THRESHOLD] = GENMASK(27, 12), 303 + [PIPE_REPLICATION_EN] = BIT(28), 304 + [PAD_EN] = BIT(29), 305 + [HDR_FTCH_DISABLE] = BIT(30), 306 + /* Bit 31 reserved */ 307 + }; 308 + 309 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 310 + 311 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 312 + [AGGR_EN] = GENMASK(1, 0), 313 + [AGGR_TYPE] = GENMASK(4, 2), 314 + [BYTE_LIMIT] = GENMASK(9, 5), 315 + [TIME_LIMIT] = GENMASK(14, 10), 316 + [PKT_LIMIT] = GENMASK(20, 15), 317 + [SW_EOF_ACTIVE] = BIT(21), 318 + [FORCE_CLOSE] = BIT(22), 319 + /* Bit 23 reserved */ 320 + [HARD_BYTE_LIMIT_EN] = BIT(24), 321 + /* Bits 25-31 reserved */ 322 + }; 323 + 324 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 325 + 326 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 327 + [HOL_BLOCK_EN] = BIT(0), 328 + /* Bits 1-31 reserved */ 329 + }; 330 + 331 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 332 + 0x0000082c, 0x0070); 333 + 334 + /* Entire register is a tick count */ 335 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 336 + [TIMER_BASE_VALUE] = GENMASK(31, 0), 337 + }; 338 + 339 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 340 + 0x00000830, 0x0070); 341 + 342 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 343 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 344 + [SYSPIPE_ERR_DETECTION] = BIT(6), 345 + [PACKET_OFFSET_VALID] = BIT(7), 346 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 347 + [IGNORE_MIN_PKT_ERR] = BIT(14), 348 + /* Bit 15 reserved */ 349 + [MAX_PACKET_LEN] = GENMASK(31, 16), 350 + }; 351 + 352 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 353 + 354 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 355 + [ENDP_RSRC_GRP] = GENMASK(2, 0), 356 + /* Bits 3-31 reserved */ 357 + }; 358 + 359 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 360 + 0x00000838, 0x0070); 361 + 362 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 363 + [SEQ_TYPE] = GENMASK(7, 0), 364 + [SEQ_REP_TYPE] = GENMASK(15, 8), 365 + /* Bits 16-31 reserved */ 366 + }; 367 + 368 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 369 + 370 + static const u32 ipa_reg_endp_status_fmask[] = { 371 + [STATUS_EN] = BIT(0), 372 + [STATUS_ENDP] = GENMASK(5, 1), 373 + /* Bits 6-7 reserved */ 374 + [STATUS_LOCATION] = BIT(8), 375 + /* Bits 9-31 reserved */ 376 + }; 377 + 378 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 379 + 380 + static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 381 + [FILTER_HASH_MSK_SRC_ID] = BIT(0), 382 + [FILTER_HASH_MSK_SRC_IP] = BIT(1), 383 + [FILTER_HASH_MSK_DST_IP] = BIT(2), 384 + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 385 + [FILTER_HASH_MSK_DST_PORT] = BIT(4), 386 + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 387 + [FILTER_HASH_MSK_METADATA] = BIT(6), 388 + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 389 + /* Bits 7-15 reserved */ 390 + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 391 + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 392 + [ROUTER_HASH_MSK_DST_IP] = BIT(18), 393 + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 394 + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 395 + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 396 + [ROUTER_HASH_MSK_METADATA] = BIT(22), 397 + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 398 + /* Bits 23-31 reserved */ 399 + }; 400 + 401 + IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 402 + 0x0000085c, 0x0070); 403 + 404 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 405 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 406 + 407 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 408 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 409 + 410 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 411 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 412 + 413 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 414 + [UC_INTR] = BIT(0), 415 + /* Bits 1-31 reserved */ 416 + }; 417 + 418 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 419 + 420 + /* Valid bits defined by ipa->available */ 421 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); 422 + 423 + /* Valid bits defined by ipa->available */ 424 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); 425 + 426 + /* Valid bits defined by ipa->available */ 427 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); 428 + 429 + static const struct ipa_reg *ipa_reg_array[] = { 430 + [COMP_CFG] = &ipa_reg_comp_cfg, 431 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 432 + [ROUTE] = &ipa_reg_route, 433 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 434 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 435 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 436 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 437 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 438 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 439 + [IPA_BCR] = &ipa_reg_ipa_bcr, 440 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 441 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 442 + [COUNTER_CFG] = &ipa_reg_counter_cfg, 443 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 444 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 445 + [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, 446 + [SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type, 447 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 448 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 449 + [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, 450 + [DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type, 451 + [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, 452 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 453 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 454 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 455 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 456 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 457 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 458 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 459 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 460 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 461 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 462 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 463 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 464 + [ENDP_STATUS] = &ipa_reg_endp_status, 465 + [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 466 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 467 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 468 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 469 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 470 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 471 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 472 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 473 + }; 474 + 475 + const struct ipa_regs ipa_regs_v3_1 = { 476 + .reg_count = ARRAY_SIZE(ipa_reg_array), 477 + .reg = ipa_reg_array, 478 + };
+456
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + [COMP_CFG_ENABLE] = BIT(0), 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 + /* Bits 5-31 reserved */ 17 + }; 18 + 19 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 20 + 21 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 22 + [CLKON_RX] = BIT(0), 23 + [CLKON_PROC] = BIT(1), 24 + [TX_WRAPPER] = BIT(2), 25 + [CLKON_MISC] = BIT(3), 26 + [RAM_ARB] = BIT(4), 27 + [FTCH_HPS] = BIT(5), 28 + [FTCH_DPS] = BIT(6), 29 + [CLKON_HPS] = BIT(7), 30 + [CLKON_DPS] = BIT(8), 31 + [RX_HPS_CMDQS] = BIT(9), 32 + [HPS_DPS_CMDQS] = BIT(10), 33 + [DPS_TX_CMDQS] = BIT(11), 34 + [RSRC_MNGR] = BIT(12), 35 + [CTX_HANDLER] = BIT(13), 36 + [ACK_MNGR] = BIT(14), 37 + [D_DCPH] = BIT(15), 38 + [H_DCPH] = BIT(16), 39 + /* Bit 17 reserved */ 40 + [NTF_TX_CMDQS] = BIT(18), 41 + [CLKON_TX_0] = BIT(19), 42 + [CLKON_TX_1] = BIT(20), 43 + [CLKON_FNR] = BIT(21), 44 + /* Bits 22-31 reserved */ 45 + }; 46 + 47 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 48 + 49 + static const u32 ipa_reg_route_fmask[] = { 50 + [ROUTE_DIS] = BIT(0), 51 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 52 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 53 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 54 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 55 + /* Bits 22-23 reserved */ 56 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 57 + /* Bits 25-31 reserved */ 58 + }; 59 + 60 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 61 + 62 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 63 + [MEM_SIZE] = GENMASK(15, 0), 64 + [MEM_BADDR] = GENMASK(31, 16), 65 + }; 66 + 67 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 68 + 69 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 70 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 71 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 72 + /* Bits 8-31 reserved */ 73 + }; 74 + 75 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 76 + 77 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 78 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 79 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 80 + }; 81 + 82 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 83 + 84 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 85 + [IPV6_ROUTER_HASH] = BIT(0), 86 + /* Bits 1-3 reserved */ 87 + [IPV6_FILTER_HASH] = BIT(4), 88 + /* Bits 5-7 reserved */ 89 + [IPV4_ROUTER_HASH] = BIT(8), 90 + /* Bits 9-11 reserved */ 91 + [IPV4_FILTER_HASH] = BIT(12), 92 + /* Bits 13-31 reserved */ 93 + }; 94 + 95 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 96 + 97 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 98 + [IPV6_ROUTER_HASH] = BIT(0), 99 + /* Bits 1-3 reserved */ 100 + [IPV6_FILTER_HASH] = BIT(4), 101 + /* Bits 5-7 reserved */ 102 + [IPV4_ROUTER_HASH] = BIT(8), 103 + /* Bits 9-11 reserved */ 104 + [IPV4_FILTER_HASH] = BIT(12), 105 + /* Bits 13-31 reserved */ 106 + }; 107 + 108 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 109 + 110 + /* Valid bits defined by ipa->available */ 111 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); 112 + 113 + IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); 114 + 115 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 116 + [IPA_BASE_ADDR] = GENMASK(16, 0), 117 + /* Bits 17-31 reserved */ 118 + }; 119 + 120 + /* Offset must be a multiple of 8 */ 121 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 122 + 123 + /* Valid bits defined by ipa->available */ 124 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 125 + 126 + static const u32 ipa_reg_counter_cfg_fmask[] = { 127 + /* Bits 0-3 reserved */ 128 + [AGGR_GRANULARITY] = GENMASK(8, 4), 129 + /* Bits 5-31 reserved */ 130 + }; 131 + 132 + IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 133 + 134 + static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 135 + [TX0_PREFETCH_DISABLE] = BIT(0), 136 + [TX1_PREFETCH_DISABLE] = BIT(1), 137 + [PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2), 138 + /* Bits 5-31 reserved */ 139 + }; 140 + 141 + IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 142 + 143 + static const u32 ipa_reg_flavor_0_fmask[] = { 144 + [MAX_PIPES] = GENMASK(3, 0), 145 + /* Bits 4-7 reserved */ 146 + [MAX_CONS_PIPES] = GENMASK(12, 8), 147 + /* Bits 13-15 reserved */ 148 + [MAX_PROD_PIPES] = GENMASK(20, 16), 149 + /* Bits 21-23 reserved */ 150 + [PROD_LOWEST] = GENMASK(27, 24), 151 + /* Bits 28-31 reserved */ 152 + }; 153 + 154 + IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 155 + 156 + static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 157 + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 158 + [CONST_NON_IDLE_ENABLE] = BIT(16), 159 + /* Bits 17-31 reserved */ 160 + }; 161 + 162 + IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); 163 + 164 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 165 + [X_MIN_LIM] = GENMASK(5, 0), 166 + /* Bits 6-7 reserved */ 167 + [X_MAX_LIM] = GENMASK(13, 8), 168 + /* Bits 14-15 reserved */ 169 + [Y_MIN_LIM] = GENMASK(21, 16), 170 + /* Bits 22-23 reserved */ 171 + [Y_MAX_LIM] = GENMASK(29, 24), 172 + /* Bits 30-31 reserved */ 173 + }; 174 + 175 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 176 + 0x00000400, 0x0020); 177 + 178 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 179 + [X_MIN_LIM] = GENMASK(5, 0), 180 + /* Bits 6-7 reserved */ 181 + [X_MAX_LIM] = GENMASK(13, 8), 182 + /* Bits 14-15 reserved */ 183 + [Y_MIN_LIM] = GENMASK(21, 16), 184 + /* Bits 22-23 reserved */ 185 + [Y_MAX_LIM] = GENMASK(29, 24), 186 + /* Bits 30-31 reserved */ 187 + }; 188 + 189 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 190 + 0x00000404, 0x0020); 191 + 192 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 193 + [X_MIN_LIM] = GENMASK(5, 0), 194 + /* Bits 6-7 reserved */ 195 + [X_MAX_LIM] = GENMASK(13, 8), 196 + /* Bits 14-15 reserved */ 197 + [Y_MIN_LIM] = GENMASK(21, 16), 198 + /* Bits 22-23 reserved */ 199 + [Y_MAX_LIM] = GENMASK(29, 24), 200 + /* Bits 30-31 reserved */ 201 + }; 202 + 203 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 204 + 0x00000500, 0x0020); 205 + 206 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 207 + [X_MIN_LIM] = GENMASK(5, 0), 208 + /* Bits 6-7 reserved */ 209 + [X_MAX_LIM] = GENMASK(13, 8), 210 + /* Bits 14-15 reserved */ 211 + [Y_MIN_LIM] = GENMASK(21, 16), 212 + /* Bits 22-23 reserved */ 213 + [Y_MAX_LIM] = GENMASK(29, 24), 214 + /* Bits 30-31 reserved */ 215 + }; 216 + 217 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 218 + 0x00000504, 0x0020); 219 + 220 + static const u32 ipa_reg_endp_init_ctrl_fmask[] = { 221 + [ENDP_SUSPEND] = BIT(0), 222 + [ENDP_DELAY] = BIT(1), 223 + /* Bits 2-31 reserved */ 224 + }; 225 + 226 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 227 + 228 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 229 + [FRAG_OFFLOAD_EN] = BIT(0), 230 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 231 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 232 + /* Bit 7 reserved */ 233 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 234 + /* Bits 9-31 reserved */ 235 + }; 236 + 237 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 238 + 239 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 240 + [NAT_EN] = GENMASK(1, 0), 241 + /* Bits 2-31 reserved */ 242 + }; 243 + 244 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 245 + 246 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 247 + [HDR_LEN] = GENMASK(5, 0), 248 + [HDR_OFST_METADATA_VALID] = BIT(6), 249 + [HDR_OFST_METADATA] = GENMASK(12, 7), 250 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 251 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 252 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 253 + [HDR_A5_MUX] = BIT(26), 254 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 255 + [HDR_METADATA_REG_VALID] = BIT(28), 256 + /* Bits 29-31 reserved */ 257 + }; 258 + 259 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 260 + 261 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 262 + [HDR_ENDIANNESS] = BIT(0), 263 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 264 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 265 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 266 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 267 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 268 + /* Bits 14-31 reserved */ 269 + }; 270 + 271 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 272 + 273 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 274 + 0x00000818, 0x0070); 275 + 276 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 277 + [ENDP_MODE] = GENMASK(2, 0), 278 + /* Bit 3 reserved */ 279 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 280 + /* Bits 9-11 reserved */ 281 + [BYTE_THRESHOLD] = GENMASK(27, 12), 282 + [PIPE_REPLICATION_EN] = BIT(28), 283 + [PAD_EN] = BIT(29), 284 + [HDR_FTCH_DISABLE] = BIT(30), 285 + /* Bit 31 reserved */ 286 + }; 287 + 288 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 289 + 290 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 291 + [AGGR_EN] = GENMASK(1, 0), 292 + [AGGR_TYPE] = GENMASK(4, 2), 293 + [BYTE_LIMIT] = GENMASK(9, 5), 294 + [TIME_LIMIT] = GENMASK(14, 10), 295 + [PKT_LIMIT] = GENMASK(20, 15), 296 + [SW_EOF_ACTIVE] = BIT(21), 297 + [FORCE_CLOSE] = BIT(22), 298 + /* Bit 23 reserved */ 299 + [HARD_BYTE_LIMIT_EN] = BIT(24), 300 + /* Bits 25-31 reserved */ 301 + }; 302 + 303 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 304 + 305 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 306 + [HOL_BLOCK_EN] = BIT(0), 307 + /* Bits 1-31 reserved */ 308 + }; 309 + 310 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 311 + 0x0000082c, 0x0070); 312 + 313 + /* Entire register is a tick count */ 314 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 315 + [TIMER_BASE_VALUE] = GENMASK(31, 0), 316 + }; 317 + 318 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 319 + 0x00000830, 0x0070); 320 + 321 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 322 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 323 + [SYSPIPE_ERR_DETECTION] = BIT(6), 324 + [PACKET_OFFSET_VALID] = BIT(7), 325 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 326 + [IGNORE_MIN_PKT_ERR] = BIT(14), 327 + /* Bit 15 reserved */ 328 + [MAX_PACKET_LEN] = GENMASK(31, 16), 329 + }; 330 + 331 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 332 + 333 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 334 + [ENDP_RSRC_GRP] = GENMASK(1, 0), 335 + /* Bits 2-31 reserved */ 336 + }; 337 + 338 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 339 + 0x00000838, 0x0070); 340 + 341 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 342 + [SEQ_TYPE] = GENMASK(7, 0), 343 + [SEQ_REP_TYPE] = GENMASK(15, 8), 344 + /* Bits 16-31 reserved */ 345 + }; 346 + 347 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 348 + 349 + static const u32 ipa_reg_endp_status_fmask[] = { 350 + [STATUS_EN] = BIT(0), 351 + [STATUS_ENDP] = GENMASK(5, 1), 352 + /* Bits 6-7 reserved */ 353 + [STATUS_LOCATION] = BIT(8), 354 + /* Bits 9-31 reserved */ 355 + }; 356 + 357 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 358 + 359 + static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 360 + [FILTER_HASH_MSK_SRC_ID] = BIT(0), 361 + [FILTER_HASH_MSK_SRC_IP] = BIT(1), 362 + [FILTER_HASH_MSK_DST_IP] = BIT(2), 363 + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 364 + [FILTER_HASH_MSK_DST_PORT] = BIT(4), 365 + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 366 + [FILTER_HASH_MSK_METADATA] = BIT(6), 367 + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 368 + /* Bits 7-15 reserved */ 369 + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 370 + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 371 + [ROUTER_HASH_MSK_DST_IP] = BIT(18), 372 + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 373 + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 374 + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 375 + [ROUTER_HASH_MSK_METADATA] = BIT(22), 376 + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 377 + /* Bits 23-31 reserved */ 378 + }; 379 + 380 + IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 381 + 0x0000085c, 0x0070); 382 + 383 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 384 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 385 + 386 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 387 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 388 + 389 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 390 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 391 + 392 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 393 + [UC_INTR] = BIT(0), 394 + /* Bits 1-31 reserved */ 395 + }; 396 + 397 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 398 + 399 + /* Valid bits defined by ipa->available */ 400 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); 401 + 402 + /* Valid bits defined by ipa->available */ 403 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); 404 + 405 + /* Valid bits defined by ipa->available */ 406 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); 407 + 408 + static const struct ipa_reg *ipa_reg_array[] = { 409 + [COMP_CFG] = &ipa_reg_comp_cfg, 410 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 411 + [ROUTE] = &ipa_reg_route, 412 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 413 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 414 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 415 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 416 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 417 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 418 + [IPA_BCR] = &ipa_reg_ipa_bcr, 419 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 420 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 421 + [COUNTER_CFG] = &ipa_reg_counter_cfg, 422 + [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 423 + [FLAVOR_0] = &ipa_reg_flavor_0, 424 + [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 425 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 426 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 427 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 428 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 429 + [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, 430 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 431 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 432 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 433 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 434 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 435 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 436 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 437 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 438 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 439 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 440 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 441 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 442 + [ENDP_STATUS] = &ipa_reg_endp_status, 443 + [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 444 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 445 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 446 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 447 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 448 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 449 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 450 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 451 + }; 452 + 453 + const struct ipa_regs ipa_regs_v3_5_1 = { 454 + .reg_count = ARRAY_SIZE(ipa_reg_array), 455 + .reg = ipa_reg_array, 456 + };
+512
drivers/net/ipa/reg/ipa_reg-v4.11.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + /* Bit 4 reserved */ 16 + [IPA_QMB_SELECT_CONS_EN] = BIT(5), 17 + [IPA_QMB_SELECT_PROD_EN] = BIT(6), 18 + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 19 + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 20 + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 21 + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 22 + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 23 + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 24 + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 25 + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 26 + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 27 + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 28 + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17), 29 + /* Bit 18 reserved */ 30 + [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 31 + [GENQMB_AOOOWR] = BIT(20), 32 + [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 33 + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22), 34 + /* Bits 24-29 reserved */ 35 + [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 36 + [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 37 + }; 38 + 39 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 40 + 41 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 42 + [CLKON_RX] = BIT(0), 43 + [CLKON_PROC] = BIT(1), 44 + [TX_WRAPPER] = BIT(2), 45 + [CLKON_MISC] = BIT(3), 46 + [RAM_ARB] = BIT(4), 47 + [FTCH_HPS] = BIT(5), 48 + [FTCH_DPS] = BIT(6), 49 + [CLKON_HPS] = BIT(7), 50 + [CLKON_DPS] = BIT(8), 51 + [RX_HPS_CMDQS] = BIT(9), 52 + [HPS_DPS_CMDQS] = BIT(10), 53 + [DPS_TX_CMDQS] = BIT(11), 54 + [RSRC_MNGR] = BIT(12), 55 + [CTX_HANDLER] = BIT(13), 56 + [ACK_MNGR] = BIT(14), 57 + [D_DCPH] = BIT(15), 58 + [H_DCPH] = BIT(16), 59 + /* Bit 17 reserved */ 60 + [NTF_TX_CMDQS] = BIT(18), 61 + [CLKON_TX_0] = BIT(19), 62 + [CLKON_TX_1] = BIT(20), 63 + [CLKON_FNR] = BIT(21), 64 + [QSB2AXI_CMDQ_L] = BIT(22), 65 + [AGGR_WRAPPER] = BIT(23), 66 + [RAM_SLAVEWAY] = BIT(24), 67 + [CLKON_QMB] = BIT(25), 68 + [WEIGHT_ARB] = BIT(26), 69 + [GSI_IF] = BIT(27), 70 + [CLKON_GLOBAL] = BIT(28), 71 + [GLOBAL_2X_CLK] = BIT(29), 72 + [DPL_FIFO] = BIT(30), 73 + [DRBIP] = BIT(31), 74 + }; 75 + 76 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 77 + 78 + static const u32 ipa_reg_route_fmask[] = { 79 + [ROUTE_DIS] = BIT(0), 80 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 81 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 82 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 83 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 84 + /* Bits 22-23 reserved */ 85 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 86 + /* Bits 25-31 reserved */ 87 + }; 88 + 89 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 90 + 91 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 92 + [MEM_SIZE] = GENMASK(15, 0), 93 + [MEM_BADDR] = GENMASK(31, 16), 94 + }; 95 + 96 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 97 + 98 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 99 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 100 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 101 + /* Bits 8-31 reserved */ 102 + }; 103 + 104 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 105 + 106 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 107 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 108 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 109 + /* Bits 8-15 reserved */ 110 + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 111 + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 112 + }; 113 + 114 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 115 + 116 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 117 + [IPV6_ROUTER_HASH] = BIT(0), 118 + /* Bits 1-3 reserved */ 119 + [IPV6_FILTER_HASH] = BIT(4), 120 + /* Bits 5-7 reserved */ 121 + [IPV4_ROUTER_HASH] = BIT(8), 122 + /* Bits 9-11 reserved */ 123 + [IPV4_FILTER_HASH] = BIT(12), 124 + /* Bits 13-31 reserved */ 125 + }; 126 + 127 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 128 + 129 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 130 + [IPV6_ROUTER_HASH] = BIT(0), 131 + /* Bits 1-3 reserved */ 132 + [IPV6_FILTER_HASH] = BIT(4), 133 + /* Bits 5-7 reserved */ 134 + [IPV4_ROUTER_HASH] = BIT(8), 135 + /* Bits 9-11 reserved */ 136 + [IPV4_FILTER_HASH] = BIT(12), 137 + /* Bits 13-31 reserved */ 138 + }; 139 + 140 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 141 + 142 + /* Valid bits defined by ipa->available */ 143 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); 144 + 145 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 146 + [IPA_BASE_ADDR] = GENMASK(17, 0), 147 + /* Bits 18-31 reserved */ 148 + }; 149 + 150 + /* Offset must be a multiple of 8 */ 151 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 152 + 153 + /* Valid bits defined by ipa->available */ 154 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 155 + 156 + static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 157 + /* Bits 0-1 reserved */ 158 + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 159 + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 160 + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 161 + [DMAW_MAX_BEATS_256_DIS] = BIT(11), 162 + [PA_MASK_EN] = BIT(12), 163 + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 164 + [DUAL_TX_ENABLE] = BIT(17), 165 + [SSPND_PA_NO_START_STATE] = BIT(18), 166 + /* Bits 19-31 reserved */ 167 + }; 168 + 169 + IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 170 + 171 + static const u32 ipa_reg_flavor_0_fmask[] = { 172 + [MAX_PIPES] = GENMASK(4, 0), 173 + /* Bits 5-7 reserved */ 174 + [MAX_CONS_PIPES] = GENMASK(12, 8), 175 + /* Bits 13-15 reserved */ 176 + [MAX_PROD_PIPES] = GENMASK(20, 16), 177 + /* Bits 21-23 reserved */ 178 + [PROD_LOWEST] = GENMASK(27, 24), 179 + /* Bits 28-31 reserved */ 180 + }; 181 + 182 + IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 183 + 184 + static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 185 + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 186 + [CONST_NON_IDLE_ENABLE] = BIT(16), 187 + /* Bits 17-31 reserved */ 188 + }; 189 + 190 + IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 191 + 192 + static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { 193 + [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 194 + /* Bits 5-6 reserved */ 195 + [DPL_TIMESTAMP_SEL] = BIT(7), 196 + [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 197 + /* Bits 13-15 reserved */ 198 + [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 199 + /* Bits 21-31 reserved */ 200 + }; 201 + 202 + IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 203 + 204 + static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { 205 + [DIV_VALUE] = GENMASK(8, 0), 206 + /* Bits 9-30 reserved */ 207 + [DIV_ENABLE] = BIT(31), 208 + }; 209 + 210 + IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 211 + 212 + static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { 213 + [PULSE_GRAN_0] = GENMASK(2, 0), 214 + [PULSE_GRAN_1] = GENMASK(5, 3), 215 + [PULSE_GRAN_2] = GENMASK(8, 6), 216 + /* Bits 9-31 reserved */ 217 + }; 218 + 219 + IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 220 + 221 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 222 + [X_MIN_LIM] = GENMASK(5, 0), 223 + /* Bits 6-7 reserved */ 224 + [X_MAX_LIM] = GENMASK(13, 8), 225 + /* Bits 14-15 reserved */ 226 + [Y_MIN_LIM] = GENMASK(21, 16), 227 + /* Bits 22-23 reserved */ 228 + [Y_MAX_LIM] = GENMASK(29, 24), 229 + /* Bits 30-31 reserved */ 230 + }; 231 + 232 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 233 + 0x00000400, 0x0020); 234 + 235 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 236 + [X_MIN_LIM] = GENMASK(5, 0), 237 + /* Bits 6-7 reserved */ 238 + [X_MAX_LIM] = GENMASK(13, 8), 239 + /* Bits 14-15 reserved */ 240 + [Y_MIN_LIM] = GENMASK(21, 16), 241 + /* Bits 22-23 reserved */ 242 + [Y_MAX_LIM] = GENMASK(29, 24), 243 + /* Bits 30-31 reserved */ 244 + }; 245 + 246 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 247 + 0x00000404, 0x0020); 248 + 249 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 250 + [X_MIN_LIM] = GENMASK(5, 0), 251 + /* Bits 6-7 reserved */ 252 + [X_MAX_LIM] = GENMASK(13, 8), 253 + /* Bits 14-15 reserved */ 254 + [Y_MIN_LIM] = GENMASK(21, 16), 255 + /* Bits 22-23 reserved */ 256 + [Y_MAX_LIM] = GENMASK(29, 24), 257 + /* Bits 30-31 reserved */ 258 + }; 259 + 260 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 261 + 0x00000500, 0x0020); 262 + 263 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 264 + [X_MIN_LIM] = GENMASK(5, 0), 265 + /* Bits 6-7 reserved */ 266 + [X_MAX_LIM] = GENMASK(13, 8), 267 + /* Bits 14-15 reserved */ 268 + [Y_MIN_LIM] = GENMASK(21, 16), 269 + /* Bits 22-23 reserved */ 270 + [Y_MAX_LIM] = GENMASK(29, 24), 271 + /* Bits 30-31 reserved */ 272 + }; 273 + 274 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 275 + 0x00000504, 0x0020); 276 + 277 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 278 + [FRAG_OFFLOAD_EN] = BIT(0), 279 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 280 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 281 + /* Bit 7 reserved */ 282 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 283 + /* Bits 9-31 reserved */ 284 + }; 285 + 286 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 287 + 288 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 289 + [NAT_EN] = GENMASK(1, 0), 290 + /* Bits 2-31 reserved */ 291 + }; 292 + 293 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 294 + 295 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 296 + [HDR_LEN] = GENMASK(5, 0), 297 + [HDR_OFST_METADATA_VALID] = BIT(6), 298 + [HDR_OFST_METADATA] = GENMASK(12, 7), 299 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 300 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 301 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 302 + /* Bit 26 reserved */ 303 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 304 + [HDR_LEN_MSB] = GENMASK(29, 28), 305 + [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 306 + }; 307 + 308 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 309 + 310 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 311 + [HDR_ENDIANNESS] = BIT(0), 312 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 313 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 314 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 315 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 316 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 317 + /* Bits 14-15 reserved */ 318 + [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 319 + [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 320 + [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 321 + /* Bits 22-31 reserved */ 322 + }; 323 + 324 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 325 + 326 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 327 + 0x00000818, 0x0070); 328 + 329 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 330 + [ENDP_MODE] = GENMASK(2, 0), 331 + [DCPH_ENABLE] = BIT(3), 332 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 333 + /* Bits 9-11 reserved */ 334 + [BYTE_THRESHOLD] = GENMASK(27, 12), 335 + [PIPE_REPLICATION_EN] = BIT(28), 336 + [PAD_EN] = BIT(29), 337 + [DRBIP_ACL_ENABLE] = BIT(30), 338 + /* Bit 31 reserved */ 339 + }; 340 + 341 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 342 + 343 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 344 + [AGGR_EN] = GENMASK(1, 0), 345 + [AGGR_TYPE] = GENMASK(4, 2), 346 + [BYTE_LIMIT] = GENMASK(10, 5), 347 + /* Bit 11 reserved */ 348 + [TIME_LIMIT] = GENMASK(16, 12), 349 + [PKT_LIMIT] = GENMASK(22, 17), 350 + [SW_EOF_ACTIVE] = BIT(23), 351 + [FORCE_CLOSE] = BIT(24), 352 + /* Bit 25 reserved */ 353 + [HARD_BYTE_LIMIT_EN] = BIT(26), 354 + [AGGR_GRAN_SEL] = BIT(27), 355 + /* Bits 28-31 reserved */ 356 + }; 357 + 358 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 359 + 360 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 361 + [HOL_BLOCK_EN] = BIT(0), 362 + /* Bits 1-31 reserved */ 363 + }; 364 + 365 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 366 + 0x0000082c, 0x0070); 367 + 368 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 369 + [TIMER_LIMIT] = GENMASK(4, 0), 370 + /* Bits 5-7 reserved */ 371 + [TIMER_GRAN_SEL] = BIT(8), 372 + /* Bits 9-31 reserved */ 373 + }; 374 + 375 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 376 + 0x00000830, 0x0070); 377 + 378 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 379 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 380 + [SYSPIPE_ERR_DETECTION] = BIT(6), 381 + [PACKET_OFFSET_VALID] = BIT(7), 382 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 383 + [IGNORE_MIN_PKT_ERR] = BIT(14), 384 + /* Bit 15 reserved */ 385 + [MAX_PACKET_LEN] = GENMASK(31, 16), 386 + }; 387 + 388 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 389 + 390 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 391 + [ENDP_RSRC_GRP] = GENMASK(1, 0), 392 + /* Bits 2-31 reserved */ 393 + }; 394 + 395 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 396 + 0x00000838, 0x0070); 397 + 398 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 399 + [SEQ_TYPE] = GENMASK(7, 0), 400 + /* Bits 8-31 reserved */ 401 + }; 402 + 403 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 404 + 405 + static const u32 ipa_reg_endp_status_fmask[] = { 406 + [STATUS_EN] = BIT(0), 407 + [STATUS_ENDP] = GENMASK(5, 1), 408 + /* Bits 6-8 reserved */ 409 + [STATUS_PKT_SUPPRESS] = BIT(9), 410 + /* Bits 10-31 reserved */ 411 + }; 412 + 413 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 414 + 415 + static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 416 + [FILTER_HASH_MSK_SRC_ID] = BIT(0), 417 + [FILTER_HASH_MSK_SRC_IP] = BIT(1), 418 + [FILTER_HASH_MSK_DST_IP] = BIT(2), 419 + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 420 + [FILTER_HASH_MSK_DST_PORT] = BIT(4), 421 + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 422 + [FILTER_HASH_MSK_METADATA] = BIT(6), 423 + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 424 + /* Bits 7-15 reserved */ 425 + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 426 + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 427 + [ROUTER_HASH_MSK_DST_IP] = BIT(18), 428 + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 429 + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 430 + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 431 + [ROUTER_HASH_MSK_METADATA] = BIT(22), 432 + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 433 + /* Bits 23-31 reserved */ 434 + }; 435 + 436 + IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 437 + 0x0000085c, 0x0070); 438 + 439 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 440 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); 441 + 442 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 443 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); 444 + 445 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 446 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); 447 + 448 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 449 + [UC_INTR] = BIT(0), 450 + /* Bits 1-31 reserved */ 451 + }; 452 + 453 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); 454 + 455 + /* Valid bits defined by ipa->available */ 456 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00004030 + 0x1000 * GSI_EE_AP); 457 + 458 + /* Valid bits defined by ipa->available */ 459 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00004034 + 0x1000 * GSI_EE_AP); 460 + 461 + /* Valid bits defined by ipa->available */ 462 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00004038 + 0x1000 * GSI_EE_AP); 463 + 464 + static const struct ipa_reg *ipa_reg_array[] = { 465 + [COMP_CFG] = &ipa_reg_comp_cfg, 466 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 467 + [ROUTE] = &ipa_reg_route, 468 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 469 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 470 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 471 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 472 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 473 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 474 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 475 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 476 + [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 477 + [FLAVOR_0] = &ipa_reg_flavor_0, 478 + [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 479 + [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, 480 + [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, 481 + [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, 482 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 483 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 484 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 485 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 486 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 487 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 488 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 489 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 490 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 491 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 492 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 493 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 494 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 495 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 496 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 497 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 498 + [ENDP_STATUS] = &ipa_reg_endp_status, 499 + [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 500 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 501 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 502 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 503 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 504 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 505 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 506 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 507 + }; 508 + 509 + const struct ipa_regs ipa_regs_v4_11 = { 510 + .reg_count = ARRAY_SIZE(ipa_reg_array), 511 + .reg = ipa_reg_array, 512 + };
+456
drivers/net/ipa/reg/ipa_reg-v4.2.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + /* Bit 0 reserved */ 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 + [IPA_QMB_SELECT_CONS_EN] = BIT(5), 17 + [IPA_QMB_SELECT_PROD_EN] = BIT(6), 18 + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 19 + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 20 + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 21 + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 22 + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 23 + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 24 + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 25 + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 26 + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 27 + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 28 + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 29 + /* Bits 21-31 reserved */ 30 + }; 31 + 32 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 33 + 34 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 35 + [CLKON_RX] = BIT(0), 36 + [CLKON_PROC] = BIT(1), 37 + [TX_WRAPPER] = BIT(2), 38 + [CLKON_MISC] = BIT(3), 39 + [RAM_ARB] = BIT(4), 40 + [FTCH_HPS] = BIT(5), 41 + [FTCH_DPS] = BIT(6), 42 + [CLKON_HPS] = BIT(7), 43 + [CLKON_DPS] = BIT(8), 44 + [RX_HPS_CMDQS] = BIT(9), 45 + [HPS_DPS_CMDQS] = BIT(10), 46 + [DPS_TX_CMDQS] = BIT(11), 47 + [RSRC_MNGR] = BIT(12), 48 + [CTX_HANDLER] = BIT(13), 49 + [ACK_MNGR] = BIT(14), 50 + [D_DCPH] = BIT(15), 51 + [H_DCPH] = BIT(16), 52 + /* Bit 17 reserved */ 53 + [NTF_TX_CMDQS] = BIT(18), 54 + [CLKON_TX_0] = BIT(19), 55 + [CLKON_TX_1] = BIT(20), 56 + [CLKON_FNR] = BIT(21), 57 + [QSB2AXI_CMDQ_L] = BIT(22), 58 + [AGGR_WRAPPER] = BIT(23), 59 + [RAM_SLAVEWAY] = BIT(24), 60 + [CLKON_QMB] = BIT(25), 61 + [WEIGHT_ARB] = BIT(26), 62 + [GSI_IF] = BIT(27), 63 + [CLKON_GLOBAL] = BIT(28), 64 + [GLOBAL_2X_CLK] = BIT(29), 65 + /* Bits 30-31 reserved */ 66 + }; 67 + 68 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 69 + 70 + static const u32 ipa_reg_route_fmask[] = { 71 + [ROUTE_DIS] = BIT(0), 72 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 73 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 74 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 75 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 76 + /* Bits 22-23 reserved */ 77 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 78 + /* Bits 25-31 reserved */ 79 + }; 80 + 81 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 82 + 83 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 84 + [MEM_SIZE] = GENMASK(15, 0), 85 + [MEM_BADDR] = GENMASK(31, 16), 86 + }; 87 + 88 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 89 + 90 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 91 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 92 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 93 + /* Bits 8-31 reserved */ 94 + }; 95 + 96 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 97 + 98 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 99 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 100 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 101 + /* Bits 8-15 reserved */ 102 + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 103 + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 104 + }; 105 + 106 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 107 + 108 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 109 + [IPV6_ROUTER_HASH] = BIT(0), 110 + /* Bits 1-3 reserved */ 111 + [IPV6_FILTER_HASH] = BIT(4), 112 + /* Bits 5-7 reserved */ 113 + [IPV4_ROUTER_HASH] = BIT(8), 114 + /* Bits 9-11 reserved */ 115 + [IPV4_FILTER_HASH] = BIT(12), 116 + /* Bits 13-31 reserved */ 117 + }; 118 + 119 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 120 + 121 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 122 + [IPV6_ROUTER_HASH] = BIT(0), 123 + /* Bits 1-3 reserved */ 124 + [IPV6_FILTER_HASH] = BIT(4), 125 + /* Bits 5-7 reserved */ 126 + [IPV4_ROUTER_HASH] = BIT(8), 127 + /* Bits 9-11 reserved */ 128 + [IPV4_FILTER_HASH] = BIT(12), 129 + /* Bits 13-31 reserved */ 130 + }; 131 + 132 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 133 + 134 + /* Valid bits defined by ipa->available */ 135 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); 136 + 137 + IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); 138 + 139 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 140 + [IPA_BASE_ADDR] = GENMASK(16, 0), 141 + /* Bits 17-31 reserved */ 142 + }; 143 + 144 + /* Offset must be a multiple of 8 */ 145 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 146 + 147 + /* Valid bits defined by ipa->available */ 148 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 149 + 150 + static const u32 ipa_reg_counter_cfg_fmask[] = { 151 + /* Bits 0-3 reserved */ 152 + [AGGR_GRANULARITY] = GENMASK(8, 4), 153 + /* Bits 9-31 reserved */ 154 + }; 155 + 156 + IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 157 + 158 + static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 159 + /* Bits 0-1 reserved */ 160 + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 161 + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 162 + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 163 + [DMAW_MAX_BEATS_256_DIS] = BIT(11), 164 + [PA_MASK_EN] = BIT(12), 165 + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 166 + /* Bit 17 reserved */ 167 + [SSPND_PA_NO_START_STATE] = BIT(18), 168 + [SSPND_PA_NO_BQ_STATE] = BIT(19), 169 + /* Bits 20-31 reserved */ 170 + }; 171 + 172 + IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 173 + 174 + static const u32 ipa_reg_flavor_0_fmask[] = { 175 + [MAX_PIPES] = GENMASK(3, 0), 176 + /* Bits 4-7 reserved */ 177 + [MAX_CONS_PIPES] = GENMASK(12, 8), 178 + /* Bits 13-15 reserved */ 179 + [MAX_PROD_PIPES] = GENMASK(20, 16), 180 + /* Bits 21-23 reserved */ 181 + [PROD_LOWEST] = GENMASK(27, 24), 182 + /* Bits 28-31 reserved */ 183 + }; 184 + 185 + IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 186 + 187 + static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 188 + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 189 + [CONST_NON_IDLE_ENABLE] = BIT(16), 190 + /* Bits 17-31 reserved */ 191 + }; 192 + 193 + IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 194 + 195 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 196 + [X_MIN_LIM] = GENMASK(5, 0), 197 + /* Bits 6-7 reserved */ 198 + [X_MAX_LIM] = GENMASK(13, 8), 199 + /* Bits 14-15 reserved */ 200 + [Y_MIN_LIM] = GENMASK(21, 16), 201 + /* Bits 22-23 reserved */ 202 + [Y_MAX_LIM] = GENMASK(29, 24), 203 + /* Bits 30-31 reserved */ 204 + }; 205 + 206 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 207 + 0x00000400, 0x0020); 208 + 209 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 210 + [X_MIN_LIM] = GENMASK(5, 0), 211 + /* Bits 6-7 reserved */ 212 + [X_MAX_LIM] = GENMASK(13, 8), 213 + /* Bits 14-15 reserved */ 214 + [Y_MIN_LIM] = GENMASK(21, 16), 215 + /* Bits 22-23 reserved */ 216 + [Y_MAX_LIM] = GENMASK(29, 24), 217 + /* Bits 30-31 reserved */ 218 + }; 219 + 220 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 221 + 0x00000404, 0x0020); 222 + 223 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 224 + [X_MIN_LIM] = GENMASK(5, 0), 225 + /* Bits 6-7 reserved */ 226 + [X_MAX_LIM] = GENMASK(13, 8), 227 + /* Bits 14-15 reserved */ 228 + [Y_MIN_LIM] = GENMASK(21, 16), 229 + /* Bits 22-23 reserved */ 230 + [Y_MAX_LIM] = GENMASK(29, 24), 231 + /* Bits 30-31 reserved */ 232 + }; 233 + 234 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 235 + 0x00000500, 0x0020); 236 + 237 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 238 + [X_MIN_LIM] = GENMASK(5, 0), 239 + /* Bits 6-7 reserved */ 240 + [X_MAX_LIM] = GENMASK(13, 8), 241 + /* Bits 14-15 reserved */ 242 + [Y_MIN_LIM] = GENMASK(21, 16), 243 + /* Bits 22-23 reserved */ 244 + [Y_MAX_LIM] = GENMASK(29, 24), 245 + /* Bits 30-31 reserved */ 246 + }; 247 + 248 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 249 + 0x00000504, 0x0020); 250 + 251 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 252 + [FRAG_OFFLOAD_EN] = BIT(0), 253 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 254 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 255 + /* Bit 7 reserved */ 256 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 257 + /* Bits 9-31 reserved */ 258 + }; 259 + 260 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 261 + 262 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 263 + [NAT_EN] = GENMASK(1, 0), 264 + /* Bits 2-31 reserved */ 265 + }; 266 + 267 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 268 + 269 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 270 + [HDR_LEN] = GENMASK(5, 0), 271 + [HDR_OFST_METADATA_VALID] = BIT(6), 272 + [HDR_OFST_METADATA] = GENMASK(12, 7), 273 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 274 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 275 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 276 + [HDR_A5_MUX] = BIT(26), 277 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 278 + [HDR_METADATA_REG_VALID] = BIT(28), 279 + /* Bits 29-31 reserved */ 280 + }; 281 + 282 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 283 + 284 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 285 + [HDR_ENDIANNESS] = BIT(0), 286 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 287 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 288 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 289 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 290 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 291 + /* Bits 14-31 reserved */ 292 + }; 293 + 294 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 295 + 296 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 297 + 0x00000818, 0x0070); 298 + 299 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 300 + [ENDP_MODE] = GENMASK(2, 0), 301 + /* Bit 3 reserved */ 302 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 303 + /* Bits 9-11 reserved */ 304 + [BYTE_THRESHOLD] = GENMASK(27, 12), 305 + [PIPE_REPLICATION_EN] = BIT(28), 306 + [PAD_EN] = BIT(29), 307 + [HDR_FTCH_DISABLE] = BIT(30), 308 + /* Bit 31 reserved */ 309 + }; 310 + 311 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 312 + 313 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 314 + [AGGR_EN] = GENMASK(1, 0), 315 + [AGGR_TYPE] = GENMASK(4, 2), 316 + [BYTE_LIMIT] = GENMASK(9, 5), 317 + [TIME_LIMIT] = GENMASK(14, 10), 318 + [PKT_LIMIT] = GENMASK(20, 15), 319 + [SW_EOF_ACTIVE] = BIT(21), 320 + [FORCE_CLOSE] = BIT(22), 321 + /* Bit 23 reserved */ 322 + [HARD_BYTE_LIMIT_EN] = BIT(24), 323 + /* Bits 25-31 reserved */ 324 + }; 325 + 326 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 327 + 328 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 329 + [HOL_BLOCK_EN] = BIT(0), 330 + /* Bits 1-31 reserved */ 331 + }; 332 + 333 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 334 + 0x0000082c, 0x0070); 335 + 336 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 337 + [TIMER_BASE_VALUE] = GENMASK(4, 0), 338 + /* Bits 5-7 reserved */ 339 + [TIMER_SCALE] = GENMASK(12, 8), 340 + /* Bits 9-31 reserved */ 341 + }; 342 + 343 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 344 + 0x00000830, 0x0070); 345 + 346 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 347 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 348 + [SYSPIPE_ERR_DETECTION] = BIT(6), 349 + [PACKET_OFFSET_VALID] = BIT(7), 350 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 351 + [IGNORE_MIN_PKT_ERR] = BIT(14), 352 + /* Bit 15 reserved */ 353 + [MAX_PACKET_LEN] = GENMASK(31, 16), 354 + }; 355 + 356 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 357 + 358 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 359 + [ENDP_RSRC_GRP] = BIT(0), 360 + /* Bits 1-31 reserved */ 361 + }; 362 + 363 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 364 + 0x00000838, 0x0070); 365 + 366 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 367 + [SEQ_TYPE] = GENMASK(7, 0), 368 + [SEQ_REP_TYPE] = GENMASK(15, 8), 369 + /* Bits 16-31 reserved */ 370 + }; 371 + 372 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 373 + 374 + static const u32 ipa_reg_endp_status_fmask[] = { 375 + [STATUS_EN] = BIT(0), 376 + [STATUS_ENDP] = GENMASK(5, 1), 377 + /* Bits 6-7 reserved */ 378 + [STATUS_LOCATION] = BIT(8), 379 + [STATUS_PKT_SUPPRESS] = BIT(9), 380 + /* Bits 10-31 reserved */ 381 + }; 382 + 383 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 384 + 385 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 386 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 387 + 388 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 389 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 390 + 391 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 392 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 393 + 394 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 395 + [UC_INTR] = BIT(0), 396 + /* Bits 1-31 reserved */ 397 + }; 398 + 399 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 400 + 401 + /* Valid bits defined by ipa->available */ 402 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); 403 + 404 + /* Valid bits defined by ipa->available */ 405 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); 406 + 407 + /* Valid bits defined by ipa->available */ 408 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); 409 + 410 + static const struct ipa_reg *ipa_reg_array[] = { 411 + [COMP_CFG] = &ipa_reg_comp_cfg, 412 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 413 + [ROUTE] = &ipa_reg_route, 414 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 415 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 416 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 417 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 418 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 419 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 420 + [IPA_BCR] = &ipa_reg_ipa_bcr, 421 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 422 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 423 + [COUNTER_CFG] = &ipa_reg_counter_cfg, 424 + [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 425 + [FLAVOR_0] = &ipa_reg_flavor_0, 426 + [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 427 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 428 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 429 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 430 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 431 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 432 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 433 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 434 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 435 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 436 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 437 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 438 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 439 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 440 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 441 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 442 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 443 + [ENDP_STATUS] = &ipa_reg_endp_status, 444 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 445 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 446 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 447 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 448 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 449 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 450 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 451 + }; 452 + 453 + const struct ipa_regs ipa_regs_v4_2 = { 454 + .reg_count = ARRAY_SIZE(ipa_reg_array), 455 + .reg = ipa_reg_array, 456 + };
+533
drivers/net/ipa/reg/ipa_reg-v4.5.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + /* Bit 0 reserved */ 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + /* Bit 4 reserved */ 16 + [IPA_QMB_SELECT_CONS_EN] = BIT(5), 17 + [IPA_QMB_SELECT_PROD_EN] = BIT(6), 18 + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 19 + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 20 + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 21 + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 22 + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 23 + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 24 + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 25 + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 26 + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 27 + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 28 + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 29 + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), 30 + /* Bits 22-31 reserved */ 31 + }; 32 + 33 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 34 + 35 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 36 + [CLKON_RX] = BIT(0), 37 + [CLKON_PROC] = BIT(1), 38 + [TX_WRAPPER] = BIT(2), 39 + [CLKON_MISC] = BIT(3), 40 + [RAM_ARB] = BIT(4), 41 + [FTCH_HPS] = BIT(5), 42 + [FTCH_DPS] = BIT(6), 43 + [CLKON_HPS] = BIT(7), 44 + [CLKON_DPS] = BIT(8), 45 + [RX_HPS_CMDQS] = BIT(9), 46 + [HPS_DPS_CMDQS] = BIT(10), 47 + [DPS_TX_CMDQS] = BIT(11), 48 + [RSRC_MNGR] = BIT(12), 49 + [CTX_HANDLER] = BIT(13), 50 + [ACK_MNGR] = BIT(14), 51 + [D_DCPH] = BIT(15), 52 + [H_DCPH] = BIT(16), 53 + [CLKON_DCMP] = BIT(17), 54 + [NTF_TX_CMDQS] = BIT(18), 55 + [CLKON_TX_0] = BIT(19), 56 + [CLKON_TX_1] = BIT(20), 57 + [CLKON_FNR] = BIT(21), 58 + [QSB2AXI_CMDQ_L] = BIT(22), 59 + [AGGR_WRAPPER] = BIT(23), 60 + [RAM_SLAVEWAY] = BIT(24), 61 + [CLKON_QMB] = BIT(25), 62 + [WEIGHT_ARB] = BIT(26), 63 + [GSI_IF] = BIT(27), 64 + [CLKON_GLOBAL] = BIT(28), 65 + [GLOBAL_2X_CLK] = BIT(29), 66 + [DPL_FIFO] = BIT(30), 67 + /* Bit 31 reserved */ 68 + }; 69 + 70 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 71 + 72 + static const u32 ipa_reg_route_fmask[] = { 73 + [ROUTE_DIS] = BIT(0), 74 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 75 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 76 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 77 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 78 + /* Bits 22-23 reserved */ 79 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 80 + /* Bits 25-31 reserved */ 81 + }; 82 + 83 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 84 + 85 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 86 + [MEM_SIZE] = GENMASK(15, 0), 87 + [MEM_BADDR] = GENMASK(31, 16), 88 + }; 89 + 90 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 91 + 92 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 93 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 94 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 95 + /* Bits 8-31 reserved */ 96 + }; 97 + 98 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 99 + 100 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 101 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 102 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 103 + /* Bits 8-15 reserved */ 104 + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 105 + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 106 + }; 107 + 108 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 109 + 110 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 111 + [IPV6_ROUTER_HASH] = BIT(0), 112 + /* Bits 1-3 reserved */ 113 + [IPV6_FILTER_HASH] = BIT(4), 114 + /* Bits 5-7 reserved */ 115 + [IPV4_ROUTER_HASH] = BIT(8), 116 + /* Bits 9-11 reserved */ 117 + [IPV4_FILTER_HASH] = BIT(12), 118 + /* Bits 13-31 reserved */ 119 + }; 120 + 121 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 122 + 123 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 124 + [IPV6_ROUTER_HASH] = BIT(0), 125 + /* Bits 1-3 reserved */ 126 + [IPV6_FILTER_HASH] = BIT(4), 127 + /* Bits 5-7 reserved */ 128 + [IPV4_ROUTER_HASH] = BIT(8), 129 + /* Bits 9-11 reserved */ 130 + [IPV4_FILTER_HASH] = BIT(12), 131 + /* Bits 13-31 reserved */ 132 + }; 133 + 134 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 135 + 136 + /* Valid bits defined by ipa->available */ 137 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); 138 + 139 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 140 + [IPA_BASE_ADDR] = GENMASK(17, 0), 141 + /* Bits 18-31 reserved */ 142 + }; 143 + 144 + /* Offset must be a multiple of 8 */ 145 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 146 + 147 + /* Valid bits defined by ipa->available */ 148 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 149 + 150 + static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 151 + /* Bits 0-1 reserved */ 152 + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 153 + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 154 + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 155 + [DMAW_MAX_BEATS_256_DIS] = BIT(11), 156 + [PA_MASK_EN] = BIT(12), 157 + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 158 + [DUAL_TX_ENABLE] = BIT(17), 159 + /* Bits 18-31 reserved */ 160 + }; 161 + 162 + IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 163 + 164 + static const u32 ipa_reg_flavor_0_fmask[] = { 165 + [MAX_PIPES] = GENMASK(3, 0), 166 + /* Bits 4-7 reserved */ 167 + [MAX_CONS_PIPES] = GENMASK(12, 8), 168 + /* Bits 13-15 reserved */ 169 + [MAX_PROD_PIPES] = GENMASK(20, 16), 170 + /* Bits 21-23 reserved */ 171 + [PROD_LOWEST] = GENMASK(27, 24), 172 + /* Bits 28-31 reserved */ 173 + }; 174 + 175 + IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 176 + 177 + static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 178 + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 179 + [CONST_NON_IDLE_ENABLE] = BIT(16), 180 + /* Bits 17-31 reserved */ 181 + }; 182 + 183 + IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 184 + 185 + static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { 186 + [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 187 + /* Bits 5-6 reserved */ 188 + [DPL_TIMESTAMP_SEL] = BIT(7), 189 + [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 190 + /* Bits 13-15 reserved */ 191 + [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 192 + /* Bits 21-31 reserved */ 193 + }; 194 + 195 + IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 196 + 197 + static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { 198 + [DIV_VALUE] = GENMASK(8, 0), 199 + /* Bits 9-30 reserved */ 200 + [DIV_ENABLE] = BIT(31), 201 + }; 202 + 203 + IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 204 + 205 + static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { 206 + [PULSE_GRAN_0] = GENMASK(2, 0), 207 + [PULSE_GRAN_1] = GENMASK(5, 3), 208 + [PULSE_GRAN_2] = GENMASK(8, 6), 209 + }; 210 + 211 + IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 212 + 213 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 214 + [X_MIN_LIM] = GENMASK(5, 0), 215 + /* Bits 6-7 reserved */ 216 + [X_MAX_LIM] = GENMASK(13, 8), 217 + /* Bits 14-15 reserved */ 218 + [Y_MIN_LIM] = GENMASK(21, 16), 219 + /* Bits 22-23 reserved */ 220 + [Y_MAX_LIM] = GENMASK(29, 24), 221 + /* Bits 30-31 reserved */ 222 + }; 223 + 224 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 225 + 0x00000400, 0x0020); 226 + 227 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 228 + [X_MIN_LIM] = GENMASK(5, 0), 229 + /* Bits 6-7 reserved */ 230 + [X_MAX_LIM] = GENMASK(13, 8), 231 + /* Bits 14-15 reserved */ 232 + [Y_MIN_LIM] = GENMASK(21, 16), 233 + /* Bits 22-23 reserved */ 234 + [Y_MAX_LIM] = GENMASK(29, 24), 235 + /* Bits 30-31 reserved */ 236 + }; 237 + 238 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 239 + 0x00000404, 0x0020); 240 + 241 + static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 242 + [X_MIN_LIM] = GENMASK(5, 0), 243 + /* Bits 6-7 reserved */ 244 + [X_MAX_LIM] = GENMASK(13, 8), 245 + /* Bits 14-15 reserved */ 246 + [Y_MIN_LIM] = GENMASK(21, 16), 247 + /* Bits 22-23 reserved */ 248 + [Y_MAX_LIM] = GENMASK(29, 24), 249 + /* Bits 30-31 reserved */ 250 + }; 251 + 252 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 253 + 0x00000408, 0x0020); 254 + 255 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 256 + [X_MIN_LIM] = GENMASK(5, 0), 257 + /* Bits 6-7 reserved */ 258 + [X_MAX_LIM] = GENMASK(13, 8), 259 + /* Bits 14-15 reserved */ 260 + [Y_MIN_LIM] = GENMASK(21, 16), 261 + /* Bits 22-23 reserved */ 262 + [Y_MAX_LIM] = GENMASK(29, 24), 263 + /* Bits 30-31 reserved */ 264 + }; 265 + 266 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 267 + 0x00000500, 0x0020); 268 + 269 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 270 + [X_MIN_LIM] = GENMASK(5, 0), 271 + /* Bits 6-7 reserved */ 272 + [X_MAX_LIM] = GENMASK(13, 8), 273 + /* Bits 14-15 reserved */ 274 + [Y_MIN_LIM] = GENMASK(21, 16), 275 + /* Bits 22-23 reserved */ 276 + [Y_MAX_LIM] = GENMASK(29, 24), 277 + /* Bits 30-31 reserved */ 278 + }; 279 + 280 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 281 + 0x00000504, 0x0020); 282 + 283 + static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 284 + [X_MIN_LIM] = GENMASK(5, 0), 285 + /* Bits 6-7 reserved */ 286 + [X_MAX_LIM] = GENMASK(13, 8), 287 + /* Bits 14-15 reserved */ 288 + [Y_MIN_LIM] = GENMASK(21, 16), 289 + /* Bits 22-23 reserved */ 290 + [Y_MAX_LIM] = GENMASK(29, 24), 291 + /* Bits 30-31 reserved */ 292 + }; 293 + 294 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 295 + 0x00000508, 0x0020); 296 + 297 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 298 + [FRAG_OFFLOAD_EN] = BIT(0), 299 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 300 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 301 + /* Bit 7 reserved */ 302 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 303 + /* Bits 9-31 reserved */ 304 + }; 305 + 306 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 307 + 308 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 309 + [NAT_EN] = GENMASK(1, 0), 310 + /* Bits 2-31 reserved */ 311 + }; 312 + 313 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 314 + 315 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 316 + [HDR_LEN] = GENMASK(5, 0), 317 + [HDR_OFST_METADATA_VALID] = BIT(6), 318 + [HDR_OFST_METADATA] = GENMASK(12, 7), 319 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 320 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 321 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 322 + [HDR_A5_MUX] = BIT(26), 323 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 324 + [HDR_LEN_MSB] = GENMASK(29, 28), 325 + [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 326 + }; 327 + 328 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 329 + 330 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 331 + [HDR_ENDIANNESS] = BIT(0), 332 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 333 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 334 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 335 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 336 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 337 + /* Bits 14-15 reserved */ 338 + [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 339 + [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 340 + [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 341 + /* Bits 22-31 reserved */ 342 + }; 343 + 344 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 345 + 346 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 347 + 0x00000818, 0x0070); 348 + 349 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 350 + [ENDP_MODE] = GENMASK(2, 0), 351 + [DCPH_ENABLE] = BIT(3), 352 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 353 + /* Bits 9-11 reserved */ 354 + [BYTE_THRESHOLD] = GENMASK(27, 12), 355 + [PIPE_REPLICATION_EN] = BIT(28), 356 + [PAD_EN] = BIT(29), 357 + /* Bits 30-31 reserved */ 358 + }; 359 + 360 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 361 + 362 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 363 + [AGGR_EN] = GENMASK(1, 0), 364 + [AGGR_TYPE] = GENMASK(4, 2), 365 + [BYTE_LIMIT] = GENMASK(10, 5), 366 + /* Bit 11 reserved */ 367 + [TIME_LIMIT] = GENMASK(16, 12), 368 + [PKT_LIMIT] = GENMASK(22, 17), 369 + [SW_EOF_ACTIVE] = BIT(23), 370 + [FORCE_CLOSE] = BIT(24), 371 + /* Bit 25 reserved */ 372 + [HARD_BYTE_LIMIT_EN] = BIT(26), 373 + [AGGR_GRAN_SEL] = BIT(27), 374 + /* Bits 28-31 reserved */ 375 + }; 376 + 377 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 378 + 379 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 380 + [HOL_BLOCK_EN] = BIT(0), 381 + /* Bits 1-31 reserved */ 382 + }; 383 + 384 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 385 + 0x0000082c, 0x0070); 386 + 387 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 388 + [TIMER_LIMIT] = GENMASK(4, 0), 389 + /* Bits 5-7 reserved */ 390 + [TIMER_GRAN_SEL] = BIT(8), 391 + /* Bits 9-31 reserved */ 392 + }; 393 + 394 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 395 + 0x00000830, 0x0070); 396 + 397 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 398 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 399 + [SYSPIPE_ERR_DETECTION] = BIT(6), 400 + [PACKET_OFFSET_VALID] = BIT(7), 401 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 402 + [IGNORE_MIN_PKT_ERR] = BIT(14), 403 + /* Bit 15 reserved */ 404 + [MAX_PACKET_LEN] = GENMASK(31, 16), 405 + }; 406 + 407 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 408 + 409 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 410 + [ENDP_RSRC_GRP] = GENMASK(2, 0), 411 + /* Bits 3-31 reserved */ 412 + }; 413 + 414 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 415 + 0x00000838, 0x0070); 416 + 417 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 418 + [SEQ_TYPE] = GENMASK(7, 0), 419 + /* Bits 8-31 reserved */ 420 + }; 421 + 422 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 423 + 424 + static const u32 ipa_reg_endp_status_fmask[] = { 425 + [STATUS_EN] = BIT(0), 426 + [STATUS_ENDP] = GENMASK(5, 1), 427 + /* Bits 6-8 reserved */ 428 + [STATUS_PKT_SUPPRESS] = BIT(9), 429 + /* Bits 10-31 reserved */ 430 + }; 431 + 432 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 433 + 434 + static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 435 + [FILTER_HASH_MSK_SRC_ID] = BIT(0), 436 + [FILTER_HASH_MSK_SRC_IP] = BIT(1), 437 + [FILTER_HASH_MSK_DST_IP] = BIT(2), 438 + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 439 + [FILTER_HASH_MSK_DST_PORT] = BIT(4), 440 + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 441 + [FILTER_HASH_MSK_METADATA] = BIT(6), 442 + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 443 + /* Bits 7-15 reserved */ 444 + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 445 + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 446 + [ROUTER_HASH_MSK_DST_IP] = BIT(18), 447 + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 448 + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 449 + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 450 + [ROUTER_HASH_MSK_METADATA] = BIT(22), 451 + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 452 + /* Bits 23-31 reserved */ 453 + }; 454 + 455 + IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 456 + 0x0000085c, 0x0070); 457 + 458 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 459 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 460 + 461 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 462 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 463 + 464 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 465 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 466 + 467 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 468 + [UC_INTR] = BIT(0), 469 + /* Bits 1-31 reserved */ 470 + }; 471 + 472 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 473 + 474 + /* Valid bits defined by ipa->available */ 475 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); 476 + 477 + /* Valid bits defined by ipa->available */ 478 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); 479 + 480 + /* Valid bits defined by ipa->available */ 481 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); 482 + 483 + static const struct ipa_reg *ipa_reg_array[] = { 484 + [COMP_CFG] = &ipa_reg_comp_cfg, 485 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 486 + [ROUTE] = &ipa_reg_route, 487 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 488 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 489 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 490 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 491 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 492 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 493 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 494 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 495 + [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 496 + [FLAVOR_0] = &ipa_reg_flavor_0, 497 + [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 498 + [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, 499 + [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, 500 + [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, 501 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 502 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 503 + [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, 504 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 505 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 506 + [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, 507 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 508 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 509 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 510 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 511 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 512 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 513 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 514 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 515 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 516 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 517 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 518 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 519 + [ENDP_STATUS] = &ipa_reg_endp_status, 520 + [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 521 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 522 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 523 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 524 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 525 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 526 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 527 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 528 + }; 529 + 530 + const struct ipa_regs ipa_regs_v4_5 = { 531 + .reg_count = ARRAY_SIZE(ipa_reg_array), 532 + .reg = ipa_reg_array, 533 + };
+509
drivers/net/ipa/reg/ipa_reg-v4.9.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* Copyright (C) 2022 Linaro Ltd. */ 4 + 5 + #include <linux/types.h> 6 + 7 + #include "../ipa.h" 8 + #include "../ipa_reg.h" 9 + 10 + static const u32 ipa_reg_comp_cfg_fmask[] = { 11 + [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 12 + [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 + /* Bit 4 reserved */ 16 + [IPA_QMB_SELECT_CONS_EN] = BIT(5), 17 + [IPA_QMB_SELECT_PROD_EN] = BIT(6), 18 + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 19 + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 20 + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 21 + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 22 + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 23 + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 24 + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 25 + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 26 + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 27 + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 28 + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17), 29 + [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 30 + [GENQMB_AOOOWR] = BIT(20), 31 + [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 32 + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22), 33 + /* Bits 25-29 reserved */ 34 + [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 35 + [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 36 + }; 37 + 38 + IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 39 + 40 + static const u32 ipa_reg_clkon_cfg_fmask[] = { 41 + [CLKON_RX] = BIT(0), 42 + [CLKON_PROC] = BIT(1), 43 + [TX_WRAPPER] = BIT(2), 44 + [CLKON_MISC] = BIT(3), 45 + [RAM_ARB] = BIT(4), 46 + [FTCH_HPS] = BIT(5), 47 + [FTCH_DPS] = BIT(6), 48 + [CLKON_HPS] = BIT(7), 49 + [CLKON_DPS] = BIT(8), 50 + [RX_HPS_CMDQS] = BIT(9), 51 + [HPS_DPS_CMDQS] = BIT(10), 52 + [DPS_TX_CMDQS] = BIT(11), 53 + [RSRC_MNGR] = BIT(12), 54 + [CTX_HANDLER] = BIT(13), 55 + [ACK_MNGR] = BIT(14), 56 + [D_DCPH] = BIT(15), 57 + [H_DCPH] = BIT(16), 58 + [CLKON_DCMP] = BIT(17), 59 + [NTF_TX_CMDQS] = BIT(18), 60 + [CLKON_TX_0] = BIT(19), 61 + [CLKON_TX_1] = BIT(20), 62 + [CLKON_FNR] = BIT(21), 63 + [QSB2AXI_CMDQ_L] = BIT(22), 64 + [AGGR_WRAPPER] = BIT(23), 65 + [RAM_SLAVEWAY] = BIT(24), 66 + [CLKON_QMB] = BIT(25), 67 + [WEIGHT_ARB] = BIT(26), 68 + [GSI_IF] = BIT(27), 69 + [CLKON_GLOBAL] = BIT(28), 70 + [GLOBAL_2X_CLK] = BIT(29), 71 + [DPL_FIFO] = BIT(30), 72 + [DRBIP] = BIT(31), 73 + }; 74 + 75 + IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 76 + 77 + static const u32 ipa_reg_route_fmask[] = { 78 + [ROUTE_DIS] = BIT(0), 79 + [ROUTE_DEF_PIPE] = GENMASK(5, 1), 80 + [ROUTE_DEF_HDR_TABLE] = BIT(6), 81 + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 82 + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 83 + /* Bits 22-23 reserved */ 84 + [ROUTE_DEF_RETAIN_HDR] = BIT(24), 85 + /* Bits 25-31 reserved */ 86 + }; 87 + 88 + IPA_REG_FIELDS(ROUTE, route, 0x00000048); 89 + 90 + static const u32 ipa_reg_shared_mem_size_fmask[] = { 91 + [MEM_SIZE] = GENMASK(15, 0), 92 + [MEM_BADDR] = GENMASK(31, 16), 93 + }; 94 + 95 + IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 96 + 97 + static const u32 ipa_reg_qsb_max_writes_fmask[] = { 98 + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 99 + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 100 + /* Bits 8-31 reserved */ 101 + }; 102 + 103 + IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 104 + 105 + static const u32 ipa_reg_qsb_max_reads_fmask[] = { 106 + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 107 + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 108 + /* Bits 8-15 reserved */ 109 + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 110 + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 111 + }; 112 + 113 + IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 114 + 115 + static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 116 + [IPV6_ROUTER_HASH] = BIT(0), 117 + /* Bits 1-3 reserved */ 118 + [IPV6_FILTER_HASH] = BIT(4), 119 + /* Bits 5-7 reserved */ 120 + [IPV4_ROUTER_HASH] = BIT(8), 121 + /* Bits 9-11 reserved */ 122 + [IPV4_FILTER_HASH] = BIT(12), 123 + /* Bits 13-31 reserved */ 124 + }; 125 + 126 + IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 127 + 128 + static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 129 + [IPV6_ROUTER_HASH] = BIT(0), 130 + /* Bits 1-3 reserved */ 131 + [IPV6_FILTER_HASH] = BIT(4), 132 + /* Bits 5-7 reserved */ 133 + [IPV4_ROUTER_HASH] = BIT(8), 134 + /* Bits 9-11 reserved */ 135 + [IPV4_FILTER_HASH] = BIT(12), 136 + /* Bits 13-31 reserved */ 137 + }; 138 + 139 + IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 140 + 141 + /* Valid bits defined by ipa->available */ 142 + IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); 143 + 144 + static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 145 + [IPA_BASE_ADDR] = GENMASK(17, 0), 146 + /* Bits 18-31 reserved */ 147 + }; 148 + 149 + /* Offset must be a multiple of 8 */ 150 + IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 151 + 152 + /* Valid bits defined by ipa->available */ 153 + IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 154 + 155 + static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 156 + /* Bits 0-1 reserved */ 157 + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 158 + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 159 + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 160 + [DMAW_MAX_BEATS_256_DIS] = BIT(11), 161 + [PA_MASK_EN] = BIT(12), 162 + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 163 + [DUAL_TX_ENABLE] = BIT(17), 164 + [SSPND_PA_NO_START_STATE] = BIT(18), 165 + /* Bits 19-31 reserved */ 166 + }; 167 + 168 + IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 169 + 170 + static const u32 ipa_reg_flavor_0_fmask[] = { 171 + [MAX_PIPES] = GENMASK(3, 0), 172 + /* Bits 4-7 reserved */ 173 + [MAX_CONS_PIPES] = GENMASK(12, 8), 174 + /* Bits 13-15 reserved */ 175 + [MAX_PROD_PIPES] = GENMASK(20, 16), 176 + /* Bits 21-23 reserved */ 177 + [PROD_LOWEST] = GENMASK(27, 24), 178 + /* Bits 28-31 reserved */ 179 + }; 180 + 181 + IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 182 + 183 + static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 184 + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 185 + [CONST_NON_IDLE_ENABLE] = BIT(16), 186 + /* Bits 17-31 reserved */ 187 + }; 188 + 189 + IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 190 + 191 + static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { 192 + [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 193 + /* Bits 5-6 reserved */ 194 + [DPL_TIMESTAMP_SEL] = BIT(7), 195 + [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 196 + /* Bits 13-15 reserved */ 197 + [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 198 + /* Bits 21-31 reserved */ 199 + }; 200 + 201 + IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 202 + 203 + static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { 204 + [DIV_VALUE] = GENMASK(8, 0), 205 + /* Bits 9-30 reserved */ 206 + [DIV_ENABLE] = BIT(31), 207 + }; 208 + 209 + IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 210 + 211 + static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { 212 + [PULSE_GRAN_0] = GENMASK(2, 0), 213 + [PULSE_GRAN_1] = GENMASK(5, 3), 214 + [PULSE_GRAN_2] = GENMASK(8, 6), 215 + }; 216 + 217 + IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 218 + 219 + static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 220 + [X_MIN_LIM] = GENMASK(5, 0), 221 + /* Bits 6-7 reserved */ 222 + [X_MAX_LIM] = GENMASK(13, 8), 223 + /* Bits 14-15 reserved */ 224 + [Y_MIN_LIM] = GENMASK(21, 16), 225 + /* Bits 22-23 reserved */ 226 + [Y_MAX_LIM] = GENMASK(29, 24), 227 + /* Bits 30-31 reserved */ 228 + }; 229 + 230 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 231 + 0x00000400, 0x0020); 232 + 233 + static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 234 + [X_MIN_LIM] = GENMASK(5, 0), 235 + /* Bits 6-7 reserved */ 236 + [X_MAX_LIM] = GENMASK(13, 8), 237 + /* Bits 14-15 reserved */ 238 + [Y_MIN_LIM] = GENMASK(21, 16), 239 + /* Bits 22-23 reserved */ 240 + [Y_MAX_LIM] = GENMASK(29, 24), 241 + /* Bits 30-31 reserved */ 242 + }; 243 + 244 + IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 245 + 0x00000404, 0x0020); 246 + 247 + static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 248 + [X_MIN_LIM] = GENMASK(5, 0), 249 + /* Bits 6-7 reserved */ 250 + [X_MAX_LIM] = GENMASK(13, 8), 251 + /* Bits 14-15 reserved */ 252 + [Y_MIN_LIM] = GENMASK(21, 16), 253 + /* Bits 22-23 reserved */ 254 + [Y_MAX_LIM] = GENMASK(29, 24), 255 + /* Bits 30-31 reserved */ 256 + }; 257 + 258 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 259 + 0x00000500, 0x0020); 260 + 261 + static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 262 + [X_MIN_LIM] = GENMASK(5, 0), 263 + /* Bits 6-7 reserved */ 264 + [X_MAX_LIM] = GENMASK(13, 8), 265 + /* Bits 14-15 reserved */ 266 + [Y_MIN_LIM] = GENMASK(21, 16), 267 + /* Bits 22-23 reserved */ 268 + [Y_MAX_LIM] = GENMASK(29, 24), 269 + /* Bits 30-31 reserved */ 270 + }; 271 + 272 + IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 273 + 0x00000504, 0x0020); 274 + 275 + static const u32 ipa_reg_endp_init_cfg_fmask[] = { 276 + [FRAG_OFFLOAD_EN] = BIT(0), 277 + [CS_OFFLOAD_EN] = GENMASK(2, 1), 278 + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 279 + /* Bit 7 reserved */ 280 + [CS_GEN_QMB_MASTER_SEL] = BIT(8), 281 + /* Bits 9-31 reserved */ 282 + }; 283 + 284 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 285 + 286 + static const u32 ipa_reg_endp_init_nat_fmask[] = { 287 + [NAT_EN] = GENMASK(1, 0), 288 + /* Bits 2-31 reserved */ 289 + }; 290 + 291 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 292 + 293 + static const u32 ipa_reg_endp_init_hdr_fmask[] = { 294 + [HDR_LEN] = GENMASK(5, 0), 295 + [HDR_OFST_METADATA_VALID] = BIT(6), 296 + [HDR_OFST_METADATA] = GENMASK(12, 7), 297 + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 298 + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 299 + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 300 + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 301 + [HDR_LEN_MSB] = GENMASK(29, 28), 302 + [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 303 + }; 304 + 305 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 306 + 307 + static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 308 + [HDR_ENDIANNESS] = BIT(0), 309 + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 310 + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 311 + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 312 + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 313 + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 314 + /* Bits 14-15 reserved */ 315 + [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 316 + [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 317 + [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 318 + /* Bits 22-31 reserved */ 319 + }; 320 + 321 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 322 + 323 + IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 324 + 0x00000818, 0x0070); 325 + 326 + static const u32 ipa_reg_endp_init_mode_fmask[] = { 327 + [ENDP_MODE] = GENMASK(2, 0), 328 + [DCPH_ENABLE] = BIT(3), 329 + [DEST_PIPE_INDEX] = GENMASK(8, 4), 330 + /* Bits 9-11 reserved */ 331 + [BYTE_THRESHOLD] = GENMASK(27, 12), 332 + [PIPE_REPLICATION_EN] = BIT(28), 333 + [PAD_EN] = BIT(29), 334 + [DRBIP_ACL_ENABLE] = BIT(30), 335 + /* Bit 31 reserved */ 336 + }; 337 + 338 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 339 + 340 + static const u32 ipa_reg_endp_init_aggr_fmask[] = { 341 + [AGGR_EN] = GENMASK(1, 0), 342 + [AGGR_TYPE] = GENMASK(4, 2), 343 + [BYTE_LIMIT] = GENMASK(10, 5), 344 + /* Bit 11 reserved */ 345 + [TIME_LIMIT] = GENMASK(16, 12), 346 + [PKT_LIMIT] = GENMASK(22, 17), 347 + [SW_EOF_ACTIVE] = BIT(23), 348 + [FORCE_CLOSE] = BIT(24), 349 + /* Bit 25 reserved */ 350 + [HARD_BYTE_LIMIT_EN] = BIT(26), 351 + [AGGR_GRAN_SEL] = BIT(27), 352 + /* Bits 28-31 reserved */ 353 + }; 354 + 355 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 356 + 357 + static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 358 + [HOL_BLOCK_EN] = BIT(0), 359 + /* Bits 1-31 reserved */ 360 + }; 361 + 362 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 363 + 0x0000082c, 0x0070); 364 + 365 + static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 366 + [TIMER_LIMIT] = GENMASK(4, 0), 367 + /* Bits 5-7 reserved */ 368 + [TIMER_GRAN_SEL] = BIT(8), 369 + /* Bits 9-31 reserved */ 370 + }; 371 + 372 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 373 + 0x00000830, 0x0070); 374 + 375 + static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 376 + [DEAGGR_HDR_LEN] = GENMASK(5, 0), 377 + [SYSPIPE_ERR_DETECTION] = BIT(6), 378 + [PACKET_OFFSET_VALID] = BIT(7), 379 + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 380 + [IGNORE_MIN_PKT_ERR] = BIT(14), 381 + /* Bit 15 reserved */ 382 + [MAX_PACKET_LEN] = GENMASK(31, 16), 383 + }; 384 + 385 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 386 + 387 + static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 388 + [ENDP_RSRC_GRP] = GENMASK(1, 0), 389 + /* Bits 2-31 reserved */ 390 + }; 391 + 392 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 393 + 0x00000838, 0x0070); 394 + 395 + static const u32 ipa_reg_endp_init_seq_fmask[] = { 396 + [SEQ_TYPE] = GENMASK(7, 0), 397 + /* Bits 8-31 reserved */ 398 + }; 399 + 400 + IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 401 + 402 + static const u32 ipa_reg_endp_status_fmask[] = { 403 + [STATUS_EN] = BIT(0), 404 + [STATUS_ENDP] = GENMASK(5, 1), 405 + /* Bits 6-8 reserved */ 406 + [STATUS_PKT_SUPPRESS] = BIT(9), 407 + /* Bits 10-31 reserved */ 408 + }; 409 + 410 + IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 411 + 412 + static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 413 + [FILTER_HASH_MSK_SRC_ID] = BIT(0), 414 + [FILTER_HASH_MSK_SRC_IP] = BIT(1), 415 + [FILTER_HASH_MSK_DST_IP] = BIT(2), 416 + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 417 + [FILTER_HASH_MSK_DST_PORT] = BIT(4), 418 + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 419 + [FILTER_HASH_MSK_METADATA] = BIT(6), 420 + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 421 + /* Bits 7-15 reserved */ 422 + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 423 + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 424 + [ROUTER_HASH_MSK_DST_IP] = BIT(18), 425 + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 426 + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 427 + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 428 + [ROUTER_HASH_MSK_METADATA] = BIT(22), 429 + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 430 + /* Bits 23-31 reserved */ 431 + }; 432 + 433 + IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 434 + 0x0000085c, 0x0070); 435 + 436 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 437 + IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); 438 + 439 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 440 + IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); 441 + 442 + /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 443 + IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); 444 + 445 + static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 446 + [UC_INTR] = BIT(0), 447 + /* Bits 1-31 reserved */ 448 + }; 449 + 450 + IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); 451 + 452 + /* Valid bits defined by ipa->available */ 453 + IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00004030 + 0x1000 * GSI_EE_AP); 454 + 455 + /* Valid bits defined by ipa->available */ 456 + IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00004034 + 0x1000 * GSI_EE_AP); 457 + 458 + /* Valid bits defined by ipa->available */ 459 + IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00004038 + 0x1000 * GSI_EE_AP); 460 + 461 + static const struct ipa_reg *ipa_reg_array[] = { 462 + [COMP_CFG] = &ipa_reg_comp_cfg, 463 + [CLKON_CFG] = &ipa_reg_clkon_cfg, 464 + [ROUTE] = &ipa_reg_route, 465 + [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 466 + [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 467 + [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 468 + [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 469 + [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 470 + [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 471 + [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 472 + [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 473 + [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 474 + [FLAVOR_0] = &ipa_reg_flavor_0, 475 + [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 476 + [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, 477 + [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, 478 + [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, 479 + [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 480 + [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 481 + [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 482 + [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 483 + [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 484 + [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 485 + [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 486 + [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 487 + [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 488 + [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 489 + [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 490 + [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 491 + [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 492 + [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 493 + [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 494 + [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 495 + [ENDP_STATUS] = &ipa_reg_endp_status, 496 + [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 497 + [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 498 + [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 499 + [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 500 + [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 501 + [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 502 + [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 503 + [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 504 + }; 505 + 506 + const struct ipa_regs ipa_regs_v4_9 = { 507 + .reg_count = ARRAY_SIZE(ipa_reg_array), 508 + .reg = ipa_reg_array, 509 + };