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drm/amdgpu/mes_v12_1: Fix iterator reuse in mes_v12_1_test_ring()

This code waits for the MES self-test to complete by repeatedly checking
a register or memory value until it becomes valid or a timeout occurs.
The fix ensures the timeout counter works correctly by not reusing the
same variable inside another loop.

mes_v12_1_test_ring() uses 'i' as the outer timeout loop counter, but
reuses the same variable for the inner XCC scan in cooperative mode.

This makes the timeout counter ambiguous and can lead to incorrect
timeout handling. It also triggers a Smatch warning about reusing the
outer loop iterator.

Fix this by introducing a separate iterator for the inner XCC loop so
that 'i' continues to represent only the timeout wait duration.

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c:2080 mes_v12_1_test_ring()
warn: reusing outside iterator: 'i'

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
2069 atomic64_set((atomic64_t *)wptr_cpu_addr, wptr);
2070 WDOORBELL64(doorbell_idx, wptr);
2071
2072 for (i = 0; i < adev->usec_timeout; i++) {

i is counting usec

2073 if (queue_type == AMDGPU_RING_TYPE_SDMA) {
2074 tmp = le32_to_cpu(*cpu_ptr);
2075 } else {
2076 if (!adev->mes.enable_coop_mode) {
2077 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2078 regSCRATCH_REG0);
2079 } else {
--> 2080 for (i = 0; i < num_xcc; i++) {

and then re-used to count something else

Fixes: 44e5195fa3d4 ("drm/amdgpu/mes_v12_1: add mes self test")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Jack Xiao <Jack.Xiao@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Srinivasan Shanmugam and committed by
Alex Deucher
e1fb16ce 4f2c86c6

+4 -4
+4 -4
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
··· 2028 2028 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2029 2029 int sdma_ring_align = 0x10, compute_ring_align = 0x100; 2030 2030 uint32_t tmp, xcc_offset; 2031 - int r = 0, i, wptr = 0; 2031 + int r = 0, i, j, wptr = 0; 2032 2032 2033 2033 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 2034 2034 if (!adev->mes.enable_coop_mode) { ··· 2077 2077 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2078 2078 regSCRATCH_REG0); 2079 2079 } else { 2080 - for (i = 0; i < num_xcc; i++) { 2081 - if (xcc_id != adev->mes.master_xcc_ids[i]) 2080 + for (j = 0; j < num_xcc; j++) { 2081 + if (xcc_id != adev->mes.master_xcc_ids[j]) 2082 2082 continue; 2083 2083 2084 - tmp = RREG32_SOC15(GC, GET_INST(GC, i), 2084 + tmp = RREG32_SOC15(GC, GET_INST(GC, j), 2085 2085 regSCRATCH_REG0); 2086 2086 if (tmp != 0xDEADBEEF) 2087 2087 break;