Merge tag 'drm-misc-next-2025-02-27' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

+2 -1

.mailmap

··· 323 323 Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net> 324 324 Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com> 325 325 Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com> 326 - Jeffrey Hugo <quic_jhugo@quicinc.com> <jhugo@codeaurora.org> 326 + Jeff Hugo <jeff.hugo@oss.qualcomm.com> <jhugo@codeaurora.org> 327 + Jeff Hugo <jeff.hugo@oss.qualcomm.com> <quic_jhugo@quicinc.com> 327 328 Jens Axboe <axboe@kernel.dk> <axboe@suse.de> 328 329 Jens Axboe <axboe@kernel.dk> <jens.axboe@oracle.com> 329 330 Jens Axboe <axboe@kernel.dk> <axboe@fb.com>

+2

Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml

··· 40 40 - auo,g185han01 41 41 # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel 42 42 - auo,g190ean01 43 + # BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel 44 + - boe,av123z7m-n17 43 45 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel 44 46 - koe,tx26d202vm0bwa 45 47 # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200

+2

Documentation/devicetree/bindings/display/panel/panel-simple.yaml

··· 63 63 - auo,t215hvn01 64 64 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel 65 65 - avic,tm070ddh03 66 + # BOE AV101HDT-a10 10.1" 1280x720 LVDS panel 67 + - boe,av101hdt-a10 66 68 # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel 67 69 - boe,bp082wx1-100 68 70 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel

+72

Documentation/devicetree/bindings/display/panel/raydium,rm67200.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/panel/raydium,rm67200.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Raydium RM67200 based MIPI-DSI panels 8 + 9 + maintainers: 10 + - Sebastian Reichel <sebastian.reichel@collabora.com> 11 + 12 + allOf: 13 + - $ref: panel-common.yaml# 14 + 15 + properties: 16 + compatible: 17 + items: 18 + - enum: 19 + - wanchanglong,w552793baa 20 + - const: raydium,rm67200 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + vdd-supply: 26 + description: 2.8V Logic voltage 27 + 28 + iovcc-supply: 29 + description: 1.8V IO voltage 30 + 31 + vsp-supply: 32 + description: positive 5.5V voltage 33 + 34 + vsn-supply: 35 + description: negative 5.5V voltage 36 + 37 + backlight: true 38 + port: true 39 + reset-gpios: true 40 + 41 + required: 42 + - compatible 43 + - port 44 + - reg 45 + - reset-gpios 46 + 47 + additionalProperties: false 48 + 49 + examples: 50 + - | 51 + #include <dt-bindings/gpio/gpio.h> 52 + dsi { 53 + #address-cells = <1>; 54 + #size-cells = <0>; 55 + panel@0 { 56 + compatible = "wanchanglong,w552793baa", "raydium,rm67200"; 57 + reg = <0>; 58 + 59 + vdd-supply = <&regulator1>; 60 + iovcc-supply = <&regulator2>; 61 + vsp-supply = <&regulator3>; 62 + vsn-supply = <&regulator4>; 63 + reset-gpios = <&gpiobank 42 GPIO_ACTIVE_LOW>; 64 + 65 + port { 66 + panel0_in: endpoint { 67 + remote-endpoint = <&dsi0_out>; 68 + }; 69 + }; 70 + }; 71 + }; 72 + ...

+77

Documentation/devicetree/bindings/display/panel/visionox,rm692e5.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/panel/visionox,rm692e5.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Visionox RM692E5 6.55" 2400x1080 120Hz MIPI-DSI Panel 8 + 9 + maintainers: 10 + - Danila Tikhonov <danila@jiaxyga.com> 11 + 12 + description: 13 + The Visionox RM692E5 is a generic DSI Panel IC used to control 14 + AMOLED panels. 15 + 16 + allOf: 17 + - $ref: panel-common.yaml# 18 + 19 + properties: 20 + compatible: 21 + oneOf: 22 + - enum: 23 + - visionox,rm692e5 24 + - items: 25 + - enum: 26 + - nothing,rm692e5-spacewar 27 + - const: visionox,rm692e5 28 + 29 + reg: 30 + maxItems: 1 31 + 32 + vdd-supply: 33 + description: 3.3V source voltage rail 34 + 35 + vddio-supply: 36 + description: 1.8V I/O source voltage rail 37 + 38 + reset-gpios: true 39 + port: true 40 + 41 + required: 42 + - compatible 43 + - reg 44 + - reset-gpios 45 + - vdd-supply 46 + - vddio-supply 47 + - port 48 + 49 + additionalProperties: false 50 + 51 + examples: 52 + - | 53 + #include <dt-bindings/gpio/gpio.h> 54 + 55 + dsi { 56 + #address-cells = <1>; 57 + #size-cells = <0>; 58 + 59 + panel@0 { 60 + compatible = "nothing,rm692e5-spacewar", 61 + "visionox,rm692e5"; 62 + reg = <0>; 63 + 64 + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 65 + 66 + vdd-supply = <&vdd_oled>; 67 + vddio-supply = <&vdd_io_oled>; 68 + 69 + port { 70 + panel_in: endpoint { 71 + remote-endpoint = <&mdss_dsi0_out>; 72 + }; 73 + }; 74 + }; 75 + }; 76 + 77 + ...

+7

Documentation/gpu/drm-internals.rst

··· 208 208 ``CONFIG_VIRTIO_UML`` and ``CONFIG_UML_PCI_OVER_VIRTIO`` are not 209 209 included in it because they are only required for User Mode Linux. 210 210 211 + KUnit Coverage Rules 212 + ~~~~~~~~~~~~~~~~~~~~ 213 + 214 + KUnit support is gradually added to the DRM framework and helpers. There's no 215 + general requirement for the framework and helpers to have KUnit tests at the 216 + moment. However, patches that are affecting a function or helper already 217 + covered by KUnit tests must provide tests if the change calls for one. 211 218 212 219 Legacy Support Code 213 220 ===================

+5 -3

MAINTAINERS

··· 7347 7347 F: drivers/gpu/drm/mgag200/ 7348 7348 7349 7349 DRM DRIVER FOR MI0283QT 7350 - S: Orphan 7350 + M: Alex Lanzano <lanzano.alex@gmail.com> 7351 + S: Maintained 7351 7352 T: git https://gitlab.freedesktop.org/drm/misc/kernel.git 7352 7353 F: Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt 7353 7354 F: drivers/gpu/drm/tiny/mi0283qt.c ··· 7450 7449 F: drivers/gpu/drm/bridge/parade-ps8640.c 7451 7450 7452 7451 DRM DRIVER FOR PERVASIVE DISPLAYS REPAPER PANELS 7453 - S: Orphan 7452 + M: Alex Lanzano <lanzano.alex@gmail.com> 7453 + S: Maintained 7454 7454 T: git https://gitlab.freedesktop.org/drm/misc/kernel.git 7455 7455 F: Documentation/devicetree/bindings/display/repaper.txt 7456 7456 F: drivers/gpu/drm/tiny/repaper.c ··· 19427 19425 F: include/dt-bindings/clock/qcom,* 19428 19426 19429 19427 QUALCOMM CLOUD AI (QAIC) DRIVER 19430 - M: Jeffrey Hugo <quic_jhugo@quicinc.com> 19428 + M: Jeff Hugo <jeff.hugo@oss.qualcomm.com> 19431 19429 R: Carl Vanderlip <quic_carlv@quicinc.com> 19432 19430 L: linux-arm-msm@vger.kernel.org 19433 19431 L: dri-devel@lists.freedesktop.org

+1 -1

drivers/bus/mhi/host/boot.c

··· 608 608 return; 609 609 610 610 error_ready_state: 611 - if (fw_load_type == MHI_FW_LOAD_FBC) { 611 + if (mhi_cntrl->fbc_image) { 612 612 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); 613 613 mhi_cntrl->fbc_image = NULL; 614 614 }

+19 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

··· 411 411 return fence; 412 412 } 413 413 414 - #define to_drm_sched_job(sched_job) \ 415 - container_of((sched_job), struct drm_sched_job, queue_node) 414 + /* 415 + * This is a duplicate function from DRM scheduler sched_internal.h. 416 + * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due 417 + * latter being incorrect and racy. 418 + * 419 + * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/ 420 + */ 421 + static struct drm_sched_job * 422 + drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 423 + { 424 + struct spsc_node *node; 425 + 426 + node = spsc_queue_pop(&entity->job_queue); 427 + if (!node) 428 + return NULL; 429 + 430 + return container_of(node, struct drm_sched_job, queue_node); 431 + } 416 432 417 433 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 418 434 { ··· 441 425 struct drm_sched_rq *rq = sched->sched_rq[i]; 442 426 spin_lock(&rq->lock); 443 427 list_for_each_entry(s_entity, &rq->entities, list) { 444 - while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 428 + while ((s_job = drm_sched_entity_queue_pop(s_entity))) { 445 429 struct drm_sched_fence *s_fence = s_job->s_fence; 446 430 447 431 dma_fence_signal(&s_fence->scheduled);

+1 -3

drivers/gpu/drm/aspeed/aspeed_gfx_drv.c

··· 144 144 struct aspeed_gfx *priv = to_aspeed_gfx(drm); 145 145 struct device_node *np = pdev->dev.of_node; 146 146 const struct aspeed_gfx_config *config; 147 - struct resource *res; 148 147 int ret; 149 148 150 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 151 - priv->base = devm_ioremap_resource(drm->dev, res); 149 + priv->base = devm_platform_ioremap_resource(pdev, 0); 152 150 if (IS_ERR(priv->base)) 153 151 return PTR_ERR(priv->base); 154 152

+3 -3

drivers/gpu/drm/bridge/ti-sn65dsi86.c

··· 195 195 struct gpio_chip gchip; 196 196 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 197 197 #endif 198 - #if defined(CONFIG_PWM) 198 + #if IS_REACHABLE(CONFIG_PWM) 199 199 struct pwm_chip *pchip; 200 200 bool pwm_enabled; 201 201 atomic_t pwm_pin_busy; ··· 1362 1362 /* ----------------------------------------------------------------------------- 1363 1363 * PWM Controller 1364 1364 */ 1365 - #if defined(CONFIG_PWM) 1365 + #if IS_REACHABLE(CONFIG_PWM) 1366 1366 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1367 1367 { 1368 1368 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; ··· 1956 1956 return ret; 1957 1957 } 1958 1958 1959 - if (IS_ENABLED(CONFIG_PWM)) { 1959 + if (IS_REACHABLE(CONFIG_PWM)) { 1960 1960 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1961 1961 if (ret) 1962 1962 return ret;

+61

drivers/gpu/drm/display/drm_dp_helper.c

··· 2876 2876 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2877 2877 2878 2878 /** 2879 + * drm_dp_lttpr_set_transparent_mode() - set the LTTPR in transparent mode 2880 + * @aux: DisplayPort AUX channel 2881 + * @enable: Enable or disable transparent mode 2882 + * 2883 + * Returns: 0 on success or a negative error code on failure. 2884 + */ 2885 + int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable) 2886 + { 2887 + u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 2888 + DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 2889 + int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val); 2890 + 2891 + if (ret < 0) 2892 + return ret; 2893 + 2894 + return (ret == 1) ? 0 : -EIO; 2895 + } 2896 + EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode); 2897 + 2898 + /** 2899 + * drm_dp_lttpr_init() - init LTTPR transparency mode according to DP standard 2900 + * @aux: DisplayPort AUX channel 2901 + * @lttpr_count: Number of LTTPRs. Between 0 and 8, according to DP standard. 2902 + * Negative error code for any non-valid number. 2903 + * See drm_dp_lttpr_count(). 2904 + * 2905 + * Returns: 0 on success or a negative error code on failure. 2906 + */ 2907 + int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count) 2908 + { 2909 + int ret; 2910 + 2911 + if (!lttpr_count) 2912 + return 0; 2913 + 2914 + /* 2915 + * See DP Standard v2.0 3.6.6.1 about the explicit disabling of 2916 + * non-transparent mode and the disable->enable non-transparent mode 2917 + * sequence. 2918 + */ 2919 + ret = drm_dp_lttpr_set_transparent_mode(aux, true); 2920 + if (ret) 2921 + return ret; 2922 + 2923 + if (lttpr_count < 0) 2924 + return -ENODEV; 2925 + 2926 + if (drm_dp_lttpr_set_transparent_mode(aux, false)) { 2927 + /* 2928 + * Roll-back to transparent mode if setting non-transparent 2929 + * mode has failed 2930 + */ 2931 + drm_dp_lttpr_set_transparent_mode(aux, true); 2932 + return -EINVAL; 2933 + } 2934 + 2935 + return 0; 2936 + } 2937 + EXPORT_SYMBOL(drm_dp_lttpr_init); 2938 + 2939 + /** 2879 2940 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2880 2941 * @caps: LTTPR common capabilities 2881 2942 *

+4

drivers/gpu/drm/drm_atomic_helper.c

··· 3409 3409 * This implies a reset of all active components available between the CRTC and 3410 3410 * connectors. 3411 3411 * 3412 + * NOTE: This relies on resetting &drm_crtc_state.connectors_changed. 3413 + * For drivers which optimize out unnecessary modesets this will result in 3414 + * a no-op commit, achieving nothing. 3415 + * 3412 3416 * Returns: 3413 3417 * 0 on success or a negative error code on failure. 3414 3418 */

+23 -19

drivers/gpu/drm/drm_mipi_dsi.c

··· 1266 1266 EXPORT_SYMBOL(mipi_dsi_dcs_set_page_address); 1267 1267 1268 1268 /** 1269 - * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect 1270 - * output signal on the TE signal line 1271 - * @dsi: DSI peripheral device 1272 - * 1273 - * Return: 0 on success or a negative error code on failure 1274 - */ 1275 - int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi) 1276 - { 1277 - ssize_t err; 1278 - 1279 - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0); 1280 - if (err < 0) 1281 - return err; 1282 - 1283 - return 0; 1284 - } 1285 - EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_off); 1286 - 1287 - /** 1288 1269 * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect 1289 1270 * output signal on the TE signal line. 1290 1271 * @dsi: DSI peripheral device ··· 1693 1712 } 1694 1713 } 1695 1714 EXPORT_SYMBOL(mipi_dsi_turn_on_peripheral_multi); 1715 + 1716 + /** 1717 + * mipi_dsi_dcs_set_tear_off_multi() - turn off the display module's Tearing Effect 1718 + * output signal on the TE signal line 1719 + * @ctx: Context for multiple DSI transactions 1720 + */ 1721 + void mipi_dsi_dcs_set_tear_off_multi(struct mipi_dsi_multi_context *ctx) 1722 + { 1723 + struct mipi_dsi_device *dsi = ctx->dsi; 1724 + struct device *dev = &dsi->dev; 1725 + ssize_t err; 1726 + 1727 + if (ctx->accum_err) 1728 + return; 1729 + 1730 + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0); 1731 + if (err < 0) { 1732 + ctx->accum_err = err; 1733 + dev_err(dev, "Failed to set tear off: %d\n", 1734 + ctx->accum_err); 1735 + } 1736 + } 1737 + EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_off_multi); 1696 1738 1697 1739 /** 1698 1740 * mipi_dsi_dcs_soft_reset_multi() - perform a software reset of the display module

+1 -1

drivers/gpu/drm/drm_writeback.c

··· 213 213 } 214 214 215 215 /** 216 - * drm_writeback_connector_init_with_encoder - Initialize a writeback connector with 216 + * __drm_writeback_connector_init - Initialize a writeback connector with 217 217 * a custom encoder 218 218 * 219 219 * @dev: DRM device

+5 -19

drivers/gpu/drm/i915/display/intel_dp_link_training.c

··· 119 119 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 120 120 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 121 121 122 - if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1) 123 - return false; 124 - 125 122 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 126 123 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 127 124 ··· 143 146 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 144 147 { 145 148 int lttpr_count; 149 + int ret; 146 150 147 151 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 148 152 return 0; ··· 170 172 return lttpr_count; 171 173 } 172 174 173 - /* 174 - * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 175 - * non-transparent mode and the disable->enable non-transparent mode 176 - * sequence. 177 - */ 178 - intel_dp_set_lttpr_transparent_mode(intel_dp, true); 179 - 180 - /* 181 - * In case of unsupported number of LTTPRs or failing to switch to 182 - * non-transparent mode fall-back to transparent link training mode, 183 - * still taking into account any LTTPR common lane- rate/count limits. 184 - */ 185 - if (lttpr_count < 0) 186 - goto out_reset_lttpr_count; 187 - 188 - if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 175 + ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); 176 + if (ret) { 189 177 lt_dbg(intel_dp, DP_PHY_DPRX, 190 178 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 191 179 ··· 179 195 180 196 goto out_reset_lttpr_count; 181 197 } 198 + 199 + intel_dp_set_lttpr_transparent_mode(intel_dp, false); 182 200 183 201 return lttpr_count; 184 202

+1 -3

drivers/gpu/drm/mediatek/mtk_disp_color.c

··· 96 96 { 97 97 struct device *dev = &pdev->dev; 98 98 struct mtk_disp_color *priv; 99 - struct resource *res; 100 99 int ret; 101 100 102 101 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 107 108 return dev_err_probe(dev, PTR_ERR(priv->clk), 108 109 "failed to get color clk\n"); 109 110 110 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 111 - priv->regs = devm_ioremap_resource(dev, res); 111 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 112 112 if (IS_ERR(priv->regs)) 113 113 return dev_err_probe(dev, PTR_ERR(priv->regs), 114 114 "failed to ioremap color\n");

+1 -3

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

··· 256 256 { 257 257 struct device *dev = &pdev->dev; 258 258 struct mtk_disp_gamma *priv; 259 - struct resource *res; 260 259 int ret; 261 260 262 261 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 267 268 return dev_err_probe(dev, PTR_ERR(priv->clk), 268 269 "failed to get gamma clk\n"); 269 270 270 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 271 - priv->regs = devm_ioremap_resource(dev, res); 271 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 272 272 if (IS_ERR(priv->regs)) 273 273 return dev_err_probe(dev, PTR_ERR(priv->regs), 274 274 "failed to ioremap gamma\n");

+1 -3

drivers/gpu/drm/mediatek/mtk_disp_merge.c

··· 306 306 static int mtk_disp_merge_probe(struct platform_device *pdev) 307 307 { 308 308 struct device *dev = &pdev->dev; 309 - struct resource *res; 310 309 struct mtk_disp_merge *priv; 311 310 int ret; 312 311 ··· 313 314 if (!priv) 314 315 return -ENOMEM; 315 316 316 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 317 - priv->regs = devm_ioremap_resource(dev, res); 317 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 318 318 if (IS_ERR(priv->regs)) 319 319 return dev_err_probe(dev, PTR_ERR(priv->regs), 320 320 "failed to ioremap merge\n");

+1 -3

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

··· 604 604 { 605 605 struct device *dev = &pdev->dev; 606 606 struct mtk_disp_ovl *priv; 607 - struct resource *res; 608 607 int irq; 609 608 int ret; 610 609 ··· 620 621 return dev_err_probe(dev, PTR_ERR(priv->clk), 621 622 "failed to get ovl clk\n"); 622 623 623 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 624 - priv->regs = devm_ioremap_resource(dev, res); 624 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 625 625 if (IS_ERR(priv->regs)) 626 626 return dev_err_probe(dev, PTR_ERR(priv->regs), 627 627 "failed to ioremap ovl\n");

+1 -3

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

··· 313 313 { 314 314 struct device *dev = &pdev->dev; 315 315 struct mtk_disp_rdma *priv; 316 - struct resource *res; 317 316 int irq; 318 317 int ret; 319 318 ··· 329 330 return dev_err_probe(dev, PTR_ERR(priv->clk), 330 331 "failed to get rdma clk\n"); 331 332 332 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 333 - priv->regs = devm_ioremap_resource(dev, res); 333 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 334 334 if (IS_ERR(priv->regs)) 335 335 return dev_err_probe(dev, PTR_ERR(priv->regs), 336 336 "failed to ioremap rdma\n");

+1 -3

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 1192 1192 { 1193 1193 struct mtk_dsi *dsi; 1194 1194 struct device *dev = &pdev->dev; 1195 - struct resource *regs; 1196 1195 int irq_num; 1197 1196 int ret; 1198 1197 ··· 1216 1217 if (IS_ERR(dsi->hs_clk)) 1217 1218 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n"); 1218 1219 1219 - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1220 - dsi->regs = devm_ioremap_resource(dev, regs); 1220 + dsi->regs = devm_platform_ioremap_resource(pdev, 0); 1221 1221 if (IS_ERR(dsi->regs)) 1222 1222 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n"); 1223 1223

+1 -3

drivers/gpu/drm/mediatek/mtk_hdmi.c

··· 1424 1424 struct device_node *cec_np, *remote, *i2c_np; 1425 1425 struct platform_device *cec_pdev; 1426 1426 struct regmap *regmap; 1427 - struct resource *mem; 1428 1427 int ret; 1429 1428 1430 1429 ret = mtk_hdmi_get_all_clk(hdmi, np); ··· 1469 1470 } 1470 1471 hdmi->sys_regmap = regmap; 1471 1472 1472 - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1473 - hdmi->regs = devm_ioremap_resource(dev, mem); 1473 + hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 1474 1474 if (IS_ERR(hdmi->regs)) { 1475 1475 ret = PTR_ERR(hdmi->regs); 1476 1476 goto put_device;

+1 -3

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

··· 291 291 static int mtk_mdp_rdma_probe(struct platform_device *pdev) 292 292 { 293 293 struct device *dev = &pdev->dev; 294 - struct resource *res; 295 294 struct mtk_mdp_rdma *priv; 296 295 int ret = 0; 297 296 ··· 298 299 if (!priv) 299 300 return -ENOMEM; 300 301 301 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 302 - priv->regs = devm_ioremap_resource(dev, res); 302 + priv->regs = devm_platform_ioremap_resource(pdev, 0); 303 303 if (IS_ERR(priv->regs)) 304 304 return dev_err_probe(dev, PTR_ERR(priv->regs), 305 305 "failed to ioremap rdma\n");

+15

drivers/gpu/drm/msm/dp/dp_display.c

··· 367 367 return 0; 368 368 } 369 369 370 + static void msm_dp_display_lttpr_init(struct msm_dp_display_private *dp) 371 + { 372 + u8 lttpr_caps[DP_LTTPR_COMMON_CAP_SIZE]; 373 + int rc; 374 + 375 + if (drm_dp_read_lttpr_common_caps(dp->aux, dp->panel->dpcd, lttpr_caps)) 376 + return; 377 + 378 + rc = drm_dp_lttpr_init(dp->aux, drm_dp_lttpr_count(lttpr_caps)); 379 + if (rc) 380 + DRM_ERROR("failed to set LTTPRs transparency mode, rc=%d\n", rc); 381 + } 382 + 370 383 static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) 371 384 { 372 385 struct drm_connector *connector = dp->msm_dp_display.connector; ··· 389 376 rc = msm_dp_panel_read_sink_caps(dp->panel, connector); 390 377 if (rc) 391 378 goto end; 379 + 380 + msm_dp_display_lttpr_init(dp); 392 381 393 382 msm_dp_link_process_request(dp->link); 394 383

+2 -15

drivers/gpu/drm/nouveau/nouveau_dp.c

··· 79 79 !drm_dp_read_lttpr_common_caps(aux, dpcd, outp->dp.lttpr.caps)) { 80 80 int nr = drm_dp_lttpr_count(outp->dp.lttpr.caps); 81 81 82 - if (nr) { 83 - drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, 84 - DP_PHY_REPEATER_MODE_TRANSPARENT); 85 - 86 - if (nr > 0) { 87 - ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, 88 - DP_PHY_REPEATER_MODE_NON_TRANSPARENT); 89 - if (ret != 1) { 90 - drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, 91 - DP_PHY_REPEATER_MODE_TRANSPARENT); 92 - } else { 93 - outp->dp.lttpr.nr = nr; 94 - } 95 - } 96 - } 82 + if (!drm_dp_lttpr_init(aux, nr)) 83 + outp->dp.lttpr.nr = nr; 97 84 } 98 85 99 86 ret = drm_dp_read_dpcd_caps(aux, dpcd);

+29

drivers/gpu/drm/panel/Kconfig

··· 573 573 Say Y here if you want to enable support for Raydium RM67191 FHD 574 574 (1080x1920) DSI panel. 575 575 576 + config DRM_PANEL_RAYDIUM_RM67200 577 + tristate "Raydium RM67200-based DSI panel" 578 + depends on OF 579 + depends on DRM_MIPI_DSI 580 + help 581 + Say Y here if you want to enable support for Raydium RM67200-based 582 + DSI video mode panels. This panel controller can be found in the 583 + Wanchanglong W552793BAA panel found on the Rockchip RK3588 EVB1 584 + evaluation boards. 585 + 576 586 config DRM_PANEL_RAYDIUM_RM68200 577 587 tristate "Raydium RM68200 720x1280 DSI video mode panel" 578 588 depends on OF ··· 935 925 that it can be automatically turned off when the panel goes into a 936 926 low power state. 937 927 928 + config DRM_PANEL_SUMMIT 929 + tristate "Apple Summit display panel" 930 + depends on OF 931 + depends on DRM_MIPI_DSI 932 + depends on BACKLIGHT_CLASS_DEVICE 933 + help 934 + Say Y if you want to enable support for the "Summit" display panel 935 + used as a touchbar on certain Apple laptops. 936 + 938 937 config DRM_PANEL_SYNAPTICS_R63353 939 938 tristate "Synaptics R63353-based panels" 940 939 depends on OF ··· 1014 995 help 1015 996 Say Y here if you want to enable support for Visionox 1016 997 RM69299 DSI Video Mode panel. 998 + 999 + config DRM_PANEL_VISIONOX_RM692E5 1000 + tristate "Visionox RM692E5" 1001 + depends on OF 1002 + depends on DRM_MIPI_DSI 1003 + depends on BACKLIGHT_CLASS_DEVICE 1004 + help 1005 + Say Y here if you want to enable support for Visionox RM692E5 amoled 1006 + display panels, such as the one found in the Nothing Phone (1) 1007 + smartphone. 1017 1008 1018 1009 config DRM_PANEL_VISIONOX_VTDR6130 1019 1010 tristate "Visionox VTDR6130"

+3

drivers/gpu/drm/panel/Makefile

··· 58 58 obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o 59 59 obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o 60 60 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o 61 + obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67200) += panel-raydium-rm67200.o 61 62 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o 62 63 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o 63 64 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o ··· 90 89 obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o 91 90 obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o 92 91 obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o 92 + obj-$(CONFIG_DRM_PANEL_SUMMIT) += panel-summit.o 93 93 obj-$(CONFIG_DRM_PANEL_SYNAPTICS_R63353) += panel-synaptics-r63353.o 94 94 obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o 95 95 obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) += panel-sony-td4353-jdi.o ··· 102 100 obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o 103 101 obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o 104 102 obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o 103 + obj-$(CONFIG_DRM_PANEL_VISIONOX_RM692E5) += panel-visionox-rm692e5.o 105 104 obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o 106 105 obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o 107 106 obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o

+1 -1

drivers/gpu/drm/panel/panel-ilitek-ili9882t.c

··· 607 607 608 608 ili->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 609 609 if (IS_ERR(ili->enable_gpio)) { 610 - dev_err(dev, "cannot get reset-gpios %ld\n", 610 + dev_err(dev, "cannot get enable-gpios %ld\n", 611 611 PTR_ERR(ili->enable_gpio)); 612 612 return PTR_ERR(ili->enable_gpio); 613 613 }

+499

drivers/gpu/drm/panel/panel-raydium-rm67200.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + // Copyright (c) 2024 Collabora 3 + 4 + #include <linux/delay.h> 5 + #include <linux/gpio/consumer.h> 6 + #include <linux/module.h> 7 + #include <linux/mod_devicetable.h> 8 + #include <linux/property.h> 9 + #include <linux/regulator/consumer.h> 10 + 11 + #include <drm/drm_mipi_dsi.h> 12 + #include <drm/drm_probe_helper.h> 13 + #include <drm/drm_modes.h> 14 + #include <drm/drm_panel.h> 15 + 16 + struct raydium_rm67200_panel_info { 17 + struct drm_display_mode mode; 18 + const struct regulator_bulk_data *regulators; 19 + int num_regulators; 20 + void (*panel_setup)(struct mipi_dsi_multi_context *ctx); 21 + }; 22 + 23 + struct raydium_rm67200 { 24 + struct drm_panel panel; 25 + const struct raydium_rm67200_panel_info *panel_info; 26 + struct mipi_dsi_device *dsi; 27 + struct gpio_desc *reset_gpio; 28 + struct regulator_bulk_data *supplies; 29 + int num_supplies; 30 + }; 31 + 32 + static inline struct raydium_rm67200 *to_raydium_rm67200(struct drm_panel *panel) 33 + { 34 + return container_of(panel, struct raydium_rm67200, panel); 35 + } 36 + 37 + static void raydium_rm67200_reset(struct raydium_rm67200 *ctx) 38 + { 39 + gpiod_set_value_cansleep(ctx->reset_gpio, 0); 40 + msleep(60); 41 + gpiod_set_value_cansleep(ctx->reset_gpio, 1); 42 + msleep(60); 43 + gpiod_set_value_cansleep(ctx->reset_gpio, 0); 44 + msleep(60); 45 + } 46 + 47 + static void raydium_rm67200_write(struct mipi_dsi_multi_context *ctx, 48 + u8 arg1, u8 arg2) 49 + { 50 + u8 d[] = { arg1, arg2 }; 51 + 52 + mipi_dsi_generic_write_multi(ctx, d, ARRAY_SIZE(d)); 53 + } 54 + 55 + static void w552793baa_setup(struct mipi_dsi_multi_context *ctx) 56 + { 57 + raydium_rm67200_write(ctx, 0xfe, 0x21); 58 + raydium_rm67200_write(ctx, 0x04, 0x00); 59 + raydium_rm67200_write(ctx, 0x00, 0x64); 60 + raydium_rm67200_write(ctx, 0x2a, 0x00); 61 + raydium_rm67200_write(ctx, 0x26, 0x64); 62 + raydium_rm67200_write(ctx, 0x54, 0x00); 63 + raydium_rm67200_write(ctx, 0x50, 0x64); 64 + raydium_rm67200_write(ctx, 0x7b, 0x00); 65 + raydium_rm67200_write(ctx, 0x77, 0x64); 66 + raydium_rm67200_write(ctx, 0xa2, 0x00); 67 + raydium_rm67200_write(ctx, 0x9d, 0x64); 68 + raydium_rm67200_write(ctx, 0xc9, 0x00); 69 + raydium_rm67200_write(ctx, 0xc5, 0x64); 70 + raydium_rm67200_write(ctx, 0x01, 0x71); 71 + raydium_rm67200_write(ctx, 0x27, 0x71); 72 + raydium_rm67200_write(ctx, 0x51, 0x71); 73 + raydium_rm67200_write(ctx, 0x78, 0x71); 74 + raydium_rm67200_write(ctx, 0x9e, 0x71); 75 + raydium_rm67200_write(ctx, 0xc6, 0x71); 76 + raydium_rm67200_write(ctx, 0x02, 0x89); 77 + raydium_rm67200_write(ctx, 0x28, 0x89); 78 + raydium_rm67200_write(ctx, 0x52, 0x89); 79 + raydium_rm67200_write(ctx, 0x79, 0x89); 80 + raydium_rm67200_write(ctx, 0x9f, 0x89); 81 + raydium_rm67200_write(ctx, 0xc7, 0x89); 82 + raydium_rm67200_write(ctx, 0x03, 0x9e); 83 + raydium_rm67200_write(ctx, 0x29, 0x9e); 84 + raydium_rm67200_write(ctx, 0x53, 0x9e); 85 + raydium_rm67200_write(ctx, 0x7a, 0x9e); 86 + raydium_rm67200_write(ctx, 0xa0, 0x9e); 87 + raydium_rm67200_write(ctx, 0xc8, 0x9e); 88 + raydium_rm67200_write(ctx, 0x09, 0x00); 89 + raydium_rm67200_write(ctx, 0x05, 0xb0); 90 + raydium_rm67200_write(ctx, 0x31, 0x00); 91 + raydium_rm67200_write(ctx, 0x2b, 0xb0); 92 + raydium_rm67200_write(ctx, 0x5a, 0x00); 93 + raydium_rm67200_write(ctx, 0x55, 0xb0); 94 + raydium_rm67200_write(ctx, 0x80, 0x00); 95 + raydium_rm67200_write(ctx, 0x7c, 0xb0); 96 + raydium_rm67200_write(ctx, 0xa7, 0x00); 97 + raydium_rm67200_write(ctx, 0xa3, 0xb0); 98 + raydium_rm67200_write(ctx, 0xce, 0x00); 99 + raydium_rm67200_write(ctx, 0xca, 0xb0); 100 + raydium_rm67200_write(ctx, 0x06, 0xc0); 101 + raydium_rm67200_write(ctx, 0x2d, 0xc0); 102 + raydium_rm67200_write(ctx, 0x56, 0xc0); 103 + raydium_rm67200_write(ctx, 0x7d, 0xc0); 104 + raydium_rm67200_write(ctx, 0xa4, 0xc0); 105 + raydium_rm67200_write(ctx, 0xcb, 0xc0); 106 + raydium_rm67200_write(ctx, 0x07, 0xcf); 107 + raydium_rm67200_write(ctx, 0x2f, 0xcf); 108 + raydium_rm67200_write(ctx, 0x58, 0xcf); 109 + raydium_rm67200_write(ctx, 0x7e, 0xcf); 110 + raydium_rm67200_write(ctx, 0xa5, 0xcf); 111 + raydium_rm67200_write(ctx, 0xcc, 0xcf); 112 + raydium_rm67200_write(ctx, 0x08, 0xdd); 113 + raydium_rm67200_write(ctx, 0x30, 0xdd); 114 + raydium_rm67200_write(ctx, 0x59, 0xdd); 115 + raydium_rm67200_write(ctx, 0x7f, 0xdd); 116 + raydium_rm67200_write(ctx, 0xa6, 0xdd); 117 + raydium_rm67200_write(ctx, 0xcd, 0xdd); 118 + raydium_rm67200_write(ctx, 0x0e, 0x15); 119 + raydium_rm67200_write(ctx, 0x0a, 0xe9); 120 + raydium_rm67200_write(ctx, 0x36, 0x15); 121 + raydium_rm67200_write(ctx, 0x32, 0xe9); 122 + raydium_rm67200_write(ctx, 0x5f, 0x15); 123 + raydium_rm67200_write(ctx, 0x5b, 0xe9); 124 + raydium_rm67200_write(ctx, 0x85, 0x15); 125 + raydium_rm67200_write(ctx, 0x81, 0xe9); 126 + raydium_rm67200_write(ctx, 0xad, 0x15); 127 + raydium_rm67200_write(ctx, 0xa9, 0xe9); 128 + raydium_rm67200_write(ctx, 0xd3, 0x15); 129 + raydium_rm67200_write(ctx, 0xcf, 0xe9); 130 + raydium_rm67200_write(ctx, 0x0b, 0x14); 131 + raydium_rm67200_write(ctx, 0x33, 0x14); 132 + raydium_rm67200_write(ctx, 0x5c, 0x14); 133 + raydium_rm67200_write(ctx, 0x82, 0x14); 134 + raydium_rm67200_write(ctx, 0xaa, 0x14); 135 + raydium_rm67200_write(ctx, 0xd0, 0x14); 136 + raydium_rm67200_write(ctx, 0x0c, 0x36); 137 + raydium_rm67200_write(ctx, 0x34, 0x36); 138 + raydium_rm67200_write(ctx, 0x5d, 0x36); 139 + raydium_rm67200_write(ctx, 0x83, 0x36); 140 + raydium_rm67200_write(ctx, 0xab, 0x36); 141 + raydium_rm67200_write(ctx, 0xd1, 0x36); 142 + raydium_rm67200_write(ctx, 0x0d, 0x6b); 143 + raydium_rm67200_write(ctx, 0x35, 0x6b); 144 + raydium_rm67200_write(ctx, 0x5e, 0x6b); 145 + raydium_rm67200_write(ctx, 0x84, 0x6b); 146 + raydium_rm67200_write(ctx, 0xac, 0x6b); 147 + raydium_rm67200_write(ctx, 0xd2, 0x6b); 148 + raydium_rm67200_write(ctx, 0x13, 0x5a); 149 + raydium_rm67200_write(ctx, 0x0f, 0x94); 150 + raydium_rm67200_write(ctx, 0x3b, 0x5a); 151 + raydium_rm67200_write(ctx, 0x37, 0x94); 152 + raydium_rm67200_write(ctx, 0x64, 0x5a); 153 + raydium_rm67200_write(ctx, 0x60, 0x94); 154 + raydium_rm67200_write(ctx, 0x8a, 0x5a); 155 + raydium_rm67200_write(ctx, 0x86, 0x94); 156 + raydium_rm67200_write(ctx, 0xb2, 0x5a); 157 + raydium_rm67200_write(ctx, 0xae, 0x94); 158 + raydium_rm67200_write(ctx, 0xd8, 0x5a); 159 + raydium_rm67200_write(ctx, 0xd4, 0x94); 160 + raydium_rm67200_write(ctx, 0x10, 0xd1); 161 + raydium_rm67200_write(ctx, 0x38, 0xd1); 162 + raydium_rm67200_write(ctx, 0x61, 0xd1); 163 + raydium_rm67200_write(ctx, 0x87, 0xd1); 164 + raydium_rm67200_write(ctx, 0xaf, 0xd1); 165 + raydium_rm67200_write(ctx, 0xd5, 0xd1); 166 + raydium_rm67200_write(ctx, 0x11, 0x04); 167 + raydium_rm67200_write(ctx, 0x39, 0x04); 168 + raydium_rm67200_write(ctx, 0x62, 0x04); 169 + raydium_rm67200_write(ctx, 0x88, 0x04); 170 + raydium_rm67200_write(ctx, 0xb0, 0x04); 171 + raydium_rm67200_write(ctx, 0xd6, 0x04); 172 + raydium_rm67200_write(ctx, 0x12, 0x05); 173 + raydium_rm67200_write(ctx, 0x3a, 0x05); 174 + raydium_rm67200_write(ctx, 0x63, 0x05); 175 + raydium_rm67200_write(ctx, 0x89, 0x05); 176 + raydium_rm67200_write(ctx, 0xb1, 0x05); 177 + raydium_rm67200_write(ctx, 0xd7, 0x05); 178 + raydium_rm67200_write(ctx, 0x18, 0xaa); 179 + raydium_rm67200_write(ctx, 0x14, 0x36); 180 + raydium_rm67200_write(ctx, 0x42, 0xaa); 181 + raydium_rm67200_write(ctx, 0x3d, 0x36); 182 + raydium_rm67200_write(ctx, 0x69, 0xaa); 183 + raydium_rm67200_write(ctx, 0x65, 0x36); 184 + raydium_rm67200_write(ctx, 0x8f, 0xaa); 185 + raydium_rm67200_write(ctx, 0x8b, 0x36); 186 + raydium_rm67200_write(ctx, 0xb7, 0xaa); 187 + raydium_rm67200_write(ctx, 0xb3, 0x36); 188 + raydium_rm67200_write(ctx, 0xdd, 0xaa); 189 + raydium_rm67200_write(ctx, 0xd9, 0x36); 190 + raydium_rm67200_write(ctx, 0x15, 0x74); 191 + raydium_rm67200_write(ctx, 0x3f, 0x74); 192 + raydium_rm67200_write(ctx, 0x66, 0x74); 193 + raydium_rm67200_write(ctx, 0x8c, 0x74); 194 + raydium_rm67200_write(ctx, 0xb4, 0x74); 195 + raydium_rm67200_write(ctx, 0xda, 0x74); 196 + raydium_rm67200_write(ctx, 0x16, 0x9f); 197 + raydium_rm67200_write(ctx, 0x40, 0x9f); 198 + raydium_rm67200_write(ctx, 0x67, 0x9f); 199 + raydium_rm67200_write(ctx, 0x8d, 0x9f); 200 + raydium_rm67200_write(ctx, 0xb5, 0x9f); 201 + raydium_rm67200_write(ctx, 0xdb, 0x9f); 202 + raydium_rm67200_write(ctx, 0x17, 0xdc); 203 + raydium_rm67200_write(ctx, 0x41, 0xdc); 204 + raydium_rm67200_write(ctx, 0x68, 0xdc); 205 + raydium_rm67200_write(ctx, 0x8e, 0xdc); 206 + raydium_rm67200_write(ctx, 0xb6, 0xdc); 207 + raydium_rm67200_write(ctx, 0xdc, 0xdc); 208 + raydium_rm67200_write(ctx, 0x1d, 0xff); 209 + raydium_rm67200_write(ctx, 0x19, 0x03); 210 + raydium_rm67200_write(ctx, 0x47, 0xff); 211 + raydium_rm67200_write(ctx, 0x43, 0x03); 212 + raydium_rm67200_write(ctx, 0x6e, 0xff); 213 + raydium_rm67200_write(ctx, 0x6a, 0x03); 214 + raydium_rm67200_write(ctx, 0x94, 0xff); 215 + raydium_rm67200_write(ctx, 0x90, 0x03); 216 + raydium_rm67200_write(ctx, 0xbc, 0xff); 217 + raydium_rm67200_write(ctx, 0xb8, 0x03); 218 + raydium_rm67200_write(ctx, 0xe2, 0xff); 219 + raydium_rm67200_write(ctx, 0xde, 0x03); 220 + raydium_rm67200_write(ctx, 0x1a, 0x35); 221 + raydium_rm67200_write(ctx, 0x44, 0x35); 222 + raydium_rm67200_write(ctx, 0x6b, 0x35); 223 + raydium_rm67200_write(ctx, 0x91, 0x35); 224 + raydium_rm67200_write(ctx, 0xb9, 0x35); 225 + raydium_rm67200_write(ctx, 0xdf, 0x35); 226 + raydium_rm67200_write(ctx, 0x1b, 0x45); 227 + raydium_rm67200_write(ctx, 0x45, 0x45); 228 + raydium_rm67200_write(ctx, 0x6c, 0x45); 229 + raydium_rm67200_write(ctx, 0x92, 0x45); 230 + raydium_rm67200_write(ctx, 0xba, 0x45); 231 + raydium_rm67200_write(ctx, 0xe0, 0x45); 232 + raydium_rm67200_write(ctx, 0x1c, 0x55); 233 + raydium_rm67200_write(ctx, 0x46, 0x55); 234 + raydium_rm67200_write(ctx, 0x6d, 0x55); 235 + raydium_rm67200_write(ctx, 0x93, 0x55); 236 + raydium_rm67200_write(ctx, 0xbb, 0x55); 237 + raydium_rm67200_write(ctx, 0xe1, 0x55); 238 + raydium_rm67200_write(ctx, 0x22, 0xff); 239 + raydium_rm67200_write(ctx, 0x1e, 0x68); 240 + raydium_rm67200_write(ctx, 0x4c, 0xff); 241 + raydium_rm67200_write(ctx, 0x48, 0x68); 242 + raydium_rm67200_write(ctx, 0x73, 0xff); 243 + raydium_rm67200_write(ctx, 0x6f, 0x68); 244 + raydium_rm67200_write(ctx, 0x99, 0xff); 245 + raydium_rm67200_write(ctx, 0x95, 0x68); 246 + raydium_rm67200_write(ctx, 0xc1, 0xff); 247 + raydium_rm67200_write(ctx, 0xbd, 0x68); 248 + raydium_rm67200_write(ctx, 0xe7, 0xff); 249 + raydium_rm67200_write(ctx, 0xe3, 0x68); 250 + raydium_rm67200_write(ctx, 0x1f, 0x7e); 251 + raydium_rm67200_write(ctx, 0x49, 0x7e); 252 + raydium_rm67200_write(ctx, 0x70, 0x7e); 253 + raydium_rm67200_write(ctx, 0x96, 0x7e); 254 + raydium_rm67200_write(ctx, 0xbe, 0x7e); 255 + raydium_rm67200_write(ctx, 0xe4, 0x7e); 256 + raydium_rm67200_write(ctx, 0x20, 0x97); 257 + raydium_rm67200_write(ctx, 0x4a, 0x97); 258 + raydium_rm67200_write(ctx, 0x71, 0x97); 259 + raydium_rm67200_write(ctx, 0x97, 0x97); 260 + raydium_rm67200_write(ctx, 0xbf, 0x97); 261 + raydium_rm67200_write(ctx, 0xe5, 0x97); 262 + raydium_rm67200_write(ctx, 0x21, 0xb5); 263 + raydium_rm67200_write(ctx, 0x4b, 0xb5); 264 + raydium_rm67200_write(ctx, 0x72, 0xb5); 265 + raydium_rm67200_write(ctx, 0x98, 0xb5); 266 + raydium_rm67200_write(ctx, 0xc0, 0xb5); 267 + raydium_rm67200_write(ctx, 0xe6, 0xb5); 268 + raydium_rm67200_write(ctx, 0x25, 0xf0); 269 + raydium_rm67200_write(ctx, 0x23, 0xe8); 270 + raydium_rm67200_write(ctx, 0x4f, 0xf0); 271 + raydium_rm67200_write(ctx, 0x4d, 0xe8); 272 + raydium_rm67200_write(ctx, 0x76, 0xf0); 273 + raydium_rm67200_write(ctx, 0x74, 0xe8); 274 + raydium_rm67200_write(ctx, 0x9c, 0xf0); 275 + raydium_rm67200_write(ctx, 0x9a, 0xe8); 276 + raydium_rm67200_write(ctx, 0xc4, 0xf0); 277 + raydium_rm67200_write(ctx, 0xc2, 0xe8); 278 + raydium_rm67200_write(ctx, 0xea, 0xf0); 279 + raydium_rm67200_write(ctx, 0xe8, 0xe8); 280 + raydium_rm67200_write(ctx, 0x24, 0xff); 281 + raydium_rm67200_write(ctx, 0x4e, 0xff); 282 + raydium_rm67200_write(ctx, 0x75, 0xff); 283 + raydium_rm67200_write(ctx, 0x9b, 0xff); 284 + raydium_rm67200_write(ctx, 0xc3, 0xff); 285 + raydium_rm67200_write(ctx, 0xe9, 0xff); 286 + raydium_rm67200_write(ctx, 0xfe, 0x3d); 287 + raydium_rm67200_write(ctx, 0x00, 0x04); 288 + raydium_rm67200_write(ctx, 0xfe, 0x23); 289 + raydium_rm67200_write(ctx, 0x08, 0x82); 290 + raydium_rm67200_write(ctx, 0x0a, 0x00); 291 + raydium_rm67200_write(ctx, 0x0b, 0x00); 292 + raydium_rm67200_write(ctx, 0x0c, 0x01); 293 + raydium_rm67200_write(ctx, 0x16, 0x00); 294 + raydium_rm67200_write(ctx, 0x18, 0x02); 295 + raydium_rm67200_write(ctx, 0x1b, 0x04); 296 + raydium_rm67200_write(ctx, 0x19, 0x04); 297 + raydium_rm67200_write(ctx, 0x1c, 0x81); 298 + raydium_rm67200_write(ctx, 0x1f, 0x00); 299 + raydium_rm67200_write(ctx, 0x20, 0x03); 300 + raydium_rm67200_write(ctx, 0x23, 0x04); 301 + raydium_rm67200_write(ctx, 0x21, 0x01); 302 + raydium_rm67200_write(ctx, 0x54, 0x63); 303 + raydium_rm67200_write(ctx, 0x55, 0x54); 304 + raydium_rm67200_write(ctx, 0x6e, 0x45); 305 + raydium_rm67200_write(ctx, 0x6d, 0x36); 306 + raydium_rm67200_write(ctx, 0xfe, 0x3d); 307 + raydium_rm67200_write(ctx, 0x55, 0x78); 308 + raydium_rm67200_write(ctx, 0xfe, 0x20); 309 + raydium_rm67200_write(ctx, 0x26, 0x30); 310 + raydium_rm67200_write(ctx, 0xfe, 0x3d); 311 + raydium_rm67200_write(ctx, 0x20, 0x71); 312 + raydium_rm67200_write(ctx, 0x50, 0x8f); 313 + raydium_rm67200_write(ctx, 0x51, 0x8f); 314 + raydium_rm67200_write(ctx, 0xfe, 0x00); 315 + raydium_rm67200_write(ctx, 0x35, 0x00); 316 + } 317 + 318 + static int raydium_rm67200_prepare(struct drm_panel *panel) 319 + { 320 + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); 321 + int ret; 322 + 323 + ret = regulator_bulk_enable(ctx->num_supplies, ctx->supplies); 324 + if (ret < 0) 325 + return ret; 326 + 327 + raydium_rm67200_reset(ctx); 328 + 329 + msleep(60); 330 + 331 + return 0; 332 + } 333 + 334 + static int raydium_rm67200_unprepare(struct drm_panel *panel) 335 + { 336 + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); 337 + 338 + gpiod_set_value_cansleep(ctx->reset_gpio, 1); 339 + regulator_bulk_disable(ctx->num_supplies, ctx->supplies); 340 + 341 + msleep(60); 342 + 343 + return 0; 344 + } 345 + 346 + static int raydium_rm67200_enable(struct drm_panel *panel) 347 + { 348 + struct raydium_rm67200 *rm67200 = to_raydium_rm67200(panel); 349 + struct mipi_dsi_multi_context ctx = { .dsi = rm67200->dsi }; 350 + 351 + rm67200->panel_info->panel_setup(&ctx); 352 + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); 353 + mipi_dsi_msleep(&ctx, 120); 354 + mipi_dsi_dcs_set_display_on_multi(&ctx); 355 + mipi_dsi_msleep(&ctx, 30); 356 + 357 + return ctx.accum_err; 358 + } 359 + 360 + static int raydium_rm67200_disable(struct drm_panel *panel) 361 + { 362 + struct raydium_rm67200 *rm67200 = to_raydium_rm67200(panel); 363 + struct mipi_dsi_multi_context ctx = { .dsi = rm67200->dsi }; 364 + 365 + mipi_dsi_dcs_set_display_off_multi(&ctx); 366 + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); 367 + mipi_dsi_msleep(&ctx, 60); 368 + 369 + return ctx.accum_err; 370 + } 371 + 372 + static int raydium_rm67200_get_modes(struct drm_panel *panel, 373 + struct drm_connector *connector) 374 + { 375 + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); 376 + 377 + return drm_connector_helper_get_modes_fixed(connector, &ctx->panel_info->mode); 378 + } 379 + 380 + static const struct drm_panel_funcs raydium_rm67200_funcs = { 381 + .prepare = raydium_rm67200_prepare, 382 + .unprepare = raydium_rm67200_unprepare, 383 + .get_modes = raydium_rm67200_get_modes, 384 + .enable = raydium_rm67200_enable, 385 + .disable = raydium_rm67200_disable, 386 + }; 387 + 388 + static int raydium_rm67200_probe(struct mipi_dsi_device *dsi) 389 + { 390 + struct device *dev = &dsi->dev; 391 + struct raydium_rm67200 *ctx; 392 + int ret = 0; 393 + 394 + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 395 + if (!ctx) 396 + return -ENOMEM; 397 + 398 + ctx->panel_info = device_get_match_data(dev); 399 + if (!ctx->panel_info) 400 + return -EINVAL; 401 + 402 + ctx->num_supplies = ctx->panel_info->num_regulators; 403 + ret = devm_regulator_bulk_get_const(&dsi->dev, 404 + ctx->panel_info->num_regulators, 405 + ctx->panel_info->regulators, 406 + &ctx->supplies); 407 + if (ret < 0) 408 + return ret; 409 + 410 + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 411 + if (IS_ERR(ctx->reset_gpio)) 412 + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), 413 + "Failed to get reset-gpios\n"); 414 + 415 + ctx->dsi = dsi; 416 + mipi_dsi_set_drvdata(dsi, ctx); 417 + 418 + dsi->lanes = 4; 419 + dsi->format = MIPI_DSI_FMT_RGB888; 420 + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 421 + MIPI_DSI_MODE_LPM; 422 + ctx->panel.prepare_prev_first = true; 423 + 424 + drm_panel_init(&ctx->panel, dev, &raydium_rm67200_funcs, 425 + DRM_MODE_CONNECTOR_DSI); 426 + 427 + ret = drm_panel_of_backlight(&ctx->panel); 428 + if (ret) 429 + return ret; 430 + 431 + drm_panel_add(&ctx->panel); 432 + 433 + ret = mipi_dsi_attach(dsi); 434 + if (ret < 0) { 435 + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); 436 + drm_panel_remove(&ctx->panel); 437 + } 438 + 439 + return ret; 440 + } 441 + 442 + static void raydium_rm67200_remove(struct mipi_dsi_device *dsi) 443 + { 444 + struct raydium_rm67200 *ctx = mipi_dsi_get_drvdata(dsi); 445 + int ret; 446 + 447 + ret = mipi_dsi_detach(dsi); 448 + if (ret < 0) 449 + dev_err(&dsi->dev, "Failed to detach DSI host: %d\n", ret); 450 + 451 + drm_panel_remove(&ctx->panel); 452 + } 453 + 454 + static const struct regulator_bulk_data w552793baa_regulators[] = { 455 + { .supply = "vdd", }, /* 2.8V */ 456 + { .supply = "iovcc", }, /* 1.8V */ 457 + { .supply = "vsp", }, /* +5.5V */ 458 + { .supply = "vsn", }, /* -5.5V */ 459 + }; 460 + 461 + static const struct raydium_rm67200_panel_info w552793baa_info = { 462 + .mode = { 463 + .clock = 132000, 464 + .hdisplay = 1080, 465 + .hsync_start = 1095, 466 + .hsync_end = 1125, 467 + .htotal = 1129, 468 + .vdisplay = 1920, 469 + .vsync_start = 1935, 470 + .vsync_end = 1950, 471 + .vtotal = 1952, 472 + .width_mm = 68, /* 68.04mm */ 473 + .height_mm = 121, /* 120.96mm */ 474 + .type = DRM_MODE_TYPE_DRIVER, 475 + }, 476 + .regulators = w552793baa_regulators, 477 + .num_regulators = ARRAY_SIZE(w552793baa_regulators), 478 + .panel_setup = w552793baa_setup, 479 + }; 480 + 481 + static const struct of_device_id raydium_rm67200_of_match[] = { 482 + { .compatible = "wanchanglong,w552793baa", .data = &w552793baa_info }, 483 + { /*sentinel*/ } 484 + }; 485 + MODULE_DEVICE_TABLE(of, raydium_rm67200_of_match); 486 + 487 + static struct mipi_dsi_driver raydium_rm67200_driver = { 488 + .probe = raydium_rm67200_probe, 489 + .remove = raydium_rm67200_remove, 490 + .driver = { 491 + .name = "panel-raydium-rm67200", 492 + .of_match_table = raydium_rm67200_of_match, 493 + }, 494 + }; 495 + module_mipi_dsi_driver(raydium_rm67200_driver); 496 + 497 + MODULE_AUTHOR("Sebastian Reichel <sebastian.reichel@collabora.com>"); 498 + MODULE_DESCRIPTION("DRM driver for RM67200-equipped DSI panels"); 499 + MODULE_LICENSE("GPL");

+64

drivers/gpu/drm/panel/panel-simple.c

··· 1374 1374 }, 1375 1375 }; 1376 1376 1377 + static const struct display_timing boe_av101hdt_a10_timing = { 1378 + .pixelclock = { 74210000, 75330000, 76780000, }, 1379 + .hactive = { 1280, 1280, 1280, }, 1380 + .hfront_porch = { 10, 42, 33, }, 1381 + .hback_porch = { 10, 18, 33, }, 1382 + .hsync_len = { 30, 10, 30, }, 1383 + .vactive = { 720, 720, 720, }, 1384 + .vfront_porch = { 200, 183, 200, }, 1385 + .vback_porch = { 8, 8, 8, }, 1386 + .vsync_len = { 2, 19, 2, }, 1387 + .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1388 + }; 1389 + 1390 + static const struct panel_desc boe_av101hdt_a10 = { 1391 + .timings = &boe_av101hdt_a10_timing, 1392 + .num_timings = 1, 1393 + .bpc = 8, 1394 + .size = { 1395 + .width = 224, 1396 + .height = 126, 1397 + }, 1398 + .delay = { 1399 + .enable = 50, 1400 + .disable = 50, 1401 + }, 1402 + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1403 + .connector_type = DRM_MODE_CONNECTOR_LVDS, 1404 + }; 1405 + 1406 + static const struct display_timing boe_av123z7m_n17_timing = { 1407 + .pixelclock = { 86600000, 88000000, 90800000, }, 1408 + .hactive = { 1920, 1920, 1920, }, 1409 + .hfront_porch = { 10, 10, 10, }, 1410 + .hback_porch = { 10, 10, 10, }, 1411 + .hsync_len = { 9, 12, 25, }, 1412 + .vactive = { 720, 720, 720, }, 1413 + .vfront_porch = { 7, 10, 13, }, 1414 + .vback_porch = { 7, 10, 13, }, 1415 + .vsync_len = { 7, 11, 14, }, 1416 + .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1417 + }; 1418 + 1419 + static const struct panel_desc boe_av123z7m_n17 = { 1420 + .timings = &boe_av123z7m_n17_timing, 1421 + .bpc = 8, 1422 + .num_timings = 1, 1423 + .size = { 1424 + .width = 292, 1425 + .height = 110, 1426 + }, 1427 + .delay = { 1428 + .prepare = 50, 1429 + .disable = 50, 1430 + }, 1431 + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1432 + .connector_type = DRM_MODE_CONNECTOR_LVDS, 1433 + }; 1434 + 1377 1435 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1378 1436 .clock = 78945, 1379 1437 .hdisplay = 1280, ··· 4871 4813 }, { 4872 4814 .compatible = "bananapi,s070wv20-ct16", 4873 4815 .data = &bananapi_s070wv20_ct16, 4816 + }, { 4817 + .compatible = "boe,av101hdt-a10", 4818 + .data = &boe_av101hdt_a10, 4819 + }, { 4820 + .compatible = "boe,av123z7m-n17", 4821 + .data = &boe_av123z7m_n17, 4874 4822 }, { 4875 4823 .compatible = "boe,bp082wx1-100", 4876 4824 .data = &boe_bp082wx1_100,

+23 -84

drivers/gpu/drm/panel/panel-sony-td4353-jdi.c

··· 47 47 static int sony_td4353_jdi_on(struct sony_td4353_jdi *ctx) 48 48 { 49 49 struct mipi_dsi_device *dsi = ctx->dsi; 50 - struct device *dev = &dsi->dev; 51 - int ret; 50 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 52 51 53 52 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 54 53 55 - ret = mipi_dsi_dcs_set_column_address(dsi, 0x0000, 1080 - 1); 56 - if (ret < 0) { 57 - dev_err(dev, "Failed to set column address: %d\n", ret); 58 - return ret; 59 - } 54 + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 1080 - 1); 55 + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 2160 - 1); 56 + mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0); 57 + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 58 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 60 59 61 - ret = mipi_dsi_dcs_set_page_address(dsi, 0x0000, 2160 - 1); 62 - if (ret < 0) { 63 - dev_err(dev, "Failed to set page address: %d\n", ret); 64 - return ret; 65 - } 60 + mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); 61 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_PARTIAL_ROWS, 62 + 0x00, 0x00, 0x08, 0x6f); 66 63 67 - ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0); 68 - if (ret < 0) { 69 - dev_err(dev, "Failed to set tear scanline: %d\n", ret); 70 - return ret; 71 - } 64 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 65 + mipi_dsi_msleep(&dsi_ctx, 70); 66 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START); 67 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 72 68 73 - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 74 - if (ret < 0) { 75 - dev_err(dev, "Failed to set tear on: %d\n", ret); 76 - return ret; 77 - } 78 - 79 - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 80 - 81 - ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77); 82 - if (ret < 0) { 83 - dev_err(dev, "Failed to set pixel format: %d\n", ret); 84 - return ret; 85 - } 86 - 87 - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 88 - 0x00, 0x00, 0x08, 0x6f); 89 - 90 - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 91 - if (ret < 0) { 92 - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); 93 - return ret; 94 - } 95 - msleep(70); 96 - 97 - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); 98 - 99 - ret = mipi_dsi_dcs_set_display_on(dsi); 100 - if (ret < 0) { 101 - dev_err(dev, "Failed to turn display on: %d\n", ret); 102 - return ret; 103 - } 104 - 105 - return 0; 69 + return dsi_ctx.accum_err; 106 70 } 107 71 108 - static int sony_td4353_jdi_off(struct sony_td4353_jdi *ctx) 72 + static void sony_td4353_jdi_off(struct sony_td4353_jdi *ctx) 109 73 { 110 74 struct mipi_dsi_device *dsi = ctx->dsi; 111 - struct device *dev = &dsi->dev; 112 - int ret; 75 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 113 76 114 77 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 115 78 116 - ret = mipi_dsi_dcs_set_display_off(dsi); 117 - if (ret < 0) { 118 - dev_err(dev, "Failed to set display off: %d\n", ret); 119 - return ret; 120 - } 121 - msleep(22); 122 - 123 - ret = mipi_dsi_dcs_set_tear_off(dsi); 124 - if (ret < 0) { 125 - dev_err(dev, "Failed to set tear off: %d\n", ret); 126 - return ret; 127 - } 128 - 129 - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 130 - if (ret < 0) { 131 - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); 132 - return ret; 133 - } 134 - msleep(80); 135 - 136 - return 0; 79 + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 80 + mipi_dsi_msleep(&dsi_ctx, 22); 81 + mipi_dsi_dcs_set_tear_off_multi(&dsi_ctx); 82 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 83 + mipi_dsi_msleep(&dsi_ctx, 80); 137 84 } 138 85 139 86 static void sony_td4353_assert_reset_gpios(struct sony_td4353_jdi *ctx, int mode) ··· 93 146 static int sony_td4353_jdi_prepare(struct drm_panel *panel) 94 147 { 95 148 struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel); 96 - struct device *dev = &ctx->dsi->dev; 97 149 int ret; 98 150 99 151 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 100 - if (ret < 0) { 101 - dev_err(dev, "Failed to enable regulators: %d\n", ret); 152 + if (ret < 0) 102 153 return ret; 103 - } 104 154 105 155 msleep(100); 106 156 ··· 105 161 106 162 ret = sony_td4353_jdi_on(ctx); 107 163 if (ret < 0) { 108 - dev_err(dev, "Failed to power on panel: %d\n", ret); 109 164 sony_td4353_assert_reset_gpios(ctx, 0); 110 165 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 111 166 return ret; ··· 116 173 static int sony_td4353_jdi_unprepare(struct drm_panel *panel) 117 174 { 118 175 struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel); 119 - struct device *dev = &ctx->dsi->dev; 120 - int ret; 121 176 122 - ret = sony_td4353_jdi_off(ctx); 123 - if (ret < 0) 124 - dev_err(dev, "Failed to power off panel: %d\n", ret); 177 + sony_td4353_jdi_off(ctx); 125 178 126 179 sony_td4353_assert_reset_gpios(ctx, 0); 127 180 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);

+132

drivers/gpu/drm/panel/panel-summit.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + 3 + #include <linux/backlight.h> 4 + #include <drm/drm_device.h> 5 + #include <drm/drm_mipi_dsi.h> 6 + #include <drm/drm_mode.h> 7 + #include <drm/drm_modes.h> 8 + #include <drm/drm_panel.h> 9 + #include <drm/drm_probe_helper.h> 10 + #include <video/mipi_display.h> 11 + 12 + struct summit_data { 13 + struct mipi_dsi_device *dsi; 14 + struct backlight_device *bl; 15 + struct drm_panel panel; 16 + }; 17 + 18 + static int summit_set_brightness(struct device *dev) 19 + { 20 + struct summit_data *s_data = dev_get_drvdata(dev); 21 + int level = backlight_get_brightness(s_data->bl); 22 + 23 + return mipi_dsi_dcs_set_display_brightness(s_data->dsi, level); 24 + } 25 + 26 + static int summit_bl_update_status(struct backlight_device *dev) 27 + { 28 + return summit_set_brightness(&dev->dev); 29 + } 30 + 31 + static const struct backlight_ops summit_bl_ops = { 32 + .update_status = summit_bl_update_status, 33 + }; 34 + 35 + static struct drm_display_mode summit_mode = { 36 + .vdisplay = 2008, 37 + .hdisplay = 60, 38 + .hsync_start = 60 + 8, 39 + .hsync_end = 60 + 8 + 80, 40 + .htotal = 60 + 8 + 80 + 40, 41 + .vsync_start = 2008 + 1, 42 + .vsync_end = 2008 + 1 + 15, 43 + .vtotal = 2008 + 1 + 15 + 6, 44 + .clock = ((60 + 8 + 80 + 40) * (2008 + 1 + 15 + 6) * 60) / 1000, 45 + .type = DRM_MODE_TYPE_DRIVER, 46 + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 47 + }; 48 + 49 + static int summit_get_modes(struct drm_panel *panel, 50 + struct drm_connector *connector) 51 + { 52 + connector->display_info.non_desktop = true; 53 + drm_object_property_set_value(&connector->base, 54 + connector->dev->mode_config.non_desktop_property, 55 + connector->display_info.non_desktop); 56 + 57 + return drm_connector_helper_get_modes_fixed(connector, &summit_mode); 58 + } 59 + 60 + static const struct drm_panel_funcs summit_panel_funcs = { 61 + .get_modes = summit_get_modes, 62 + }; 63 + 64 + static int summit_probe(struct mipi_dsi_device *dsi) 65 + { 66 + struct backlight_properties props = { 0 }; 67 + struct device *dev = &dsi->dev; 68 + struct summit_data *s_data; 69 + int ret; 70 + 71 + s_data = devm_kzalloc(dev, sizeof(*s_data), GFP_KERNEL); 72 + if (!s_data) 73 + return -ENOMEM; 74 + 75 + mipi_dsi_set_drvdata(dsi, s_data); 76 + s_data->dsi = dsi; 77 + 78 + ret = device_property_read_u32(dev, "max-brightness", &props.max_brightness); 79 + if (ret) 80 + return ret; 81 + props.type = BACKLIGHT_RAW; 82 + 83 + s_data->bl = devm_backlight_device_register(dev, dev_name(dev), 84 + dev, s_data, &summit_bl_ops, &props); 85 + if (IS_ERR(s_data->bl)) 86 + return PTR_ERR(s_data->bl); 87 + 88 + drm_panel_init(&s_data->panel, dev, &summit_panel_funcs, 89 + DRM_MODE_CONNECTOR_DSI); 90 + drm_panel_add(&s_data->panel); 91 + 92 + return mipi_dsi_attach(dsi); 93 + } 94 + 95 + static void summit_remove(struct mipi_dsi_device *dsi) 96 + { 97 + struct summit_data *s_data = mipi_dsi_get_drvdata(dsi); 98 + 99 + mipi_dsi_detach(dsi); 100 + drm_panel_remove(&s_data->panel); 101 + } 102 + 103 + static int summit_suspend(struct device *dev) 104 + { 105 + struct summit_data *s_data = dev_get_drvdata(dev); 106 + 107 + return mipi_dsi_dcs_set_display_brightness(s_data->dsi, 0); 108 + } 109 + 110 + static DEFINE_SIMPLE_DEV_PM_OPS(summit_pm_ops, summit_suspend, 111 + summit_set_brightness); 112 + 113 + static const struct of_device_id summit_of_match[] = { 114 + { .compatible = "apple,summit" }, 115 + {}, 116 + }; 117 + 118 + MODULE_DEVICE_TABLE(of, summit_of_match); 119 + 120 + static struct mipi_dsi_driver summit_driver = { 121 + .probe = summit_probe, 122 + .remove = summit_remove, 123 + .driver = { 124 + .name = "panel-summit", 125 + .of_match_table = summit_of_match, 126 + .pm = pm_sleep_ptr(&summit_pm_ops), 127 + }, 128 + }; 129 + module_mipi_dsi_driver(summit_driver); 130 + 131 + MODULE_DESCRIPTION("Summit Display Panel Driver"); 132 + MODULE_LICENSE("GPL");

+442

drivers/gpu/drm/panel/panel-visionox-rm692e5.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: 4 + * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 + * Copyright (c) 2025, Eugene Lepshy <fekz115@gmail.com> 6 + * Copyright (c) 2025, Danila Tikhonov <danila@jiaxyga.com> 7 + */ 8 + 9 + #include <linux/backlight.h> 10 + #include <linux/delay.h> 11 + #include <linux/gpio/consumer.h> 12 + #include <linux/mod_devicetable.h> 13 + #include <linux/module.h> 14 + #include <linux/regulator/consumer.h> 15 + 16 + #include <video/mipi_display.h> 17 + 18 + #include <drm/display/drm_dsc.h> 19 + #include <drm/display/drm_dsc_helper.h> 20 + #include <drm/drm_mipi_dsi.h> 21 + #include <drm/drm_modes.h> 22 + #include <drm/drm_panel.h> 23 + #include <drm/drm_probe_helper.h> 24 + 25 + struct visionox_rm692e5 { 26 + struct drm_panel panel; 27 + struct mipi_dsi_device *dsi; 28 + struct drm_dsc_config dsc; 29 + struct gpio_desc *reset_gpio; 30 + struct regulator_bulk_data *supplies; 31 + }; 32 + 33 + static const struct regulator_bulk_data visionox_rm692e5_supplies[] = { 34 + { .supply = "vddio" }, /* 1p8 */ 35 + { .supply = "vdd" }, /* 3p3 */ 36 + }; 37 + 38 + static inline 39 + struct visionox_rm692e5 *to_visionox_rm692e5(struct drm_panel *panel) 40 + { 41 + return container_of(panel, struct visionox_rm692e5, panel); 42 + } 43 + 44 + static void visionox_rm692e5_reset(struct visionox_rm692e5 *ctx) 45 + { 46 + gpiod_set_value_cansleep(ctx->reset_gpio, 0); 47 + usleep_range(10000, 11000); 48 + gpiod_set_value_cansleep(ctx->reset_gpio, 1); 49 + usleep_range(1000, 2000); 50 + gpiod_set_value_cansleep(ctx->reset_gpio, 0); 51 + msleep(32); 52 + } 53 + 54 + static int visionox_rm692e5_on(struct visionox_rm692e5 *ctx) 55 + { 56 + struct mipi_dsi_device *dsi = ctx->dsi; 57 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 58 + 59 + dsi->mode_flags |= MIPI_DSI_MODE_LPM; 60 + 61 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); 62 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07); 63 + mipi_dsi_usleep_range(&dsi_ctx, 17000, 18000); 64 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2); 65 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11); 66 + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ab); 67 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30); 68 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x09); 69 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60); 70 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x04); 71 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x38); 72 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x00); 73 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x14); 74 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x02); 75 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1c); 76 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x02); 77 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x00); 78 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20); 79 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x01); 80 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0xe8); 81 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x00); 82 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x07); 83 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x0c); 84 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x05); 85 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x0e); 86 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x05); 87 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x16); 88 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x18); 89 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x00); 90 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x10); 91 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0xf0); 92 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x07); 93 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x10); 94 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20); 95 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00); 96 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x06); 97 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x0f); 98 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x0f); 99 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x33); 100 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x0e); 101 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x1c); 102 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a); 103 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x38); 104 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x46); 105 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x54); 106 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x62); 107 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x69); 108 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x70); 109 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x77); 110 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x79); 111 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x7b); 112 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x7d); 113 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x7e); 114 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x01); 115 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x83, 0x02); 116 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x22); 117 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x00); 118 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x2a); 119 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x40); 120 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x2a); 121 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0xbe); 122 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8a, 0x3a); 123 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8b, 0xfc); 124 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8c, 0x3a); 125 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8d, 0xfa); 126 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0x3a); 127 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8f, 0xf8); 128 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x3b); 129 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x38); 130 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x3b); 131 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x93, 0x78); 132 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x3b); 133 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x95, 0xb6); 134 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x96, 0x4b); 135 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0xf6); 136 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x98, 0x4c); 137 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x34); 138 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9a, 0x4c); 139 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9b, 0x74); 140 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9c, 0x5c); 141 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9d, 0x74); 142 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9e, 0x8c); 143 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9f, 0xf4); 144 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_START, 0x02); 145 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa3, 0x1c); 146 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa4, 0x00); 147 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa5, 0x00); 148 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa6, 0x00); 149 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa7, 0x00); 150 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_CONTINUE, 0x00); 151 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xaa, 0x00); 152 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa0, 0x80); 153 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xa1); 154 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x6b); 155 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0xbb); 156 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd1); 157 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x01); 158 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x38); 159 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x0f); 160 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x0f); 161 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x00); 162 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfa, 0x01); 163 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x08); 164 + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 165 + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x000d); 166 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 167 + mipi_dsi_msleep(&dsi_ctx, 50); 168 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 169 + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); 170 + 171 + return dsi_ctx.accum_err; 172 + } 173 + 174 + static int visionox_rm692e5_disable(struct drm_panel *panel) 175 + { 176 + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); 177 + struct mipi_dsi_device *dsi = ctx->dsi; 178 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 179 + 180 + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 181 + 182 + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 183 + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); 184 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 185 + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); 186 + 187 + return dsi_ctx.accum_err; 188 + } 189 + 190 + static int visionox_rm692e5_prepare(struct drm_panel *panel) 191 + { 192 + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); 193 + struct drm_dsc_picture_parameter_set pps; 194 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 195 + int ret; 196 + 197 + ret = regulator_bulk_enable(ARRAY_SIZE(visionox_rm692e5_supplies), 198 + ctx->supplies); 199 + if (ret < 0) 200 + return ret; 201 + 202 + visionox_rm692e5_reset(ctx); 203 + 204 + ret = visionox_rm692e5_on(ctx); 205 + if (ret < 0) { 206 + gpiod_set_value_cansleep(ctx->reset_gpio, 1); 207 + goto err; 208 + } 209 + 210 + drm_dsc_pps_payload_pack(&pps, &ctx->dsc); 211 + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); 212 + mipi_dsi_compression_mode_ext_multi(&dsi_ctx, true, MIPI_DSI_COMPRESSION_DSC, 0); 213 + 214 + mipi_dsi_msleep(&dsi_ctx, 28); 215 + 216 + if (dsi_ctx.accum_err < 0) { 217 + ret = dsi_ctx.accum_err; 218 + goto err; 219 + } 220 + 221 + return dsi_ctx.accum_err; 222 + err: 223 + regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies), 224 + ctx->supplies); 225 + return ret; 226 + } 227 + 228 + static int visionox_rm692e5_unprepare(struct drm_panel *panel) 229 + { 230 + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); 231 + 232 + gpiod_set_value_cansleep(ctx->reset_gpio, 1); 233 + regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies), 234 + ctx->supplies); 235 + 236 + return 0; 237 + } 238 + 239 + static const struct drm_display_mode visionox_rm692e5_modes[] = { 240 + /* Let's initialize the highest frequency first */ 241 + { /* 120Hz mode */ 242 + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 120 / 1000, 243 + .hdisplay = 1080, 244 + .hsync_start = 1080 + 26, 245 + .hsync_end = 1080 + 26 + 39, 246 + .htotal = 1080 + 26 + 39 + 36, 247 + .vdisplay = 2400, 248 + .vsync_start = 2400 + 16, 249 + .vsync_end = 2400 + 16 + 21, 250 + .vtotal = 2400 + 16 + 21 + 16, 251 + .width_mm = 68, 252 + .height_mm = 152, 253 + .type = DRM_MODE_TYPE_DRIVER, 254 + }, 255 + { /* 90Hz mode */ 256 + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 90 / 1000, 257 + .hdisplay = 1080, 258 + .hsync_start = 1080 + 26, 259 + .hsync_end = 1080 + 26 + 39, 260 + .htotal = 1080 + 26 + 39 + 36, 261 + .vdisplay = 2400, 262 + .vsync_start = 2400 + 16, 263 + .vsync_end = 2400 + 16 + 21, 264 + .vtotal = 2400 + 16 + 21 + 16, 265 + .width_mm = 68, 266 + .height_mm = 152, 267 + .type = DRM_MODE_TYPE_DRIVER, 268 + }, 269 + { /* 60Hz mode */ 270 + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 60 / 1000, 271 + .hdisplay = 1080, 272 + .hsync_start = 1080 + 26, 273 + .hsync_end = 1080 + 26 + 39, 274 + .htotal = 1080 + 26 + 39 + 36, 275 + .vdisplay = 2400, 276 + .vsync_start = 2400 + 16, 277 + .vsync_end = 2400 + 16 + 21, 278 + .vtotal = 2400 + 16 + 21 + 16, 279 + .width_mm = 68, 280 + .height_mm = 152, 281 + .type = DRM_MODE_TYPE_DRIVER, 282 + }, 283 + }; 284 + 285 + static int visionox_rm692e5_get_modes(struct drm_panel *panel, 286 + struct drm_connector *connector) 287 + { 288 + int count = 0; 289 + 290 + for (int i = 0; i < ARRAY_SIZE(visionox_rm692e5_modes); i++) 291 + count += drm_connector_helper_get_modes_fixed(connector, 292 + &visionox_rm692e5_modes[i]); 293 + 294 + return count; 295 + } 296 + 297 + static const struct drm_panel_funcs visionox_rm692e5_panel_funcs = { 298 + .prepare = visionox_rm692e5_prepare, 299 + .unprepare = visionox_rm692e5_unprepare, 300 + .disable = visionox_rm692e5_disable, 301 + .get_modes = visionox_rm692e5_get_modes, 302 + }; 303 + 304 + static int visionox_rm692e5_bl_update_status(struct backlight_device *bl) 305 + { 306 + struct mipi_dsi_device *dsi = bl_get_data(bl); 307 + u16 brightness = backlight_get_brightness(bl); 308 + int ret; 309 + 310 + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 311 + 312 + ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); 313 + if (ret < 0) 314 + return ret; 315 + 316 + dsi->mode_flags |= MIPI_DSI_MODE_LPM; 317 + 318 + return 0; 319 + } 320 + 321 + static int visionox_rm692e5_bl_get_brightness(struct backlight_device *bl) 322 + { 323 + struct mipi_dsi_device *dsi = bl_get_data(bl); 324 + u16 brightness; 325 + int ret; 326 + 327 + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 328 + 329 + ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness); 330 + if (ret < 0) 331 + return ret; 332 + 333 + dsi->mode_flags |= MIPI_DSI_MODE_LPM; 334 + 335 + return brightness; 336 + } 337 + 338 + static const struct backlight_ops visionox_rm692e5_bl_ops = { 339 + .update_status = visionox_rm692e5_bl_update_status, 340 + .get_brightness = visionox_rm692e5_bl_get_brightness, 341 + }; 342 + 343 + static struct backlight_device * 344 + visionox_rm692e5_create_backlight(struct mipi_dsi_device *dsi) 345 + { 346 + struct device *dev = &dsi->dev; 347 + const struct backlight_properties props = { 348 + .type = BACKLIGHT_RAW, 349 + .brightness = 2047, 350 + .max_brightness = 4095, 351 + }; 352 + 353 + return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, 354 + &visionox_rm692e5_bl_ops, &props); 355 + } 356 + 357 + static int visionox_rm692e5_probe(struct mipi_dsi_device *dsi) 358 + { 359 + struct device *dev = &dsi->dev; 360 + struct visionox_rm692e5 *ctx; 361 + int ret; 362 + 363 + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 364 + if (!ctx) 365 + return -ENOMEM; 366 + 367 + ret = devm_regulator_bulk_get_const(&dsi->dev, 368 + ARRAY_SIZE(visionox_rm692e5_supplies), 369 + visionox_rm692e5_supplies, 370 + &ctx->supplies); 371 + if (ret < 0) 372 + return dev_err_probe(dev, ret, "Failed to get regulators\n"); 373 + 374 + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 375 + if (IS_ERR(ctx->reset_gpio)) 376 + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), 377 + "Failed to get reset-gpios\n"); 378 + 379 + ctx->dsi = dsi; 380 + mipi_dsi_set_drvdata(dsi, ctx); 381 + 382 + dsi->lanes = 4; 383 + dsi->format = MIPI_DSI_FMT_RGB888; 384 + dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS; 385 + 386 + drm_panel_init(&ctx->panel, dev, &visionox_rm692e5_panel_funcs, 387 + DRM_MODE_CONNECTOR_DSI); 388 + ctx->panel.prepare_prev_first = true; 389 + 390 + ctx->panel.backlight = visionox_rm692e5_create_backlight(dsi); 391 + if (IS_ERR(ctx->panel.backlight)) 392 + return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight), 393 + "Failed to create backlight\n"); 394 + 395 + drm_panel_add(&ctx->panel); 396 + 397 + dsi->dsc = &ctx->dsc; 398 + ctx->dsc.dsc_version_major = 1; 399 + ctx->dsc.dsc_version_minor = 1; 400 + ctx->dsc.slice_height = 20; 401 + ctx->dsc.slice_width = 540; 402 + ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; 403 + ctx->dsc.bits_per_component = 10; 404 + ctx->dsc.bits_per_pixel = 8 << 4; 405 + ctx->dsc.block_pred_enable = true; 406 + 407 + ret = devm_mipi_dsi_attach(dev, dsi); 408 + if (ret < 0) { 409 + drm_panel_remove(&ctx->panel); 410 + return dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); 411 + } 412 + 413 + return 0; 414 + } 415 + 416 + static void visionox_rm692e5_remove(struct mipi_dsi_device *dsi) 417 + { 418 + struct visionox_rm692e5 *ctx = mipi_dsi_get_drvdata(dsi); 419 + 420 + drm_panel_remove(&ctx->panel); 421 + } 422 + 423 + static const struct of_device_id visionox_rm692e5_of_match[] = { 424 + { .compatible = "visionox,rm692e5" }, 425 + { /* sentinel */ } 426 + }; 427 + MODULE_DEVICE_TABLE(of, visionox_rm692e5_of_match); 428 + 429 + static struct mipi_dsi_driver visionox_rm692e5_driver = { 430 + .probe = visionox_rm692e5_probe, 431 + .remove = visionox_rm692e5_remove, 432 + .driver = { 433 + .name = "panel-visionox-rm692e5", 434 + .of_match_table = visionox_rm692e5_of_match, 435 + }, 436 + }; 437 + module_mipi_dsi_driver(visionox_rm692e5_driver); 438 + 439 + MODULE_AUTHOR("Eugene Lepshy <fekz115@gmail.com>"); 440 + MODULE_AUTHOR("Danila Tikhonov <danila@jiaxyga.com>"); 441 + MODULE_DESCRIPTION("DRM driver for Visionox RM692E5 cmd mode dsi panel"); 442 + MODULE_LICENSE("GPL");

+5 -18

drivers/gpu/drm/scheduler/sched_entity.c

··· 28 28 #include <drm/drm_print.h> 29 29 #include <drm/gpu_scheduler.h> 30 30 31 - #include "gpu_scheduler_trace.h" 31 + #include "sched_internal.h" 32 32 33 - #define to_drm_sched_job(sched_job) \ 34 - container_of((sched_job), struct drm_sched_job, queue_node) 33 + #include "gpu_scheduler_trace.h" 35 34 36 35 /** 37 36 * drm_sched_entity_init - Init a context entity used by scheduler when ··· 151 152 return false; 152 153 } 153 154 154 - /* Return true if entity could provide a job. */ 155 - bool drm_sched_entity_is_ready(struct drm_sched_entity *entity) 156 - { 157 - if (spsc_queue_peek(&entity->job_queue) == NULL) 158 - return false; 159 - 160 - if (READ_ONCE(entity->dependency)) 161 - return false; 162 - 163 - return true; 164 - } 165 - 166 155 /** 167 156 * drm_sched_entity_error - return error of last scheduled job 168 157 * @entity: scheduler entity to check ··· 242 255 /* The entity is guaranteed to not be used by the scheduler */ 243 256 prev = rcu_dereference_check(entity->last_scheduled, true); 244 257 dma_fence_get(prev); 245 - while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_queue)))) { 258 + while ((job = drm_sched_entity_queue_pop(entity))) { 246 259 struct drm_sched_fence *s_fence = job->s_fence; 247 260 248 261 dma_fence_get(&s_fence->finished); ··· 464 477 { 465 478 struct drm_sched_job *sched_job; 466 479 467 - sched_job = to_drm_sched_job(spsc_queue_peek(&entity->job_queue)); 480 + sched_job = drm_sched_entity_queue_peek(entity); 468 481 if (!sched_job) 469 482 return NULL; 470 483 ··· 500 513 if (drm_sched_policy == DRM_SCHED_POLICY_FIFO) { 501 514 struct drm_sched_job *next; 502 515 503 - next = to_drm_sched_job(spsc_queue_peek(&entity->job_queue)); 516 + next = drm_sched_entity_queue_peek(entity); 504 517 if (next) { 505 518 struct drm_sched_rq *rq; 506 519

+2

drivers/gpu/drm/scheduler/sched_fence.c

··· 29 29 30 30 #include <drm/gpu_scheduler.h> 31 31 32 + #include "sched_internal.h" 33 + 32 34 static struct kmem_cache *sched_fence_slab; 33 35 34 36 static int __init drm_sched_fence_slab_init(void)

+91

drivers/gpu/drm/scheduler/sched_internal.h

··· 1 + /* SPDX-License-Identifier: MIT */ 2 + 3 + #ifndef _DRM_GPU_SCHEDULER_INTERNAL_H_ 4 + #define _DRM_GPU_SCHEDULER_INTERNAL_H_ 5 + 6 + 7 + /* Used to choose between FIFO and RR job-scheduling */ 8 + extern int drm_sched_policy; 9 + 10 + #define DRM_SCHED_POLICY_RR 0 11 + #define DRM_SCHED_POLICY_FIFO 1 12 + 13 + void drm_sched_wakeup(struct drm_gpu_scheduler *sched); 14 + 15 + void drm_sched_rq_add_entity(struct drm_sched_rq *rq, 16 + struct drm_sched_entity *entity); 17 + void drm_sched_rq_remove_entity(struct drm_sched_rq *rq, 18 + struct drm_sched_entity *entity); 19 + 20 + void drm_sched_rq_update_fifo_locked(struct drm_sched_entity *entity, 21 + struct drm_sched_rq *rq, ktime_t ts); 22 + 23 + void drm_sched_entity_select_rq(struct drm_sched_entity *entity); 24 + struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity); 25 + 26 + struct drm_sched_fence *drm_sched_fence_alloc(struct drm_sched_entity *s_entity, 27 + void *owner); 28 + void drm_sched_fence_init(struct drm_sched_fence *fence, 29 + struct drm_sched_entity *entity); 30 + void drm_sched_fence_free(struct drm_sched_fence *fence); 31 + 32 + void drm_sched_fence_scheduled(struct drm_sched_fence *fence, 33 + struct dma_fence *parent); 34 + void drm_sched_fence_finished(struct drm_sched_fence *fence, int result); 35 + 36 + /** 37 + * drm_sched_entity_queue_pop - Low level helper for popping queued jobs 38 + * 39 + * @entity: scheduler entity 40 + * 41 + * Low level helper for popping queued jobs. 42 + * 43 + * Returns: The job dequeued or NULL. 44 + */ 45 + static inline struct drm_sched_job * 46 + drm_sched_entity_queue_pop(struct drm_sched_entity *entity) 47 + { 48 + struct spsc_node *node; 49 + 50 + node = spsc_queue_pop(&entity->job_queue); 51 + if (!node) 52 + return NULL; 53 + 54 + return container_of(node, struct drm_sched_job, queue_node); 55 + } 56 + 57 + /** 58 + * drm_sched_entity_queue_peek - Low level helper for peeking at the job queue 59 + * 60 + * @entity: scheduler entity 61 + * 62 + * Low level helper for peeking at the job queue 63 + * 64 + * Returns: The job at the head of the queue or NULL. 65 + */ 66 + static inline struct drm_sched_job * 67 + drm_sched_entity_queue_peek(struct drm_sched_entity *entity) 68 + { 69 + struct spsc_node *node; 70 + 71 + node = spsc_queue_peek(&entity->job_queue); 72 + if (!node) 73 + return NULL; 74 + 75 + return container_of(node, struct drm_sched_job, queue_node); 76 + } 77 + 78 + /* Return true if entity could provide a job. */ 79 + static inline bool 80 + drm_sched_entity_is_ready(struct drm_sched_entity *entity) 81 + { 82 + if (!spsc_queue_count(&entity->job_queue)) 83 + return false; 84 + 85 + if (READ_ONCE(entity->dependency)) 86 + return false; 87 + 88 + return true; 89 + } 90 + 91 + #endif

+3 -4

drivers/gpu/drm/scheduler/sched_main.c

··· 78 78 #include <drm/gpu_scheduler.h> 79 79 #include <drm/spsc_queue.h> 80 80 81 + #include "sched_internal.h" 82 + 81 83 #define CREATE_TRACE_POINTS 82 84 #include "gpu_scheduler_trace.h" 83 85 ··· 88 86 .name = "drm_sched_lockdep_map" 89 87 }; 90 88 #endif 91 - 92 - #define to_drm_sched_job(sched_job) \ 93 - container_of((sched_job), struct drm_sched_job, queue_node) 94 89 95 90 int drm_sched_policy = DRM_SCHED_POLICY_FIFO; 96 91 ··· 122 123 { 123 124 struct drm_sched_job *s_job; 124 125 125 - s_job = to_drm_sched_job(spsc_queue_peek(&entity->job_queue)); 126 + s_job = drm_sched_entity_queue_peek(entity); 126 127 if (!s_job) 127 128 return false; 128 129

+1 -3

drivers/gpu/drm/stm/ltdc.c

··· 1900 1900 struct drm_panel *panel; 1901 1901 struct drm_crtc *crtc; 1902 1902 struct reset_control *rstc; 1903 - struct resource *res; 1904 1903 int irq, i, nb_endpoints; 1905 1904 int ret = -ENODEV; 1906 1905 ··· 1965 1966 reset_control_deassert(rstc); 1966 1967 } 1967 1968 1968 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1969 - ldev->regs = devm_ioremap_resource(dev, res); 1969 + ldev->regs = devm_platform_ioremap_resource(pdev, 0); 1970 1970 if (IS_ERR(ldev->regs)) { 1971 1971 DRM_ERROR("Unable to get ltdc registers\n"); 1972 1972 ret = PTR_ERR(ldev->regs);

+1 -3

drivers/gpu/drm/tiny/arcpgu.c

··· 253 253 struct device_node *encoder_node = NULL, *endpoint_node = NULL; 254 254 struct drm_connector *connector = NULL; 255 255 struct drm_device *drm = &arcpgu->drm; 256 - struct resource *res; 257 256 int ret; 258 257 259 258 arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); ··· 269 270 drm->mode_config.max_height = 1080; 270 271 drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; 271 272 272 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 273 - arcpgu->regs = devm_ioremap_resource(&pdev->dev, res); 273 + arcpgu->regs = devm_platform_ioremap_resource(pdev, 0); 274 274 if (IS_ERR(arcpgu->regs)) 275 275 return PTR_ERR(arcpgu->regs); 276 276

+2 -2

drivers/gpu/drm/tiny/repaper.c

··· 456 456 enum repaper_stage stage) 457 457 { 458 458 u64 start = local_clock(); 459 - u64 end = start + (epd->factored_stage_time * 1000 * 1000); 459 + u64 end = start + ((u64)epd->factored_stage_time * 1000 * 1000); 460 460 461 461 do { 462 462 repaper_frame_fixed(epd, fixed_value, stage); ··· 467 467 const u8 *mask, enum repaper_stage stage) 468 468 { 469 469 u64 start = local_clock(); 470 - u64 end = start + (epd->factored_stage_time * 1000 * 1000); 470 + u64 end = start + ((u64)epd->factored_stage_time * 1000 * 1000); 471 471 472 472 do { 473 473 repaper_frame_data(epd, image, mask, stage);

+18 -35

drivers/gpu/drm/vc4/vc4_hdmi.c

··· 2926 2926 struct resource *res; 2927 2927 int ret; 2928 2928 2929 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2930 - if (!res) 2931 - return -ENODEV; 2932 - 2933 - vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2934 - resource_size(res)); 2929 + vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 2930 + "hdmi"); 2935 2931 if (!vc4_hdmi->hdmicore_regs) 2936 2932 return -ENOMEM; 2937 2933 2934 + /* This is shared between both HDMI controllers. Cannot 2935 + * claim for both instances. Lets not convert to using 2936 + * devm_platform_ioremap_resource_byname() like 2937 + * the rest 2938 + */ 2938 2939 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2939 2940 if (!res) 2940 2941 return -ENODEV; ··· 2944 2943 if (!vc4_hdmi->hd_regs) 2945 2944 return -ENOMEM; 2946 2945 2947 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2948 - if (!res) 2949 - return -ENODEV; 2950 - 2951 - vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2946 + vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 2947 + "cec"); 2952 2948 if (!vc4_hdmi->cec_regs) 2953 2949 return -ENOMEM; 2954 2950 2955 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2956 - if (!res) 2957 - return -ENODEV; 2958 - 2959 - vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2951 + vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 2952 + "csc"); 2960 2953 if (!vc4_hdmi->csc_regs) 2961 2954 return -ENOMEM; 2962 2955 2963 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2964 - if (!res) 2965 - return -ENODEV; 2966 - 2967 - vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2956 + vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 2957 + "dvp"); 2968 2958 if (!vc4_hdmi->dvp_regs) 2969 2959 return -ENOMEM; 2970 2960 2971 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2972 - if (!res) 2973 - return -ENODEV; 2961 + vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 2962 + "phy"); 2974 2963 2975 - vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2976 2964 if (!vc4_hdmi->phy_regs) 2977 2965 return -ENOMEM; 2978 2966 2979 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2980 - if (!res) 2981 - return -ENODEV; 2982 - 2983 - vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2967 + vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 2968 + "packet"); 2984 2969 if (!vc4_hdmi->ram_regs) 2985 2970 return -ENOMEM; 2986 2971 2987 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2988 - if (!res) 2989 - return -ENODEV; 2990 - 2991 - vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2972 + vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 2992 2973 if (!vc4_hdmi->rm_regs) 2993 2974 return -ENOMEM; 2994 2975

+2

include/drm/display/drm_dp_helper.h

··· 630 630 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 631 631 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 632 632 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 633 + int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 634 + int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 633 635 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 634 636 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 635 637 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);

+1 -1

include/drm/drm_mipi_dsi.h

··· 346 346 u16 end); 347 347 int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, 348 348 u16 end); 349 - int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi); 350 349 int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, 351 350 enum mipi_dsi_dcs_tear_mode mode); 352 351 int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); ··· 378 379 u16 start, u16 end); 379 380 void mipi_dsi_dcs_set_tear_scanline_multi(struct mipi_dsi_multi_context *ctx, 380 381 u16 scanline); 382 + void mipi_dsi_dcs_set_tear_off_multi(struct mipi_dsi_multi_context *ctx); 381 383 382 384 /** 383 385 * mipi_dsi_generic_write_seq - transmit data using a generic write packet

+52 -72

include/drm/gpu_scheduler.h

··· 71 71 DRM_SCHED_PRIORITY_COUNT 72 72 }; 73 73 74 - /* Used to choose between FIFO and RR job-scheduling */ 75 - extern int drm_sched_policy; 76 - 77 - #define DRM_SCHED_POLICY_RR 0 78 - #define DRM_SCHED_POLICY_FIFO 1 79 - 80 74 /** 81 75 * struct drm_sched_entity - A wrapper around a job queue (typically 82 76 * attached to the DRM file_priv). ··· 332 338 * to schedule the job. 333 339 */ 334 340 struct drm_sched_job { 335 - struct spsc_node queue_node; 336 - struct list_head list; 341 + u64 id; 342 + 343 + /** 344 + * @submit_ts: 345 + * 346 + * When the job was pushed into the entity queue. 347 + */ 348 + ktime_t submit_ts; 337 349 338 350 /** 339 351 * @sched: ··· 349 349 * has finished. 350 350 */ 351 351 struct drm_gpu_scheduler *sched; 352 - struct drm_sched_fence *s_fence; 353 352 353 + struct drm_sched_fence *s_fence; 354 + struct drm_sched_entity *entity; 355 + 356 + enum drm_sched_priority s_priority; 354 357 u32 credits; 358 + /** @last_dependency: tracks @dependencies as they signal */ 359 + unsigned int last_dependency; 360 + atomic_t karma; 361 + 362 + struct spsc_node queue_node; 363 + struct list_head list; 355 364 356 365 /* 357 366 * work is used only after finish_cb has been used and will not be 358 367 * accessed anymore. 359 368 */ 360 369 union { 361 - struct dma_fence_cb finish_cb; 362 - struct work_struct work; 370 + struct dma_fence_cb finish_cb; 371 + struct work_struct work; 363 372 }; 364 373 365 - uint64_t id; 366 - atomic_t karma; 367 - enum drm_sched_priority s_priority; 368 - struct drm_sched_entity *entity; 369 374 struct dma_fence_cb cb; 375 + 370 376 /** 371 377 * @dependencies: 372 378 * ··· 381 375 * drm_sched_job_add_implicit_dependencies(). 382 376 */ 383 377 struct xarray dependencies; 384 - 385 - /** @last_dependency: tracks @dependencies as they signal */ 386 - unsigned long last_dependency; 387 - 388 - /** 389 - * @submit_ts: 390 - * 391 - * When the job was pushed into the entity queue. 392 - */ 393 - ktime_t submit_ts; 394 378 }; 395 - 396 - static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job, 397 - int threshold) 398 - { 399 - return s_job && atomic_inc_return(&s_job->karma) > threshold; 400 - } 401 379 402 380 enum drm_gpu_sched_stat { 403 381 DRM_GPU_SCHED_STAT_NONE, /* Reserve 0 */ ··· 560 570 struct device *dev; 561 571 }; 562 572 573 + /* Scheduler operations */ 574 + 563 575 int drm_sched_init(struct drm_gpu_scheduler *sched, 564 576 const struct drm_sched_init_args *args); 565 577 566 578 void drm_sched_fini(struct drm_gpu_scheduler *sched); 579 + 580 + unsigned long drm_sched_suspend_timeout(struct drm_gpu_scheduler *sched); 581 + void drm_sched_resume_timeout(struct drm_gpu_scheduler *sched, 582 + unsigned long remaining); 583 + void drm_sched_tdr_queue_imm(struct drm_gpu_scheduler *sched); 584 + bool drm_sched_wqueue_ready(struct drm_gpu_scheduler *sched); 585 + void drm_sched_wqueue_stop(struct drm_gpu_scheduler *sched); 586 + void drm_sched_wqueue_start(struct drm_gpu_scheduler *sched); 587 + void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad); 588 + void drm_sched_start(struct drm_gpu_scheduler *sched, int errno); 589 + void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched); 590 + void drm_sched_fault(struct drm_gpu_scheduler *sched); 591 + 592 + struct drm_gpu_scheduler * 593 + drm_sched_pick_best(struct drm_gpu_scheduler **sched_list, 594 + unsigned int num_sched_list); 595 + 596 + /* Jobs */ 597 + 567 598 int drm_sched_job_init(struct drm_sched_job *job, 568 599 struct drm_sched_entity *entity, 569 600 u32 credits, void *owner); 570 601 void drm_sched_job_arm(struct drm_sched_job *job); 602 + void drm_sched_entity_push_job(struct drm_sched_job *sched_job); 571 603 int drm_sched_job_add_dependency(struct drm_sched_job *job, 572 604 struct dma_fence *fence); 573 605 int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job, ··· 604 592 bool write); 605 593 bool drm_sched_job_has_dependency(struct drm_sched_job *job, 606 594 struct dma_fence *fence); 607 - 608 - void drm_sched_entity_modify_sched(struct drm_sched_entity *entity, 609 - struct drm_gpu_scheduler **sched_list, 610 - unsigned int num_sched_list); 611 - 612 - void drm_sched_tdr_queue_imm(struct drm_gpu_scheduler *sched); 613 595 void drm_sched_job_cleanup(struct drm_sched_job *job); 614 - void drm_sched_wakeup(struct drm_gpu_scheduler *sched); 615 - bool drm_sched_wqueue_ready(struct drm_gpu_scheduler *sched); 616 - void drm_sched_wqueue_stop(struct drm_gpu_scheduler *sched); 617 - void drm_sched_wqueue_start(struct drm_gpu_scheduler *sched); 618 - void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad); 619 - void drm_sched_start(struct drm_gpu_scheduler *sched, int errno); 620 - void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched); 621 596 void drm_sched_increase_karma(struct drm_sched_job *bad); 622 - void drm_sched_fault(struct drm_gpu_scheduler *sched); 623 597 624 - void drm_sched_rq_add_entity(struct drm_sched_rq *rq, 625 - struct drm_sched_entity *entity); 626 - void drm_sched_rq_remove_entity(struct drm_sched_rq *rq, 627 - struct drm_sched_entity *entity); 598 + static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job, 599 + int threshold) 600 + { 601 + return s_job && atomic_inc_return(&s_job->karma) > threshold; 602 + } 628 603 629 - void drm_sched_rq_update_fifo_locked(struct drm_sched_entity *entity, 630 - struct drm_sched_rq *rq, ktime_t ts); 604 + /* Entities */ 631 605 632 606 int drm_sched_entity_init(struct drm_sched_entity *entity, 633 607 enum drm_sched_priority priority, ··· 623 625 long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout); 624 626 void drm_sched_entity_fini(struct drm_sched_entity *entity); 625 627 void drm_sched_entity_destroy(struct drm_sched_entity *entity); 626 - void drm_sched_entity_select_rq(struct drm_sched_entity *entity); 627 - struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity); 628 - void drm_sched_entity_push_job(struct drm_sched_job *sched_job); 629 628 void drm_sched_entity_set_priority(struct drm_sched_entity *entity, 630 629 enum drm_sched_priority priority); 631 - bool drm_sched_entity_is_ready(struct drm_sched_entity *entity); 632 630 int drm_sched_entity_error(struct drm_sched_entity *entity); 633 - 634 - struct drm_sched_fence *drm_sched_fence_alloc( 635 - struct drm_sched_entity *s_entity, void *owner); 636 - void drm_sched_fence_init(struct drm_sched_fence *fence, 637 - struct drm_sched_entity *entity); 638 - void drm_sched_fence_free(struct drm_sched_fence *fence); 639 - 640 - void drm_sched_fence_scheduled(struct drm_sched_fence *fence, 641 - struct dma_fence *parent); 642 - void drm_sched_fence_finished(struct drm_sched_fence *fence, int result); 643 - 644 - unsigned long drm_sched_suspend_timeout(struct drm_gpu_scheduler *sched); 645 - void drm_sched_resume_timeout(struct drm_gpu_scheduler *sched, 646 - unsigned long remaining); 647 - struct drm_gpu_scheduler * 648 - drm_sched_pick_best(struct drm_gpu_scheduler **sched_list, 649 - unsigned int num_sched_list); 631 + void drm_sched_entity_modify_sched(struct drm_sched_entity *entity, 632 + struct drm_gpu_scheduler **sched_list, 633 + unsigned int num_sched_list); 650 634 651 635 #endif

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