tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Pull media fixes from Mauro Carvalho Chehab:
"For some media fixes:
- dvb_usb_v2: some fixes at the core
- Some fixes on some embedded drivers: soc_camera, adv7604, omap3isp,
exynos/s5p
- Several Exynos4/5 camera fixes
- a fix at stv0900 driver
- a few USB ID additions to detect more variants of rtl28xxu-based
sticks"

* 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (25 commits)
[media] rtl28xxu: 0ccd:00d7 TerraTec Cinergy T Stick+
[media] rtl28xxu: 1d19:1102 Dexatek DK mini DVB-T Dongle
[media] mt9v022: fix the V4L2_CID_EXPOSURE control
[media] mx2_camera: fix missing unlock on error in mx2_start_streaming()
[media] media: omap1_camera: fix const cropping related warnings
[media] media: mx1_camera: use the default .set_crop() implementation
[media] media: mx2_camera: fix const cropping related warnings
[media] media: mx3_camera: fix const cropping related warnings
[media] media: pxa_camera: fix const cropping related warnings
[media] media: sh_mobile_ceu_camera: fix const cropping related warnings
[media] media: sh_vou: fix const cropping related warnings
[media] adv7604: restart STDI once if format is not found
[media] adv7604: use presets where possible
[media] adv7604: Replace prim_mode by mode
[media] adv7604: cleanup references
[media] dvb_usb_v2: switch interruptible mutex to normal
[media] dvb_usb_v2: fix pid_filter callback error logging
[media] exynos-gsc: change driver compatible string
[media] omap3isp: Fix warning caused by bad subdev events operations prototypes
[media] omap3isp: video: Fix warning caused by bad vidioc_s_crop prototype
...

Linus Torvalds e23739b4 2844a487

+366 -189
+3 -3
drivers/media/dvb-frontends/stv0900_core.c
··· 300 300 { 301 301 u32 m_div, clk_sel; 302 302 303 - dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 304 - intp->quartz); 305 - 306 303 if (intp == NULL) 307 304 return STV0900_INVALID_HANDLE; 308 305 309 306 if (intp->errs) 310 307 return STV0900_I2C_ERROR; 308 + 309 + dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 310 + intp->quartz); 311 311 312 312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); 313 313 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
+272 -105
drivers/media/i2c/adv7604.c
··· 53 53 /* ADV7604 system clock frequency */ 54 54 #define ADV7604_fsc (28636360) 55 55 56 - #define DIGITAL_INPUT ((state->prim_mode == ADV7604_PRIM_MODE_HDMI_COMP) || \ 57 - (state->prim_mode == ADV7604_PRIM_MODE_HDMI_GR)) 56 + #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI) 58 57 59 58 /* 60 59 ********************************************************************** ··· 67 68 struct v4l2_subdev sd; 68 69 struct media_pad pad; 69 70 struct v4l2_ctrl_handler hdl; 70 - enum adv7604_prim_mode prim_mode; 71 + enum adv7604_mode mode; 71 72 struct v4l2_dv_timings timings; 72 73 u8 edid[256]; 73 74 unsigned edid_blocks; ··· 76 77 struct workqueue_struct *work_queues; 77 78 struct delayed_work delayed_work_enable_hotplug; 78 79 bool connector_hdmi; 80 + bool restart_stdi_once; 79 81 80 82 /* i2c clients */ 81 83 struct i2c_client *i2c_avlink; ··· 106 106 V4L2_DV_BT_CEA_720X576P50, 107 107 V4L2_DV_BT_CEA_1280X720P24, 108 108 V4L2_DV_BT_CEA_1280X720P25, 109 - V4L2_DV_BT_CEA_1280X720P30, 110 109 V4L2_DV_BT_CEA_1280X720P50, 111 110 V4L2_DV_BT_CEA_1280X720P60, 112 111 V4L2_DV_BT_CEA_1920X1080P24, ··· 114 115 V4L2_DV_BT_CEA_1920X1080P50, 115 116 V4L2_DV_BT_CEA_1920X1080P60, 116 117 118 + /* sorted by DMT ID */ 117 119 V4L2_DV_BT_DMT_640X350P85, 118 120 V4L2_DV_BT_DMT_640X400P85, 119 121 V4L2_DV_BT_DMT_720X400P85, ··· 161 161 V4L2_DV_BT_DMT_1920X1200P60_RB, 162 162 V4L2_DV_BT_DMT_1366X768P60, 163 163 V4L2_DV_BT_DMT_1920X1080P60, 164 + { }, 165 + }; 166 + 167 + struct adv7604_video_standards { 168 + struct v4l2_dv_timings timings; 169 + u8 vid_std; 170 + u8 v_freq; 171 + }; 172 + 173 + /* sorted by number of lines */ 174 + static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 175 + /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 176 + { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 177 + { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 178 + { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 179 + { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 180 + { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 181 + { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 182 + { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 183 + { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 184 + /* TODO add 1920x1080P60_RB (CVT timing) */ 185 + { }, 186 + }; 187 + 188 + /* sorted by number of lines */ 189 + static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 190 + { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 191 + { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 192 + { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 193 + { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 194 + { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 195 + { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 196 + { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 197 + { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 198 + { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 199 + { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 200 + { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 201 + { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 202 + { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 203 + { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 204 + { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 205 + { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 206 + { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 207 + { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 208 + { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 209 + { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 210 + /* TODO add 1600X1200P60_RB (not a DMT timing) */ 211 + { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 212 + { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 213 + { }, 214 + }; 215 + 216 + /* sorted by number of lines */ 217 + static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 218 + { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 219 + { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 220 + { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 221 + { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 222 + { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 223 + { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 224 + { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 225 + { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 226 + { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 227 + { }, 228 + }; 229 + 230 + /* sorted by number of lines */ 231 + static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 232 + { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 233 + { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 234 + { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 235 + { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 236 + { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 237 + { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 238 + { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 239 + { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 240 + { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 241 + { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 242 + { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 243 + { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 244 + { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 245 + { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 246 + { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 164 247 { }, 165 248 }; 166 249 ··· 755 672 ((io_read(sd, 0x6f) & 0x10) >> 4)); 756 673 } 757 674 758 - static void configure_free_run(struct v4l2_subdev *sd, const struct v4l2_bt_timings *timings) 675 + static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 676 + u8 prim_mode, 677 + const struct adv7604_video_standards *predef_vid_timings, 678 + const struct v4l2_dv_timings *timings) 759 679 { 680 + struct adv7604_state *state = to_state(sd); 681 + int i; 682 + 683 + for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 684 + if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings, 685 + DIGITAL_INPUT ? 250000 : 1000000)) 686 + continue; 687 + io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 688 + io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 689 + prim_mode); /* v_freq and prim mode */ 690 + return 0; 691 + } 692 + 693 + return -1; 694 + } 695 + 696 + static int configure_predefined_video_timings(struct v4l2_subdev *sd, 697 + struct v4l2_dv_timings *timings) 698 + { 699 + struct adv7604_state *state = to_state(sd); 700 + int err; 701 + 702 + v4l2_dbg(1, debug, sd, "%s", __func__); 703 + 704 + /* reset to default values */ 705 + io_write(sd, 0x16, 0x43); 706 + io_write(sd, 0x17, 0x5a); 707 + /* disable embedded syncs for auto graphics mode */ 708 + cp_write_and_or(sd, 0x81, 0xef, 0x00); 709 + cp_write(sd, 0x8f, 0x00); 710 + cp_write(sd, 0x90, 0x00); 711 + cp_write(sd, 0xa2, 0x00); 712 + cp_write(sd, 0xa3, 0x00); 713 + cp_write(sd, 0xa4, 0x00); 714 + cp_write(sd, 0xa5, 0x00); 715 + cp_write(sd, 0xa6, 0x00); 716 + cp_write(sd, 0xa7, 0x00); 717 + cp_write(sd, 0xab, 0x00); 718 + cp_write(sd, 0xac, 0x00); 719 + 720 + switch (state->mode) { 721 + case ADV7604_MODE_COMP: 722 + case ADV7604_MODE_GR: 723 + err = find_and_set_predefined_video_timings(sd, 724 + 0x01, adv7604_prim_mode_comp, timings); 725 + if (err) 726 + err = find_and_set_predefined_video_timings(sd, 727 + 0x02, adv7604_prim_mode_gr, timings); 728 + break; 729 + case ADV7604_MODE_HDMI: 730 + err = find_and_set_predefined_video_timings(sd, 731 + 0x05, adv7604_prim_mode_hdmi_comp, timings); 732 + if (err) 733 + err = find_and_set_predefined_video_timings(sd, 734 + 0x06, adv7604_prim_mode_hdmi_gr, timings); 735 + break; 736 + default: 737 + v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 738 + __func__, state->mode); 739 + err = -1; 740 + break; 741 + } 742 + 743 + 744 + return err; 745 + } 746 + 747 + static void configure_custom_video_timings(struct v4l2_subdev *sd, 748 + const struct v4l2_bt_timings *bt) 749 + { 750 + struct adv7604_state *state = to_state(sd); 760 751 struct i2c_client *client = v4l2_get_subdevdata(sd); 761 - u32 width = htotal(timings); 762 - u32 height = vtotal(timings); 763 - u16 ch1_fr_ll = (((u32)timings->pixelclock / 100) > 0) ? 764 - ((width * (ADV7604_fsc / 100)) / ((u32)timings->pixelclock / 100)) : 0; 752 + u32 width = htotal(bt); 753 + u32 height = vtotal(bt); 754 + u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 755 + u16 cp_start_eav = width - bt->hfrontporch; 756 + u16 cp_start_vbi = height - bt->vfrontporch; 757 + u16 cp_end_vbi = bt->vsync + bt->vbackporch; 758 + u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 759 + ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 760 + const u8 pll[2] = { 761 + 0xc0 | ((width >> 8) & 0x1f), 762 + width & 0xff 763 + }; 765 764 766 765 v4l2_dbg(2, debug, sd, "%s\n", __func__); 767 766 768 - cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); /* CH1_FR_LL */ 769 - cp_write(sd, 0x90, ch1_fr_ll & 0xff); /* CH1_FR_LL */ 770 - cp_write(sd, 0xab, (height >> 4) & 0xff); /* CP_LCOUNT_MAX */ 771 - cp_write(sd, 0xac, (height & 0x0f) << 4); /* CP_LCOUNT_MAX */ 772 - /* TODO support interlaced */ 773 - cp_write(sd, 0x91, 0x10); /* INTERLACED */ 767 + switch (state->mode) { 768 + case ADV7604_MODE_COMP: 769 + case ADV7604_MODE_GR: 770 + /* auto graphics */ 771 + io_write(sd, 0x00, 0x07); /* video std */ 772 + io_write(sd, 0x01, 0x02); /* prim mode */ 773 + /* enable embedded syncs for auto graphics mode */ 774 + cp_write_and_or(sd, 0x81, 0xef, 0x10); 774 775 775 - /* Should only be set in auto-graphics mode [REF_02 p. 91-92] */ 776 - if ((io_read(sd, 0x00) == 0x07) && (io_read(sd, 0x01) == 0x02)) { 777 - u16 cp_start_sav, cp_start_eav, cp_start_vbi, cp_end_vbi; 778 - const u8 pll[2] = { 779 - (0xc0 | ((width >> 8) & 0x1f)), 780 - (width & 0xff) 781 - }; 782 - 776 + /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 783 777 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 784 778 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 785 779 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 786 780 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 787 - return; 781 + break; 788 782 } 789 783 790 784 /* active video - horizontal timing */ 791 - cp_start_sav = timings->hsync + timings->hbackporch - 4; 792 - cp_start_eav = width - timings->hfrontporch; 793 785 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 794 - cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | ((cp_start_eav >> 8) & 0x0f)); 786 + cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 787 + ((cp_start_eav >> 8) & 0x0f)); 795 788 cp_write(sd, 0xa4, cp_start_eav & 0xff); 796 789 797 790 /* active video - vertical timing */ 798 - cp_start_vbi = height - timings->vfrontporch; 799 - cp_end_vbi = timings->vsync + timings->vbackporch; 800 791 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 801 - cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | ((cp_end_vbi >> 8) & 0xf)); 792 + cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 793 + ((cp_end_vbi >> 8) & 0xf)); 802 794 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 803 - } else { 804 - /* reset to default values */ 805 - io_write(sd, 0x16, 0x43); 806 - io_write(sd, 0x17, 0x5a); 807 - cp_write(sd, 0xa2, 0x00); 808 - cp_write(sd, 0xa3, 0x00); 809 - cp_write(sd, 0xa4, 0x00); 810 - cp_write(sd, 0xa5, 0x00); 811 - cp_write(sd, 0xa6, 0x00); 812 - cp_write(sd, 0xa7, 0x00); 795 + break; 796 + case ADV7604_MODE_HDMI: 797 + /* set default prim_mode/vid_std for HDMI 798 + accoring to [REF_03, c. 4.2] */ 799 + io_write(sd, 0x00, 0x02); /* video std */ 800 + io_write(sd, 0x01, 0x06); /* prim mode */ 801 + break; 802 + default: 803 + v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 804 + __func__, state->mode); 805 + break; 813 806 } 814 - } 815 807 808 + cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 809 + cp_write(sd, 0x90, ch1_fr_ll & 0xff); 810 + cp_write(sd, 0xab, (height >> 4) & 0xff); 811 + cp_write(sd, 0xac, (height & 0x0f) << 4); 812 + } 816 813 817 814 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 818 815 { ··· 901 738 switch (state->rgb_quantization_range) { 902 739 case V4L2_DV_RGB_RANGE_AUTO: 903 740 /* automatic */ 904 - if ((hdmi_read(sd, 0x05) & 0x80) || 905 - (state->prim_mode == ADV7604_PRIM_MODE_COMP) || 906 - (state->prim_mode == ADV7604_PRIM_MODE_RGB)) { 907 - /* receiving HDMI or analog signal */ 908 - io_write_and_or(sd, 0x02, 0x0f, 0xf0); 909 - } else { 741 + if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) { 910 742 /* receiving DVI-D signal */ 911 743 912 744 /* ADV7604 selects RGB limited range regardless of ··· 914 756 /* RGB full range (0-255) */ 915 757 io_write_and_or(sd, 0x02, 0x0f, 0x10); 916 758 } 759 + } else { 760 + /* receiving HDMI or analog signal, set automode */ 761 + io_write_and_or(sd, 0x02, 0x0f, 0xf0); 917 762 } 918 763 break; 919 764 case V4L2_DV_RGB_RANGE_LIMITED: ··· 1128 967 state->aspect_ratio, timings)) 1129 968 return 0; 1130 969 1131 - v4l2_dbg(2, debug, sd, "%s: No format candidate found for lcf=%d, bl = %d\n", 1132 - __func__, stdi->lcf, stdi->bl); 970 + v4l2_dbg(2, debug, sd, 971 + "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 972 + __func__, stdi->lcvs, stdi->lcf, stdi->bl, 973 + stdi->hs_pol, stdi->vs_pol); 1133 974 return -1; 1134 975 } 1135 976 ··· 1286 1123 adv7604_fill_optional_dv_timings_fields(sd, timings); 1287 1124 } else { 1288 1125 /* find format 1289 - * Since LCVS values are inaccurate (REF_03, page 275-276), 1126 + * Since LCVS values are inaccurate [REF_03, p. 275-276], 1290 1127 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1291 1128 */ 1292 1129 if (!stdi2dv_timings(sd, &stdi, timings)) ··· 1298 1135 stdi.lcvs -= 2; 1299 1136 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1300 1137 if (stdi2dv_timings(sd, &stdi, timings)) { 1138 + /* 1139 + * The STDI block may measure wrong values, especially 1140 + * for lcvs and lcf. If the driver can not find any 1141 + * valid timing, the STDI block is restarted to measure 1142 + * the video timings again. The function will return an 1143 + * error, but the restart of STDI will generate a new 1144 + * STDI interrupt and the format detection process will 1145 + * restart. 1146 + */ 1147 + if (state->restart_stdi_once) { 1148 + v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1149 + /* TODO restart STDI for Sync Channel 2 */ 1150 + /* enter one-shot mode */ 1151 + cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1152 + /* trigger STDI restart */ 1153 + cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1154 + /* reset to continuous mode */ 1155 + cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1156 + state->restart_stdi_once = false; 1157 + return -ENOLINK; 1158 + } 1301 1159 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1302 1160 return -ERANGE; 1303 1161 } 1162 + state->restart_stdi_once = true; 1304 1163 } 1305 1164 found: 1306 1165 ··· 1351 1166 { 1352 1167 struct adv7604_state *state = to_state(sd); 1353 1168 struct v4l2_bt_timings *bt; 1169 + int err; 1354 1170 1355 1171 if (!timings) 1356 1172 return -EINVAL; ··· 1364 1178 __func__, (u32)bt->pixelclock); 1365 1179 return -ERANGE; 1366 1180 } 1181 + 1367 1182 adv7604_fill_optional_dv_timings_fields(sd, timings); 1368 1183 1369 1184 state->timings = *timings; 1370 1185 1371 - /* freerun */ 1372 - configure_free_run(sd, bt); 1186 + cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10); 1187 + 1188 + /* Use prim_mode and vid_std when available */ 1189 + err = configure_predefined_video_timings(sd, timings); 1190 + if (err) { 1191 + /* custom settings when the video format 1192 + does not have prim_mode/vid_std */ 1193 + configure_custom_video_timings(sd, bt); 1194 + } 1373 1195 1374 1196 set_rgb_quantization_range(sd); 1375 1197 ··· 1397 1203 return 0; 1398 1204 } 1399 1205 1400 - static void enable_input(struct v4l2_subdev *sd, enum adv7604_prim_mode prim_mode) 1206 + static void enable_input(struct v4l2_subdev *sd) 1401 1207 { 1402 - switch (prim_mode) { 1403 - case ADV7604_PRIM_MODE_COMP: 1404 - case ADV7604_PRIM_MODE_RGB: 1208 + struct adv7604_state *state = to_state(sd); 1209 + 1210 + switch (state->mode) { 1211 + case ADV7604_MODE_COMP: 1212 + case ADV7604_MODE_GR: 1405 1213 /* enable */ 1406 1214 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1407 1215 break; 1408 - case ADV7604_PRIM_MODE_HDMI_COMP: 1409 - case ADV7604_PRIM_MODE_HDMI_GR: 1216 + case ADV7604_MODE_HDMI: 1410 1217 /* enable */ 1411 1218 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */ 1412 1219 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1413 1220 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1414 1221 break; 1415 1222 default: 1416 - v4l2_err(sd, "%s: reserved primary mode 0x%0x\n", 1417 - __func__, prim_mode); 1223 + v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1224 + __func__, state->mode); 1418 1225 break; 1419 1226 } 1420 1227 } ··· 1428 1233 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1429 1234 } 1430 1235 1431 - static void select_input(struct v4l2_subdev *sd, enum adv7604_prim_mode prim_mode) 1236 + static void select_input(struct v4l2_subdev *sd) 1432 1237 { 1433 - switch (prim_mode) { 1434 - case ADV7604_PRIM_MODE_COMP: 1435 - case ADV7604_PRIM_MODE_RGB: 1436 - /* set mode and select free run resolution */ 1437 - io_write(sd, 0x00, 0x07); /* video std */ 1438 - io_write(sd, 0x01, 0x02); /* prim mode */ 1439 - /* enable embedded syncs for auto graphics mode */ 1440 - cp_write_and_or(sd, 0x81, 0xef, 0x10); 1238 + struct adv7604_state *state = to_state(sd); 1441 1239 1240 + switch (state->mode) { 1241 + case ADV7604_MODE_COMP: 1242 + case ADV7604_MODE_GR: 1442 1243 /* reset ADI recommended settings for HDMI: */ 1443 1244 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 1444 1245 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */ ··· 1462 1271 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1463 1272 break; 1464 1273 1465 - case ADV7604_PRIM_MODE_HDMI_COMP: 1466 - case ADV7604_PRIM_MODE_HDMI_GR: 1467 - /* set mode and select free run resolution */ 1468 - /* video std */ 1469 - io_write(sd, 0x00, 1470 - (prim_mode == ADV7604_PRIM_MODE_HDMI_GR) ? 0x02 : 0x1e); 1471 - io_write(sd, 0x01, prim_mode); /* prim mode */ 1472 - /* disable embedded syncs for auto graphics mode */ 1473 - cp_write_and_or(sd, 0x81, 0xef, 0x00); 1474 - 1274 + case ADV7604_MODE_HDMI: 1475 1275 /* set ADI recommended settings for HDMI: */ 1476 1276 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 1477 1277 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */ ··· 1491 1309 1492 1310 break; 1493 1311 default: 1494 - v4l2_err(sd, "%s: reserved primary mode 0x%0x\n", __func__, prim_mode); 1312 + v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1313 + __func__, state->mode); 1495 1314 break; 1496 1315 } 1497 1316 } ··· 1504 1321 1505 1322 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input); 1506 1323 1507 - switch (input) { 1508 - case 0: 1509 - /* TODO select HDMI_COMP or HDMI_GR */ 1510 - state->prim_mode = ADV7604_PRIM_MODE_HDMI_COMP; 1511 - break; 1512 - case 1: 1513 - state->prim_mode = ADV7604_PRIM_MODE_RGB; 1514 - break; 1515 - case 2: 1516 - state->prim_mode = ADV7604_PRIM_MODE_COMP; 1517 - break; 1518 - default: 1519 - return -EINVAL; 1520 - } 1324 + state->mode = input; 1521 1325 1522 1326 disable_input(sd); 1523 1327 1524 - select_input(sd, state->prim_mode); 1328 + select_input(sd); 1525 1329 1526 - enable_input(sd, state->prim_mode); 1330 + enable_input(sd); 1527 1331 1528 1332 return 0; 1529 1333 } ··· 1719 1549 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 1720 1550 v4l2_info(sd, "CP free run: %s\n", 1721 1551 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 1722 - v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 1723 - io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 1552 + v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 1553 + io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 1554 + (io_read(sd, 0x01) & 0x70) >> 4); 1724 1555 1725 1556 v4l2_info(sd, "-----Video Timings-----\n"); 1726 1557 if (read_stdi(sd, &stdi)) ··· 1883 1712 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 1884 1713 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 1885 1714 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 1886 - ADI recommended setting [REF_01 c. 2.3.3] */ 1715 + ADI recommended setting [REF_01, c. 2.3.3] */ 1887 1716 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 1888 - ADI recommended setting [REF_01 c. 2.3.3] */ 1717 + ADI recommended setting [REF_01, c. 2.3.3] */ 1889 1718 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 1890 1719 for digital formats */ 1891 1720 ··· 1894 1723 1895 1724 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 1896 1725 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 1897 - 1898 - state->prim_mode = pdata->prim_mode; 1899 - select_input(sd, pdata->prim_mode); 1900 - 1901 - enable_input(sd, pdata->prim_mode); 1902 1726 1903 1727 /* interrupts */ 1904 1728 io_write(sd, 0x40, 0xc2); /* Configure INT1 */ ··· 2049 1883 v4l2_err(sd, "failed to create all i2c clients\n"); 2050 1884 goto err_i2c; 2051 1885 } 1886 + state->restart_stdi_once = true; 2052 1887 2053 1888 /* work queues */ 2054 1889 state->work_queues = create_singlethread_workqueue(client->name);
+8 -3
drivers/media/i2c/soc_camera/mt9v022.c
··· 263 263 if (ret & 1) /* Autoexposure */ 264 264 ret = reg_write(client, mt9v022->reg->max_total_shutter_width, 265 265 rect.height + mt9v022->y_skip_top + 43); 266 - else 267 - ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 268 - rect.height + mt9v022->y_skip_top + 43); 266 + /* 267 + * If autoexposure is off, there is no need to set 268 + * MT9V022_TOTAL_SHUTTER_WIDTH here. Autoexposure can be off 269 + * only if the user has set exposure manually, using the 270 + * V4L2_CID_EXPOSURE_AUTO with the value V4L2_EXPOSURE_MANUAL. 271 + * In this case the register MT9V022_TOTAL_SHUTTER_WIDTH 272 + * already contains the correct value. 273 + */ 269 274 } 270 275 /* Setup frame format: defaults apart from width and height */ 271 276 if (!ret)
+4 -2
drivers/media/platform/exynos-gsc/gsc-core.c
··· 965 965 MODULE_DEVICE_TABLE(platform, gsc_driver_ids); 966 966 967 967 static const struct of_device_id exynos_gsc_match[] = { 968 - { .compatible = "samsung,exynos5250-gsc", 969 - .data = &gsc_v_100_drvdata, }, 968 + { 969 + .compatible = "samsung,exynos5-gsc", 970 + .data = &gsc_v_100_drvdata, 971 + }, 970 972 {}, 971 973 }; 972 974 MODULE_DEVICE_TABLE(of, exynos_gsc_match);
+2 -2
drivers/media/platform/omap3isp/ispccdc.c
··· 1706 1706 } 1707 1707 1708 1708 static int ccdc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1709 - const struct v4l2_event_subscription *sub) 1709 + struct v4l2_event_subscription *sub) 1710 1710 { 1711 1711 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1712 1712 return -EINVAL; ··· 1719 1719 } 1720 1720 1721 1721 static int ccdc_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1722 - const struct v4l2_event_subscription *sub) 1722 + struct v4l2_event_subscription *sub) 1723 1723 { 1724 1724 return v4l2_event_unsubscribe(fh, sub); 1725 1725 }
+2 -2
drivers/media/platform/omap3isp/ispstat.c
··· 1025 1025 1026 1026 int omap3isp_stat_subscribe_event(struct v4l2_subdev *subdev, 1027 1027 struct v4l2_fh *fh, 1028 - const struct v4l2_event_subscription *sub) 1028 + struct v4l2_event_subscription *sub) 1029 1029 { 1030 1030 struct ispstat *stat = v4l2_get_subdevdata(subdev); 1031 1031 ··· 1037 1037 1038 1038 int omap3isp_stat_unsubscribe_event(struct v4l2_subdev *subdev, 1039 1039 struct v4l2_fh *fh, 1040 - const struct v4l2_event_subscription *sub) 1040 + struct v4l2_event_subscription *sub) 1041 1041 { 1042 1042 return v4l2_event_unsubscribe(fh, sub); 1043 1043 }
+2 -2
drivers/media/platform/omap3isp/ispstat.h
··· 147 147 void omap3isp_stat_cleanup(struct ispstat *stat); 148 148 int omap3isp_stat_subscribe_event(struct v4l2_subdev *subdev, 149 149 struct v4l2_fh *fh, 150 - const struct v4l2_event_subscription *sub); 150 + struct v4l2_event_subscription *sub); 151 151 int omap3isp_stat_unsubscribe_event(struct v4l2_subdev *subdev, 152 152 struct v4l2_fh *fh, 153 - const struct v4l2_event_subscription *sub); 153 + struct v4l2_event_subscription *sub); 154 154 int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable); 155 155 156 156 int omap3isp_stat_busy(struct ispstat *stat);
+1 -1
drivers/media/platform/omap3isp/ispvideo.c
··· 792 792 } 793 793 794 794 static int 795 - isp_video_set_crop(struct file *file, void *fh, struct v4l2_crop *crop) 795 + isp_video_set_crop(struct file *file, void *fh, const struct v4l2_crop *crop) 796 796 { 797 797 struct isp_video *video = video_drvdata(file); 798 798 struct v4l2_subdev *subdev;
+1
drivers/media/platform/s5p-fimc/Kconfig
··· 24 24 config VIDEO_S5P_MIPI_CSIS 25 25 tristate "S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS) driver" 26 26 depends on REGULATOR 27 + select S5P_SETUP_MIPIPHY 27 28 help 28 29 This is a V4L2 driver for Samsung S5P and EXYNOS4 SoC MIPI-CSI2 29 30 receiver (MIPI-CSIS) devices.
+3 -1
drivers/media/platform/s5p-fimc/fimc-capture.c
··· 1736 1736 q->mem_ops = &vb2_dma_contig_memops; 1737 1737 q->buf_struct_size = sizeof(struct fimc_vid_buffer); 1738 1738 1739 - vb2_queue_init(q); 1739 + ret = vb2_queue_init(q); 1740 + if (ret) 1741 + goto err_ent; 1740 1742 1741 1743 vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK; 1742 1744 ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0);
+3 -1
drivers/media/platform/s5p-fimc/fimc-lite.c
··· 1253 1253 q->buf_struct_size = sizeof(struct flite_buffer); 1254 1254 q->drv_priv = fimc; 1255 1255 1256 - vb2_queue_init(q); 1256 + ret = vb2_queue_init(q); 1257 + if (ret < 0) 1258 + return ret; 1257 1259 1258 1260 fimc->vd_pad.flags = MEDIA_PAD_FL_SINK; 1259 1261 ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
+20 -21
drivers/media/platform/s5p-fimc/fimc-mdevice.c
··· 343 343 static int fimc_register_callback(struct device *dev, void *p) 344 344 { 345 345 struct fimc_dev *fimc = dev_get_drvdata(dev); 346 - struct v4l2_subdev *sd = &fimc->vid_cap.subdev; 346 + struct v4l2_subdev *sd; 347 347 struct fimc_md *fmd = p; 348 - int ret = 0; 348 + int ret; 349 349 350 - if (!fimc || !fimc->pdev) 350 + if (fimc == NULL || fimc->id >= FIMC_MAX_DEVS) 351 351 return 0; 352 352 353 - if (fimc->pdev->id < 0 || fimc->pdev->id >= FIMC_MAX_DEVS) 354 - return 0; 355 - 356 - fimc->pipeline_ops = &fimc_pipeline_ops; 357 - fmd->fimc[fimc->pdev->id] = fimc; 353 + sd = &fimc->vid_cap.subdev; 358 354 sd->grp_id = FIMC_GROUP_ID; 359 355 360 356 ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd); 361 357 if (ret) { 362 358 v4l2_err(&fmd->v4l2_dev, "Failed to register FIMC.%d (%d)\n", 363 359 fimc->id, ret); 360 + return ret; 364 361 } 365 362 366 - return ret; 363 + fimc->pipeline_ops = &fimc_pipeline_ops; 364 + fmd->fimc[fimc->id] = fimc; 365 + return 0; 367 366 } 368 367 369 368 static int fimc_lite_register_callback(struct device *dev, void *p) 370 369 { 371 370 struct fimc_lite *fimc = dev_get_drvdata(dev); 372 - struct v4l2_subdev *sd = &fimc->subdev; 373 371 struct fimc_md *fmd = p; 374 372 int ret; 375 373 376 - if (fimc == NULL) 374 + if (fimc == NULL || fimc->index >= FIMC_LITE_MAX_DEVS) 377 375 return 0; 378 376 379 - if (fimc->index >= FIMC_LITE_MAX_DEVS) 380 - return 0; 377 + fimc->subdev.grp_id = FLITE_GROUP_ID; 381 378 382 - fimc->pipeline_ops = &fimc_pipeline_ops; 383 - fmd->fimc_lite[fimc->index] = fimc; 384 - sd->grp_id = FLITE_GROUP_ID; 385 - 386 - ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd); 379 + ret = v4l2_device_register_subdev(&fmd->v4l2_dev, &fimc->subdev); 387 380 if (ret) { 388 381 v4l2_err(&fmd->v4l2_dev, 389 382 "Failed to register FIMC-LITE.%d (%d)\n", 390 383 fimc->index, ret); 384 + return ret; 391 385 } 392 - return ret; 386 + 387 + fimc->pipeline_ops = &fimc_pipeline_ops; 388 + fmd->fimc_lite[fimc->index] = fimc; 389 + return 0; 393 390 } 394 391 395 392 static int csis_register_callback(struct device *dev, void *p) ··· 404 407 v4l2_info(sd, "csis%d sd: %s\n", pdev->id, sd->name); 405 408 406 409 id = pdev->id < 0 ? 0 : pdev->id; 407 - fmd->csis[id].sd = sd; 408 410 sd->grp_id = CSIS_GROUP_ID; 411 + 409 412 ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd); 410 - if (ret) 413 + if (!ret) 414 + fmd->csis[id].sd = sd; 415 + else 411 416 v4l2_err(&fmd->v4l2_dev, 412 417 "Failed to register CSIS subdevice: %d\n", ret); 413 418 return ret;
+2 -1
drivers/media/platform/sh_vou.c
··· 935 935 /* Assume a dull encoder, do all the work ourselves. */ 936 936 static int sh_vou_s_crop(struct file *file, void *fh, const struct v4l2_crop *a) 937 937 { 938 + struct v4l2_crop a_writable = *a; 938 939 struct video_device *vdev = video_devdata(file); 939 940 struct sh_vou_device *vou_dev = video_get_drvdata(vdev); 940 - struct v4l2_rect *rect = &a->c; 941 + struct v4l2_rect *rect = &a_writable.c; 941 942 struct v4l2_crop sd_crop = {.type = V4L2_BUF_TYPE_VIDEO_OUTPUT}; 942 943 struct v4l2_pix_format *pix = &vou_dev->pix; 943 944 struct sh_vou_geometry geo;
-9
drivers/media/platform/soc_camera/mx1_camera.c
··· 470 470 pcdev->icd = NULL; 471 471 } 472 472 473 - static int mx1_camera_set_crop(struct soc_camera_device *icd, 474 - struct v4l2_crop *a) 475 - { 476 - struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 477 - 478 - return v4l2_subdev_call(sd, video, s_crop, a); 479 - } 480 - 481 473 static int mx1_camera_set_bus_param(struct soc_camera_device *icd) 482 474 { 483 475 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); ··· 681 689 .add = mx1_camera_add_device, 682 690 .remove = mx1_camera_remove_device, 683 691 .set_bus_param = mx1_camera_set_bus_param, 684 - .set_crop = mx1_camera_set_crop, 685 692 .set_fmt = mx1_camera_set_fmt, 686 693 .try_fmt = mx1_camera_try_fmt, 687 694 .init_videobuf = mx1_camera_init_videobuf,
+9 -4
drivers/media/platform/soc_camera/mx2_camera.c
··· 864 864 865 865 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 866 866 icd->current_fmt->host_fmt); 867 - if (bytesperline < 0) 867 + if (bytesperline < 0) { 868 + spin_unlock_irqrestore(&pcdev->lock, flags); 868 869 return bytesperline; 870 + } 869 871 870 872 /* 871 873 * I didn't manage to properly enable/disable the prp ··· 880 878 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 881 879 pcdev->discard_size, &pcdev->discard_buffer_dma, 882 880 GFP_KERNEL); 883 - if (!pcdev->discard_buffer) 881 + if (!pcdev->discard_buffer) { 882 + spin_unlock_irqrestore(&pcdev->lock, flags); 884 883 return -ENOMEM; 884 + } 885 885 886 886 pcdev->buf_discard[0].discard = true; 887 887 list_add_tail(&pcdev->buf_discard[0].queue, ··· 1103 1099 } 1104 1100 1105 1101 static int mx2_camera_set_crop(struct soc_camera_device *icd, 1106 - struct v4l2_crop *a) 1102 + const struct v4l2_crop *a) 1107 1103 { 1108 - struct v4l2_rect *rect = &a->c; 1104 + struct v4l2_crop a_writable = *a; 1105 + struct v4l2_rect *rect = &a_writable.c; 1109 1106 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1110 1107 struct v4l2_mbus_framefmt mf; 1111 1108 int ret;
+3 -2
drivers/media/platform/soc_camera/mx3_camera.c
··· 799 799 * default g_crop and cropcap from soc_camera.c 800 800 */ 801 801 static int mx3_camera_set_crop(struct soc_camera_device *icd, 802 - struct v4l2_crop *a) 802 + const struct v4l2_crop *a) 803 803 { 804 - struct v4l2_rect *rect = &a->c; 804 + struct v4l2_crop a_writable = *a; 805 + struct v4l2_rect *rect = &a_writable.c; 805 806 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 806 807 struct mx3_camera_dev *mx3_cam = ici->priv; 807 808 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+2 -2
drivers/media/platform/soc_camera/omap1_camera.c
··· 1215 1215 } 1216 1216 1217 1217 static int omap1_cam_set_crop(struct soc_camera_device *icd, 1218 - struct v4l2_crop *crop) 1218 + const struct v4l2_crop *crop) 1219 1219 { 1220 - struct v4l2_rect *rect = &crop->c; 1220 + const struct v4l2_rect *rect = &crop->c; 1221 1221 const struct soc_camera_format_xlate *xlate = icd->current_fmt; 1222 1222 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1223 1223 struct device *dev = icd->parent;
+2 -2
drivers/media/platform/soc_camera/pxa_camera.c
··· 1337 1337 } 1338 1338 1339 1339 static int pxa_camera_set_crop(struct soc_camera_device *icd, 1340 - struct v4l2_crop *a) 1340 + const struct v4l2_crop *a) 1341 1341 { 1342 - struct v4l2_rect *rect = &a->c; 1342 + const struct v4l2_rect *rect = &a->c; 1343 1343 struct device *dev = icd->parent; 1344 1344 struct soc_camera_host *ici = to_soc_camera_host(dev); 1345 1345 struct pxa_camera_dev *pcdev = ici->priv;
+7 -6
drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
··· 1182 1182 } 1183 1183 1184 1184 /* Check if any dimension of r1 is smaller than respective one of r2 */ 1185 - static bool is_smaller(struct v4l2_rect *r1, struct v4l2_rect *r2) 1185 + static bool is_smaller(const struct v4l2_rect *r1, const struct v4l2_rect *r2) 1186 1186 { 1187 1187 return r1->width < r2->width || r1->height < r2->height; 1188 1188 } 1189 1189 1190 1190 /* Check if r1 fails to cover r2 */ 1191 - static bool is_inside(struct v4l2_rect *r1, struct v4l2_rect *r2) 1191 + static bool is_inside(const struct v4l2_rect *r1, const struct v4l2_rect *r2) 1192 1192 { 1193 1193 return r1->left > r2->left || r1->top > r2->top || 1194 1194 r1->left + r1->width < r2->left + r2->width || ··· 1263 1263 * 3. if (2) failed, try to request the maximum image 1264 1264 */ 1265 1265 static int client_s_crop(struct soc_camera_device *icd, struct v4l2_crop *crop, 1266 - const struct v4l2_crop *cam_crop) 1266 + struct v4l2_crop *cam_crop) 1267 1267 { 1268 1268 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1269 1269 struct v4l2_rect *rect = &crop->c, *cam_rect = &cam_crop->c; ··· 1519 1519 static int sh_mobile_ceu_set_crop(struct soc_camera_device *icd, 1520 1520 const struct v4l2_crop *a) 1521 1521 { 1522 - struct v4l2_rect *rect = &a->c; 1522 + struct v4l2_crop a_writable = *a; 1523 + const struct v4l2_rect *rect = &a_writable.c; 1523 1524 struct device *dev = icd->parent; 1524 1525 struct soc_camera_host *ici = to_soc_camera_host(dev); 1525 1526 struct sh_mobile_ceu_dev *pcdev = ici->priv; ··· 1546 1545 * 1. - 2. Apply iterative camera S_CROP for new input window, read back 1547 1546 * actual camera rectangle. 1548 1547 */ 1549 - ret = client_s_crop(icd, a, &cam_crop); 1548 + ret = client_s_crop(icd, &a_writable, &cam_crop); 1550 1549 if (ret < 0) 1551 1550 return ret; 1552 1551 ··· 1947 1946 } 1948 1947 1949 1948 static int sh_mobile_ceu_set_livecrop(struct soc_camera_device *icd, 1950 - struct v4l2_crop *a) 1949 + const struct v4l2_crop *a) 1951 1950 { 1952 1951 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1953 1952 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
+5 -6
drivers/media/usb/dvb-usb-v2/dvb_usb_core.c
··· 283 283 284 284 /* activate the pid on the device pid filter */ 285 285 if (adap->props->caps & DVB_USB_ADAP_HAS_PID_FILTER && 286 - adap->pid_filtering && 287 - adap->props->pid_filter) 286 + adap->pid_filtering && adap->props->pid_filter) { 288 287 ret = adap->props->pid_filter(adap, dvbdmxfeed->index, 289 288 dvbdmxfeed->pid, (count == 1) ? 1 : 0); 290 - if (ret < 0) 291 - dev_err(&d->udev->dev, "%s: pid_filter() " \ 292 - "failed=%d\n", KBUILD_MODNAME, 293 - ret); 289 + if (ret < 0) 290 + dev_err(&d->udev->dev, "%s: pid_filter() failed=%d\n", 291 + KBUILD_MODNAME, ret); 292 + } 294 293 295 294 /* start feeding if it is first pid */ 296 295 if (adap->feed_count == 1 && count == 1) {
+1 -3
drivers/media/usb/dvb-usb-v2/dvb_usb_urb.c
··· 32 32 return -EINVAL; 33 33 } 34 34 35 - ret = mutex_lock_interruptible(&d->usb_mutex); 36 - if (ret < 0) 37 - return ret; 35 + mutex_lock(&d->usb_mutex); 38 36 39 37 dev_dbg(&d->udev->dev, "%s: >>> %*ph\n", __func__, wlen, wbuf); 40 38
+4
drivers/media/usb/dvb-usb-v2/rtl28xxu.c
··· 1346 1346 &rtl2832u_props, "DigitalNow Quad DVB-T Receiver", NULL) }, 1347 1347 { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x00d3, 1348 1348 &rtl2832u_props, "TerraTec Cinergy T Stick RC (Rev. 3)", NULL) }, 1349 + { DVB_USB_DEVICE(USB_VID_DEXATEK, 0x1102, 1350 + &rtl2832u_props, "Dexatek DK mini DVB-T Dongle", NULL) }, 1351 + { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x00d7, 1352 + &rtl2832u_props, "TerraTec Cinergy T Stick+", NULL) }, 1349 1353 { } 1350 1354 }; 1351 1355 MODULE_DEVICE_TABLE(usb, rtl28xxu_id_table);
+10 -11
include/media/adv7604.h
··· 40 40 ADV7604_OP_CH_SEL_RBG = 5, 41 41 }; 42 42 43 - /* Primary mode (IO register 0x01, [3:0]) */ 44 - enum adv7604_prim_mode { 45 - ADV7604_PRIM_MODE_COMP = 1, 46 - ADV7604_PRIM_MODE_RGB = 2, 47 - ADV7604_PRIM_MODE_HDMI_COMP = 5, 48 - ADV7604_PRIM_MODE_HDMI_GR = 6, 49 - }; 50 - 51 43 /* Input Color Space (IO register 0x02, [7:4]) */ 52 44 enum adv7604_inp_color_space { 53 45 ADV7604_INP_COLOR_SPACE_LIM_RGB = 0, ··· 95 103 /* Bus rotation and reordering */ 96 104 enum adv7604_op_ch_sel op_ch_sel; 97 105 98 - /* Primary mode */ 99 - enum adv7604_prim_mode prim_mode; 100 - 101 106 /* Select output format */ 102 107 enum adv7604_op_format_sel op_format_sel; 103 108 ··· 129 140 u8 i2c_test; 130 141 u8 i2c_cp; 131 142 u8 i2c_vdp; 143 + }; 144 + 145 + /* 146 + * Mode of operation. 147 + * This is used as the input argument of the s_routing video op. 148 + */ 149 + enum adv7604_mode { 150 + ADV7604_MODE_COMP, 151 + ADV7604_MODE_GR, 152 + ADV7604_MODE_HDMI, 132 153 }; 133 154 134 155 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)