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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: rockchip: introduce GRF gates
Some rockchip SoCs, namely the RK3576, have bits in a General Register
File (GRF) that act just like clock gates. The downstream vendor kernel
simply maps over the already mapped GRF range with a generic clock gate
driver. This solution isn't suitable for upstream, as a memory range
will be in use by multiple drivers at the same time, and it leaks
implementation details into the device tree.
Instead, implement this with a new clock branch type in the Rockchip
clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch
depends on the type of GRF, but functions like a gate instead.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Nicolas Frattaroli
and committed by
Heiko Stuebner
e277168c
70a114da
+134
-1
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
+8
-1
drivers/clk/rockchip/clk.c
+8
-1
drivers/clk/rockchip/clk.c
···
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clk = NULL;
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/* for GRF-dependent branches, choose the right grf first */
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-
if (list->branch_type == branch_muxgrf &&
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if ((list->branch_type == branch_muxgrf || list->branch_type == branch_grf_gate) &&
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list->grf_type != grf_type_sys) {
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hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
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if (agrf->type == list->grf_type) {
···
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list->parent_names[0], flags,
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ctx->reg_base + list->gate_offset,
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list->gate_shift, list->gate_flags, &ctx->lock);
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break;
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case branch_grf_gate:
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flags |= CLK_SET_RATE_PARENT;
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clk = rockchip_clk_register_gate_grf(list->name,
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list->parent_names[0], flags, grf,
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list->gate_offset, list->gate_shift,
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list->gate_flags);
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break;
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case branch_composite:
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clk = rockchip_clk_register_branch(list->name,
+20
drivers/clk/rockchip/clk.h
+20
drivers/clk/rockchip/clk.h
···
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int flags, struct regmap *grf, int reg,
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int shift, int width, int mux_flags);
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struct clk *rockchip_clk_register_gate_grf(const char *name,
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const char *parent_name, unsigned long flags,
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struct regmap *regmap, unsigned int reg,
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unsigned int shift, u8 gate_flags);
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#define PNAME(x) static const char *const x[] __initconst
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enum rockchip_clk_branch_type {
···
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branch_divider,
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branch_fraction_divider,
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branch_gate,
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branch_grf_gate,
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branch_linked_gate,
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branch_mmc,
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branch_inverter,
···
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.gate_offset = o, \
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.gate_shift = b, \
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.gate_flags = gf, \
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}
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#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
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{ \
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.id = _id, \
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.branch_type = branch_grf_gate, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.gate_offset = o, \
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.gate_shift = b, \
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.gate_flags = gf, \
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.grf_type = gt, \
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}
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#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
+105
drivers/clk/rockchip/gate-grf.c
+105
drivers/clk/rockchip/gate-grf.c
···
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2025 Collabora Ltd.
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* Author: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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*
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* Certain clocks on Rockchip are "gated" behind an additional register bit
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* write in a GRF register, such as the SAI MCLKs on RK3576. This code
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* implements a clock driver for these types of gates, based on regmaps.
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*/
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+
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "clk.h"
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struct rockchip_gate_grf {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned int reg;
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unsigned int shift;
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u8 flags;
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};
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+
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#define to_gate_grf(_hw) container_of(_hw, struct rockchip_gate_grf, hw)
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static int rockchip_gate_grf_enable(struct clk_hw *hw)
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{
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struct rockchip_gate_grf *gate = to_gate_grf(hw);
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u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0;
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u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
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int ret;
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ret = regmap_update_bits(gate->regmap, gate->reg,
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hiword | BIT(gate->shift), hiword | val);
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return ret;
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}
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static void rockchip_gate_grf_disable(struct clk_hw *hw)
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{
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struct rockchip_gate_grf *gate = to_gate_grf(hw);
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u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift);
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u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
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regmap_update_bits(gate->regmap, gate->reg,
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hiword | BIT(gate->shift), hiword | val);
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}
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static int rockchip_gate_grf_is_enabled(struct clk_hw *hw)
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{
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struct rockchip_gate_grf *gate = to_gate_grf(hw);
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bool invert = !!(gate->flags & CLK_GATE_SET_TO_DISABLE);
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int ret;
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ret = regmap_test_bits(gate->regmap, gate->reg, BIT(gate->shift));
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if (ret < 0)
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ret = 0;
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return invert ? 1 - ret : ret;
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}
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static const struct clk_ops rockchip_gate_grf_ops = {
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.enable = rockchip_gate_grf_enable,
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.disable = rockchip_gate_grf_disable,
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.is_enabled = rockchip_gate_grf_is_enabled,
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};
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struct clk *rockchip_clk_register_gate_grf(const char *name,
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const char *parent_name, unsigned long flags,
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struct regmap *regmap, unsigned int reg, unsigned int shift,
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u8 gate_flags)
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{
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struct rockchip_gate_grf *gate;
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struct clk_init_data init;
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struct clk *clk;
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if (IS_ERR(regmap)) {
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pr_err("%s: regmap not available\n", __func__);
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return ERR_PTR(-EOPNOTSUPP);
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}
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags;
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init.num_parents = parent_name ? 1 : 0;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.ops = &rockchip_gate_grf_ops;
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gate->hw.init = &init;
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gate->regmap = regmap;
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gate->reg = reg;
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gate->shift = shift;
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gate->flags = gate_flags;
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clk = clk_register(NULL, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}